EVALUATION KIT AVAILABLE

MAX6620
Quad Linear Fan-Speed Controller

General Description Features

The MAX6620 controls the speeds of up to four fans o Controls Up to Four Independent Fans With
using four independent linear voltage outputs. The Linear (DC) Drive
drive voltages for the fans are controlled directly over o Uses Four External Low-Cost Pass Transistors
the I2C interface. Each output drives the base of an o 1% Accuracy Precision RPM Control
external bipolar transistor or the gate of a FET in high-
side drive configuration. Voltage feedback at the fan’s o Controlled Voltage Rate-Of-Change for Best
power-supply terminal is used to force the correct out- Acoustics
put voltage. o I2C Bus Interface
The MAX6620 offers two methods for fan control. In o 3.0V to 5.5V Supply Voltage Range
RPM mode, the MAX6620 monitors four fan tachometer o 250µA (typ) Operating Supply Current
logic outputs for precise (±1%) control of fan RPM and o 3µA (typ) Shutdown Supply Current
detection of fan failure. In DAC mode, each fan is dri-
ven with a voltage resolution of 9 bits and the tachome- o Small 5mm x 5mm Footprint
ter outputs of the fans are monitored for failure.
The DAC_START input selects the fan power-supply
voltage at startup to ensure appropriate fan drive when
power is first applied. A watchdog feature turns the Ordering Information
fans fully on to protect the system if there are no valid
I2C communications within a preset timeout period. PART TEMP RANGE PIN-PACKAGE

The MAX6620 operates from a 3.0V to 5.5V power sup- MAX6620ATI+ -40°C to +125°C 28 TQFN-EP*
ply with low 250µA supply current, and the I2C-compati- +Denotes a lead-free package.
ble interface makes it ideal for fan control in a wide *EP = Exposed paddle.
range of cooling applications. The MAX6620 is avail-
able in a 28-pin TQFN package and operates over the
-40°C to +125°C automotive temperature range.

Applications Pin Configuration

Consumer Products
DACOUT2

DACOUT3

TOP VIEW
DACFB2

DACFB3

Servers
TACH2

TACH3
GND

Communications Equipment
Storage Equipment 21 20 19 18 17 16 15

TACH1 22 14 TACH4

DACFB1 23 13 DACFB4

DACOUT1 24 12 DACOUT4

GND 25
MAX6620 11 GND

FAN 26 10 GND

VCC 27 9 X2
+
FAN_FAIL 28 8 X1

1 2 3 4 5 6 7
SCL

SDA

WD_START

GND

ADDR

DAC_START

SPINUP_START

Typical Application Circuit appears at end of data sheet.

TQFN
(5mm × 5mm × 0.8mm)

For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-4039; Rev 1; 1/13
MAX6620
Quad Linear Fan-Speed Controller

ABSOLUTE MAXIMUM RATINGS

VCC to GND ..........................................................-0.3V to +6.0V Continuous Power Dissipation (TA = +70°C)
FAN_FAIL, SDA, SCL to GND ...............................-0.3V to +6.0V 28-Pin TQFN (derate 34.5mW/°C above +70°C) ....2758.6mW
ADDR, SPINUP_START, DAC_START, WD_START, Operating Temperature Range .........................-40°C to +125°C
X1, X2 to GND ........................................-0.3V to (VCC + 0.3V) Junction Temperature ......................................................+150°C
All Other Pins to GND..........................................-0.3V to +13.5V Storage Temperature Range .............................-65°C to +150°C
Input Current at DACOUT_ Pins (Note 1) ...............+5mA/-50mA Soldering Temperature (reflow) .......................................+260°C
Input Current at Any Pin (Note 1)..........................................5mA Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (all pins, Human Body Model) (Note 2) ...±2000V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifica-
tions do not apply when operating the device beyond its rated operating conditions.
Note 2: Human Body Model, 100pF discharged through a 1.5kΩ resistor.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(TA = -40°C to +125°C, VCC = 3.0V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C, VCC = 3.3V.) (Note 3)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Operating Supply Voltage VCC 3.0 5.5 V
Operating Supply Current ICC VCC = 5.5V 0.25 0.60 mA
I2C inactive 0.2 0.5 mA
Quiescent Supply Current
Shutdown mode 3 20 µA
VFANHI 10 12 13.5
VFAN Supply Voltage V
VFANLO 4.0 5.0 5.5
VGND + 10V < VDACOUT_ < 11.5V,
-18
VFAN = 12V
DACOUT_ Output Current IDACOUT_ mA
VGND + 3V < VDACOUT_ < 10V,
-16
VFAN = 12V
VFAN -
DACOUT_ Output Voltage VDACOUT_ IDACOUT_ = 5mA 0.05 V
0.1
VFAN = VFANHI 256/535
At DACFB_, VFAN = VFANLO 256/567
DAC Feedback Voltage at Half
DACFBHS code = 0x100, V
Scale VFAN = 12V 5.54 5.74 5.94
IDACOUT_ = 5mA
VFAN = 5V 2.05 2.25 2.45
VFAN = VFANHI 511/535
DACFBFS At DACFB_,
DAC Feedback Voltage at Full VFAN = VFANLO 511/567
code = 0x1FF, V
Scale VFAN = 12V 11.25 11.45 11.65
VDACFB511 IDACOUT_ = 5mA
VFAN = 5V 4.3 4.5 4.7
Drive Voltage Resolution 9 Bit
DACFB_ Impedance RDACFB 1 MΩ
TACH Minimum Input Pulse Width 25 µs
Internal Reference Frequency
(Note 4) -3 +3 %
Accuracy
Using 32.768kHz crystal -0.1 +0.1
TACH Count Accuracy (Note 4) %
Using on-chip oscillator -2 +2

2 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

ELECTRICAL CHARACTERISTICS (continued)

(TA = -40°C to +125°C, VCC = 3.0V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C, VCC = 3.3V.) (Note 3)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Using 32.768kHz crystal, test at 850RPM -1 +1
Fan Control Accuracy (Note 4) %
Using on-chip oscillator -3 +3
XTAL Oscillator Startup Time 2 s
X1 Input Threshold 0.7 V
VCC 2
POR Threshold V
VFAN 3.5
LOGIC (SDA, SCL, FAN_FAIL, WD_START, TACH_)
VCC x
Input High Voltage VIH V
0.7
VCC x
Input Low Voltage VIL V
0.3
Input High Current IIH 1.0 µA
Input Low Current IIL -1.0 µA
Input Capacitance All digital inputs 6 pF
Output High Current 100 µA
Output Low Voltage IOL = 3mA 0.4 V
LOGIC (DAC_START, SPIN_START, ADDR)
VCC -
Input High Voltage VIH V
0.5
Input Low Voltage VIL 0.5 V
Input High Current IIH 1.0 µA
Input Low Current IIL -1.0 µA
Input Capacitance All digital inputs 6 pF
I2C-COMPATIBLE TIMING (Notes 5, 6)
Serial Clock Frequency fSCL 400 kHz
Bus Free Time Between STOP
tBUF 1.3 µs
and START Conditions
START Condition Hold Time tHD:STA 0.6 µs
STOP Condition Setup Time tSU:STO 600 ns
Clock Low Period tLOW 1.3 µs
Clock High Period tHIGH 0.6 µs
START Condition Setup Time tSU:STA 600 ns
Data Setup Time tSU:DAT 100 ns
Data Out Hold Time tDH 100 ns
Data In Hold Time tHD:DAT (Note 6) 0 0.9 µs
Maximum Receive SCL/SDA Rise
tR (Note 8) 300 ns
Time
Minimum Receive SCL/SDA Rise 20 + 0.1
tR (Note 7) ns
Time x CB

Maxim Integrated 3
MAX6620
Quad Linear Fan-Speed Controller

ELECTRICAL CHARACTERISTICS (continued)

(TA = -40°C to +125°C, VCC = 3.0V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C, VCC = 3.3V.) (Note 3)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

Maximum Receive SCL/SDA Fall
tF 300 ns
Time
Minimum Receive SCL/SDA Fall 20 + 0.1
tF (Note 7) ns
Time x CB
20 + 0.1
Transmit SDA Fall Time tF (Note 7) 250 ns
x CB
Pulse Width of Suppressed Spike tSP (Note 8) 0 50 ns
Output Fall Time CL = 400pF, IOUT = 3mA 250 ns
SDA Time Low for Reset of Serial
tTIMEOUT (Note 9) 20 50 ms
Interface
Note 3: All parts will operate properly over the VCC supply voltage range of 3.0V to 5.5V.
Note 4: Guaranteed by design and characterization.
Note 5: All timing specifications are guaranteed by design.
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling edge.
Note 7: CB = total capacitance of one bus line in pF. Tested with CB = 400pF.
Note 8: Input filters on SDA and SCL suppress noise spikes less than 50ns.
Note 9: Holding the SDA line low for a time greater than tTIMEOUT will cause the devices to reset SDA to the idle state of the serial
bus communication (SDA set high).

tR tF

SDA

tSU,DAT tHD,DAT tBUF

tHD,STA
tLOW tSU,STA tSU,STO

SCL

tHIGH
tHD,STA
tR tF
S Sr A P S

Figure 1. I2C Serial Interface Timing

4 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Typical Operating Characteristics

(VCC = 3.3V, VFAN = 12V, TA = +25°C, unless otherwise noted.)

TACH COUNT ACCURACY WITH INT CLK TACH COUNT ACCURACY WITH EXT CLK TACH COUNT ACCURACY WITH INT CLK
vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. TEMPERATURE
2.0 2.0 2.0
MAX6620 toc01

MAX6620 toc02

MAX6620 toc03
TACH COUNT ACCURACY WITH EXT CLK (%)
TACH COUNT ACCURACY WITH INT CLK (%)

TACH COUNT ACCURACY WITH INT CLK (%)

VFAN = 12V VFAN = 12V VFAN = 12V
1.5 1.5 1.5

1.0 1.0 1.0

TA = 0°C, +70°C, +125°C
0.5 TA = 0°C 0.5 0.5
TA = +25°C VCC = 5.0V
0 0 0

-0.5 -0.5 -0.5

TA = +25°C
-1.0 -1.0 -1.0 VCC = 3.3V
TA = +70°C
-1.5 TA = +125°C -1.5 -1.5

-2.0 -2.0 -2.0

3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5 -55 -10 35 80 125
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C)

TACH COUNT ACCURACY WITH EXT CLK DACFB_ VOLTAGE ACCURACY DACFB_ VOLTAGE ACCURACY
vs. TEMPERATURE vs. TEMPERATURE vs. SUPPLY VOLTAGE
2.0 2.0 2.0

MAX6620 toc06
MAX6620 toc05
MAX6620 toc04

VFAN = 12V
TACH COUNT ACCURACY WITH EXT CLK (%)

VFAN = 12V VFAN = 12V

1.5 1.5 1.5
VCC = 3.0V, 3.3V, 5.0V
DACFB VOLTAGE ACCURACY (%)
DACFB VOLTAGE ACCURACY (%)

1.0 1.0 1.0

VCC = 3.3V, 5.0V
0.5 0.5 0.5

0 0 0

-0.5 -0.5 -0.5

-1.0 -1.0 -1.0

-1.5 -1.5 -1.5

-2.0 -2.0 -2.0

-55 -10 35 80 125 -55 -10 35 80 125 3.0 3.5 4.0 4.5 5.0 5.5
TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY VOLTAGE (V)

DACFB_ VOLTAGE ACCURACY STANDBY SUPPLY CURRENT OPERATING SUPPLY CURRENT

vs. OUTPUT CURRENT vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
2.0 500 0.6
MAX6620 toc09
MAX6620 toc08
MAX6620 toc07

VFAN = 12V VFAN = 12V VFAN = 12V

1.5 450
OPERATING SUPPLY CURRENT (mA)
STANDBY SUPPLY CURRENT (µA)

0.5
DACFB VOLTAGE ACCURACY (%)

400
1.0 VCC = 3.0V, 3.3V
350 0.4
0.5
300
0 250 INT CLK 0.3
INT CLK
200
-0.5 VCC = 5.5V 0.2
150
-1.0
100 0.1
-1.5 EXT CLK EXT CLK
50
-2.0 0 0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT CURRENT (mA) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

Maxim Integrated 5
MAX6620
Quad Linear Fan-Speed Controller

Typical Operating Characteristics (continued)

(VCC = 3.3V, VFAN = 12V, TA = +25°C, unless otherwise noted.)

TACH COUNT ACCURACY WITH INT CLK TACH COUNT ACCURACY WITH EXT CLK TACH COUNT ACCURACY WITH INT CLK
vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE vs. TEMPERATURE
2.0 2.0 2.0
MAX6620 toc10

MAX6620 toc11

MAX6620 toc12
VFAN = 5.0V
TACH COUNT ACCURACY WITH INT CLK (%)

TACH COUNT ACCURACY WITH EXT CLK (%)

VFAN = 5.0V VFAN = 5.0V

TACH COUNT ACCURACY WITH INT CLK (%)

1.5 TA = 0°C 1.5 1.5
TA = +25°C
1.0 VCC = 3.3V
1.0 1.0
TA = 0°C, +70°C, +125°C
0.5 0.5 0.5

0 0 0
-0.5 TA = +125°C TA = +70°C
-0.5 -0.5 VCC = 5.0V
TA = +25°C
-1.0 -1.0 -1.0
-1.5 -1.5 -1.5

-2.0 -2.0 -2.0

3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5 -55 -10 35 80 125
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TEMPERATURE (°C)

TACH COUNT ACCURACY WITH EXT CLK DACFB_ VOLTAGE ACCURACY DACFB_ VOLTAGE ACCURACY
vs. TEMPERATURE vs. TEMPERATURE vs. SUPPLY VOLTAGE
2.0 4.5 4.5
MAX6620 toc13

MAX6620 toc14

MAX6620 toc15
TACH COUNT ACCURACY WITH EXT CLK (%)

VFAN = 5.0V VFAN = 5.0V VFAN = 5.0V

1.5 3.5 3.5
DACFB VOLTAGE ACCURACY (%)

DACFB VOLTAGE ACCURACY (%)

VCC = 3.0V
1.0 2.5 2.5
VCC = 3.3V, 5.0V
1.5 1.5
0.5
0.5 0.5
0
-0.5 -0.5
-0.5 VCC = 3.3V VCC = 5.5V
-1.5 -1.5
-1.0
-2.5 -2.5
-1.5 -3.5 -3.5
-2.0 -4.5 -4.5
-55 -10 35 80 125 -55 -10 35 80 125 3.0 3.5 4.0 4.5 5.0 5.5
TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY VOLTAGE (V)

DACFB_ VOLTAGE ACCURACY STANDBY SUPPLY CURRENT OPERATING SUPPLY CURRENT

vs. OUTPUT CURRENT vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
4.5 500 0.6
MAX6620 toc17

MAX6620 toc18
MAX6620 toc16

VFAN = 5.0V VFAN = 5.0V VFAN = 5.0V

3.5 450
OPERATING SUPPLY CURRENT (mA)

0.5
STANDBY SUPPLY CURRENT (µA)
DACFB VOLTAGE ACCURACY (%)

400
2.5
VCC = 3.0V, 3.3V 350
1.5 0.4
300
0.5
250 INT CLK 0.3
-0.5 INT CLK
200
-1.5 VCC = 5.5V 0.2
150
-2.5 100
0.1
-3.5 50 EXT CLK
EXT CLK
-4.5 0 0
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 3.0 3.5 4.0 4.5 5.0 5.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT CURRENT (mA) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

6 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Pin Description
PIN NAME FUNCTION
2
1 SCL I C Serial-Clock Input. Can be pulled up to 5.5V regardless of VCC. Open circuit when VCC = 0V.
Open-Drain, I2C Serial-Data Input/Output. Can be pulled up to 5.5V regardless of VCC. Open
2 SDA
circuit when VCC = 0V.
Startup Watchdog Set Input. This input is sampled when power is first applied and sets the initial
I2C watchdog behavior. When connected to GND, the watchdog function is disabled. When
3 WD_START
connected to VCC, the MAX6620 monitors SDA. If 10s elapse without a valid I2C transaction, the
fan drive goes to 100%.
4, 10, 11, 18,
GND Ground
25
I2C Address Set Input. This input is sampled when power is first applied and sets the I2C slave
5 ADDR address. When connected to GND, the slave address will be 0x50. When unconnected, the slave
address will be 0x52. When connected to VCC, the slave address will be 0x54.
Startup Fan Drive DAC Set Input. This input is sampled when power is first applied and sets the
power-up value for the fan drive voltage. When connected to GND, the fan drive voltage will be
6 DAC_START
0%. When unconnected, the fan drive voltage will be 75%. When connected to VCC, the fan drive
voltage will be 100%.
Startup Spin-Up Set Input. This input is sampled when power is first applied and sets the initial
spin-up behavior. When connected to GND, spin-up is disabled. When connected to VCC at
power-up, the fan is driven with a full-scale drive voltage until two tachometer pulses have been
7 SPINUP_START
detected, or 1s has elapsed. When unconnected, the fan is driven with a full-scale drive voltage
until two tachometer pulses have been detected, or 0.5s has elapsed. Spin-up behavior may be
modified by writing appropriate settings to the MAX6620’s registers.
Crystal Oscillator Inputs. Connections for a standard 32.768kHz quartz crystal. The internal
oscillator circuitry is designed for operation with a crystal having a specified load capacitance
8, 9 X1, X2 (CL) of 12pF. Connect an external 32.768kHz oscillator across X1 and X2 for operation with the
external oscillator. If no crystal or external oscillator is connected, the MAX6620 will use its
internal oscillator.
DACOUT4– Fan Drive DAC Outputs. Connect to the gate of a p-channel MOSFET or base of a PNP bipolar
12, 17, 19, 24
DACOUT1 transistor.
DACFB4– DAC Feedback Inputs. Connect a 0.1µF capacitor between these pins and GND. Connect to the
13, 16, 20, 23
DACFB1 supply pin of the fan and to the drain of a p-channel MOSFET or collector of a PNP bipolar transistor.
14, 15, 21, 22 TACH4–TACH1 Fan Tachometer Logic Inputs. These inputs accept input voltages up to VFAN.
Fan Power-Supply Voltage Input. Connect to the fan power supply (VFAN). Bypass with a 0.1µF
26 FAN
capacitor to GND.
27 VCC Power-Supply Input. 3.3V nominal. Bypass VCC to GND with a 0.1µF capacitor.
Active-Low, Open-Drain Fan Failure Output. Active only when fault is present; open-circuit when
28 FAN_FAIL
VCC = 0V. This pin can be pulled up to 5.5V regardless of VCC.
Exposed Paddle. Internally connected to GND. Connect to a large ground plane to maximize
— EP
thermal performance. Not intended as an electrical connection point.

Maxim Integrated 7
MAX6620
Quad Linear Fan-Speed Controller

Detailed Description whether lack of I2C activity will force the fans to full
speed. When the watchdog function is enabled, the
The MAX6620 controls the speeds of up to four fans
fans will be driven to full speed if there is no I2C activity
using four independent linear voltage outputs. The
for a period of 2s, 6s, or 10s.
drive voltages for the fans are controlled directly over
the I 2 C interface. Each of the outputs (DACOUT1– Digital Interface
DACOUT4) drive the base of an external PNP or the The MAX6620 features an I2C-compatible, 2-wire serial
gate of a p-channel MOSFET. Voltage feedback at the interface consisting of a bidirectional serial data line
fan’s power-supply terminal is used to force the output (SDA) and a serial clock line (SCL). SDA and SCL facili-
voltage. tate bidirectional communication between the MAX6620
The MAX6620 monitors fan tachometer logic outputs for and the master at rates up to 400kHz. The master (typi-
precise (1%) control of fan RPM and detection of fan cally a microcontroller) initiates data transfer on the bus
failure. When the MAX6620 is used with 2-wire fans, and generates SCL. SDA and SCL require 4.7kΩ (typ)
these inputs are not used, and the fans can be driven pullup resistors.
to the desired voltage without using tachometer feed-
back.
Bit Transfer
One data bit is transferred during each SCL clock
Three inputs set the fan drive status on application of cycle. Nine clock cycles are required to transfer the
power. The DAC_START input selects the fan-supply data into or out of the MAX6620. The data on SDA must
voltage (100%, 75%, or 0%) at startup to ensure appro- remain stable during the high period of the SCL clock
priate fan drive when power is first applied. The pulse, as changes in SDA while SCL is high are control
SPIN_START input selects whether spin-up will be signals (see the START and STOP Conditions section).
applied to the fans at power-up. WD_START selects Both SDA and SCL idle high.

Write Byte Format

S ADDRESS WR A COMMAND A DATA A P
7 bits 8 bits 8 bits 1
Slave Address: equiva- Command Byte: selects which Data Byte: data goes into the register
lent to chip-select line of register you are writing to set by the command byte (to set
a 3-wire interface thresholds, configuration masks, and
sampling rate)
Read Byte Format

S ADDRESS WR A COMMAND A S ADDRESS RD A DATA A P

7 bits 8 bits 7 bits 8 bits
Slave Address: equiva- Command Byte: selects Slave Address: repeated Data Byte: reads from
lent to chip-select line which register you are due to change in data- the register set by the
reading from flow direction command byte
Send Byte Format Receive Byte Format
S ADDRESS WR A COMMAND A P S ADDRESS RD A DATA A P
7 bits 8 bits 7 bits 8 bits

Command Byte: sends com- Data Byte: reads data from

mand with no data, usually the register commanded
used for one-shot command by the last read byte or
write byte transmission;
S = START CONDITION SHADED = SLAVE TRANSMISSION also used for SMBus alert
P = STOP CONDITION A = NOT ACKNOWLEDGED response return address

Figure 2. I2C Protocols

8 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

A B C D E F G H I J K L M
tLOW tHIGH

SCL

SDA

tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF

A = START CONDITION E = SLAVE PULLS SMBDATA LINE LOW I = MASTER PULLS DATA LINE LOW
B = MSB OF ADDRESS CLOCKED INTO SLAVE F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = ACKNOWLEDGE CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO SLAVE K = ACKNOWLEDGE CLOCK PULSE
D = R/W BIT CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE L = STOP CONDITION
M = NEW START CONDITION

Figure 3. I2C Write Timing Diagram

A B C D E F G H I J K L M
tLOW tHIGH

SCL

SDA

tSU:STO tBUF
tSU:STA tHD:STA tSU:DAT

A = START CONDITION F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = ACKNOWLEDGE CLOCKED INTO SLAVE
B = MSB OF ADDRESS CLOCKED INTO SLAVE G = MSB OF DATA CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE
C = LSB OF ADDRESS CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO MASTER L = STOP CONDITION
D = R/W BIT CLOCKED INTO SLAVE I = MASTER PULLS DATA LINE LOW M = NEW START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW

Figure 4. I2C Read Timing Diagram

START and STOP Conditions edge bits. To generate an acknowledge, the receiving
The master initiates a transmission with a START condi- device must pull SDA low before the rising edge of the
tion (S), a high-to-low transition on SDA with SCL high. acknowledge-related clock pulse (9th pulse), and keep it
The master terminates a transmission with a STOP condi- low during the high period of the clock pulse (Figure 4).
tion (P), a low-to-high transition on SDA while SCL is high To generate a not acknowledge, the receiver allows
(Figure 3). The STOP condition frees the bus and places SDA to be pulled high before the rising edge of the
all devices in F/S mode (Figure 1). Use a repeated acknowledge-related clock pulse, and leaves it high
START condition (Sr) in place of a STOP condition to during the high period of the clock pulse. Monitoring
leave the bus active and in its current timing mode. the acknowledge bits allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
Acknowledge Bits happens if a receiving device is busy or if a system
Successful data transfers are acknowledged with an fault has occurred. In the event of an unsuccessful data
acknowledge bit (A) or a not-acknowledge bit (A). Both transfer, the master should reattempt communication at
the master and the MAX6620 (slave) generate acknowl- a later time.

Maxim Integrated 9
MAX6620
Quad Linear Fan-Speed Controller

Slave Address In a burst read, the process is the same as a single

A master initiates communication with a slave device by read except that the bus master issues an acknowl-
issuing a START condition followed by a slave address edge bit after each byte transmitted by the slave. After
byte. As shown in Figure 5, the slave address byte con- each acknowledge bit, the register address increments
sists of 7 address bits and a read/write bit (R/W). When by one, and the data from the next register is transmit-
idle, the MAX6620 continuously waits for a START con- ted by the slave. The process continues, with data
dition followed by its slave address. The first four bits reads followed by acknowledges. After the register with
(MSBs) of the slave address have been factory pro- the highest address is read, the register pointer rolls
grammed and are always 0101 and the seventh bit is 0. over to point to the first register. To terminate a burst
Connect ADDR to GND or VCC, or leave it unconnected read, the bus master issues a STOP condition.
to program D2 and D1 of the slave address according Single Write and Burst Write. A single write begins
to Table 1. with the bus master issuing a START condition followed
Table 1. Slave Address Setting with by the seven slave ID address bits and a zero (WR,
Figure 2), which is followed by an acknowledge bit (A)
ADDR Pin from the slave corresponding to the slave ID. Next, the
SLAVE ADDRESS master sends out an 8-bit register address, which is
ADDR CONNECTION also followed by an acknowledge bit from the slave.
HEX BINARY
After the acknowledge bit, 8-bit data is written to the
GND 0x50 0101 000
register, and the slave issues a third acknowledgement.
Unconnected 0x52 0101 010 A STOP condition is issued by the bus master to com-
VCC 0x54 0101 100 plete the single write process.
In a burst write, the process is similar to a single write
After receiving the address, the MAX6620 (slave) except that the master does not issue a STOP condition
issues an acknowledgement by pulling SDA low for one immediately after the first byte has been written. After
clock cycle. the first write is completed, the slave issues an
Data Byte (Read and Write) acknowledge bit, the register address increments by
Single Read and Burst Read. A single read begins one, and the data to be written to the next register is
with the bus master issuing a START condition followed transmitted by the master. The process continues, with
by the seven slave ID address bits and a zero (WR, data writes followed by acknowledges. After the regis-
Figure 2), which is followed by an acknowledge bit (A) ter with the highest available address is written, the reg-
from the slave corresponding to the slave ID. Next, the ister pointer rolls over to point to the first register. To
master sends out an 8-bit register address, which is terminate a burst write, the bus master issues a STOP
also followed by an acknowledge bit from the slave. condition.
The bus master issues another START condition and Fan Drive
the same seven slave ID address bits followed by a one The MAX6620 uses external pass transistors to power
(RD, Figure 2), with the slave producing an acknowl- the fans. DACOUT1–DACOUT4 adjust the power-
edge bit. The slave then sends out the 8-bit data corre- supply voltage for each fan by driving the base of a
sponding to the register address previously written by PNP bipolar transistor, or the gate of a p-MOSFET. The
the master. The bus master sends back a not-acknowl- resulting fan-supply voltage is fed back to DACFB_.
edge bit (A). This completes the single read process This closes the voltage feedback loop. The system
and a STOP condition is issued by the bus master. power supply for the output devices is VFAN. VFAN is

SDA 0 1 0 1 D2 D1 0 R/W A

ACKNOWLEDGE
SCL 1 2 3 4 5 6 7 8 9

Figure 5. MAX6620 Slave Address Byte

10 Maxim Integrated
Maxim Integrated
SINGLE WRITE

Figure 6. Read and Write Summary

BIT 7…………….……………… BIT 0 ACK BIT BIT 7…………….…………………BIT ACK BIT BIT 7…….…….…………BIT 0 ACK BIT

S 7-BIT SLAVE ID 0 AS 8-BIT REGISTER ADDRESS AS 8-BIT DATA AS P

SINGLE READ

BIT 7…………….……….BIT 0 ACK BIT BIT 7…………….……………BIT 0 ACK BIT BIT 7………….…………BIT 0 ACK BIT BIT 7…….…………BIT 0 ACK BIT

S 7-BIT SLAVE ID 0 AS 8-BIT REGISTER ADDRESS AS S 7-BIT SLAVE ID 1 AS 8-BIT DATA AM P

BURST WRITE

BIT 7…………….…………BIT 0 ACK BIT BIT 7…………….………BIT 0 ACK BIT BIT 7…………….……………BIT 0 ACK BIT BIT 7…………….…………BIT 0 ACK BIT

S 7-BIT SLAVE ID 0 AS 8-BIT REGISTER ADDRESS AS FIRST 8-BIT DATA AS LAST 8-BIT DATA AS P

BURST READ

BIT 7…………….………… BIT 0 ACK BIT BIT 7…………….…………… BIT 0 ACK BIT BIT 7……….…………………BIT 0 ACK BIT

S 7-BIT SLAVE ID 0 AS 8-BIT REGISTER ADDRESS AS S 7-BIT SLAVE ID 1 AS FIRST 8-BIT DATA AM

S: 2-WIRE BUS START CONDITION BY MASTER

P: 2-WIRE BUS STOP CONDITION BY MASTER
AS: ACKNOWLEDGE BY SLAVE BIT 7……….……………BIT 0 ACK BIT
AM: ACKNOWLEDGE BY MASTER
AM: NO ACKNOWLEDGE BY MASTER LAST 8-BIT DATA AM P

11
MAX6620
Quad Linear Fan-Speed Controller
MAX6620
Quad Linear Fan-Speed Controller

nominally 12V or 5V. The drive to the fans is proportion- The TACH count for a given RPM can be obtained from
al to VFAN. See the Fan_ Target Drive Voltage Registers the following equation:
and the Applications Information sections for more
details. 60 491520 × SR
TACH count = × SR × 8192 =
NP × RPM NP × RPM
Fan-Speed Control
DAC (Voltage) Mode. In DAC mode, the MAX6620 sim-
ply sets the voltage that powers the fan. The fan’s where:
speed is related, but not precisely proportional to, the NP = number of tachometer pulses per revolution. Most
drive voltage. The drive voltage is set by the Fan_ general-purpose brushless DC fans produce two
Target Drive Voltage registers and may be read from tachometer pulses per revolution.
the Fan_ Drive Voltage registers. Because the output SR = 1, 2, 4, 8, 16, or 32. See the Fan_ Speed Range
voltage can ramp to new values at a controlled rate, the information in the Fan_ Dynamics Registers (06h, 07h,
values in the two registers may be different. See the 08h, 09h)—POR = 0100 1100 section.
Register Descriptions and Applications Information sec-
tions for details. The tachometer count consists of 11 bits in the Fan_
TACH Count registers and is available in RPM and DAC
RPM Mode. In RPM mode, the MAX6620 monitors modes. In RPM mode, the desired fan count is written
tachometer output pulses from the fan and adjusts the to the Fan_ Target TACH Count registers.
fan drive voltage to force the fan’s speed to the desired
value. Fan speed is measured by counting the number Fan Failure Detection
of internal 8192Hz clock cycles that take place during a When enabled, the MAX6620 monitors the TACH_
selectable number of tachometer periods. The number inputs to determine when a fan has failed. For fans with
of clock cycles counted (11-bit value) is stored in the tachometer outputs, failure is detected in various ways
Fan_ TACH Count registers, and the desired number of depending on the fan control mode. In every case, four
cycles is stored in the Fan_ Target TACH Count regis- consecutive fault detections are required to decide
ters. See the Register Descriptions and Applications whether the fan has failed. In DAC mode, the Fan_
Information sections for details. Target TACH Count registers hold the upper limit for
Rate-of-Change Control. Sudden changes in fan tachometer count values; a fault condition is identified
speed can be easily heard by users. The MAX6620 when a TACH count exceeds the value written to the
helps reduce the audibility of fan-speed changes by Fan_ Target TACH Count registers for more than 1s. In
controlling the rate at which the drive to the fan is incre- RPM mode, a fault condition is identified when any of
mented. Four bits in the Fan_ Dynamics registers set the following three conditions occur for more than 1s: 1)
the rate at which the fan drive voltage is incremented. the TACH count exceeds the value of the Fan_ Target
This allows the time required for a change in fan speed TACH Count registers while the fan drive voltage is at
to be varied from 0 (in DAC mode only) to several min- full-scale, 2) the TACH count exceeds two times the
utes. See the Register Descriptions and Applications Fan_ Target TACH Count value, or 3) the TACH count
Information sections for details. reaches its full count of 7FFh.
Monitoring Tachometer Signals. The TACH_ inputs Some fans have locked rotor outputs that produce a
accept tachometer or “locked-rotor” output signals from logic-level output to indicate that the fan has stopped
3- or 4-wire fans. When measuring fan speed, the spinning. These signals can be monitored by setting
MAX6620 counts the number of internal 8192Hz clock D2:D1 in the Fan_ Configuration registers. D2 selects
cycles that occur during 1, 2, 4, 8, 16, or 32 tachometer locked rotor or tachometer monitoring and D1 selects the
periods. The number of tachometer periods is selec- polarity of the locked rotor signal. A fan fault has occurred
table for each fan by using the appropriate Fan_ when a locked rotor signal has been present for 1s.
Dynamics register. Tachometer pulses <25µs in dura- Fan failure is indicated in the Fan Fault register and
tion are ignored to minimize the effect of noise on the also with the open-drain FAN_FAIL output. The
tachometer lines. FAN_FAIL output may be masked using the mask bits
in the Fan Fault register. When a fan failure is detected,
drive to the affected fan is removed. Drive may be
restored by writing a new DAC or fan count target to the
fan’s control registers. The global configuration regis-

12 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

ter’s bit D4 can be used to cause a fan failure to force POR Options
the remaining fan speeds to 100%. Three inputs allow set up of the MAX6620’s behavior at
power-up. These inputs are sampled when power is
Watchdog first applied to the MAX6620:
The MAX6620 includes an optional I2C watchdog func-
tion that monitors the I2C bus for transactions. When the • WD_START. Connect WD_START to VCC to enable,
watchdog function is enabled, all fans will be forced to or to ground to disable, the watchdog function. When
full speed if no I2C transactions occur within a selected enabled using WD_START, the timeout period is 10s.
period (2s, 6s, or 10s). After power is applied, the watchdog function may be
enabled or disabled through the global configuration
Spin-Up register.
When a fan is not spinning, and a voltage less than the • SPINUP_START. At power-up, spin-up operation is
nominal fan-supply voltage is applied to its power- controlled by the SPINUP_START pin, which can be
supply terminals, it may fail to start spinning. To over- connected to ground (spin-up disabled), VCC (spin-
come this, the full nominal supply voltage may be up for a maximum of 1s), or unconnected (spin-up for
applied to the fan terminals for a short time before a a maximum of 0.5s).
lower voltage is applied. This “spin-up” period allows
the fan to overcome inertia and begin operating. Spin- • DAC_START. This input controls the fan drive volt-
up is controlled using the Fan_ Configuration registers. age (for all four fans) at power-up. When connected
Spin-up can be disabled, or it can cause the fan to be to ground, the initial fan drive voltage will be 0V.
driven with the full supply voltage until it produces two When connected to VCC, the initial fan drive voltage
tachometer pulses, up to a maximum of 0.5s, 1s, or 2s will be full scale. When unconnected, the initial fan
when the fan is started. drive voltage will be 75% of VFAN.

Maxim Integrated 13
 14
REGISTER POR
R/W FUNCTION D7 D6 D5 D4 D3 D2 D1 D0
NO./ADDRESS STATE

Bus Fans to I2C

I2C Watchdog:
POR: OSC: Watchdog
Run: Timeout 100% on 00 = No watchdog
MAX6620

Global Status
R/W 00h 0000 0XXX 0 = run 0 = normal (35ms): failure: 0 = internal 01 = 2s
Configuration (read only):
1 = standby 1 = reset 0 = enabled 0 = enabled 1 = XTAL 10 = 6s
1=
1 = disabled 1 = disabled 11 = 10s
elapsed
R/W 01h 0000 1111 Fan Fault Fan 4 Fault Fan 3 Fault Fan 2 Fault Fan 1 Fault Fan 4 Mask Fan 3 Mask Fan 2 Mask Fan 1 Mask
Spin-Up:
00 = No spin-up TACH/
Locked
01 = two TACH counts Locked
Mode: TACH Rotor
Fan 1 or 0.5s Rotor:
R/W 02h 0XX0 0000 0 = DAC input Polarity:
Configuration 10 = two TACH counts 0 = TACH
1 = RPM enable 0 = low
or 1s 1 = locked
1 = high
11 = two TACH counts rotor
or 2s
Fan 2
R/W 03h 0XX0 0000 Same as Fan 1 Configuration
Configuration
Fan 3
R/W 04h 0XX0 0000 Same as Fan 1 Configuration
Configuration
Fan 4
R/W 05h 0XX0 0000 Same as Fan 1 Configuration
Configuration
DAC Rate-of-Change:
Speed Range (TACH periods):
000 = 0s per LSB (DAC mode)
000 = 1
0.0625s per LSB (RPM mode)
001 = 2
001 = 0.015625s per LSB
010 = 4
Fan 1 010 = 0.03125s per LSB
R/W 06h 0100 1100 011 = 8
Dynamics 011 = 0.0625s per LSB
100 = 16
100 = 0.125s per LSB
Quad Linear Fan-Speed Controller

101 = 32
101 = 0.25s per LSB
110 = 32
110 = 0.5s per LSB
111 = 32
111 = 1s per LSB
Fan 2
R/W 07h 0100 1100 Same as Fan 1 Dynamics
Dynamics
Fan 3
R/W 08h 0100 1100 Same as Fan 1 Dynamics
Dynamics
Fan 4
R/W 09h 0100 1100 Same as Fan 1 Dynamics
Dynamics
Registers

Maxim Integrated
Register Map
 REGISTER POR

Maxim Integrated
R/W FUNCTION D7 D6 D5 D4 D3 D2 D1 D0
NO./ADDRESS STATE
10h 1111 1111 Fan 1 TACH D10 D9 D8 D7 D6 D5 D4 D3
R
11h 1110 0000 Count D2 D1 D0 — — — — —
12h 1111 1111 Fan 2 TACH
R Same as Fan 1 TACH Count
13h 1110 0000 Count
14h 1111 1111 Fan 3 TACH
R Same as Fan 1 TACH Count
15h 1110 0000 Count
16h 1111 1111 Fan 4 TACH
R Same as Fan 1 TACH Count
17h 1110 0000 Count
18h 0000 0000 Fan 1 Drive D8 D7 D6 D5 D4 D3 D2 D1
R
19h 0000 0000 Voltage D0 — — — — — — Full
1Ah 0000 0000 Fan 2 Drive
R Same as Fan 1 Drive Voltage
1Bh 0000 0000 Voltage
1Ch 0000 0000 Fan 3 Drive
R Same as Fan 1 Drive Voltage
1Dh 0000 0000 Voltage
1Eh 0000 0000 Fan 4 Drive
R Same as Fan 1 Drive Voltage
1Fh 0000 0000 Voltage
20h 0011 1100 Fan 1 Target D10 D9 D8 D7 D6 D5 D4 D3
R/W
21h 0000 0000 TACH Count D2 D1 D0 — — — — —
22h 0011 1100 Fan 2 Target
R/W Same as Fan 1 Target TACH Count
23h 0000 0000 TACH Count
24h 0011 1100 Fan 3 Target
R/W Same as Fan 1 Target TACH Count
25h 0000 0000 TACH Count
26h 0011 1100 Fan 4 Target
R/W Same as Fan 1 Target TACH Count
27h 0000 0000 TACH Count
28h XXXX XXXX Fan 1 Target D8 D7 D6 D5 D4 D3 D2 D1
R/W
29h X000 0000 Drive Voltage D0 — — — — — — —
2Ah XXXX XXXX Fan 2 Target
R/W Same as Fan 1 Target Drive Voltage
2Bh X000 0000 Drive Voltage
2Ch XXXX XXXX Fan 3 Target
R/W Same as Fan 1 Target Drive Voltage
2Dh X000 0000 Drive Voltage
2Eh XXXX XXXX Fan 4 Target
R/W Same as Fan 1 Target Drive Voltage
2Fh X000 0000 Drive Voltage

X = Depends on input states at power-up.

15
Register Map (continued)
MAX6620
Quad Linear Fan-Speed Controller
MAX6620
Quad Linear Fan-Speed Controller

Register Descriptions
Global Configuration Register (00h)—POR = 0000 0XXX
BIT R/W FUNCTION
Run:
7 R/W 0 = run
1 = standby

POR:
0 = normal operation
6 R/W
1 = reset all registers to POR values
This bit automatically resets itself and will always return a 0 when read.

I2C Bus Timeout:

0 = enabled
5 R/W
1 = disabled
The I2C interface will reset if SDA is low for more than 35ms.

Fans to 100% on failure:

0 = if a fan failure is detected, all other fan channels immediately go to full-scale drive voltage to
4 R/W
ensure adequate cooling
1 = disabled

Oscillator Selection:
Selects on-chip oscillator or 32.768kHz crystal/ceramic resonator. Use crystal if 1% RPM accuracy is
required.
0 = internal oscillator (default at power-on)
3 R/W
1 = external 32.768kHz crystal
When switching from the internal oscillator to an external crystal, the MAX6620 operates from the internal
oscillator until the crystal oscillator has started up. If the crystal is damaged or the oscillator fails to start,
the MAX6620 will continue to operate from the internal oscillator.

16 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Global Configuration Register (00h)—POR = 0000 0XXX (continued)

BIT R/W FUNCTION

I2C Watchdog:
When active, the watchdog monitors SDA and SCL for valid I2C transactions. If there are no valid
transactions between the master and the MAX6620 within the watchdog period, all fan output voltages
will go to full-scale drive voltage.
2
If the watchdog times out and valid I2C transactions begin to occur again, operation will resume with the
previous DAC value. The master can then program the output voltages, target TACH counts, or other
functions in the normal manner.

When the watchdog function is active, ensure that the master communicates to the MAX6620
R/W
periodically, for example reading a status register.

The POR state is set by the state of the WD_START pin at power-up.
D2:D1 I2C WATCHDOG PERIOD (s) POR CONDITION
1 00 Inactive (no watchdog) WD_START = GND
01 2 —
10 6 —
11 10 WD_START = VCC

I2C Watchdog Status:

0 = I2C transactions occurred within watchdog period
0 R
1 = time between I2C transaction exceeds watchdog period
This bit is cleared by I2C read from this register.

Maxim Integrated 17
MAX6620
Quad Linear Fan-Speed Controller

Fan Fault Register (01h)—POR = 0000 1111

BIT R/W FUNCTION
Fan 4 Fault Status:
Indicates which fans have had faults detected. When a fan fault is detected, the drive to the fan is disabled
and the corresponding fault bit is set. The fault bits latch until they are cleared by reading, thus allowing
short-term faults to be identified. After a fault status bit is cleared by reading, the corresponding output
voltage will remain zero until a Fan_ Target Drive Voltage register or Fan_ Target TACH Register is
written. Writing a new target drive voltage or target TACH count will cause drive to be applied to the fan
again, at which time a new failure-detection cycle will begin.
Fault Conditions Are:
FAN_ DRIVE TIME
MODE CONDITION
VOLTAGE REGISTER (s)
7 R TACH count exceeds value of Fan_ Target
DAC Any TACH count >1
Locked rotor asserts
TACH count exceeds value of Fan_ Target
1FFh (full)
TACH Count
RPM TACH count exceeds two times of Fan_ Target >1
<1FFh TACH Count value
TACH count reaches it full count of 7FFh

FAN_FAIL will be asserted when four consecutive faults are detected.

6 R Fan 3 Fault Status
5 R Fan 2 Fault Status
4 R Fan 1 Fault Status
Fan 4 Fault Mask:
Masks faults on selected fans from asserting the FAN_FAIL output. Faults will still be indicated by the
3 R/W fault status bits:
0 = not masked
1 = masked
2 R/W Fan 3 Fault Mask
1 R/W Fan 2 Fault Mask
0 R/W Fan 1 Fault Mask

18 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Fan_ Configuration Registers (02h, 03h, 04h, 05h)—POR = 0XX0 0000

BIT R/W FUNCTION

RPM/DAC:
0 = DAC mode. The fan drive voltage is set by the value in the Fan_ Target Drive Voltage register.
1 = RPM mode. The fan drive voltage is adjusted to produce the TACH count value in the Fan_ Target
TACH Count register.
7 R/W
When changing from DAC to RPM mode, if the current RPM value is different from the value selected in
the Fan_ Target TACH Count register, the drive voltage will start from the current value and increment/
decrement toward the desired value at the selected DAC rate-of-change.

Spin-Up:
When the fan drive voltage increases from 0V to a value less than the full-scale drive voltage, it may be
necessary to drive the fan with the full-scale drive voltage for a brief period to ensure that the fan is
spinning before reducing the drive to the selected value.

6 R/W When spin-up is selected, the fan is driven at the full-scale drive voltage until two tachometer pulses
have been detected or locked rotor has been cleared. A maximum spin-up time is also selectable to
ensure that the spin-up time is not excessive. After two tachometer pulses have been detected, or locked
rotor has been cleared or the spin-up has timed out, the drive voltage goes to the value in the Fan_ Target
Drive Voltage register.

The POR state is set by the state of the SPINUP_START pin at power-up.

D6:D5 FUNCTION POR CONDITION

00 No spin-up SPIN_START pin = ground
Spin-up until two tachometer pulses or
01 SPIN_START pin = open
clearing of locked rotor, or 0.5s (max)
5 R/W
Spin-up until two tachometer pulses or
10 SPIN_START pin = VCC
clearing of locked rotor, or 1s (max)
Spin-up until two tachometer pulses or
11 —
clearing of locked rotor, or 2s (max)

4 Reserved
TACH Input Enable:
Enables TACH input function and fan fault detection (automatically enabled in RPM mode).
3 R/W
0 = disabled. When disabled and TACH input is not used, bit 1 and bit 2 are ignored.
1 = enabled

TACH/Locked Rotor:
Selects TACH input function as TACH count or locked rotor. In locked rotor mode, the TACH count stops
2 R/W and assertion of the TACH input indicates that the fan has stopped.
0 = TACH count
1 = locked rotor

Locked Rotor Polarity:

1 R/W 0 = low locked rotor. TACH input low in locked rotor mode indicates fan is stopped.
1 = high locked rotor. TACH input high in locked rotor mode indicates fan is stopped.
0 — Reserved

Maxim Integrated 19
MAX6620
Quad Linear Fan-Speed Controller

Fan_ Dynamics Registers (06h, 07h, 08h, 09h)—POR = 0100 1100

BIT R/W FUNCTION
Fan_ Speed Range:
The MAX6620 determines fan speed by counting the number of internal 8192Hz clock cycles (using an
11-bit counter) during one or more fan tachometer periods. Three bits set the nominal RPM range for the
fan, as shown in the table below. As an example, a setting of 010 causes the MAX6620 to count the
number of 8192Hz clock cycles that occur during four complete tachometer periods. If the fan has a
nominal speed of 2000RPM and two tachometer pulses per revolution, one tachometer period will be
7 R/W nominally 15ms, and four tachometer periods will be 60ms. With an 8192Hz clock, the TACH count will
therefore be equal to 491. With a fan speed of 1/3 the nominal value, the count will be 1474. If the fan’s
nominal speed is 1000RPM, the full-speed TACH count will be 983. At 1/3 the nominal speed, there will
be 2948 clock cycles in four tachometer periods. This is greater than the maximum 11-bit count of 2047,
so four tachometer periods is too many for this fan; a setting of 001 (two clock cycles) is recommended
instead.

The table below shows the full-speed tachometer counts for several combinations of nominal fan speeds
and D7:D5 settings. The shaded combinations will provide the best results. When setting D7:D5, the goal
is to obtain the highest tachometer count without exceeding the maximum count of 2047 when the fan is
at the minimum speed of interest. For example, if the minimum speed of interest is 1/3 of full speed, the
maximum tachometer count will be three times the value shown in the table below:

6 R/W Tachometer Counts/(Counting Period) (8192Hz Clock Used):

NUMBER OF RPM
D7:D5 TACH PERIODS
COUNTED 500 1000 2000 4000 8000 16000

491 245 122 61 30 15

000 1
(60ms) (30ms) (15ms) (7.5ms) (3.75ms) (1.875ms)
983 491 245 122 61 30
001 2
(120ms) (60ms) (30ms) (15ms) (7.5ms) (3.75ms)
1966 983 491 245 122 61
010 4
(240ms) (120ms) (60ms) (30ms) (15ms) (7.5ms
2047 1966 983 491 245 122
011 8
5 R/W (480ms) (240ms) (120ms) (60ms) (30ms) (15ms)
2047 2047 1966 983 491 245
100 16
(960ms) (480ms) (240ms) (120ms (60ms) (30ms)

101,
2047 2047 2047 1966 983 491
110, 32
(1920ms) (960ms) (480ms) (240ms) (120ms) (60ms)
111

20 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Fan_ Dynamics Registers (06h, 07h, 08h, 09h)—POR = 0100 1100 (continued)
BIT R/W FUNCTION
Fan_ DAC Rate-of-Change:
The fan drive voltage (at the DACFB_ inputs) varies from 0 to full scale in 512 increments. The rate-of-
change bits determine the time interval between output voltage increments/decrements. In RPM mode, a
setting of 0 would result in an unstable feedback loop, so a default value of 0.0625 is in effect when 0 is
selected.

4 R/W Regardless of the settings, there are a few cases for which the rate-of-change is always 0:
• When a target TACH count of 2047 (7FFh) is selected, the fan drive voltage immediately goes to 0V.
A full-scale target count is assumed to mean that the intent is to shut down the fan, and going
directly to 0 drive avoids the possibility of loss of control-loop feedback at high TACH counts. If a
slow- speed decrease toward 0 is desired, a target TACH count at the slowest practical value for the
fan should be chosen. Once that count has been reached, selecting a count of 2047 (7FFh) will then
take the drive immediately to 0V.
• When a target fan drive voltage of 0V is selected, the drive voltage immediately goes to 0V. Again, it
is assumed that the intent is to shut down the fan. If a slow-speed decrease toward 0 is desired, a
target fan drive voltage of the slowest practical value for the fan in question should be chosen. Once
that drive voltage has been reached, selecting a target value of 0 will then take the drive
immediately to 0V.
• When the current drive level is 0 in DAC mode, selecting a new target fan drive voltage will
3 R/W immediately take the voltage to that value. The fan will spin-up first if spin-up is enabled.
• When the current drive level is 0 in RPM mode, selecting a new target TACH count that is less than
2047 (7FFh) will immediately take the drive voltage to the value in the Fan_ Target Drive Voltage
register. From this value, the drive voltage will increment as needed to achieve the desired TACH
count. The fan will spin-up first if spin-up is enabled.
TIME BETWEEN OUTPUT VOLTAGE TIME FROM 33%
D4:D2 INCREMENTS (s) TO 100%
DAC MODE RPM MODE (s)
000 0 0.0625 0
001 0.015625 10
010 0.03125 20
2 R/W 011 0.0625 (default) 40
100 0.125 80
101 0.25 160
110 0.5 320
111 1.0 640

1 — Reserved
0 — Reserved

Maxim Integrated 21
MAX6620
Quad Linear Fan-Speed Controller

Fan_ TACH Count Registers (10h, 12h, 14h, 16h)—POR = 1111 1111
BIT R/W FUNCTION
7
6
5 Fan_ TACH Count D10:D3:
4 Indicates the number of 8192Hz clock pulses counted during the counting period. The Fan_ TACH Count
R consists of 11 bits contained in two bytes.
3
2 To minimize noise from spurious tachometer transitions, pulses less than 25µs are ignored.
1
0

Fan_ TACH Count Registers (11h, 13h, 15h, 17h)—POR = 1110 0000
BIT R/W FUNCTION
7
6 R Fan_ TACH Count D7:D5
5

Fan_ Drive Voltage Registers (18h, 1Ah, 1Ch, 1Eh)—POR = 0000 0000
BIT R/W FUNCTION
7
6
5 Fan_ Drive Voltage D8:D1:
4 This is a 9-bit value that ranges from 0 to 511.
R
3 This register shows the actual fan drive voltage. When the value in this register is 480V, the nominal fan drive
2 voltage of VFAN is supplied to the fan, as shown in the table in the Fan_ Target Drive Voltage Registers section.
1
0

Fan_ Drive Voltage Registers (19h, 1Bh, 1Dh, 1Fh)—POR = 0000 0000
BIT R/W FUNCTION
7 R Fan_ Drive Voltage D0
Full-Scale Status:
0 R 0 = DAC is driving with value of D8:D0 that is not at full scale
1 = DAC is driving with full scale voltage

22 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Fan_ Target TACH Count Registers (20h, 22h, 24h, 26h)—POR = 0011 1100
The Fan_ Target TACH Count consists of 11 bits con- writes in between. These target registers are updated
tained in two bytes. The two bytes must be written in internally at the same time when a second byte (LSB) is
order in one or two I2C transactions, with no other I2C written.

BIT R/W FUNCTION

Fan_ Target TACH Count D10:D3:
7
In RPM mode, write the desired tachometer count to this register. The MAX6620 will then adjust the fan drive
voltage to achieve this tachometer count.
6
In DAC mode, this register has no effect.
5
When changing from DAC mode to RPM mode, best results are obtained by loading this register with the
4
desired TACH count before changing to RPM mode. The target TACH count for a given RPM will be obtained
R/W
by the following equation:
3

60
2 TargetTACH = × SR × 8192
NP × RPM
where:
1
NP = number of TACH pulses per revolution
SR = 1, 2, 4, 8, 16, or 32 (see the fan_ speed range information in the Fan_ Dynamics Registers (06h, 07h, 08h,
0
09h)—POR = 0100 1100 section)

Fan_ Target TACH Count Registers (21h, 23h, 25h, 27h)—POR = 0000 0000
BIT R/W FUNCTION
7
6 R Fan_ Target TACH Count D2:D0
5

Maxim Integrated 23
MAX6620
Quad Linear Fan-Speed Controller

Fan_ Target Drive Voltage Registers (28h, 2Ah, 2Ch, 2Eh)—POR = XXXX XXXX
The Fan_ Target Drive Voltage consists of 9 bits con- writes in between. These target registers are updated
tained in two bytes. The two bytes must be written in internally at the same time when a second byte (LSB) is
order in one or two I2C transactions with no other I2C written.

BIT R/W FUNCTION

Fan_ Target Drive Voltage D8:D1:
7 This is a 9-bit value that ranges from 0 to 511 and is contained in two bytes. In DAC mode, write the
desired fan drive voltage to these two registers. The MAX6620 will then ramp the fan drive voltage to
this value at a rate determined by the DAC rate-of-change bits.
In RPM mode, the value contained in this register will be the voltage applied to the fan immediately after
6 spin-up or after changing the Fan_ Target TACH Count from 2047 (7FFh) to a value lower than 2047
(7FFh). For example, if the fan is currently stopped with spin-up disabled, and a new Fan_ Target TACH
Count corresponding to 60% of the full-scale fan speed is to be selected, the fan voltage can be
programmed to immediately go to 60% of the full-scale drive voltage when the new Fan_ Target TACH
5 Count is selected from 2047 (7FFh), and then close the RPM control loop starting from that voltage.

The register value is converted to the drive voltage at the fan (or voltage at DACFB_) as follows:
D8:D0 FAN_ DRIVE VOLTAGE (V)
4
DECIMAL HEX 5V RANGE 12V RANGE
0 000h 0.000 0.000
R/W
200 0C8h 1.764 4.486
3
300 12Ch 2.646 6.729
400 190h 3.527 8.972
480 1E0h 4.232 10.766
2
511 1FFh 4.506 11.462

The value of the Fan_ Target Drive Voltage at POR depends on state of the DAC_START pin, as shown
1 below:
D8:D0
DAC_START
DECIMAL HEX
0 000h GND
0
384 180h Open
511 1FFh VCC

Fan_ Target Drive Voltage Registers (29h, 2Bh, 2Dh, 2Fh)—POR = X000 0000
Bit R/W FUNCTION
7 R Fan_ Target Drive Voltage D0

24 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Applications Information Fan-Speed Control (DAC and RPM Modes)

The MAX6620 has two main modes for controlling fan
External Pass Transistors speeds. In DAC mode, the MAX6620 produces an out-
Match external pass transistors to the fans being used. put voltage that drives the fan. This voltage is propor-
Ensure that the pass transistor is capable of handling tional to the main fan power-supply voltage (VFAN).
the maximum fan current. For best results, the pass Write the 9-bit desired voltage value in the Fan_ Target
transistor’s maximum current rating should be at least Drive Voltage register.
50% greater than the fan’s nominal supply current.
In RPM mode, the MAX6620 monitors the tachometer
The transistor should also be capable of dissipating the signals from the fans through the TACH_ inputs and
worst-case power, which usually occurs when the fan is adjusts the drive voltage to yield the desire tachometer
being driven to approximately 50% of the nominal sup- count. The tachometer count is the number of internal
ply voltage. The maximum power dissipation will 8192 clock cycles that are counted during the selected
depend on the thermal resistance of the transistor, its number of tachometer pulses.
case, and the printed-circuit board (PCB) to which it is
soldered. For example, if the worst-case transistor Controlling 2-Wire Fans (DAC Mode)
power dissipation occurs when the fan current is In DAC mode, the MAX6620 sets the fan’s supply volt-
100mA, and the voltage across the fan is 6.5V, the age to the value selected in the Fan_ Target Drive
maximum power dissipation will be 650mW. A Voltage register. Tachometer monitoring is never done
BCP69T1-D in a SOT223-4 package is rated at 1.5W at when controlling a 2-wire fan, so the TACH input enable
25°C (about 1W at 70°C) when soldered to a 0.93in2 bit in the Fan_ Configuration register should be set to 0.
(6cm2) copper PCB pad, and can easily handle this Enabling the TACH input when using a 2-wire fan will
power dissipation. Larger copper pads, packages with result in an erroneous fan failure detection.
lower thermal resistance, or different transistors can Initial Settings:
give significantly different results.
• Begin with the POR settings. The POR value of the
The MAX6620 uses an advanced output driver design fan_ DAC rate-of-change bits (4:2 of the Fan_
that eliminates the large external capacitors often con- Dynamics Register) can yield slower fan speed
nected across the fan’s power-supply terminals. For changes than desired. If this is the case, choose a
stability with a variety of fans, connect a 0.1µF capaci- faster value, such as 001.
tor from DACFB_ to ground.
Starting the Fan:
Using a Low-Dropout Voltage Regulator • Write the desired drive voltage value to the Fan_
(LDO) as the Pass Device Target Drive Voltage register.
Voltage regulators can be used instead of discrete tran- Changing Speeds:
sistors to drive the fans (Figure 7). The voltage feed-
back loop is closed around the regulator to provide the • Write the new desired drive voltage value to the Fan_
desired output voltage. When using a voltage regulator, Target Drive Voltage register.
note the following: Stopping the Fan:
• Most regulators require relatively large capacitors at • Write a voltage value of 0 to the Fan_ Target Drive
their inputs and outputs for stability. Voltage register.
• Most regulators have a lower output voltage limit that
Controlling 3-Wire Fans (DAC Mode)
is >0V. If removing the drive from the fan is neces-
In DAC mode, the MAX6620 sets the fan’s supply volt-
sary when using a regulator, choose a regulator that
age to the value selected in the Fan_ Target Drive
has an on/off control input and drive that input from
Voltage register. 3-wire fans with tachometer outputs
the system microcontroller.
allow monitoring of the fan’s speed to detect fan failure.
To monitor a fan’s speed, the TACH input should be
enabled.

Maxim Integrated 25
MAX6620
Quad Linear Fan-Speed Controller

VFAN
+12V

0.33µF
VIN
VC VO
PQ20RX
VADJ 47µF
2.4kΩ
470Ω
DACOUT1

27kΩ

DACFB1
VFAN

VCC VFAN
3.0V TO 5.5V +12V
TACH1
0.1µF FAN1
0.1µF
VFAN

0.33µF
FAN_FAIL
VIN
VC VO
PQ20RX
VADJ 47µF
2.4kΩ
470Ω
DACOUT2

SDA 27kΩ

TO I2C MASTER DACFB2

SCL
VFAN

TACH2
FAN2
VCC
VFAN
ADDR DAC OUTPUT
I2C INTERFACE, DRIVER
REGISTERS, AND 0.33µF
CONTROL LOGIC TACH MONITOR
DAC_START VIN
VC VO
PQ20RX
VADJ 47µF
SPINUP_START 2.4kΩ
470Ω
DACOUT3

WD_START 27kΩ

DACFB3
X1 VFAN

(OPTIONAL CRYSTAL)
X2 TACH3
FAN3
VFAN

0.33µF
VIN
VC VO
PQ20RX
VADJ 47µF
2.4kΩ
470Ω
DACOUT4

27kΩ

DACFB4
VFAN

TACH4
FAN3

Figure 7. Using Low Dropout Voltage Regulators Instead of Discrete Transistors as the Pass Devices

26 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Initial Settings: operate. When the drive voltage reaches that value,
• Begin with the POR settings. The POR value of the write 0V to the Fan_ Target Drive Voltage register.
fan_ DAC rate-of-change bits (4:2 of the Fan_ Controlling 3-Wire Fans (RPM Mode)
Dynamics register) can yield slower fan speed Begin as in DAC mode and start the fan.
changes than desired. If this is the case, choose a
faster value, such as 001. Changing from DAC Mode to RPM Mode:
• Write the desired number of tachometer periods to • Write the desired tachometer count to the Fan_ TACH
be counted in the speed range bits (7:5 of the Fan_ Count registers.
Dynamics register). • Set bit 7 of the Fan_ Configuration register to 1. This
• Write the maximum allowable tachometer count to the selects RPM mode. The fan will go to the selected
Fan_ Target TACH Count registers. Tachometer speed.
counts greater than this value will result in a fan fault Note: When the DAC rate-of-change is set to one of
detection. Choose a value that will not be encoun- the faster values, the fan drive voltage can, depend-
tered during normal operation, accounting for normal ing on the fan’s characteristics, undergo a slow oscil-
fan speed tolerances. lation. While this rarely has an audible impact, it can
Note: Setting a full-scale target count (2047) will be reduced or eliminated by selecting a slower rate-
result in the fan drive going to 0V. of-change once the fan’s speed has reached or
approached its target value.
• Set the TACH input enable bit in the Fan_
Configuration register to 1. Changing Speeds:
Note: This bit can be set after the fan has been start- • Write the desired tachometer count to the Fan_
ed, if desired. If the bit is set before writing a target Target TACH Count registers.
fan drive voltage, the target drive voltage should be Stopping the Fan:
set immediately after enabling the TACH input to • Write the current drive voltage into the Fan_ Target
avoid failure detection before the fan has started Drive Voltage register.
spinning.
• Write a value greater than the current tachometer
Starting the Fan: count into the Fan_ Target TACH Count register.
• Write the desired drive voltage value to the Fan_ • Write a 0 to bit 7 of the Fan_ Configuration register.
Target Drive Voltage register. This selects DAC mode.
Changing Speeds: • Write a 0 to the TACH input enable bit in the Fan_
• Write the new desired drive voltage value to the Fan_ Configuration register. This prevents the MAX6620
Target Drive Voltage register. from detecting a high TACH count and determining
Stopping the Fan: that the fan has failed.
• Write a 0 to the TACH input enable bit in the Fan_ • Write a voltage value of 0V to the Fan_ Target Drive
Configuration register. This prevents the MAX6620 Voltage register.
from deciding that the fan has failed after it has • If a gradual decrease in fan speed is desired, write
stopped. the lowest drive voltage at which the fan will reliably
• Write a voltage value of 0V to the Fan_ Target Drive operate. When the drive voltage reaches that value,
Voltage register. write 0 to the Fan_ Target Drive Voltage register.
• If a gradual decrease in fan speed is desired, write
the lowest drive voltage at which the fan will reliably

Maxim Integrated 27
MAX6620
Quad Linear Fan-Speed Controller

Typical Application Circuit

0.1µF
4.7kΩ
DACOUT1
VFAN

DACFB1

0.1µF
4.7kΩ
VCC VFAN
TACH1
0.1µF FAN1
0.1µF

FAN_FAIL 0.1µF
4.7kΩ
DACOUT2
VFAN

DACFB2

0.1µF
SDA 4.7kΩ
TACH2
FAN2
TO I2C MASTER
SCL

0.1µF
4.7kΩ
DACOUT3
VFAN
ADDR DAC OUTPUT
VCC I2C INTERFACE, DRIVER DACFB3
REGISTERS, AND
CONTROL LOGIC 0.1µF
TACH MONITOR
DAC_START 4.7kΩ
TACH3
FAN3

SPINUP_START

WD_START 0.1µF
4.7kΩ
DACOUT4
VFAN

X1 DACFB4

0.1µF
(OPTIONAL CRYSTAL) 4.7kΩ
X2 TACH4
FAN4

GND

28 Maxim Integrated
 MAX6620
Quad Linear Fan-Speed Controller

Chip Information Package Information

PROCESS: CMOS For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE PACKAGE LAND
OUTLINE NO.
TYPE CODE PATTERN NO.
28 TQFN T2855+8 21-0140 90-0028

Maxim Integrated 29
MAX6620
Quad Linear Fan-Speed Controller

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 3/08 Initial release —
Corrected Fan_ Dynamics register typos and hex values; added soldering
1 1/13 12, 18, 20, 21, 24, 29
temp; updated package info

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

30 ________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

© 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.