Andrew Calderon

November 15, 2009

Digital Logic

Project 2

1. Implement full adder with two 4X1 mulitplexer

xyz CS
0| 000 00 S(x,y,z)=€(1,2,4,7)
1| 001 01 C(x,y,z)= €(3,5,6,7)
2| 010 01
3| 011 10
4| 100 01
5| 101 10
6| 110 10
7| 111 11

S I0 I1 I2 I3
x1 0 1 2 3
x 4 5 6 7
-----------------------
x x’ x’ x

C I0 I1 I2 I3
x1 0 1 2 3
x 4 5 6 7
----------------------
0 x x’ x 1
2. F(A,B,C,) = ∑(0,2,5,7,11,14)

INPUT
X y z c s
0   0 0 0 0 0
1   0 0 1 1 0
2   0 1 0 1 0
3   0 1 1 0 0
4   1 0 0 1 0
5   1 0 1 0 0
6   1 1 0 0 1
7   1 1 1 1 1
8  
9  
10  
11  
12  
13  
14  
15  

3. F(A,B,C,D)=E(0,6,7,9,11,12,14,15)

INPUT
A B C D
0   0 0 1 0 0
1   0 0 1 1 0 F= 0
2   0 1 0 0 0
3   0 1 0 1 0 F=0
 4   0 1 1 0 1
5   0 1 1 1 1 F=1
6   0 1 1 0 1
7   0 1 1 1 1 F=1
8   1 0 0 0 0
9   1 0 0 1 1 F=D
10   1 0 1 0 0
11   1 0 1 1 1 F=D
12   1 1 0 0 1
13   1 1 0 1 0 F=d'
14   1 1 1 0 1
15   1 1 1 1 1 F=1

4. F1=y’z+xz---------------------- ∑ (1,5,7)

0,0 0,1 1,1 1,0

m0 m1 m3 m2
0,0 x'y'z' x'y'z 1 x'yz x'yz'
m4 m5 m7 m6
0,1 xy'z' xy'z 1 xyz 1 xyz'

F2= y’z’+xy’+xy’+yz’ ∑(0,2,4,5,6)

0,0 0,1 1,1 1,0

m0 m1 m3 m2
0,0 x'y'z' 1 x'y'z x'yz x'yz'1
m4 m5 m7 m6
0,1 xy'z' 1 xy'z 1 xyz xyz'1

0,0 0,1 1,1 1,0

m0 m1 m3 m2
0,0 x'y'z' x'y'z 1 x'yz x'yz'
m4 m5 m7 m6
0,1 xy'z' xy'z 1 xyz 1 xyz' 1

F3=x’z+yz-------()€(1,3,7)
 5. F(A,B,C,D)=∑(1,3,7)

0,0 0,1 1,1 1,0

m0 m1 m3 m2
0,0 a'b'c'd' 1 a'b'c'd 1 a'b'cd 1 a'b'cd'
m4 m5 m7 m6
0,1 a'bc'd' 1 a'bc'd a'bcd a'bcd'
m12 m13 m15 m14
1,1 abc'd' abc'd abcd 1 abcd'
m8 m9 m11 m10
1,0 ab'c'd' 1 ab'c'd 1 ab'cd ab'cd'

ABCD F

0 0000 1

1 0001 1 A F0 F1 F2 F3 F4 F5 F6 F7

2 0010 0 0 1 2 3 4 5 6 7

3 0011 1 A’ 8 9 10 11 12 13 14 15

4 0100 1 1 1 0 A’ A’ 0 0 A

5 0101 0

6 0110 0

7 0111 0
 8 1000 1

9 1001 1

10 1010 1

11 1011 0

12 1100 0

13 1101 0

14 1110 0

15 1111 1

6. Construct a 4 to 16 line decoder with five to 2 to 4 line decoders with enable.