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Assignment 3

This document contains 8 exercises on designing and analyzing bias-stable BJT amplifier circuits. Exercise 1 involves designing a circuit with 0V output voltage. Exercise 2 designs a circuit to meet specific current and resistance requirements. Exercise 3 involves percentage changes in collector current due to base current changes. The remaining exercises involve determining voltage gains, output resistances, and bias points for various common-emitter amplifier circuits. The deadline for this assignment is November 30th, 2022.

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74 views

Assignment 3

This document contains 8 exercises on designing and analyzing bias-stable BJT amplifier circuits. Exercise 1 involves designing a circuit with 0V output voltage. Exercise 2 designs a circuit to meet specific current and resistance requirements. Exercise 3 involves percentage changes in collector current due to base current changes. The remaining exercises involve determining voltage gains, output resistances, and bias points for various common-emitter amplifier circuits. The deadline for this assignment is November 30th, 2022.

Uploaded by

Bảo Đỗ Quốc
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ASSIGNMENT 3

Deadline: 30/11/2022

1
Exercise 1
• Consider the circuit:
• VBE (on) = 0.7V
• β = 150
• RE=2kΩ
• RC=10kΩ
• Design a bias-stable
circuit such that the
quiescent output
voltage is 0V.
• Find ICQ, VCEQ

2
Exercise 1 – Answer
• ICQ =0.5mA
• VCEQ =3.99V
• R1 = 167kΩ
• R2 = 36.9kΩ

3
Exercise 2
• For the circuit:
• β = 120, VBE (on) = 0.7V
• Design the circuit such that:
• ICQ = 0.15mA
• RTH = 200kΩ
• Find VCEQ
• Answer:
• IBQ = 1.25µA
• IEQ = 0.15125mA
• VCEQ = 1.30V

4
Exercise 3
• For the circuit:
a. Design a bias-table circuit such that:

b. Using the results of part (a)


if , determine
the percentage change in ICQ
c. Repeat parts (a) and (b),
if

5
Exercise 3 – Answer
a) c)

b)

6
Exercise 4
• For the circuit:

a. Plot the Q-point on the


DC load line
b. Determine the small-
signal voltage gain
c. Determine the range in
voltage gain if R1 and R2
vary by ±5%
7
Exercise 4 – Answer
a)

b)

c)

8
Exercise 5
• For the circuit:

• Determine R1 and R2 to
obtain a bias-stable circuit
with the Q-point in the
center of the load line.
• Determine the small-signal
voltage gain:

9
Exercise 5 – Answer
• R1＝20.1kΩ
• R2＝ 3.55kΩ
• Av = -5.75

10
Exercise 6
• Design the circuit such that it is bias stable and the
small-signal voltage gain is:
• Let:

11
Exercise 6 – Answer

12
Exercise 7
• For the circuit:

a. Determine the small-


signal voltage gain Av
b. Determine the output
resistance Ro

13
Exercise 7 – Answer
a)

b)

14
Exercise 8 12 V
• For the circuit:
• RE = 0.3 kΩ
• RC = 4kΩ
• R1 = 14.4kΩ
• R2 = 110kΩ
• RL = 10kΩ
• The transistor parameters:
• β = 100,
• VEB (on) = 0.7 V, and
• VA = ∞
a. Determine the quiescent values:
ICQ and VECQ
b. Fine the small-signal paramters:
gm, rπ and ro
c. Determine the small-signal voltage
gain

15
Exercise 8 – Answer
a)
• ICQ = 1.6 mA
• VECQ = 5.11 V
b)
• gm =61.54mA/V
• rπ =1.625kΩ
• ro =∞
c)
• Av = −8.95

16

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