Vending machine main code

module fsm(clock,reset,coin,vend,state,change);

input clock;

input reset;

input [2:0]coin;

output vend;

output [2:0]state;

output [2:0]change;

reg vend;

reg [2:0]change;

wire [2:0]coin;

parameter [2:0]NICKEL=3’b001;

parameter [2:0]DIME=3’b010;

parameter [2:0]NICKEL_DIME=3’b011;

parameter [2:0]DIME_DIME=3’b100;

parameter [2:0]QUARTER=3’b101;

parameter [2:0]IDLE=3’b000;

parameter [2:0]FIVE=3’b001;

parameter [2:0]TEN=3’b010;

parameter [2:0]FIFTEEN=3’b011;

parameter [2:0]TWENTY=3’b100;

parameter [2:0]TWENTYFIVE=3’b101;

reg [2:0]state,next_state;

always @(state or coin)

begin

next_state=0;
case(state)

IDLE: case(coin)

NICKEL: next_state=FIVE;

DIME: next_state=TEN;

QUARTER: next_state=TWENTYFIVE;

default: next_state=IDLE;

endcase

FIVE: case(coin)

NICKEL: next_state=TEN;

DIME: next_state=FIFTEEN;

QUARTER: next_state=TWENTYFIVE;

default: next_state=FIVE;

endcase

TEN: case(coin)

NICKEL: next_state=FIFTEEN;

DIME: next_state=TWENTY;

QUARTER: next_state=TWENTYFIVE;

default: next_state=TEN;

endcase

FIFTEEN: case(coin)

NICKEL: next_state=TWENTY;

DIME: next_state=TWENTYFIVE;

QUARTER: next_state=TWENTYFIVE;

default: next_state=FIFTEEN;

endcase

TWENTY: case(coin)

NICKEL: next_state=TWENTYFIVE;
DIME: next_state=TWENTYFIVE;

QUATER: next_state=TWENTYFIVE;

default: next_state=TWENTY;

endcase

TWENTYFIVE: next_state=IDLE;

default : next_state=IDLE;

endcase

end

always @(clock)

begin

if(reset) begin

state <= IDLE;

vend <= 1’b0;

end

else state <= next_state;

case (state)

endcase

end

endmodule

test bench

module test;

reg clock,reset;

reg [2:0]coin;

wire vend;
wire [2:0]state;

wire [2:0]change;

parameter [2:0]IDLE=3’b000;

parameter [2:0]FIVE=3’b001;

parameter [2:0]TEN=3’b010;

parameter [2:0]FIFTEEN=3’b011;

parameter [2:0]TWENTY=3’b100;

parameter [2:0]TWENTYFIVE=3’b101;

parameter [2:0]NICKEL=3’b001;

parameter [2:0]DIME=3’b010;

parameter [2:0]NICKEL_DIME=3’b011;

parameter [2:0]DIME_DIME=3’b100;

parameter [2:0]QUARTER=3’b101;

initial begin

$display("Time\tcoin\tdrink\treset\tclock\tstate\tchange"); $monitor("%g\t%b\t%b\t%b\t%b\t%d\t
%d",$time,coin,vend,reset,clock,state,change);

$dumpvars;

$dumpfile("file.vcd");

clock=0;

reset=1

#2 reset=0;

coin=NICKEL;

#2 reset=1;

coin=2’b00;

#2 reset=0;

coin=DIME;

#2 reset=1; coin=2’b00;

#2 reset=0;
coin=QUARTER;

#2 reset=1; coin=2’b00;

#2 reset=0;

coin=NICKEL;

#2 coin=NICKEL;

#2 coin=NICKEL;

#2 coin=NICKEL;

#2 coin=NICKEL;

#2 reset=1; coin=2’b00;

#2 reset=0;

#2coin=NICKEL;

#2 coin=DIME;

#2 coin=DIME;

#2 reset=1;

coin=2’b00;

#2 reset=0;

coin=NICKEL;

#2 coin=DIME;

#2 coin=QUARTER;

#2 reset=1; coin=2’b00;

#2 reset=0;

coin=NICKEL;

#2 coin=NICKEL;

#2 coin=NICKEL;

#2 coin=DIME;

#2 reset=1; coin=2’b00;

#2 reset=0;
coin=NICKEL;

#2 coin=NICKEL;

#2 coin=NICKEL;

#2 coin=NICKEL;

#2 coin=DIME;

#2 reset=1; coin=2’b00; #2 reset=0;

#2coin=NICKEL;

#2 coin=NICKEL;

#2 coin=QUARTER;

#2 reset=1; coin=2’b00;

#2 reset=0;

coin=NICKEL;

#2 coin=QUARTER;

#2 reset=1; coin=2’b00;

#2 $finish;

end

always

#1 clock=~clock;

initial begin

if (reset)
coin=2’b00;

end

fsm inst1(clock,reset,coin,vend,state,change);

endmodule

2.4 request fcfs arbiter

Main code

module FCFS_Arbiter (
 input wire clk,

input wire reset,

input wire [3:0] requests,

output wire [1:0] grant

);

reg [1:0] grant_reg;

reg [1:0] grant_next;

reg [3:0] requests_reg;

reg [3:0] requests_next;

reg [3:0] requests_done;

reg [3:0] burst_time;

reg [3:0] arrival_time;

reg [3:0] arrival_done;

reg [3:0] serving;

reg [3:0] serving_next;

reg [2:0] state;

reg [2:0] state_next;

parameter IDLE = 3'b000;

parameter SERVING = 3'b001;

parameter DONE = 3'b010;

always @(posedge clk or posedge reset) begin

if (reset) begin

grant_reg <= 2'b00;

requests_reg <= 4'b0000;

burst_time <= 4'b0000;

arrival_time <= 4'b0000;

arrival_done <= 4'b0000;

serving <= 4'b0000;

state <= IDLE;

end else begin

grant_reg <= grant_next;

requests_reg <= requests_next;

state <= state_next;

end

end

always @(state or requests_reg) begin

case (state)

IDLE:

if (requests_reg != 4'b0000) begin

state_next = SERVING;

serving_next = requests_reg;

end else begin

state_next = IDLE;

serving_next = 4'b0000;

end

SERVING:

if (arrival_done == requests_reg) begin

state_next = DONE;

serving_next = 4'b0000;
 end else begin

state_next = SERVING;

serving_next = serving;

end

DONE:

if (requests_done != 4'b0000) begin

state_next = SERVING;

serving_next = requests_done;

end else if (requests_reg != 4'b0000) begin

state_next = SERVING;

serving_next = requests_reg;

end else begin

state_next = IDLE;

serving_next = 4'b0000;

end

endcase

end

always @(posedge clk or posedge reset) begin

if (reset) begin

grant_next <= 2'b00;

requests_next <= 4'b0000;

end else begin

grant_next <= grant_reg;

requests_next <= requests_reg;

end
 if (state == IDLE) begin

if (requests != 4'b0000) begin

burst_time[requests] <= requests[requests];

arrival_time[requests] <= 4'b0000;

requests_done[requests] <= 4'b0001;

arrival_done[requests] <= 4'b0000;

end

end else if (state == SERVING) begin

if (burst_time[serving] == 4'b0000) begin

requests_done[serving] <= 4'b0000;

arrival_done[serving] <= 4'b0001;

end else begin

burst_time[serving] <= burst_time[serving] - 1;

arrival_time[serving] <= arrival_time[serving] + 1;

end

end else if (state == DONE) begin

requests_done[serving] <= 4'b0000;

arrival_done[serving] <= 4'b0001;

end

end

assign grant = grant_reg;

endmodule

testbench
 module fcfs_arbiter_tb;

// Parameters

parameter NUM_REQUESTS = 4;

// Inputs

reg clk;

reg [NUM_REQUESTS-1:0] request;

// Outputs

wire [NUM_REQUESTS-1:0] grant;

// Clock generation

always begin

#5 clk = ~clk;

end

// Test case

initial begin

// Initialize inputs

clk = 0;

request = 0;

// Wait for a few clock cycles

#10;
// Set request for the first two inputs

request[0] = 1;

request[1] = 1;

// Wait for a few clock cycles

#10;

// Set request for the remaining inputs

request[2] = 1;

request[3] = 1;

// Wait for a few clock cycles

#10;

// Reset request for the first input

request[0] = 0;

// Wait for a few clock cycles

#10;

// Reset request for the second input

request[1] = 0;

// Wait for a few clock cycles

#10;

// Reset request for the third input

// Wait for a few clock cycles

#10;

// Reset request for the fourth input

request[3] = 0;

$display("Request: %b, Grant: %b", request, grant);

end

endmodule