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Mid 1 Question Paper Introduction To VLSI

The document is an exam for a course on Introduction to VLSI Design. It contains 5 questions testing knowledge of Verilog, digital logic design, and programmable logic devices. Question topics include modules, data types, logic expressions in Verilog, blocking vs non-blocking statements, CAD flowcharts, multiplexers, counters, finite state machines, delays, adders, and ROM architectures.

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gowri thumbur
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115 views1 page

Mid 1 Question Paper Introduction To VLSI

The document is an exam for a course on Introduction to VLSI Design. It contains 5 questions testing knowledge of Verilog, digital logic design, and programmable logic devices. Question topics include modules, data types, logic expressions in Verilog, blocking vs non-blocking statements, CAD flowcharts, multiplexers, counters, finite state machines, delays, adders, and ROM architectures.

Uploaded by

gowri thumbur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Department of Electrical Electronics and Communication Engineer-

ing

GITAM SCHOOL OF TECHNOLOGY


GANDHI INSTITUTE OF TECHNOLOGY AND MANAGEMENT (GITAM)
(Declared as Deemed to be University u/s 3 of UGC Act, 1956), Visakhapatnam

III/IV B.Tech VI Semester MID-I Examination 2022-2023


BRANCH: EECE
19EEC334: Introduction to VLSI Design Maximum Marks: 30
DATE:10-01-2023 Time:2.30-4.00AM
Answer ALL Questions

1 (a) What is Module. 2M


.
(b) Write different types of data types? 2M
(c) Write Verilog code for F= A’B+BCD+C’A . 2M
(d) Difference between Blocking and Non-blocking statements. 2M
(e) Draw the flow chart diagram of Computer Aided Design. 2M

2 Explain about Verilog assignments and procedural assignments. Write Verilog code for 8 by 1 10M
. multiplexer?
[This question relates to Course Outcome 1: Describes the design flow of integrated circuits using
hardware description languages]

(OR)
3 Describe counters and finite state machines using Verilog always statements with examples. 10M
. [This question relates to Course Outcome 1: Describes the design flow of integrated circuits using
hardware description languages]

4 Discuss briefly about delays in Verilog model. Design verilog module for 4-bit adder. 10M
.
[This question relates to Course Outcome 1: Describes the design flow of integrated circuits using
hardware description languages]

(OR)

5 Describe the operation of ROM architectures with two examples? Differentiate between SPLD, 10M
. FPGA and CPLD.
[This question relates to Course Outcome 2: Describes the architecture and usage of different types
of programmable logic devices]

Please access the solutions and scheme on Moodle’s from 011-01-2023

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