Timer_A

This is the most versatile, general-purpose timer in the MSP430 and is

included in all devices. General features same as general-purpose timer in
any other modern microcontroller.
There are two main parts to the hardware:
Timer block: The core, based on the 16-bit register TAR(timer_a reg).
There is a choice of sources for the clock, whose frequency can be divided
down (prescaled). The timer block has no output but a flag TAIFG(t_a
interrupt flag) is raised when the counter returns to 0.
Capture/compare channels: In which most events occur, each of which is
based on a register TACCRn. They all work in the same way with the
important exception of TACCR0. Each channel can
• Capture an input, which means recording the “time” (the value in TAR)
at which the input changes in TACCRn; the input can be either external or
internal from another peripheral or software.
• Compare the current value of TAR with the value stored in TACCRn and
update an output when they match; the output can again be either external
or internal.
• Request an interrupt by setting its flag TACCRn CCIFG on either of
these events; this can be done even if no output signal is produced.
• Sample an input at a compare event; this special feature is particularly
useful if Timer_A is used for serial communication in a device that lacks a
dedicated interface.
Timer_A is modular and the number of capture/compare channels varies
between devices. Most have three channels but the smallest members of
the MSP430F2xx family have only two and some earlier devices had
more.
Capture/compare channel 0 is special in two ways. Its register TACCR0 is
taken over for the modulus value in Up and Up/Down modes, so that it is
no longer available for its usual functions. It also has its own interrupt
vector with a higher priority than the other interrupts from Timer_A, which
all share a common vector. Therefore channel 0 is chosen for the most
urgent tasks if it is free.
It is important to realize that all channels within Timer_A share the same
timer block: There is only one TAR. This ensures that actions performed
by the different channels are precisely synchronized. The drawback is that
they all work at the same fundamental frequency.
Timer Block
This contains the 16-bit timer register TAR, which is central to the
operation of the timer. It is controlled by the register TACTL.
Frequency of the clock for the timer can be chosen from four sources by
using the TASSELx bits:
• SMCLK is internal and usually fast (megahertz).
• ACLK is internal and usually slow, typically 32 KHz from a watch
crystal but may be taken from the VLO in the MSP430F2xx family.
• TACLK is external.
• INCLK is also external, sometimes a separate pin but often it is
connected through an inverter to the pin for TACLK so that INCLK =
TACLK.
TAR increments on the rising (positive) edge of the clock. The
arrangement INCLK = TACLK in many devices allows TAR to be clocked
on the falling (negative) edge of the external clock if required.

The frequency of the incoming clock can be divided down by 2, 4, or 8 if

desired by configuring the IDx bits.
The period of the timer can range from 4 ms with the fastest SMCLK to
16s with a 32 KHz ACLK and maximum division (even longer with the 12
KHz VLO).

The timer has four modes of operation, selected with the MCx bits:
Stop (MC = 0): The timer is halted. All registers, including TAR, retain
their values so that the timer can be restarted later where it left off.
Continuous (2): The counter runs freely through its full range from 0x0000
to 0xFFFF, at which point it overflows and rolls over back to 0. The period
is 2 ^6 = 65,536 counts. This mode is most convenient for capturing inputs
and is also used when channels provide outputs with different frequencies
or that are not periodic at all.
Up (1): The counter counts from 0 up to the value in TACCR0, the
capture/compare register for channel 0. It returns to 0 on the next clock
transition. The period is (TACCR0 + 1) counts.Up mode is usually used
when all channels provide outputs at the same frequency, often for pulse-
width modulation.
Up/Down (3): The counter counts from 0 up to TACCR0, then down again
to 0 and repeats. The period is 2 × TACCR0 counts. This is a specialized
mode, typically used for centered pulse-width modulation.
The count in TAR and the divider can be cleared by writing a 1 to the
TACLR bit in TACTL. The TACLR bit automatically clears itself after use.
The flag TAIFG in TACTL is set when the timer counts to 0 and a
maskable interrupt is requested if the TAIE bit is set.
Often timer clock is not synchronous with the CPU clock, such as when
the timer is supplied from ACLK. In this case it is best to stop the timer
before reading the value of TAR.

Timer channel is controlled by a register TACCTLn,

Bit-8:(CAP) if 0---compare mode(default)
if 1---capture mode
In Capture mode this stores the “time”—the value in TAR—at which an
event occurs on the input; in Compare mode it specifies the time at which
the output should next be changed and an interrupt requested.

An event can be a rising edge, falling edge, or either edge on the input
according to the capture mode bits CMx. The CCISx bits in TACCTLn
select the input to be captured.

The state of the selected input can always be read in the CCI bit of
TACCTLn. The capture hardware includes a synchronizer, which is
enabled by setting the SCS bit.

Bit-4:(CCIE) if 0---interrupt disabled

if 1---interrupt enabled
Bit-0:(CCIFG) if 0---no interrupt pending
if 1---interrupt pending(maskable)

The capture overflow bit COV is set if another capture occurs before
TACCRn has been read following the previous event.

The purpose of Compare mode is to produce an output and interrupt at the

time stored in TACCRn. Several actions are triggered when TAR counts to
the value in TACCRn:
• The internal signal EQUn is set.
• This in turn raises the CCIFGn flag and requests an interrupt if enabled.
• The output signal OUTn is changed according to the mode set by the
OUTMODx bits in TACCTLn.
Interrupts can be generated by the timer block itself (flag TAIFG) and each
capture/compare channel (flag TACCRn CCIFG or CCIFGn for short).
TACCR0 is privileged and has its own interrupt vector,
TIMERA0_VECTOR. Its priority is higher than the other vector,
TIMERA1_VECTOR, which is shared by the remaining capture/compare
channels and the timer block. The CCIFG0 flag is cleared automatically
when its interrupt is serviced but this does not happen for the other
interrupts because the interrupt service routine (ISR) must first determine
the source of the interrupt.