E85

Digital Electronics & Computer Architecture

Lecture 16:
RISC-V Assembly Language
Lecture 16

• Introduction
– Instruction Set Architecture (ISA)
– RISC-V History
• RISC-V Assembly Language
– Instructions
– Register Set
– Memory
– Programming constructs

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Lecture 16

• Introduction
– Instruction Set Architecture (ISA)
– RISC-V History
• RISC-V Assembly Language
– Instructions
– Register Set
– Memory
– Programming constructs

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Introduction
• Jumping up a few levels of
abstraction
• Architecture: programmer’s
view of computer
• Defined by instructions &
operand locations
• Microarchitecture: how to
implement an architecture
in hardware (covered in
Chapter 7)

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Assembly Language
• Instructions: commands in a computer’s language
• Assembly language: human-readable format of
instructions
• Machine language: computer-readable format (1’s
and 0’s)
• RISC-V architecture:
• Developed by Krste Asanovic, David Patterson and
their colleagues at UC Berkeley in 2010.
• First open-source computer architecture

Once you’ve learned one architecture, it’s easier to learn others

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 Instruction Set Architecture Manual
• RISC-V ISA Manual available at:
https://riscv.org/specifications/
isa-spec-pdf/
• Details base integer ISA along
with optional extensions
• Gives not only the specs but
also some helpful rationale and
reasoning behind the decisions

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Krste Asanovic
• Professor of Computer Science at
the University of California,
Berkeley
• Developed RISC-V during one
summer
• Chairman of the Board of the
RISC-V Foundation
• Co-Founder of SiFive, a company
that commercializes and
develops supporting tools for
RISC-V

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David Patterson
• Professor of Computer Science at
the University of California,
Berkeley since 1976
• Coinvented the Reduced
Instruction Set Computer (RISC)
with John Hennessy in the 1980’s
• Developed the RISC architecture
at Berkeley in 1984, which was
later commercialized as SPARC
architecture

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Architecture Design Principles
Underlying design principles, as articulated by
Hennessy and Patterson:
1.Simplicity favors regularity
2.Make the common case fast
3.Smaller is faster
4.Good design demands good compromises

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Lecture 16

• Introduction
– Instruction Set Architecture (ISA)
– RISC-V History
• RISC-V Assembly Language
– Instructions
– Register Set
– Memory
– Programming constructs

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Instructions: Addition

C Code RISC-V assembly code

a = b + c; add a, b, c

• add: mnemonic indicates operation to perform

• b, c: source operands (on which the operation is performed)
• a: destination operand (to which the result is written)

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Instructions: Subtraction
Similar to addition - only mnemonic changes

C Code RISC-V assembly code

a = b - c; sub a, b, c

• sub: mnemonic
• b, c: source operands
• a: destination operand

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Design Principle 1
Simplicity favors regularity
• Consistent instruction format
• Same number of operands (two sources and one
destination)
• Easier to encode and handle in hardware

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Multiple Instructions
More complex code is handled by multiple
RISC-V instructions.
C Code RISC-V assembly code
a = b + c - d; add t, b, c # t = b + c
sub a, t, d # a = t - d

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Design Principle 2
Make the common case fast
• RISC-V includes only simple, commonly used instructions
• Hardware to decode and execute instructions can be
simple, small, and fast
• More complex instructions (that are less common)
performed using multiple simple instructions
• RISC-V is a reduced instruction set computer (RISC), with
a small number of simple instructions
• Other architectures, such as Intel’s x86, are complex
instruction set computers (CISC)

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Operands
• Operand location: physical location in
computer
– Registers
– Memory
– Constants (also called immediates)

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Operands: Registers
• RISC-V has 32 32-bit registers
• Registers are faster than memory
• RISC-V called “32-bit architecture”
because it operates on 32-bit data

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Design Principle 3
Smaller is Faster
• RISC-V includes only a small number of registers

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RISC-V Register Set
Name Register Number Usage
zero x0 Constant value 0
ra x1 Return address
sp x2 Stack pointer
gp x3 Global pointer
tp x4 Thread pointer
t0-2 x5-7 Temporaries
s0/fp x8 Saved register / Frame pointer
s1 x9 Saved register
a0-1 x10-11 Function arguments / return values
a2-7 x12-17 Function arguments
s2-11 x18-27 Saved registers
t3-6 x28-31 Temporaries
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Operands: Registers
• Registers:
– Can use either name (i.e., ra, zero) or x0, x1, etc.
– Using name is preferred
• Registers used for specific purposes:
• zero always holds the constant value 0.
• the saved registers, s0-s11, used to hold
variables
• the temporary registers, t0-t6, used to hold
intermediate values during a larger
computation
• Discuss others later

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Instructions with Registers
• Revisit add instruction

C Code RISC-V assembly code

# s0 = a, s1 = b, s2 = c
a = b + c add s0, s1, s2

# indicates a single-line comment

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Operands: Memory
• Too much data to fit in only 32 registers
• Store more data in memory
• Memory is large, but slow
• Commonly used variables kept in registers

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Memory
• First, we’ll discuss word-addressable
memory
• Then we’ll discuss byte-addressable
memory

RISC-V is byte-addressable

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Word-Addressable Memory
• Each 32-bit data word has a unique
address
Word Address Data

00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

Note: RISC-V uses byte-addressable memory, which we’ll talk about next.
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Reading Word-Addressable Memory
• Memory read called load
• Mnemonic: load word (lw)
• Format:
lw <rd>, <offset>(<base register>)
lw t1, 5(s0)
Address calculation:
– add offset (5) to the base address (s0)
– address = (s0 + 5)
• Destination register (rd):
– t1 holds the value at address (s0 + 5)
Any register may be used as base address
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Reading Word-Addressable Memory
• Example: read a word of data at memory
address 1 into s3
– address = (0 + 1) = 1
– s3 = 0xF2F1AC07 after load
Assembly code
lw s3, 1(zero) # read memory word 1 into s3

Word Address Data

00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

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Writing Word-Addressable Memory

• Memory write are called store

• Mnemonic: store word (sw)
• Format similar to load
sw <src1>, <offset>(<base register>)

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Writing Word-Addressable Memory
• Example: Write (store) the value in t4 into
memory address 7
– add the base address (zero) to the offset (0x7)
– address: (0 + 0x7) = 7
Offset can be written in decimal (default) or hexadecimal
Assembly code
sw t4, 0x7(zero) # write the value in t4
# to memory word 7
Word Address Data

00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

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Byte-Addressable Memory
• Each data byte has unique address
• Load/store words or single bytes: load byte (lb) and
store byte (sb)
• 32-bit word = 4 bytes, so word address increments by 4

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes
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Reading Byte-Addressable Memory

• The address of a memory word must now

be multiplied by 4. For example,
– the address of memory word 2 is 2 × 4 = 8
– the address of memory word 10 is 10 × 4 = 40
(0x28)
• RISC-V is byte-addressed, not word-
addressed

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Reading Byte-Addressable Memory

• Example: Load a word of data at memory

address 4 into s3.
• s3 holds the value 0xF2F1AC07 after load
RISC-V assembly code
lw s3, 4(zero) # read word at address 4 into s3

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes

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Writing Byte-Addressable Memory

• Example: stores the value held in t7 into

memory address 0x2C (44)
RISC-V assembly code
sw t7, 44(zero) # write t7 into address 44

Word Address Data

0000000C 4 0 F 3 0 7 8 8 Word 3
00000008 0 1 E E 2 8 4 2 Word 2
00000004 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0

width = 4 bytes

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Big-Endian & Little-Endian Memory
• How to number bytes within a word?
• Little-endian: byte numbers start at the little (least
significant) end
• Big-endian: byte numbers start at the big (most
significant) end
• Word address is the same for big- or little-endian
Big-Endian Little-Endian
Byte Word Byte
Address Address Address

C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
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Big-Endian & Little-Endian Memory
• Jonathan Swift’s Gulliver’s Travels: the Little-Endians
broke their eggs on the little end of the egg and the Big-
Endians broke their eggs on the big end
• It doesn’t really matter which addressing type used –
except when the two systems need to share data!
Big-Endian Little-Endian
Byte Word Byte
Address Address Address

C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB

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Big-Endian & Little-Endian Example
• Suppose t0 initially contains 0x23456789
• After following code runs on big-endian system, what
value is s0?
• In a little-endian system?
sw t0, 0(zero)
lb s0, 1(zero)

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Big-Endian & Little-Endian Example
• Suppose t0 initially contains 0x23456789
• After following code runs on big-endian system, what
value is s0?
• In a little-endian system?
sw t0, 0(zero)
lb s0, 1(zero)
• Big-endian: s0 = 0x00000045
• Little-endian: s0 = 0x00000067

Big-Endian Little-Endian
Word
Byte Address 0 1 2 3 Address 3 2 1 0 Byte Address
Data Value 23 45 67 89 0 23 45 67 89 Data Value
MSB LSB MSB LSB
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Programming
• High-level languages:
– e.g., C, Java, Python
– Written at higher level of abstraction
• Common high-level software constructs:
– if/else statements
– for loops
– while loops
– arrays
– function calls

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Ada Lovelace, 1815-1852

• Wrote the first computer

program
• Her program calculated
the Bernoulli numbers
on Charles Babbage’s
Analytical Engine
• She was the daughter of
the poet Lord Byron

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Branching
• Execute instructions out of sequence
• Types of branches:
• Conditional
• branch if equal (beq)
• branch if not equal (bne)
• branch if less than (blt/bltu)
• branch if greater than or equal to (bge/bgeu)
• Unconditional
• jump (j)
• jump register (jr) Will talk about these
• jump and link (jal) when we discuss
• jump and link register (jalr) function calls

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Conditional Branching (beq)
# RISC-V assembly
addi s0, zero, 4 # s0 = 0 + 4 = 4
addi s1, zero, 1 # s1 = 0 + 1 = 1
slli s1, s1, 2 # s1 = 1 << 2 = 4
beq s0, s1, target # branch is taken
addi s1, s1, 1 # not executed
sub s1, s1, s0 # not executed

target: # label
add s1, s1, s0 # s1 = 4 + 4 = 8
Labels indicate instruction location. They can’t be reserved words and
must be followed by colon (:)

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The Branch Not Taken (bne)
# RISC-V assembly
addi s0, zero, 4 # s0 = 0 + 4 = 4
addi s1, zero, 1 # s1 = 0 + 1 = 1
slli s1, s1, 2 # s1 = 1 << 2 = 4
bne s0, s1, target # branch not taken
addi s1, s1, 1 # s1 = 4 + 1 = 5
sub s1, s1, s0 # s1 = 5 – 4 = 1

target:
add s1, s1, s0 # s1 = 1 + 4 = 5

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 Other Conditional Branches
• Branch if less than (blt/bltu)

blt s0, s1, target # branches if s0 < s1 (signed)

bltu s0, s1, target # same as blt but interprets
# s0 and s1 as unsigned

• Branch if less than (bge/bgeu)

bge s0, s1, target # branches if s0 > s1 (signed)

bgeu s0, s1, target # branches if s0 > s1 (unsigned)

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Unconditional Branching (j)
# RISC-V assembly

j target # jump to target

srai s1, s1, 2 # not executed
addi s1, s1, 1 # not executed
sub s1, s1, s0 # not executed

target:
add s1, s1, s0 # s1 = 1 + 4 = 5

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Programming
• High-level constructs: loops, conditional
statements
• First, introduce:
• Logical operations
• Shifty instructions
• Generating constants
• Multiplication

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Logical Instructions
• and, or, xor
– and: useful for masking bits
• Masking all but the least significant byte of a value:
0xF234012F AND 0x000000FF = 0x0000002F
– or: useful for combining bit fields
• Combine 0xF2340000 with 0x000012BC:
0xF2340000 OR 0x000012BC = 0xF23412BC
– xor: useful for inverting bits:
• A xor -1 = NOT A (remember that -1 = 0xFFFFFFFF)

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Logical Instructions Example 1
Source Registers
s1 0100 0110 1010 0001 1111 0001 1011 0111
s2 1111 1111 1111 1111 0000 0000 0000 0000

Assembly Code Result

and s3, s1, s2 s3 0100 0110 1010 0001 0000 0000 0000 0000
or s4, s1, s2 s4 1111 1111 1111 1111 1111 0001 1011 0111
xor s5, s1, s2 s5 1011 1001 0101 1110 1111 0001 1011 0111

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 Logical Instructions Example 2
Source Values
t3 0011 1010 0111 0101 0000 1101 0110 1111

imm 1111 1111 1111 1111 1111 1010 0011 0100

sign-extended

Assembly Code Result

andi s5, t3, -1484 s5
ori s6, t3, -1484 s6
xori s7, t3, -1484 s7

-1484 = 0xA34 in 12-bit 2’s complement representation.

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Shift Instructions
Shift amount is in (lowest 5 bits of) a register
• sll: shift left logical
– Example: sll t0, t1, t2 # t0 = t1 << t2
• srl: shift right logical
– Example: srl t0, t1, t2 # t0 = t1 >> t2
• sra: shift right arithmetic
– Example: sra t0, t1, t2 # t0 = t1 >>> t2

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Immediate Shift Instructions
Shift amount is an immediate between 0 to 31
• slli: shift left logical immediate
– Example: slli t0, t1, 23 # t0 = t1 << 23
• srli: shift right logical immediate
– Example: srli t0, t1, 18 # t0 = t1 >> 18
• srai: shift right arithmetic imeediate
– Example: srai t0, t1, 5 # t0 = t1 >>> 5

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Generating Constants
• 12-bit signed constants using addi:
C Code RISC-V assembly code
// int is a 32-bit signed word # s0 = a
int a = -372; addi s0, 0, -372

Any immediate that needs more than 12 bits

cannot use this method.

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Generating 32-bit Constants
• Use load upper immediate (lui) and addi:
• lui: puts an immediate in the upper 20 bits
of destination register, 0’s in lower 12 bits
C Code RISC-V assembly code
# s0 = a
int a = 0xFEDC8765; lui s0, 0xFEDC8
addi s0, s0, 0x765

Remember that addi sign-extends its 12-bit

immediate

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Generating 32-bit Constants
• If bit 11 of 32-bit constant is 1, increment
upper 20 bits by 1 in lui
C Code
int a = 0xFEDC8EAB; Note: 0xEAB = -341

RISC-V assembly code

# s0 = a
lui s0, 0xFEDC9 # s0 = 0xFEDC9000
addi s0, s0, -341 # s0 = 0xFEDC9000 + 0xFFFFFEAB
# = 0xFEDC8EAB

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Multiplication
• 32 × 32 multiplication, 64-bit result
mul s0, s1, s2
s0 = lower 32 bits of result
mulh s0, s1, s2
s0 = upper 32 bits of result, treats operands as signed
mulhu s0, s1, s2
s0 = upper 32 bits of result, treats operands as
unsigned
mulhsu s0, s1, s2
s0 = upper 32 bits of result, treats s1 as signed, s3
as unsigned

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Multiplication
• 32 × 32 multiplication, 64-bit result
• For full 64-bit result:
mulh s4, s1, s2
mul s3, s1, s2

{s4, s3} = s1 x s2

• Could also use mulhu or mulhsu instead

of mulh

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Division
• 32-bit division, 32-bit quotient, remainder
– div s1, s2, s3 # s1 = s2/s3
– divu s1, s2, s3 # unsigned division

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High-Level Code Constructs
• if statements
• if/else statements
• while loops
• for loops

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If Statement

C Code RISC-V assembly code

# s0 = f, s1 = g, s2 = h
# s3 = i, s4 = j
if (i == j) bne s3, s4, L1
f = g + h; add s0, s1, s2

L1:
f = f – i; sub s0, s0, s3

Assembly tests opposite case (i != j) of high-level code (i == j)

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If/Else Statement

C Code RISC-V assembly code

# s0 = f, s1 = g, s2 = h
# s3 = i, s4 = j
if (i == j) bne s3, s4, L1
f = g + h; add s0, s1, s2
j done

else L1:
f = f – i; sub s0, s0, s3
done:

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While Loops

C Code RISC-V assembly code

// determines the power # s0 = pow, s1 = x
// of x such that 2x = 128
int pow = 1; addi s0, zero, 1
int x = 0; add s1, zero, zero
addi t0, zero, 128
while (pow != 128) { while:
pow = pow * 2; beq s0, t0, done
x = x + 1; slli s0, s0, 1
} addi s1, s1, 1
j while
done:

Assembly tests for the opposite case (pow == 128) of the C

code (pow != 128).

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For Loops
for (initialization; condition; loop operation)
statement

• initialization: executes before the loop begins

• condition: is tested at the beginning of each iteration
• loop operation: executes at the end of each iteration
• statement: executes each time the condition is met

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For Loops

C Code RISC-V assembly code

// add the numbers from 0 to 9 # s0 = i, s1 = sum
int sum = 0; addi s1, zero, 0
int i; add s0, zero, zero
addi t0, zero, 10
for (i=0; i!=10; i = i+1) { for:
sum = sum + i; beq s0, t0, done
} add s1, s1, s0
addi s0, s0, 1
j for
done:

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Less Than Comparison

C Code RISC-V assembly code

// add the powers of 2 from 1 # s0 = i, s1 = sum
// to 100 addi s1, zero, 0
int sum = 0; addi s0, zero, 1
int i; addi t0, zero, 101
loop:
for (i=1; i < 101; i = i*2) { bge s0, t0, done
sum = sum + i; add s1, s1, s0
} slli s0, s0, 1
j loop
done:

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Arrays
• Access large amounts of similar data
• Index: access each element
• SizeI number of elements

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Arrays
• 5-element array
• Base address = 0x12348000 (address of first element,
array[0])
• First step in accessing an array: load base address into a
register

0x12340010 array[4]
0x1234800C array[3]
0x12348008 array[2]
0x12348004 array[1]
0x12348000 array[0]

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Accessing Arrays
// C Code
int array[5];
array[0] = array[0] * 2;
array[1] = array[1] * 2;

# RISC-V assembly code

# s0 = array base address
lui s0, 0x12348 # 0x12348 in upper 20 bits of s0

lw t1, 0(s0) # t1 = array[0]

slli t1, t1, 1 # t1 = t1 * 2
sw t1, 0(s0) # array[0] = t1

lw t1, 4(s0) # t1 = array[1]

slli t1, t1, 1 # t1 = t1 * 2
sw t1, 4(s0) # array[1] = t1

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Arrays Using For Loops
// C Code
int array[1000];
int i;

for (i=0; i < 1000; i = i + 1)

array[i] = array[i] * 8;

# RISC-V assembly code

# s0 = array base address, s1 = i

Digital Design and Computer Architecture: RISC-V Edition

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Arrays Using For Loops
# RISC-V assembly code
# s0 = array base address, s1 = i
# initialization code
lui s0, 0x23B8F # s0 = 0x23B8F000
ori s0, s0, 0x400 # s0 = 0x23B8F400
addi s1, zero, 0 # i = 0
addi t2, zero, 1000 # t2 = 1000

loop:
bge s1, t2, done # if not then done
slli t0, s1, 2 # t0 = i * 4 (byte offset)
add t0, t0, s0 # address of array[i]
lw t1, 0(t0) # t1 = array[i]
slli t1, t1, 3 # t1 = array[i] * 8
sw t1, 0(t0) # array[i] = array[i] * 8
addi s1, s1, 1 # i = i + 1
j loop # repeat
done:

Digital Design and Computer Architecture: RISC-V Edition

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ASCII Code
• American Standard Code for Information
Interchange
• Each text character has unique byte
value
• For example, S = 0x53, a = 0x61, A = 0x41
• Lower-case and upper-case differ by 0x20 (32)

Digital Design and Computer Architecture: RISC-V Edition

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Cast of Characters

Digital Design and Computer Architecture: RISC-V Edition

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Unconditional Branching (jr)
# RISC-V assembly
0x00000200 addi s0, zero, 0x210
0x00000204 jr s0
0x00000208 addi s1, zero, 1 # not executed
0x0000020C sra s1, s1, 2 # not executed
0x00000210 lw s3, 44(s1)

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Lecture 16

• Introduction
– Instruction Set Architecture (ISA)
– RISC-V History
• RISC-V Assembly Language
– Instructions
– Register Set
– Memory
– Programming constructs

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