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Realization of Other Gates Using Universal Gates

The document discusses the realization of common logic gates using only NAND or NOR universal gates. It shows that: 1) A NOT gate can be realized from a single input NAND/NOR gate. An AND gate and OR gate can each be realized from two input NAND/NOR gates. 2) The NOR gate can similarly realize the NOT, AND, OR, and XNOR gates. The NAND gate can realize the NOT, AND, OR, and XOR gates. 3) Two examples are provided to demonstrate realizing multiple gates using only NAND or NOR gates according to the given truth tables.

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Anup Jalota
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67 views8 pages

Realization of Other Gates Using Universal Gates

The document discusses the realization of common logic gates using only NAND or NOR universal gates. It shows that: 1) A NOT gate can be realized from a single input NAND/NOR gate. An AND gate and OR gate can each be realized from two input NAND/NOR gates. 2) The NOR gate can similarly realize the NOT, AND, OR, and XNOR gates. The NAND gate can realize the NOT, AND, OR, and XOR gates. 3) Two examples are provided to demonstrate realizing multiple gates using only NAND or NOR gates according to the given truth tables.

Uploaded by

Anup Jalota
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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REALIZATION OF OTHER

GATES USING UNIVERSAL


GATES
For: CSE, II Sem

By: Tarannum Parvin


REALIZATION OF OTHER GATES USING UNIVERSAL GATES
I. Implementation using NAND gate:

(a) NOT gate: Y = A’ (c) OR gate:


A B Y
A Y 0 0 0
0 1 0 1 1
1 0 1 0 1
1 1 1

(b) AND gate: (d) NOR gate:

A B Y A B Y
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 0
REALIZATION OF OTHER GATES USING UNIVERSAL GATES
I. Implementation using NAND gate:

(e) EX-OR gate: A B Y


0 0 0
0 1 1
1 0 1
1 1 0

2. Implementation using NOR gate:


(b) AND gate: (a) NOT gate: Y = A’

A B Y
A Y
0 0 0
0 1
0 1 0
1 0
1 0 0
1 1 1
REALIZATION OF OTHER GATES USING UNIVERSAL GATES
2. Implementation using NOR gate:

(c) OR gate: (e) XNOR gate:


A B Y
0 0 0
0 1 1
1 0 1
1 1 1

(d) NAND gate:

A B Y 0 0 1
0 0 1 0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
EXAMPLE 1
EXAMPLE 2

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