Sec. 5.6. High-IP2 LNAs 313 314 Chap. 5.

Low-Noise Amplifiers

VDD VDD VDD Band

Band Select
Switch
L1 C1 R1 L1 C1 R1 Band 1 Band 2
MX 1
S1
Vout Vout
VDD VDD
C2 C2 M1 M2
Ma Ma

C GD1 MX 2
Band
C DB1
Switch S1 Band
Y Select
(a) (b)

Figure 5.63 (a) Band switching, (b) effect of switch parasitics. V in CS or CG

Stage

The choice of the width of S1 in Fig. 5.63(b) proves critical. For a very narrow transis-
tor, the on-resistance, Ron1 , remains so high that the tank does not “feel” the presence of Figure 5.64 Band switching by programmable cascode branches.
C2 when S1 is on. For a moderate device width, Ron1 limits the Q of C2 , thereby lowering
the Q of the overall tank and hence the voltage gain of the LNA. This can be readily seen
by transforming the series combination of C2 and Ron1 to a parallel network consisting of mixers as the IP2 bottleneck of the receivers. In this section, we study techniques of raising
C2 and RP1 ≈ Q2 Ron1 , where Q 5 (C2 ωRon1 )21 . That is, R1 is now shunted by a resistance the IP2 of LNAs, and in Chapter 6, we do the same for mixers.
RP1 5 (C22 ω2 Ron1 )21 .
The foregoing observation implies that Ron1 must be minimized such that RP1
R1 .
However, as the width of S1 in Fig. 5.63(b) increases, so does the capacitance that it intro- 5.6.1 Differential LNAs
duces in the off state. The equivalent capacitance seen by the tank when S1 is off is equal
to the series combination of C2 and CGD1 1 CDB1 , which means C1 must be less than its Differential LNAs can achieve high IP2 ’s because, as explained in Chapter 2, symmetric
original value by this amount. We therefore conclude that the width of S1 poses a trade-off circuits produce no even-order distortion. Of course, some (random) asymmetry plagues
between the tolerable value of C1 when S1 is off and the reduction of the gain when S1 is actual circuits, resulting in a finite, but still high, IP2 .
on. (Recall that C1 arises from Ma , the input capacitance of the next stage, and the parasitic In principle, any of the single-ended LNAs studied thus far can be converted to differ-
capacitance of L1 .) ential form. Figure 5.65 depicts two examples. Not shown here, the bias network for the
An alternative method of band switching incorporates two or more tanks as shown in input transistors is similar to those described in Sections 5.3.3 and 5.3.4.
Fig. 5.64 [8]. To select one band, the corresponding cascode transistor is turned on while
the other remains off. This scheme requires that each tank drive a copy of the following VDD VDD
stage, e.g., a mixer. Thus, when M1 and band 1 are activated, so is mixer MX1 . The prin-
cipal drawback of this approach is the capacitance contributed by the additional cascode L1 L1 L1 L1
device(s) to node Y. Also, the spiral inductors have large footprints, making the layout and Vout Vout
routing more difficult.

Vb
V in
5.6 HIGH-IP2 LNAS V in
LB LB
As explained in Chapter 4, even-order distortion can significantly degrade the performance LB LB
of direct-conversion receivers. Since the circuits following the downconversion mixers are
typically realized in differential form,18 they exhibit a high IP2 , leaving the LNA and the
(a) (b)

18. And since they employ large devices and hence have small mismatches. Figure 5.65 Differential (a) CG and (b) CS stages.
Sec. 5.6. High-IP2 LNAs 315 316 Chap. 5. Low-Noise Amplifiers

But what happens to the noise figure of the circuit if it is converted to differential we can compute the output noise of each half circuit as in Fig. 5.67(c) and add the output
form? Before answering this question, we must determine the source impedance driving powers:
the LNA. Since the antenna and the preselect filter are typically single-ended, a transformer
must precede the LNA to perform single-ended to differential conversion. Illustrated in 2
Vn,out 5 Vn,out1
2 1 Vn,out2
2 . (5.148)
Fig. 5.66(a), such a cascade processes the signal differentially from the input port of the
LNA to the end of the baseband section. The transformer is called a “balun,” an acronym Since each half circuit provides matching at the input, the CG results of Section 5.3.3
for “balanced-to-unbalanced” conversion because it can also perform differential to single- apply here as well with the substitution RS 5 RS1 /2. Specifically, the voltage gain from
ended conversion if its two ports are swapped. X to Y is equal to R1 /(2RS1 /2), where R1 denotes the load resistance of the CG half cir-
cuit. The output noise consists of (1) the input transistor contribution, given by Eq. (5.56),
(2) the load resistor contribution, 4kTR1 , and (3) the source impedance contribution,
1−to−1 Balun (4kTRS1 /2)[R1 /(2R1 /2)]:
BPF LNA LNA
⎛ ⎞2
R S1 V n,out
R S1 R in R21 RS1 ⎜ R1 ⎟
2
Vn,out1 5 kTγ 1 4kTR1 1 4kT ⎝ 2R ⎠ . (5.149)
R in R in RS1 /2 2 S1
R S2
2
(a) (b)
From Eq. (5.148), the total output noise power is twice this amount. Noting that the total
Figure 5.66 (a) Use of balun at RX input, (b) simplified circuit. voltage gain Av 5 (VY 2 VW )/(VX 2 VZ ) is equal to that of half of the circuit, VY /VX
( 5 R1 /RS1 ), we compute the noise figure with respect to a source impedance of RS1 as
If the source impedance provided by the antenna and the band-pass filter in Fig. 5.66(a) 2
is RS1 (e.g., 50 ), what is the differential source impedance seen by the LNA, RS2 ? For Vn,out 1
NF 5 · (5.150)
a lossless 1-to-1 balun, i.e., for a lossless transformer with an equal number of turns in A2v 4kTRS1
its primary and secondary, we have RS2 5 RS1 . We must thus obtain the noise figure of 2RS1
the differential LNA with respect to a differential source impedance of RS1 . Figure 5.66(b) 511γ 1 . (5.151)
R1
shows the setup for output noise calculation.
Note that the differential input impedance of the LNA, Rin , must be equal to RS1 for Interestingly, this value is lower than that of the single-ended counterpart [Eq. (5.58)]. But
proper input matching. Thus, in the LNAs of Figs. 5.66(a) and (b), the single-ended input why? Since in Fig. 5.67(c), VY /VX 5 R1 /(2RS1 /2) 5 R1 /RS1 , we observe that the voltage
impedance of each half circuit must be equal to RS1 /2, e.g., 25 . gain is twice that of the single-ended CG LNA. (After all, the transconductance of the
input transistor is doubled to lower the input impedance to RS1 /2.) On the other hand, the
Differential CG LNA We now calculate the noise figure of the differential CG LNA overall differential circuit contains two R1 ’s at its output, each contributing a noise power
of Fig. 5.65(a), assuming it is designed such that the impedance seen between each input of 4kTR1 . The total, 8kTR1 , divided by (R1 /RS1 )2 and 4kTRS1 yields 2RS1 /R1 . Of course,
node and ground is equal to RS1 /2. In other words, each CG transistor must provide an the value stipulated by Eq. (5.151) can be readily obtained in a single-ended CG LNA
input resistance of 25 . Figure 5.67(a) shows the simplified environment, emphasizing by simply doubling the load resistance. Figure 5.68 summarizes the behavior of the two
that the noise figure is calculated with respect to a source impedance of RS1 . Redrawing circuits, highlighting the greater voltage gain in the differential topology. If identical gains
Fig. 5.67(a) as shown in Fig. 5.67(b), we recognize from the symmetry of the circuit that are desired, the value of the load resistors in the differential circuit must be halved, thereby
yielding identical noise figures.
R S1
In summary, a single-ended CG LNA can be converted to differential form according
R S1 LNA
R1 R1
R S1 2 Y 2
to one of three scenarios: (1) simply copy the circuit, in which case the differential input
LNA
1:1 2 X V n,out1
resistance reaches 100 , failing to provide matching with a 1-to-1 balun; (2) copy the
V in 2 2 circuit but double the transconductance of the input transistors, in which case the input is
V n,out V n,out
R S1 2
R S1
Z V n,out2 matched but the overall voltage gain is doubled; (3) follow the second scenario but halve the
R S1 R S1 W
2 load resistance to retain the same voltage gain. The second choice is generally preferable.
2
(a) (b) (c)
Note that, for a given noise figure, a differential CG LNA consumes four times the power
of a single-ended stage.19
Figure 5.67 (a) Cascade of balun and LNA, (b) simplified circuit of (a), and (c) simplified circuit
of (b).
19. To halve the input resistance, the transistor width and bias current must be doubled.
Sec. 5.6. High-IP2 LNAs 317 318 Chap. 5. Low-Noise Amplifiers

CG LNA
Example 5.25 (Continued)
R1
R S1 VpR 1
single-ended circuit is therefore given by
Vp
2 R S1
RS1 2
V in 4kT A 1 A2 Vn2 1
R S1 NFsing 5 2 · (5.152)
A2 4kTRS1
(a)
4
VpR 1
Vn2
2 R S1 521 . (5.153)
R S1 kTRS1
1:1 R1 R1

Vp For the differential version, we write from the simplified half circuit shown in Fig. 5.69(c),
V in
R S1
2
Vn,out1 5 (4kTRS1 /4)A2 1 A2 Vn2 . The total output noise power of the differential circuit is
VpR 1
R S1 twice this amount. The corresponding noise figure is then given by
2 R S1
 
RS1 2
2 4kT A 1 A2 Vn2
4 1
(b) NFdiff 5 · (5.154)
A2 4kTRS1
Figure 5.68 Comparison of (a) single-ended and (b) differential CG LNAs. 4
2Vn2
521 . (5.155)
kTRS1
Our NF calculations have assumed an ideal balun. In reality, even external baluns have
a loss as high as 0.5 dB, raising the NF by the same amount. In this case, the noise figure of the differential circuit is higher. We conclude that whether
the differential version of an LNA exhibits a higher or lower NF depends on the circuit
topology.
Example 5.25
An amplifier having a high input impedance employs a parallel resistor at the input to
provide matching [Fig. 5.69(a)]. Determine the noise figure of the circuit and its differential
version, shown in Fig. 5.69(b), where two replicas of the amplifier are used. Differential CS LNA The differential CS LNA of Fig. 5.65(b) behaves differently from
its CG counterpart. From Section 5.3.4, we recall that the input resistance of each half
R S1
circuit is equal to L1 ωT and must now be halved. This is accomplished by halving L1 .
2 2 2
Vn Vn Vn
R S1 R S1 2 2
A 1:1 A A V n,out1 With input matching and a degeneration inductance of L1 , the voltage gain was found in
R S1
V in R S1 V in 2
R S1
Section 5.3.4 to be R1 /(2L1 ω0 ), which is now doubled. Figure 5.70(a) illustrates the overall
2
cascade of the balun and the differential LNA. We assume that the width and bias current
A
R S1 of each input transistor are the same as those of the single-ended LNA.
2 To compute the noise figure, let us first determine the output noise of the half circuit
(a) (b) (c) depicted in Fig. 5.70(b). Neglecting the contribution of the cascode device, we note from
Figure 5.69 (a) NF of an LNA with resistive termination, (b) differential version of (a), (c) simplified Section 5.3.4 that, if the input is matched, half of the noise current of the input transistor
circuit of (b). flows from the output node. Thus,
Solution:  2
RS1 R1
In the circuit of Fig. 5.69(a), the amplifier input-referred noise current is negligible and
2
Vn,out1 5 kTγ gm1 R21 1 4kTR1 1 4kT . (5.156)
2 L1 ω0
the total noise at the output is equal to (4kTRS1 /2)A2 1 A2 Vn2 . The noise figure of the
(Continues)
Sec. 5.6. High-IP2 LNAs 319 320 Chap. 5. Low-Noise Amplifiers

VDD VDD The reduction of the input transistor noise contribution in Eq. (5.157) is a remarkable
R1 LD LD R1 R1 LD
property of differential operation, reinforcing the NF advantage of the degenerated CS
2
stage over the CG LNA. However, this result holds only if the design can employ two
Vout V n,out1 degeneration inductors, each having half the value of that in the single-ended counterpart.
R S1 LG This is difficult with bond wires as their physical length cannot be shortened arbitrarily.
2 2 Alternatively, the design can incorporate on-chip degeneration inductors while converting
R S1 LG
1:1 M1 the effect of the (inevitable) bond wire to a common-mode inductance. Figure 5.72 shows
V in L1 L1 L1 such a topology. With perfect symmetry, the bond wire inductance has no effect on the
R in R S1
R S1 2 2 2 differential impedance seen between the gates. Nonetheless, as explained in Chapter 7,
2 on-chip inductors suffer from a low quality factor (e.g., a high series resistance), possibly
degrading the noise figure. We compare the power consumptions of the single-ended and
(a) (b) differential implementations in Problem 5.22.
Figure 5.70 (a) Differential CS LNA and (b) its half circuit.

R S1 LG
L1 L1
Multiplying this power by two, dividing it by A2v 5 R21 /(L1 ω0 )2 and 4kTRS1 , and noting 1:1
that L1 ωT /2 5 RS1 /2, we have V in
Bond
 2  2 Wire
γ ω0 2RS1 ω0 On−Chip
NF 5 gm1 RS1 1 1 1. (5.157) Inductors
2 ωT R1 ωT

How does this compare with the noise figure of the original single-ended LNA Figure 5.72 Differential CS stage with on-chip degeneration inductors.
[Eq. (5.101)]? We observe that both the transistor contribution and the load contribution
are halved. The transistor contribution is halved because gm1 and hence the transistor noise The NF advantage implied by Eq. (5.157) may not materialize in reality because the
current remain unchanged while the overall transconductance of the circuit is doubled. loss of the balun is not negligible.
To understand this point, recall from Section 5.3.4 that Gm 5 ωT /(2ω0 RS ) for the original Is it possible to use a differential pair to convert the single-ended antenna signal to
single-ended circuit. Now consider the equivalent circuit shown in Fig. 5.71, where the dif- differential form? As shown in Fig. 5.73(a), the signal is applied to one input while the other
ferential transconductance, (I1 2 I2 )/Vin , is equal to ωT /(ω0 RS1 ) (why?). The differential is tied to a bias voltage. At low to moderate frequencies, VX and VY are differential and the
output current contains the noise currents of both M1 and M2 and is equal to 2(kTγ gm1 ). voltage gain is equal to gm1,2 RD . At high frequencies, however, two effects degrade the
If this power is divided by the square of the transconductance and 4kTRS1 , the first term in balance of the phases: the parasitic capacitance at node P attenuates and delays the signal
Eq. (5.157) is obtained. propagating from M1 to M2 , and the gate-drain capacitance of M1 provides a non-inverting
feedforward path around M1 (whereas M2 does not contain such a path).

I1 I2
VDD VDD
R S1 LG LG R S1
2 2 RD RD RD RD
2 2
X Vout Y X Vout Y

L1 L1 V in M1 M2 Vb V in M1 M2 Vb
2 2 P P
LP
CP CP

V in
(a) (b)
Figure 5.71 Differential CS stage viewed as a transconductor.
Figure 5.73 Single-ended to differential conversion by (a) a simple differential pair, (b) a differen-
tial pair including tail resonance.
Sec. 5.6. High-IP2 LNAs 321 322 Chap. 5. Low-Noise Amplifiers

The capacitance at P can be nulled through the use of a parallel inductor [Fig. 5.73(b)] M1 M2
[9], but the CGD1 feedforward persists. The tail inductor can be realized on-chip because
V in L S1 L S2 Vb
its parallel equivalent resistance at resonance (RP 5 QLP ω0 ) is typically much greater than
1/gm1,2 .
C P1 L P1 L P2 C P2

Example 5.26
A student computes CP in Fig. 5.73(b) as CSB1 1 CSB2 1 CGS2 , and selects the value of LP
accordingly. Is this an appropriate choice? Figure 5.75 Use of on-chip inductors for resonance and degeneration.

Solution:
No, it is not. For LP to null the phase shift at P, it must resonate with only CSB1 1 CSB2 .
This point can be seen by examining the voltage division at node P. As shown in Fig. 5.74,
in the absence of CSB1 1 CSB2 , C

Z2
VP 5 Vin . (5.158)
Z1 1 Z2

V in M1 M2
C GS1 P C GS2 A B

Figure 5.76 Simple planar 1-to-1 balun.

Z1 Z2

Shown in Fig. 5.76 is an example, where two spiral inductors LAC and LCB are intertwined
to create a high mutual coupling. As explained in Chapter 7, the resistance and capaci-
Figure 5.74 Impedances seen at the common source of differential pair. tance associated with the spirals and the sub-unity coupling factor make such baluns less
attractive.
For VP to be exactly equal to half of Vin (with zero phase difference), we must have Z1 5 Z2 .
Since each impedance is equal to (gm 1 gmb )21 ||(CGS s)21 , we conclude that CGS2 must
not be nulled.20 Example 5.27
A student attempts to use a 1-to-N balun with a differential CS stage so as to amplify the
input voltage by a factor of N and potentially achieve a lower noise figure. Compute the
The topology of Fig. 5.73(b) still does not provide input matching. We must therefore
noise figure in this case.
insert (on-chip) inductances in series with the sources of M1 and M2 (Fig. 5.75). Here, LP1
and LP2 resonate with CP1 and CP2 , respectively, and LS1 1 LS2 provides the necessary Solution:
input resistance. Of course, LS1 1 LS2 is realized as one inductor. However, as explained in
Illustrated in Fig. 5.77, such an arrangement transforms the source impedance to a value
Section 5.7, this topology exhibits a lower IP3 than that of Fig. 5.65(b).
of N 2 RS , requiring that each half circuit provide an input real part equal to N 2 RS /2. Thus,
Balun Issues The foregoing development of differential LNAs has assumed ideal 1-to-1 L1 ωT 5 N 2 RS /2, i.e., each degeneration inductance must be reduced by a factor of N 2 .
baluns. Indeed, external baluns with a low loss (e.g., 0.5 dB) in the gigahertz range are Since still half of the noise current of each input transistor flows to the output node, the
available from manufacturers, but they consume board space and raise the cost. Inte- noise power measured at each output is given by
grated baluns, on the other hand, suffer from a relatively high loss and large capacitances.
R21
2
Vn,out1 5 Vn,out2
2 5 4kTγ gm1 1 4kTR1 . (5.159)
4
20. But the parasitic capacitance of ISS must be nulled.
Sec. 5.6. High-IP2 LNAs 323

Example 5.27 (Continued)

VDD

R1 LD LD R1
2 2
V n,out1 V n,out2

Vb

RS LG
1:N

V in 2 2 L1 L1
N RS N RS
RS

Figure 5.77 Use of 1-to-N balun in an LNA.

The gain from Vin to the differential output is now equal to NR1 /(2L1 ω0 ). Doubling the
above power, dividing by the square of the gain, and normalizing to 4kTRS , we have
 2  2
γ ω0 RS ω0
NF 5 N 2 gm1 RS 1 2N 2 1 1. (5.160)
2 ωT R1 ωT

We note, with great distress, that the first two terms have risen by a factor of N 2 !21 This
is because the condition L1 ωT 5 N 2 RS /2 inevitably leads to an N 2 -fold reduction in the
transconductance of the circuit. Thus, even with the N-fold amplification of Vin by the
balun, the overall voltage gain drops by a factor of N.

The reader may wonder if an N-to-1 (rather than 1-to-N) balun proves beneficial in
the above example as it would multiply the first two terms of Eq. (5.160) by 1/N 2 rather
than N 2 . Indeed, off-chip baluns may provide a lower noise figure if L1 (a bond wire) can be
reduced by a factor of N 2 . On the other hand, on-chip baluns with a non-unity turns ratio are
difficult to design and suffer from a higher loss and a lower coupling factor. Figure 5.78(a)
shows an example [5], where one spiral forms the primary (secondary) of the balun and
the series combination of two spirals constitutes the secondary (primary). Alternatively, as
shown in Fig. 5.78(b), spirals having different numbers of turns can be embedded [10].

5.6.2 Other Methods of IP2 Improvement

The difficulty with the use of off-chip or on-chip baluns at the input of differential LNAs
makes single-ended topologies still an attractive choice. A possible approach to raising the
IP2 entails simply filtering the low-frequency second-order intermodulation product, called
the beat component in Chapter 4. Illustrated in Fig. 5.79, the idea is to remove the beat by
a simple high-pass filter (HPF) following the LNA. For example, suppose two interferers

21. Assuming that gm1 and ωT remain unchanged.