EXPERIMENT 11

Implementation of Processor
Objective:
1. The objective of this lab is to join a program counter, instruction memory and register
files modeled in previous lab with ALU and Controller to create a processor.
2. Write few instructions in Instr. Memory and execute the processor.
Equipment/Tool:
 Vivado Software
 Computer
Background:
Figure below shows the complete diagram of the small processor. In the previous lab we made
counter, instruction memory and register files along with ALU and Controller. In this lab we
must instantiate already made components and join them in top level file.

Instr. adr ALU 4 rd_adr1

Mem 4 24 rd_data1 Regist
Instr 32 and 4 wr_adr1 er
ory 24 wr_data1
Con 1 wr_en1 File1
troll 4 rd_adr2 Regist
24 rd_data2
er 4 wr_adr2 er
24 wr_data2 File2
1 wr_en2

clk reset Processor Outputs

Figure 11.1: Block diagram of processor
Procedure/Tasks:
Task 1:
Instantiate components made in lab 10 and join them in top level file.
Task 2:
Write down machine code of following instructions in Instr. Memory using information given in
Table 1.
1. Store a value 16 at location 0 of register file 1.
2. Store a value 32 at location 1 of register file 2.
3. Perform no operation by writing all zeros in Instr. Memory location.
4. Add values stored in location 0 of register file 1 and location 1 of register file 2 and store
the result in register file 1 at location 1.
5. Perform no operation by writing all zeros in Instr. Memory location.
6. Subtract values stored in location 1 of register file 1 and location 1 of register file 2 and
store the result in register file 2 at location 2.
7. Perform no operation by writing all zeros in Instr. Memory location.
8. Multiply values stored in location 1 of register file 1 and location 2 of register file 2 and
store the MSB of result in register file 2 at location 3 and LSB in register file 1 at location
Table 11.1: Instructions format for a processor

Instruction Instruction Format

To store24 bit value <3 Bit - Instruction><1 bit - register file number><4 bit - location in
inone of the register register file><24 bit - value to store in register>
files at given location Example: 00110101101001011111011100000001
Store a value 101001011111011100000001 at location 0101 in register file
2.

To add the values in <3 Bit - Instruction><4 bit - location in register file 1 to read first
one of the registers of operand><4 bit - location in register file 2 to read second operand><1 bit
register file 1 with one - register file where to store><4 bit - location in specified register
of the registers of file><16bit - don't care>
register file 2 and store
the result at one of the Example: 010011101010 0100 XXXXXXXXXXXXXXXX
locations in one of the Add content of data placed at location 0111 of register file 1 with data
register files placed at location 0101 and place it at location 0100 of register file 0.

To subtract the values <3 Bit - Instruction><4 bit - location in register file 1 to read first
in one of the registers operand><4 bit - location in register file 2 to read second operand><1 bit
of register file 1 with - register file where to store><4 bit - location in specified register
one of the registers of file><16bit - don't care>
register file 2 and store
the result at one of the Example: 011 011101010 0100 XXXXXXXXXXXXXXXX
locations in one of the Subtract content of data placed at location 0111 of register file 1 with data
register files. placed at location 0101 and place it at location 0100 of register file 0.

To Bitwise-xor the <3 Bit - Instruction><4 bit - location in register file 1 to read first
values in one of the operand><4 bit - location in register file 2 to read second operand><1 bit
registers of register file - register file where to store><4 bit - location in specified register
1 with one of the file><16bit - don't care>
registers of register file
2 and store the result at Example: 100 011101010 0100 XXXXXXXXXXXXXXXX
one of the locations in Bitwise-xor content of data placed at location 0111 of register file 1 with
one of the register files data placed at location 0101 and place it at location 0100 of register file 0.

To Bitwise-and the <3 Bit - Instruction><4 bit - location in register file 1 to read first
values in one of the operand><4 bit - location in register file 2 to read second operand><1 bit
registers of register file - register file where to store><4 bit - location in specified register
1 with one of the file><16bit - don't care>
registers of register file
2 and store the result at Example: 101 011101010 0100XXXXXXXXXXXXXXXX
one of the locations in Bitwise-and content of data placed at location 0111 of register file 1 with
one of the register files. data placed at location 0101 and place it at location 0100 of register file 0.

To multiply the values <3 Bit - Instruction><4 bit - location in register file 1 to read first
in one of the registers operand><4 bit - location in register file 2 to read second operand><1 bit
of register file 1 with - register file where to store MSB><4 bit - location in specified register
one of the registers of file><4 bit - location in specified register file><12bit - don't care>
register file 2 and store
the 24 MSBs of results Example: 101 011101010 01001001XXXXXXXXXXXX
in one of the locations Multiply content of data placed at location 0111 of register file 1 with data
in one of the register placed at location 0101 in register file 2 and place 24 bit MSB of result at
files and 24 LSBs in location 0100 of register file 0 and 24-LSB of results at location 1001 of
one of the locations in register file 2.
other register files.
Task3:
Make test bench to simulate the design.
Code
Simulations

Conclusion…………………………………………………………………………………………

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 EXPERIMENT 12
Implementation of Programmable Logic (PL)
Objective:
 Create a Vivado Project for a Zynq System.
 Project creation in Vivado IP Integrator.
 Generating HDL wrapper of block design and and generating of bit stream for PL
portion.
 Programming Processor and FPGA using SDK tool.
Equipment/Tool:
 Vivado Software
 Computer
 ZedBoard
Background:
This lab guides you through the process of using Vivado to create a simple ARM Cortex-A9
based processor design targeting the ZC702 board. You will use Vivado to create the hardware
system and SDK (Software Development Kit) to create an example application to verify the
hardware functionality.
Procedure/Tasks:
 Create a Project Using Vivado.
 Create Processing System Using IP Integrator.
 Generate Top Level HDL and Export to SDK.
 Create a new file in SDK and select Hello World.
Follow training manual to execute all above steps in VIVADO and SDK.
Task 1:
In this lab we will first print Hello World in SDK terminal.
Secondly implement a basic OR gate also write it constraint file.
Program task on Zed Board.
Code: (Hello World and OR Gate)

IP Integrator Diagram
Results

Conclusion…………………………………………………………………………………………
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 EXPERIMENT 13
Implementation of Programmable Logic (PL) and Processing System (PS)
Objective:
 Create a Vivado Project for a Zynq System
 Project creation in Vivado IP Integrator
 Generating HDL wrapper of block design and and generating of bit stream for PL portion
 Exporting design to Software Development Kit
 Software application development
 Programming Processor and FPGA using SDK tool
Equipment/Tool:
 Vivado Software
 Computer
 Zed Board
Background:
PL stands for Programmable Logic, which is FPGA. In a Zynq device the PS or processing
system (cortex a9) is connected to the programmable logic using the AXI buses. That means
peripherals implemented in PL can communicate easily with software running on the CPU. This
lab guides you through the process of using Vivado to create a simple ARM Cortex-A9 based
processor design targeting the ZC702 board. You will use Vivado to create the hardware system
and SDK (Software Development Kit) to create an example application to verify the hardware
functionality.
Procedure/Tasks:
This lab is separated into steps that consist of general overview statements that provide
information on the detailed instructions that follow. Follow these detailed instructions to
progress through the lab. This lab comprises 4 primary steps:
 You will create a top-level project using Vivado.
 Create the processor system using the Vivado IP Integrator.
 Generate the top-level HDL and export the design to SDK.
 Create a simple NAND Gate based application, and finally, test in hardware.
Follow training manual to execute all above steps in VIVADO and SDK.
Task 1:
Implement NAND gate on Zed Board.
AND gate is implemented through PL and NOT gate is implemented through PS.

SDK CODE: (NOT Gate)

#include <stdio.h>
#include "platform.h"
#include "xgpio.h"
#include "xparameters.h"
#include "xil_printf.h"

int main()
{
init_platform();
XGpio input, output;
int a;
int y;
XGpio_Initialize(&input, XPAR_AXI_GPIO_1_DEVICE_ID);
XGpio_Initialize(&output, XPAR_AXI_GPIO_0_DEVICE_ID);

XGpio_SetDataDirection(&input,1,1);
XGpio_SetDataDirection(&output,1,0);
print("Done");
while(1)
 {
a= XGpio_DiscreteRead(&input,1);
if (a==1)
{
y=0;
}
else
{
y=1;
}
XGpio_DiscreteWrite(&output,1,y);
}
cleanup_platform();
return 0;
}
Code: (Verilog AND Gate)

IP Integrator Diagram
Results

Conclusion…………………………………………………………………………………………
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 EXPERIMENT 14
Open Ended Lab
Code
Simulations

Conclusion…………………………………………………………………………………………

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 Lab Rubrics
FPGA Based System Design (Spring’23)

Rubric for Psychomotor Domain Assessment

Level: Set (P3)
Criteria Grading scale
Excellent Good Satisfactory Needs improvement
(15-12) (11.9-9) (8.9 – 4.5) (4.4 – 1)
Able to perform an Follows the Follows the Follows the Follows the instructions
experiment and instructions to instructions to instructions to to perform the
solve the problem perform the perform the perform the experiment with no
using tools by experiment with experiment with experiment with results and cannot solve
following accurate results and good results and satisfactory results the problem using tools
instructions & solve the problem solve the problem and solve the by following
practicing. using tools by using tools by problem using tools instructions
practicing efficiently. practicing with but does not
better efficiency. practice
Attempts to Completely minimize Almost minimize Partially minimize Does not practice to
minimize the error the errors by the errors by the errors minimize the errors.
by practicing. practicing. practicing

Rubric for Psychomotor Domain Assessment

Level: Set (P4)
Criteria Grading scale
Excellent Good Satisfactory Needs
(15-12) (11.9-9) (8.9 – 4.5) improvement
(4.4 – 1)
Display Excellent display of Display proficiency Display proficiency in Unable to display
proficiency in proficiency in in handling handling of equipment / proficiency in
handling of handling of equipment equipment / tools tools with few mistakes. handing of
equipment / / tools. with focus & Measures system equipment / tools.
tools and Measures system commitment. performance but results are Unable to measure
measurement performance with Measures system not consistent system performance
of system confidence and no performance with
performance mistakes. confidence,
however, make
some mistakes
Organizes the Organizes conduction Organizes Organizes conduction of Unable to organize
conduction of of experiment within conduction of experiment with an conduction of
experiment effective manner with experiment within effective manner with less experiment in an
effectively. full commitment. effective manner focus and energy. effective manner.
with focus and
energy
 Rubric for Affective Domain Assessment
Level: Set (A2)
Criteria Grading scale
Excellent Good Satisfactory Needs improvement
(15-12) (11.9-9) (8.9 – 4.5) (4.4 – 1)
Participate and Always shares the Usually shares Often shares the Rarely shares the
respond in the information and the information, information, and information and supports
learning process supports the efforts and supports the supports the the efforts of others. Mostly
of others. Tries to efforts of other, efforts of others, is not a good team member
keep people does not cause” but sometimes is
working well ripples” in the not a good team
together group member
Communicate/answers Speaks clearly and Speaks clearly Speech is not Often mumbles or cannot
effectively distinctly all the and distinctly clear most of the be understood OR
time and most of the time time and mispronounces most of the
mispronounces no and mispronounces words. Answers less than
words. Answers all mispronounces many words. half questions correctly or
the questions some words. Answers half the doesn’t answer correctly at
correctly. Answers more questions all
than half of the correctly.
questions
correctly.