HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

No.1 Vo Van Ngan Street, Thu Duc Dist., HCMC, VN

DIGITAL IC DESIGN
USING HDL

NGUYEN THANH NGHIA

9/27/2021 11
NGUYEN THANH NGHIA
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering
No.1 Vo Van Ngan Street, Thu Duc Dist., HCMC, VN

CHAPTER 3: BASIC
LANGUAGE
CONSTRUCTS OF VHDL

NGUYEN THANH NGHIA

9/27/2021 22
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 Outline
1. Introduction.
2. Skeleton of a basic VHDL program.
3. Lexical elements and program format.
4. Objects.
5. Data types and operators.
6. Synthesis guidelines.

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 Chapter 3: Basic language constructs of VHDL
1. Introduction
 To use a programming language, we first
have to learn its syntax and language
constructs.
 VHDL is a complex language.
 It is designed to describe both the structural
and behavioral views of a digital system at
various levels of abstraction.

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 Chapter 3: Basic language constructs of VHDL
1. Introduction
 Many of the language constructs are
intended for modeling and for abstract,
behavioral description.
 Only a small portion of VHDL can be
synthesized and realized physically in
hardware.

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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
EXAMPLE OF A VHDL PROGRAM
 A VHDL program is composed of a
collection of design units.
 A synthesizable VHDL program needs at
least two design units: an entity declaration
and an architecture body associated with the
entity.
 The skeleton of a typical VHDL program
can best be explained by an example.

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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
EXAMPLE OF A VHDL PROGRAM
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity EVEN_DETECTOR is
Port ( a: in STD_LOGIC_VECTOR (2 downto 0);
even: out STD_LOGIC);
end EVEN_DETECTOR;
architecture sop_arch of EVEN_DETECTOR is
signal p1, p2, p3, p4: STD_LOGIC;
begin
even <= (p1 or p2) or (p3 or p4) after 20ns;
p1 <= (not a(2)) and (not a(1)) and (not a(0)) after 15ns;
p2 <= (not a(2)) and a(1) and a(0) after 15ns;
p3 <= a(2) and (not a(1)) and a(0) after 15ns;
p4 <= a(2) and a(1) and (not a(0)) after 15ns;
end sop_arch;

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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
ENTITY DECLARATION

 The simplified syntax of an entity

declaration is.
entity entity_name is
Port (
port_names: mode data_type;
port_names: mode data_type;
…
port_names: mode data_type;
port_names: mode data_type);
end entity_name;
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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
ARCHITECTURE BODY

 The architecture body specifies the internal

operation or organization of a circuit.
architecture arch_name of entity_name is
declarations;
begin
concurrent statement;
concurrent statement;
concurrent statement;
…
end arch_name;
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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
DESIGN UNIT AND LIBRARY

 Design units are the fundamental building

blocks in a VHDL program.
 When a program is processed, it is broken
into individual design units and each unit is
analyzed and stored independently.

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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
DESIGN UNIT AND LIBRARY

 There are five kinds of design units:

• Entity declaration
• Architecture body
• Package declaration
• Package body
• Configuration

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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
DESIGN UNIT AND LIBRARY

 A package of VHDL normally contains a

collection of commonly used items, such as
data types, subprograms and components,
which are needed by many VHDL programs.
 As the name suggests, a package declaration
consists of the declaration of these items.
 A package body normally contains the
implementation and code of the subprograms.
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 Chapter 3: Basic language constructs of VHDL
2. Skeleton of a basic VHDL program
DESIGN UNIT AND LIBRARY

 In VHDL, multiple architecture bodies can

be associated with an entity declaration.
 A configuration specifies which architecture
body is to be bound with the entity
declaration.

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Chapter 3: Basic language constructs of VHDL

The end!

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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS

 The lexical elements are the basic

syntactical units in a VHDL program.
 They include comments, identifiers, reserved
words, numbers, characters and strings.

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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS: COMMENTS

 A comment starts with two dashes, --,

followed by the comment text.
 Anything after the -- symbol in the line will
be ignored. The comment is for
documentation purposes only and has no
effect on the code.

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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS: COMMENTS

 For example, we have added comments to

the previous VHDL code:
architecture ok_arch of mode_demo is
signal ab: std_logic; -- ab is the internal signal
begin
ab <= a and b;
x <= ab; -- ab is connected to the x output
y <= not ab;
end ok_arch;

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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS: IDENTIFIERS

 An identifier is the name of an object in

VHDL.
 The basic rules to form an identifier are:
• The identifier can contain only alphabetic
letters, decimal digits and underscores.
• The first character must be a letter.
• The last character cannot be an underscore.
• Two successive underscores are not allowed.
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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS: IDENTIFIERS

 For example, the following identifiers are valid.

A10, next_state, NextState, mem_addr_enable.
 On the other hand, the following identifiers
violate one of the rules and will cause a syntax
error:
sig#3, -X10, 7segment, X10_, hi__there.
 Since VHDL is not case sensitive, the following
identifiers are the same:
nextstate, NextState, NEXTSTATE, nEXTsTATE.
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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS: RESERVED WORDS

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 Chapter 3: Basic language constructs of VHDL
3. Lexical elements and program format
LEXICAL ELEMENTS: NUMBERS, CHARACTERS AND STRINGS

 For example, 45 can be represented as

2#101101# and 16#2D# in base 2 and base 16
respectively.
 We can also add an underscore to enhance
readability.
 For example, 12_3456 is the same as 123456,
and 2#0011_1010_1101# is the same as
2#001110101101#.

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 Chapter 3: Basic language constructs of VHDL
4. Objects
SIGNAL

 The signal is the most common object and

we already used it in previous examples.
 A signal has to be declared in the
architecture body’s declaration section.
 The simplified syntax of signal declaration is
signal signal_name, signal_name, … : data_type;

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 Chapter 3: Basic language constructs of VHDL
4. Objects
SIGNAL

 For example, the following line declares the

a, b and c signals with the std_logic data type.
signal a, b, c : std_logic;
 According to the VHDL definition, we can
specify an optional initial value in the signal
declaration. For example, we can assign an
initial value of ‘0’ to the previous signals:
signal a, b, c : std_logic := ‘0’ ;
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 Chapter 3: Basic language constructs of VHDL
4. Objects
VARIABLES

 A variable is a concept found in a traditional

programming language. It can be thought of as
a “symbolic memory location” where a value
can be stored and modified.
 There is no direct mapping between a
variable and a hardware part.
 A variable can only be declared and used in
a process and is local to that process.
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 Chapter 3: Basic language constructs of VHDL
4. Objects
VARIABLES

 The main application of a variable is to

describe the abstract behavior of a system.
 The syntax of variable declaration is similar
to that of signal declaration:
variable variable_name, variable_name, … : data_type;
 The simplified syntax of variable assignment
is.
Variable_name := value_expression;
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 Chapter 3: Basic language constructs of VHDL
4. Objects
CONSTANTS

 A constant holds a value that cannot be

changed. The syntax of constant declaration is:
constant constant_name : data_type := value_expression;
 The value_expression term specifies the
value of the constant.
 A simple example is:
constant BUS_WIDTH: integer:= 32;
constant BUS_BYTES: integer:= BUS_WIDTH/8;
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
 In VHDL, each object has a data type.
 A data type is defined by:
• A set of values that an object can assume.
• A set of operations that can be performed
on objects of this data type.

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
PREDEFINED DATA TYPES IN VHDL

 Integer:
VHDL does not define the exact range of
the integer type but specifies that the
minimal range is from (-231) to (231 – 1),
which corresponds to 32 bits.
 Boolean: defined as (false, true).
 Bit: defined as (‘0’, ‘1’).
 Bit_vector: defined as a one-dimensional array
with elements of the bit data type.
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
PREDEFINED DATA TYPES IN VHDL

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
PREDEFINED DATA TYPES IN VHDL

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
PREDEFINED DATA TYPES IN VHDL

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
PREDEFINED DATA TYPES IN VHDL

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
PREDEFINED DATA TYPES IN VHDL

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 To better reflect the electrical property of

digital hardware, several new data types were
developed by IEEE to serve as an extension to
the bit and bit_vector data types.
 Theses data types are defined in the
std_logic_1164 package of IEEE standard 1164.
 The std_logic data type consists of nine
possible values, which are shown in the following
list: (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’)
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 These values are interpreted as follows:

 ‘0’ and ‘1’: stand for “forcing logic 0” and
“forcing logic 1” which mean that the signal is
driven by a circuit with a regular driving
current.
 ‘Z’: stands for high impedance, which is
usually encountered in a tri-state buffer.
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE
 ‘L’ and ‘H’: stand for “weak logic 0” and “weak
logic 1,” which means that the signal is obtained
from wired-logic types of circuits, in which the
driving current is weak.
 ‘U’: stands for uninitialized. It is used in simulation
to indicate that a signal or variable has not yet been
assigned a value.
 ‘-’: stands for don’t-care.
 ‘X’ and ‘W’: stand for “unknown” and “weak
unknown”.
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 The unknown represents that a signal

reaches an intermediate voltage value that can
be interpreted as neither logic 0 or logic 1. This
may happen because of a conflict in output
(such as a logic-0 signal and a logic-1 signal
being tied together). They are used in
simulation for an erroneous condition.
 Among these values, only ‘0’, ‘1’ and ‘Z’ are
used in synthesis.
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 The ‘L’ and ‘H’ values are seldom used now

since current design practice rarely utilizes a
wired-logic circuit.
 The use of ‘Z’ and the potential problem of
‘-’ are discussed in Chapter 6.

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 Concatenation operator
• The concatenation operator, &, is very
useful for array manipulation.
• We can combine segments of elements and
smaller arrays to form a larger array.
y <= "00" & a(7 downto 2);

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 Array aggregate
• For example, if we want to assign a value of
"10100000" to the a signal, it can be written as:
a <= "10100000 ";
• Another way is to list each value of the
element in the corresponding position, which is
known as positional association. The previous
assignment becomes.
a <= (‘1’,‘0’,‘1’, ‘0’, ‘0’,‘0’,‘0’,‘0’);
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 Array aggregate
• We can also use the form of index => value to
explicitly specify the value for each index,
known as named association.
• The statement can be written as
a <= (7=> '1', 6=> '0', 5=> '1', 4=> '0', 3=> '0',
2=> '0', 1=> '0', 0=> '0');
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 Array aggregate
• We can combine the index, as in
a <= ((7|5)=> '1', 6|4|3|2|1|0=> '0');
• or use a reserved word, others, to cover all the
unused indexes, as in
a <= ((7|5)=> '1', others=> '0');

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 Array aggregate
• For example, if we want to assign "00000000" to
the a signal, we can write
a <= (others => '0');
• It is more compact than
a <= “00000000";

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 To perform addition of the a and b signals, we

must use the integer data type, as in
signal a, b, sum: integer;
…
sum <= a + b;
 It is difficult to realize this statement in
hardware since the code doesn’t indicate the
range (number of bits) of the a and b signals.

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

signal a, b, sum: integer;

…
sum <= a + b;
 Although this does not matter for simulation,
it is important for synthesis since there is a
huge difference between the hardware
complexity of an 8-bit adder and that of a 32-
bit adder.

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 A better alternative is to use an array of 0’s

and 1’s and interpret it as an unsigned or
signed number.
 The IEEE numeric_std package was
developed for this purpose.

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

 Since the signed and unsigned data types are

arrays, their declarations are similar to that of
the std_logic_vector data type, as in
signal x, y: signed(15 downto 0);
 To use the signed and unsigned data types, we
must include the library statement before the
entity declaration.
library ieee; use ieee. Std_logic_1164. all;
use ieee. Numeric_std.all;
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE

signal u1, u2: unsigned (7 downto 0);

signal v1, v2: std_logic_vector (7 downto 0);
…
u1 <= unsigned(v1);
v2 <= std_logic_vector (u2);

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE
 Assume that some signals are declared as
follows:
library ieee;
use ieee.std_logic_1164. all;
use ieee.numeric_std.all;
…
signal s1, s2, s3, s4, s5, s6: std_logic_vector (3 downto 0);
signal u1, u2, u3, u4, u5, u6 , u7: unsigned (3 downto 0);
signal sg: signed (3 downto 0);

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE
u3 <= u2 + u1; -- ok, both operands unsigned
u4 <= u2 + 1; -- ok, operands unsigned and natural
u5 <= sg; -- not ok, type mismatch
u6 <= 5; -- not ok, type mismatch
u5 <= unsigned (sg); -- ok, type casting
u6 <= to_unsigned (5, 4); -- ok, conversion function
5 -- the value will be converted
4 -- number of bits will be converted

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN THE IEEE STD_LOGIC_1164 PACKAGE
u7 <= sg + u1; -- not ok, + undefined over the types
u7 <= unsigned (sg) + u1; -- ok, but be careful

s3 <= u3; -- not ok, type mismatch

s4 <= 5; -- not ok, type mismatch

s3 <= std_logic_vector (u3); -- ok, type casting

s4 <= std_logic_vector (to_unsigned (5, 4)); -- ok

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN NON-IEEE PACKAGE

 Package by Synopsys;
 std_logic_arith:
• Similar to numeric_std
• New data types: unsigned, signed
• Details are different
 std_logic_unsigned/ std_logic_signed
• Treat std_logic_vector as unsigned and signed
numbers
• i.e., overload std_logic_vector with arith operations

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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN NON-IEEE PACKAGE
 Software vendors frequently store them in ieee library:
 E.g.,
library ieee;
use ieee.std_logic_1164. all;
use ieee.std_arith_unsigned.all;
…
signal s1, s2, s3, s4, s5, s6: std_logic_vector (3 downto 0);
…
s5 <= s2 + s1; + overloaded with std_logic_vector
s6 <= s2 + 1; + overloaded with std_logic_vector
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 Chapter 3: Basic language constructs of VHDL
5. Data types and operators
DATA TYPES IN NON-IEEE PACKAGE

 Only one of the std_logic_unsigned and

std_logic_signed packages can be used
 The std_logic_unsigned/std_logic_signed
packages beat the motivation behind a
strongly-typed language
 Numeric_std is preferred

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Chapter 3: Basic language constructs of VHDL

The end!

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