Computer Architecture
EG 2214 CT
Total: 6 hour /week
Year: II Lecture: 3 hours/week
Semester: IV Tutorial: hours/week
Practical: 3 hours/week
Course Description:
This course is an introduction to computer architecture and organization. It covers topics in both
the physical design of the computer (organization) and the logical design of the computer
(Architecture).
Course Objectives:
After completing this course the student will able to:
1. Explain the over view of computer organization
2. Explain the principle of CPU system
3. Explain the principle of memory system
4. Explain the principle of data flow
Course Contents:
Units Topics Contents Hours Methods Marks
/Media
1 Basic computer 1.1 Introduction [6]
architecture: History of computer architecture
Overview of computer
organization
Memory Hierarchy
External Memory
Organization of Hard Disk
1.2 Instruction codes
Stored Program Organization
Computer Registers
Common bus system
Computer instruction
Instruction set
1.3 Timing and Control
1.4 Instruction Cycle
Fetch and decode
1.5 Type of Instruction
Register reference instruction
Memory reference instruction
Input-output and interrupt
101
2 Micro 2.1 Control Memory [7]
programmed 2.2 Address Sequencing
Control: Conditional Branching
Mapping of Instruction-
Subroutines
2.3 Micro program
Microinstruction Format
Symbolic Micro program
Binary Micro program
2.4 Design of control unit
Basic requirement of control
unit
Structure of control unit
Hardwired control unit
Micro program sequencer
3 Central Processing 3.1 Processor organization [12]
Internal structure of CPU
3.2 General Register Organization:
Control word.
Stack organization.
Instruction Formats
Addressing Modes
3.3 Data transfer and Manipulation:
Data Transfer Instructions
Data Manipulation Instructions
Arithmetic Instructions
Logical and Bit Manipulation
Instructions
Shift Instructions.
3.4 Program control:
Status bit conditions
Conditional Branch Instructions
Subroutine Call and Return
Program Interrupt
Types of Interrupts.
3.5 Reduced Instruction SetComputer
(RISC):
CISC Characteristics
RISC Characteristics
4 Computer 4.1 Addition and Subtraction: [12]
Arithmetic and Hardware Implementation-
Memory Hardware Algorithm
102
Organization: Addition and Subtraction with
Signed-2's Complement
4.2 Multiplication Algorithms:
Booth Multiplication Algorithm
4.3 Division Algorithms:
Divide Overflow
Hardware Algorithm
Floating Point Arithmetic
Operations
Basic Considerations
Register Configuration
4.4 Memory concept
Main Memory
Auxiliary Memory
4.5 Associative Memory Hardware
Organization
Match Logic
Read operation and Write
operation
Cache memory
Associative Mapping
Direct Mapping
Set-Associative Mapping
Writing into Cache
Cache Initialization.
4.6 Virtual Memory
Address space and Memory space
Address mapping Using Pages
Associative Memory page table
Page Replacement
5 Pipeline and 5.1 Parallel Processing [8]
Multiprocessors: Pipelining
Arithmetic Pipeline
Instruction Pipeline
5.2 Pipeline Example
Four Segment Instruction
Pipeline
Data Dependency
Handling of Branch Instructions
RISC Pipeline
Three Segment Instruction
Delayed Load
Delayed branch.
103
5.4 Multiprocessors
Characteristics of
Multiprocessors
Interconnection Structure: Time-
Shared Common Bus, Multiport
Memory, Crossbar Switch,
Multistage Switching Network,
and Hypercube interconnection
Practical: Perform the following tasks: 45hrs
1. Implement the addition and subtraction
algorithms
2. Implement the addressing modes
3. Study of 8259 programmable interrupt
controller - Development of interrupt
service routine
4. Keyboard/display controller- Keyboard
scan- blinking and rolling display
5. Parallel data transfer.
6. Study of Microcomputer development
system
Text books:
1. Morris Mano. M., Computer System architecture, PHI, Third Edition.
Reference books:
1. Hamacher.V.C.,Vranesic. Z. G and Zaky .S. G, Computer Organisation, McGraw Hill, New
York,III Edition,1990.
2. Hayes," Computer System Architecture",Mc Graw Hill,1998.
4. William Stallings, "Computer Organization and Architecture", Pearson, Tenth Edition
104
