DATASHEET

ICL7660S, ICL7660A FN3179

Super Voltage Converters Rev 7.01
Feb 10, 2020

The ICL7660S and ICL7660A Super Voltage Converters are Features

monolithic CMOS voltage conversion ICs that ensure
• Ensured Lower Max Supply Current for All Temperature
significant performance advantages over other similar
Ranges
devices. They are direct replacements for the industry
standard ICL7660 offering an extended operating supply • Wide Operating Voltage Range: 1.5V to 12V
voltage range up to 12V, with lower supply current. A • 100% Tested at 3V
Frequency Boost pin has been incorporated to enable the
user to achieve lower output impedance despite using smaller • Boost Pin (Pin 1) for Higher Switching Frequency
capacitors. All improvements are highlighted in the “Electrical • Ensured Minimum Power Efficiency of 96%
Specifications” section on page 3. Critical parameters are
• Improved Minimum Open Circuit Voltage Conversion
ensured over the entire commercial and industrial
Efficiency of 99%
temperature ranges.
• Improved SCR Latchup Protection
The ICL7660S and ICL7660A perform supply voltage
conversions from positive to negative for an input range of • Simple Conversion of +5V Logic Supply to ±5V Supplies
1.5V to 12V, resulting in complementary output voltages of • Simple Voltage Multiplication VOUT = (-)nVIN
-1.5V to -12V. Only two non-critical external capacitors are
needed, for the charge pump and charge reservoir functions. • Easy to Use; Requires Only Two External Non-Critical
Passive Components
The ICL7660S and ICL7660A can be connected to function
as a voltage doubler and will generate up to 22.8V with a • Improved Direct Replacement for Industry Standard
12V input. They can also be used as a voltage multipliers or ICL7660 and Other Second Source Devices
voltage dividers. • Pb-Free Available (RoHS Compliant)
Each chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
Applications
MOS switches. The oscillator, when unloaded, oscillates at a • Simple Conversion of +5V to ±5V Supplies
nominal frequency of 10kHz for an input supply voltage of
• Voltage Multiplication VOUT = ±nVIN
5.0V. This frequency can be lowered by the addition of an
external capacitor to the “OSC” terminal, or the oscillator • Negative Supplies for Data Acquisition Systems and
may be over-driven by an external clock. Instrumentation

The “LV” terminal may be tied to GND to bypass the internal • RS232 Power Supplies
series regulator and improve low voltage (LV) operation. At • Supply Splitter, VOUT = ±VS
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latchup.

In some applications, an external Schottky diode from VOUT

to CAP- is needed to ensure latchup free operation (see Do’s
and Dont’s section on page 8).

Pin Configurations
ICL7660S ICL7660A
(8 LD PDIP, SOIC) (8 LD PDIP, SOIC)
TOP VIEW TOP VIEW

BOOST 1 8 V+ NC 1 8 V+

CAP+ 2 7 OSC CAP+ 2 7 OSC

GND 3 6 LV GND 3 6 LV

CAP- 4 5 VOUT CAP- 4 5 VOUT

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ICL7660S, ICL7660A

Ordering Information
PART NUMBER PART TEMP. RANGE PKG.
(Note 3) MARKING (°C) PACKAGE DWG. #
ICL7660SCBA (No longer available, recommended 7660 SCBA 0 to +70 8 Ld SOIC M8.15
replacement: ICL7660SCBAZ, ICL7660ACBAZ-T)
ICL7660SCBAZ (Notes 1, 2) 7660 SCBAZ 0 to +70 8 Ld SOIC (Pb-free) M8.15
ICL7660SCPA (No longer available, recommended 7660S CPA 0 to +70 8 Ld PDIP E8.3
replacement: ICL7660SCPAZ)
ICL7660SCPAZ (Note 2) 7660S CPAZ 0 to +70 8 Ld PDIP (Pb-free; Note 4) E8.3
ICL7660SIBA (No longer available, recommended 7660 SIBA -40 to +85 8 Ld SOIC M8.15
replacement: ICL7660SIBAZ, ICL7660SIBAZ-T)
ICL7660SIBAZ (Notes 1, 2) 7660 SIBAZ -40 to +85 8 Ld SOIC (Pb-free) M8.15
ICL7660SIPA (No longer available, recommended 7660 SIPA -40 to +85 8 Ld PDIP E8.3
replacement: ICL7660SIPAZ)
ICL7660SIPAZ (Note 2) 7660S IPAZ -40 to +85 8 Ld PDIP (Pb-free; Note 4) E8.3
ICL7660ACBA (No longer available, recommended 7660ACBA 0 to 70 8 Ld SOIC (N) M8.15
replacement: ICL7660ACBAZA, ICL7660ACBAZA-T)
ICL7660ACBAZA (Notes 1, 2) 7660ACBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15
ICL7660ACPA (No longer available, recommended 7660ACPA 0 to 70 8 Ld PDIP E8.3
replacement: ICL7660ACPAZ)
ICL7660ACPAZ (Note 2) 7660ACPAZ 0 to 70 8 Ld PDIP (Pb-free; Note 4) E8.3
ICL7660AIBA (No longer available, recommended 7660AIBA -40 to 85 8 Ld SOIC (N) M8.15
replacement: ICL7660AIBAZA, ICL7660AIBAZA-T)
ICL7660AIBAZA (Notes 1, 2) 7660AIBAZ -40 to 85 8 Ld SOIC (N) (Pb-free) M8.15
NOTES:
1. Add “-T*” suffix for tape and reel. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.
3. For Moisture Sensitivity Level (MSL), see ICL7660S, ICL7660A device information pages. For more information about MSL, see TB363.
4. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications.

FN3179 Rev 7.01 Page 2 of 14

Feb 10, 2020
ICL7660S, ICL7660A

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V Thermal Resistance (Typical, Notes 6, 7) JA (°C/W) JC (°C/W)
LV and OSC Input Voltage (Note 5) 8 Ld PDIP (Note 8). . . . . . . . . . . . . . . . 110 59
V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V 8 Ld Plastic SOIC. . . . . . . . . . . . . . . . . 160 48
V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ -5.5V to V+ +0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Current into LV (Note 5) Pb-Free Reflow Profile (Note 8). . . . . . . . . . . . . . . . . . . . . . . TB493
V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20µA
Output Short Duration
VSUPPLY  5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous

Operating Conditions
Temperature Range
ICL7660SI, ICL7660AI . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ICL7660SC, ICL7660AC . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
5. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S and ICL7660A.
6. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For JC, the “case temp” location is taken at the package top center.
8. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in reflow solder processing applications.

Electrical Specifications ICL7660S and ICL7660A, V+ = 5V, TA = +25°C, OSC = Free running (see Figure 12 on page 7, “ICL7660S
Test Circuit”and Figure Figure 13 on page 7 “ICL7660A Test Circuit”), unless otherwise specified.

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 9) TYP (Note 9) UNITS

Supply Current (Note 11) I+ RL =  , +25°C - 80 160 µA

0°C < TA < +70°C - - 180 µA

-40°C < TA < +85°C - - 180 µA

-55°C < TA < +125°C - - 200 µA

Supply Voltage Range - High V+H RL = 10k, LV Open, TMIN < TA < TMAX 3.0 - 12 V
(Note 12)

Supply Voltage Range - Low V+L RL = 10k, LV to GND, TMIN < TA < TMAX 1.5 - 3.5 V

Output Source Resistance ROUT IOUT = 20mA - 60 100 

IOUT = 20mA, 0°C < TA < +70°C - - 120 

IOUT = 20mA, -25°C < TA < +85°C - - 120 

IOUT = 20mA, -55°C < TA < +125°C - - 150 

IOUT = 3mA, V+ = 2V, LV = GND, - - 250 

0°C < TA < +70°C

IOUT = 3mA, V+ = 2V, LV = GND, - - 300 

-40°C < TA < +85°C

IOUT = 3mA, V+ = 2V, LV = GND, - - 400 

-55°C < TA < +125°C

Oscillator Frequency (Note 10) fOSC COSC = 0, Pin 1 Open or GND 5 10 - kHz

COSC = 0, Pin 1 = V+ - 35 - kHz

Power Efficiency PEFF RL = 5k 96 98 - %

TMIN < TA < TMAX RL = 5k 95 97 - -

Voltage Conversion Efficiency VOUTEFF RL =  99 99.9 - %

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ICL7660S, ICL7660A

Electrical Specifications ICL7660S and ICL7660A, V+ = 5V, TA = +25°C, OSC = Free running (see Figure 12 on page 7, “ICL7660S
Test Circuit”and Figure Figure 13 on page 7 “ICL7660A Test Circuit”), unless otherwise specified. (Continued)

MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 9) TYP (Note 9) UNITS

Oscillator Impedance ZOSC V+ = 2V - 1 - M

V+ = 5V - 100 - k

ICL7660A, V+ = 3V, TA = 25°C, OSC = Free running, Test Circuit Figure 13, unless otherwise specified

Supply Current (Note 13) I+ V+ = 3V, RL =  , +25°C - 26 100 A

0°C < TA < +70°C - - 125 A

-40°C < TA < +85°C - - 125 A

Output Source Resistance ROUT V+ = 3V, IOUT = 10mA - 97 150 

0°C < TA < +70°C - - 200 

-40°C < TA < +85°C - - 200 

Oscillator Frequency (Note 13) fOSC V+ = 3V (same as 5V conditions) 5.0 8 - kHz

0°C < TA < +70°C 3.0 - - kHz

-40°C < TA < +85°C 3.0 - - kHz

NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, on the order of 5pF.
11. The ICL7660S and ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function in
existing designs that incorporate an external diode with no degradation in overall circuit performance.
12. All significant improvements over the industry standard ICL7660 are highlighted.
13. Derate linearly above 50°C by 5.5mW/°C.

FN3179 Rev 7.01 Page 4 of 14

Feb 10, 2020
ICL7660S, ICL7660A

Functional Block Diagram

V+
8

Q1
OSCILLATOR VOLTAGE
OSC AND DIVIDE-BY- LEVEL CAP+
7 2 COUNTER TRANSLATOR 2
Q2
GND
LV 3
6
CAP-
Q4 4
INTERNAL SUPPLY
REGULATOR VOUT
5
Q3
3 SUBSTRATE
LOGIC
3 NETWORK

Typical Performance Curves

See Figure 12 on page 7, “ICL7660S Test Circuit”) and Figure 13 on page 7 “ICL7660A Test Circuit”

12 250

TA = +125°C
10 OUTPUT SOURCE RESISTANCE (Ω)
200
SUPPLY VOLTAGE (V)

8 TA = +25°C
SUPPLY VOLTAGE RANGE
150
(NO DIODE REQUIRED)
6 TA = -55°C

100
4

2 50

0
0
-55 -25 0 25 50 100 125 0 2 4 6 8 10 12

TEMPERATURE (°C) SUPPLY VOLTAGE (V)

FIGURE 1. OPERATING VOLTAGE AS A FIGURE 2. OUTPUT SOURCE RESISTANCE AS A

FUNCTION OF TEMPERATURE FUNCTION OF SUPPLY VOLTAGE

350 98
POWER CONVERSION EFFICIENCY (%)

96
OUTPUT SOURCE RESISTANCE (Ω)

300 V+ = 5V
94 TA = +25°C
250 IOUT = 1mA
92
IOUT = 3mA,
200 IOUT = 20mA, V+ = 2V 90
V+ = 5V
88
150
IOUT = 20mA,
V+ = 5V 86
100
84
50 82
IOUT = 20mA,
V+ = 12V 80
0
-50 -25 0 25 50 75 100 125 100 1k 10k 50k
TEMPERATURE (°C) OSC FREQUENCY fOSC (Hz)

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FIGURE 4. POWER CONVERSION EFFICIENCY AS A

FUNCTION OF TEMPERATURE FUNCTION OF OSCILLATOR FREQUENCY

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ICL7660S, ICL7660A

Typical Performance Curves

See Figure 12 on page 7, “ICL7660S Test Circuit”) and Figure 13 on page 7 “ICL7660A Test Circuit” (Continued)

10 20
V+ = 5V

OSCILLATOR FREQUENCY fOSC (kHz)

OSCILLATOR FREQUENCY fOSC (kHz)

9
TA = +25°C 18
8

7 16
6
14
5
V+ = 10V
4 12
3
10
2
V+ = 5V
1 8
0
1 10 100 1k -55 -25 0 25 50 75 100 125
COSC (pF) TEMPERATURE (°C)

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

OF EXTERNAL OSCILLATOR CAPACITANCE FUNCTION OF TEMPERATURE

1 100 100
V+ = 5V POWER CONVERSION EFFICIENCY (%) 90 90
0 TA = +25°C
80 80

SUPPLY CURRENT (mA)

OUTPUT VOLTAGE (V)

70 70
-1
60 60

-2 50 50

40 40
-3 30 30

20 V+ = 5V 20
-4
10 TA = +25°C 10

-5 0 0
0 10 20 30 40 0 10 20 30 40 50 60
LOAD CURRENT (mA) LOAD CURRENT (mA)

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
OF OUTPUT CURRENT EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
2 100
V+ = 2V
90
TA = +25°C SUPPLY CURRENT (mA) (NOTE 14)
80 16
1
OUTPUT VOLTAGE (V)

POWER CONVERSION

70 14
EFFICIENCY (%)

60 12
0 50 10
40 8
30 6
-1 V+ = 2V
20 4
TA = +25°C
10 2
-2 0 0
0 1 2 3 4 5 6 7 8 9 0 1.5 3.0 4.5 6.0 7.5 9.0
LOAD CURRENT (mA) LOAD CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
CURRENT EFFICIENCY AS A FUNCTION OF LOAD CURRENT

FN3179 Rev 7.01 Page 6 of 14

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ICL7660S, ICL7660A

Typical Performance Curves

See Figure 12 on page 7, “ICL7660S Test Circuit”) and Figure 13 on page 7 “ICL7660A Test Circuit” (Continued)

V+ = 5V
C1 = C2 = 1mF
TA = +25°C
I = 10mA
400

OUTPUT RESISTANCE (Ω)

C1 = C2 = 10mF
300
C1 = C2 = 100mF

200

100

0
100 1k 10k 100k
OSCILLATOR FREQUENCY (Hz)

FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY

NOTE:
14. These curves include, in the supply current, that current fed directly into the load RL from the V+ (see Figure 12). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S and ICL7660A, goes to the negative side
of the load. Ideally, VOUT 2VIN, IS  2IL, so VIN x IS  VOUT x IL.

IS V+
V+ 1 8 (+5V)
IS V+ 2 7
1 8 (+5V) ICL7660A IL
C1 +
10µF 3 6
2 7 IL -
ICL7660S
C1 + 4 5 RL
3 6 RL
10µF -
COSC
4 5 -VOUT (NOTE)
-VOUT

C2 -
10µF + C2 -
10µF +

NOTE: For large values of COSC (>1000pF), the values of C1 and C2 NOTE: For large values of COSC (>1000pF) the values of C1 and C2
should be increased to 100µF. should be increased to 100µF.
FIGURE 12. ICL7660S TEST CIRCUIT FIGURE 13. ICL7660A TEST CIRCUIT

FN3179 Rev 7.01 Page 7 of 14

Feb 10, 2020
ICL7660S, ICL7660A

Detailed Description Theoretical Power Efficiency

The ICL7660S and ICL7660A contain all the necessary Considerations
circuitry to complete a negative voltage converter, with the In theory, a voltage converter can approach 100% efficiency if
exception of two external capacitors, which may be certain conditions are met:
inexpensive 10µF polarized electrolytic types. The mode of
operation of the device may best be understood by considering 1. The drive circuitry consumes minimal power.
Figure 14, which shows an idealized negative voltage 2. The output switches have extremely low ON resistance and
converter. Capacitor C1 is charged to a voltage, V+, for the half virtually no offset.
cycle, when switches S1 and S3 are closed. (Note: Switches 3. The impedance of the pump and reservoir capacitors are
S2 and S4 are open during this half cycle). During the second negligible at the pump frequency.
half cycle of operation, switches S2 and S4 are closed, with S1 The ICL7660S and ICL7660A approach these conditions for
and S3 open, thereby shifting capacitor C1 to C2 such that the negative voltage conversion if large values of C1 and C2 are
voltage on C2 is exactly V+, assuming ideal switches and no used. ENERGY IS LOST ONLY IN THE TRANSFER OF
load on C2. The ICL7660S and ICL7660A approach this ideal CHARGE BETWEEN CAPACITORS IF A CHANGE IN
situation more closely than existing non-mechanical circuits. VOLTAGE OCCURS. The energy lost is defined as shown in
8 S1 2 S2 Equation 1:
VIN
1
E = --- C 1  V 1 2 – V 2 2  (EQ. 1)
2
C1
3 3
where V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
C2 high at the pump frequency (see Figure 14) compared to the
S3 S4 5 value of RL, there will be a substantial difference in the
voltages, V1 and V2. Therefore it is not only desirable to make
4 VOUT = -VIN
C2 as large as possible to eliminate output voltage ripple, but
also to employ a correspondingly large value for C1 in order to
7
achieve maximum efficiency of operation.

FIGURE 14. IDEALIZED NEGATIVE VOLTAGE CONVERTER

Do’s and Don’ts
1. Do not exceed maximum supply voltages.
In the ICL7660S and ICL7660A, the four switches of Figure 14 2. Do not connect LV terminal to GND for supply voltage
are MOS power switches; S1 is a P-Channel device; and S2, greater than 3.5V.
S3 and S4 are N-Channel devices. The main difficulty with this 3. Do not short circuit the output to V+ supply for supply
approach is that in integrating the switches, the substrates of voltages above 5.5V for extended periods; however,
S3 and S4 must always remain reverse biased with respect to transient conditions including start-up are okay.
their sources, but not so much as to degrade their “ON” 4. When using polarized capacitors, the + terminal of C1 must
resistances. In addition, at circuit start-up, and under output be connected to pin 2 of the ICL7660S and ICL7660A, and
short circuit conditions (VOUT = V+), the output voltage must the + terminal of C2 must be connected to GND.
be sensed and the substrate bias adjusted accordingly. Failure 5. If the voltage supply driving the ICL7660S and ICL7660A
to accomplish this would result in high power losses and has a large source impedance (25 to 30), then a 2.2µF
probable device latch-up. capacitor from pin 8 to ground may be required to limit the
rate of rise of input voltage to less than 2V/µs.
This problem is eliminated in the ICL7660S and ICL7660A by a
logic network that senses the output voltage (VOUT) together 6. If the input voltage is higher than 5V and it has a rise rate
with the level translators, and switches the substrates of S3 and more than 2V/µs, an external Schottky diode from VOUT to
CAP- is needed to prevent latchup (triggered by forward
S4 to the correct level to maintain necessary reverse bias.
biasing Q4’s body diode) by keeping the output (pin 5) from
The voltage regulator portion of the ICL7660S and ICL7660A is going more positive than CAP- (pin 4).
an integral part of the anti-latchup circuitry; however, its 7. User should ensure that the output (pin 5) does not go more
inherent voltage drop can degrade operation at low voltages. positive than GND (pin 3). Device latch-up will occur under
Therefore, to improve low voltage operation, the “LV” pin these conditions. To provide additional protection, a 1N914
should be connected to GND, thus disabling the regulator. For or similar diode placed in parallel with C2 will prevent the
supply voltages greater than 3.5V, the LV terminal must be left device from latching up under these conditions, when the
open to ensure latchup-proof operation and to prevent device load on VOUT creates a path to pull up VOUT before the IC
is active (anode pin 5, cathode pin 3).
damage.

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ICL7660S, ICL7660A

Typical Applications Equation 4 shows a typical application where fOSC = 10kHz and
C = C1 = C2 = 10µF:
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the 1
R 0  2x23 + --------------------------------------------------- + 4xESR C1 + ESR C2
ICL7660S and ICL7660A for generation of negative supply 3 –6
5  10  10  10
(EQ. 4)
voltages. Figure 15 shows typical connections to provide a
R 0  46 + 20 + 5  ESR C
negative supply where a positive supply of +1.5V to +12V is
available. Keep in mind that pin 6 (LV) is tied to the supply Since the ESRs of the capacitors are reflected in the output
negative (GND) for supply voltage below 3.5V. impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/fPUMP x C1 term, rendering an
V+
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10.
1 8
10µF
2 7 Output Ripple
ICL7660S
+ ICL7660A ESR also affects the ripple voltage seen at the output. The
3 6
- RO VOUT peak-to-peak output ripple voltage is given by Equation 5:
4 5
- 1
V+ V RIPPLE   ----------------------------------------- + 2ESR C2  I OUT (EQ. 5)
2  f 
PUMP  C 2
- VOUT = -V+
+
10µF +
A low ESR capacitor will result in a higher performance output.
15A. 15B.
Paralleling Devices
FIGURE 15. SIMPLE NEGATIVE CONVERTER AND ITS
Any number of ICL7660S and ICL7660A voltage converters
OUTPUT EQUIVALENT
may be paralleled to reduce output resistance. The reservoir
The output characteristics of the circuit in Figure 15 can be capacitor, C2, serves all devices, while each device requires its
approximated by an ideal voltage source in series with a own pump capacitor, C1. The resultant output resistance is
resistance as shown in Figure 15B. The voltage source has a approximated in Equation 6:
value of -(V+). The output impedance (RO) is a function of the R OUT  of ICL7660S 
ON resistance of the internal MOS switches (shown in Figure R OUT = --------------------------------------------------------- (EQ. 6)
n  number of devices 
14), the switching frequency, the value of C1 and C2, and the
ESR (equivalent series resistance) of C1 and C2. A good first
Cascading Devices
order approximation for RO is shown in Equation 2:
The ICL7660S and ICL7660A may be cascaded as shown to
R 0  2   R SW1 + R SW3 + ESR C1  + 2  R SW2 + R SW4 + ESR C1   produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
1
-------------------------------- + ESR C2 (EQ. 2) the practical limit is 10 devices for light loads. The output
f PUMP  C 1
voltage is defined as shown in Equation 7:
f OSC
f PUMP = --------------  R SWX = MOSFET Switch Resistance  V OUT = – n  V IN  (EQ. 7)
2

where n is an integer representing the number of devices

Combining the four RSWX terms as RSW, we see in Equation 3 cascaded. The resulting output resistance would be
that: approximately the weighted sum of the individual ICL7660S
1 and ICL7660A ROUT values.
R 0  2xR SW + -------------------------------- + 4xESR C1 + ESR C2 (EQ. 3)
f PUMP  C 1
Changing the ICL7660S and ICL7660A Oscillator
RSW , the total switch resistance, is a function of supply voltage Frequency
and temperature (see the output source resistance graphs, It may be desirable in some applications, due to noise or other
Figures 2, 3, and 11), typically 23 at +25°C and 5V. Careful considerations, to alter the oscillator frequency. This can be
selection of C1 and C2 will reduce the remaining terms, achieved simply by one of several methods.
minimizing the output impedance. High value capacitors will
reduce the 1/(fPUMP x C1) component, and low ESR capacitors By connecting the Boost Pin (Pin 1) to V+, the oscillator charge
will lower the ESR term. Increasing the oscillator frequency will and discharge current is increased and, hence, the oscillator
reduce the 1/(fPUMP x C1) term, but may have the side effect of frequency is increased by approximately 3.5 times. The result
a net increase in output impedance when C1 > 10µF and is not is a decrease in the output impedance and ripple. This is of
long enough to fully charge the capacitors every cycle. major importance for surface mount applications where
capacitor size and cost are critical. Smaller capacitors, such as

FN3179 Rev 7.01 Page 9 of 14

Feb 10, 2020
ICL7660S, ICL7660A

0.1µF, can be used in conjunction with the Boost Pin to achieve VF, where V+ is the supply voltage and VF is the forward
similar output currents compared to the device free running voltage on C1, plus the supply voltage (V+) is applied through
with C1 = C2 = 10µF or 100µF. (see Figure 11). diode D2 to capacitor C2. The voltage thus created on C2
becomes (2V+) - (2VF) or twice the supply voltage minus the
Increasing the oscillator frequency can also be achieved by
combined forward voltage drops of diodes D1 and D2.
overdriving the oscillator from an external clock, as shown in
Figure 16. In order to prevent device latchup, a 1k resistor The source impedance of the output (VOUT) will depend on the
must be used in series with the clock output. In a situation output current, but for V+ = 5V and an output current of 10mA,
where the designer has generated the external clock frequency it will be approximately 60.
using TTL logic, the addition of a 10k pull-up resistor to V+
V+
supply is required. Note that the pump frequency with external
clocking, as with internal clocking, will be one-half of the clock 1 8
frequency. Output transitions occur on the positive going edge
2 7 D1
of the clock. ICL7660S
3 ICL7660A 6 D2 VOUT =
V+ V+ (2V+) - (2VF)
4 5 +
+ C2
1 8
C1
-
1kΩ -
CMOS
2 7 GATE
ICL7660S
+ ICL7660A
10µF 3 6 NOTE: D1 AND D2 CAN BE ANY SUITABLE DIODE.
-
4 5
- VOUT FIGURE 18. POSITIVE VOLTAGE DOUBLER
10µF
+
Combined Negative Voltage Conversion and
Positive Supply Doubling
FIGURE 16. EXTERNAL CLOCKING
Figure 19 combines the functions shown in Figure 15 and
Figure 18 to provide negative voltage conversion and positive
It is also possible to increase the conversion efficiency of the
voltage doubling simultaneously. This approach would be
ICL7660S and ICL7660A at low load levels by lowering the
suitable, for example, for generating +9V and -5V from an
oscillator frequency. This reduces the switching losses, and is
existing +5V supply. In this instance, capacitors C1 and C3
shown in Figure 17. However, lowering the oscillator frequency
perform the pump and reservoir functions, respectively, for
will cause an undesirable increase in the impedance of the
negative voltage generation, while capacitors C2 and C4 are
pump (C1) and reservoir (C2) capacitors; this is overcome by
pump and reservoir, respectively, for the doubled positive
increasing the values of C1 and C2 by the same factor by
voltage. There is a penalty in this configuration which
which the frequency has been reduced. For example, the
combines both functions, however, in that the source
addition of a 100pF capacitor between pin 7 (OSC and V+) will
impedances of the generated supplies will be somewhat
lower the oscillator frequency to 1kHz from its nominal
higher, due to the finite impedance of the common charge
frequency of 10kHz (a multiple of 10), and thereby necessitate
pump driver at pin 2 of the device.
a corresponding increase in the value of C1 and C2 (from 10µF
to 100µF). V+

V+ 1 8 VOUT = -VIN

2 7 -
ICL7660S D1 C3
1 8 + ICL7660A +
COSC C1 3 6
2 7 -
ICL7660S
+ 4 5
C1 3 ICL7660A 6
- D2
- + VOUT = (2V+) -
4 5 VOUT (VFD1) - (VFD2)
-
C2 C2 +
+ C
- 4
D3
FIGURE 17. LOWERING OSCILLATOR FREQUENCY
FIGURE 19. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
Positive Voltage Doubling
The ICL7660S and ICL7660A may be employed to achieve Voltage Splitting
positive voltage doubling using the circuit shown in Figure 18. The bidirectional characteristics can also be used to split a
In this application, the pump inverter switches of the ICL7660S high supply in half, as shown in Figure 20. The combined load
and ICL7660A are used to charge C1 to a voltage level of V+ - will be evenly shared between the two sides, and a high value

FN3179 Rev 7.01 Page 10 of 14

Feb 10, 2020
ICL7660S, ICL7660A

resistor to the LV pin ensures start-up. Because the switches Regulated Negative Voltage Supply
share the load in parallel, the output impedance is much lower In some cases, the output impedance of the ICL7660S and
than in the standard circuits, and higher currents can be drawn ICL7660A can be a problem, particularly if the load current
from the device. By using this circuit, and then the circuit of varies substantially. The circuit of Figure 21 can be used to
Figure 15, +15V can be converted, via +7.5 and -7.5, to a overcome this by controlling the input voltage, via an ICL7611
nominal -15V, although with rather high series output low-power CMOS op amp, in such a way as to maintain a
resistance (250Ω). nearly constant output voltage. Direct feedback is inadvisable,
since the ICL7660S’s and ICL7660A’s output does not respond
V+
+
instantaneously to change in input, but only after the switching
RL1 50µF
-
delay. The circuit shown supplies enough delay to
1 8 accommodate the ICL7660S and ICL7660A, while maintaining
VOUT = V+ - V- 2 7
adequate feedback. An increase in pump and storage
2 ICL7660S
+ ICL7660A capacitors is desirable, and the values shown provide an
50µF 3 6
- output impedance of less than 5Ω to a load of 10mA.
RL2 4 5
+
50µF Other Applications
-
V- Further information on the operation and use of the ICL7660S
and ICL7660A may be found in application note AN051,
FIGURE 20. SPLITTING A SUPPLY IN HALF
“Principles and Applications of the ICL7660 CMOS Voltage
Converter”.

+8V 50k

56k -
+8V 10µF
50k 100 +
-
100k ICL7611
+
1 8

2 7
ICL7660S
ICL8069 + ICL7660A
100µF 3 6
-
4 5 VOUT

800k -
250k 100µF
VOLTAGE +
ADJUST

FIGURE 21. REGULATING THE OUTPUT VOLTAGE

Revision History
Rev. Date Description
7.01 Feb 10, 2020 Updated Ordering Information table.
Added Revision History
Updated Disclaimer.

FN3179 Rev 7.01 Page 11 of 14

Feb 10, 2020
ICL7660S, ICL7660A

Package Outline Drawings For the most recent package outline drawing, see E8.3.

N
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
SEATING
B 0.014 0.022 0.356 0.558 -
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.355 0.400 9.01 10.16 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between
e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated
N 8 8 9
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

FN3179 Rev 7.01 Page 12 of 14

Feb 10, 2020
ICL7660S, ICL7660A

M8.15 For the most recent package outline drawing, see M8.15.
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12

DETAIL "A"
1.27 (0.050)
0.40 (0.016)

INDEX 6.20 (0.244)

AREA 5.80 (0.228)
0.50 (0.20)
x 45°
4.00 (0.157) 0.25 (0.01)
3.80 (0.150)

8°
1 2 3 0°

0.25 (0.010)
0.19 (0.008)
TOP VIEW SIDE VIEW “B”

2.20 (0.087)

1 8
SEATING PLANE

1.75 (0.069) 0.60 (0.023)

5.00 (0.197) 2 7
4.80 (0.189) 1.35 (0.053)
1.27 (0.050)

3 6
-C-

4 5
1.27 (0.050) 0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013) 5.20(0.205)

SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN

NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

FN3179 Rev 7.01 Page 13 of 14

Feb 10, 2020
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ICL7660SCBAZ ICL7660SCBAZ-T ICL7660SIBAZ ICL7660SIBAZT ICL7660ACBAZA ICL7660ACBAZA-T
ICL7660ACPAZ ICL7660AIBAZA ICL7660AIBAZA-T ICL7660CBAZ ICL7660CBAZA ICL7660CBAZA-T
ICL7660CBAZ-T ICL7660CPAZ ICL7660SCPAZ ICL7660SIPAZ