UNIT 1:- Data Processing Circuits

Introduction to Multiplexers-
Multiplexing is the property of combining one or more signals and
transmitting on a single channel .This is achieved by the device multiplexer. A multiplexer is
the most frequently used combinational circuits and important building block in many in
digital systems.

These are mostly used to form a selected path between multiple sources and a single
destination. A basic multiplexer has various data input lines and a single output line. These
are found in many digital system applications such as data selection and data routing, logic
function generators, digital counters with multiplexed displays, telephone network,
communication systems, waveform generators, etc. In this article we are going to discuss
about types of multiplexers and its design.

The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational
circuit with more than one input line, one output line and more than one select line. It allows
the binary information from several input lines or sources and depending on the set of select
lines, particular input line, is routed onto a single output line.

The below figure shows the block diagram of a multiplexer consisting of m input lines, n
selection lines and one output line. If there are n selection lines, then the number of possible
input lines is 2n. Alternatively we can say that if the number of input lines is equal to 2n, then
n selection lines are required to select one of m (consider 2n = m) input lines.

This type of multiplexer is referred to as 2n × 1 multiplexer or 2n -to-1 multiplexer. For

example, if one of the 4 input lines has to be selected, then two select lines are required.
Similarly, to select one of 8 input lines, three select lines are required.
Generally a strobe (or enable) input in corporate which helps in cascading and it is generally
active low which means it performs its intended operation when it is low.
The single pole multi-position switch is a simple example of non-electronic circuit of
multiplexer, and it is widely used in many electronic circuits. The multiplexer is used to
perform high-speed switching and is constructed by electronic components.
Multiplexers are capable of handling both analog and digital applications. In analog
applications, multiplexers are made up of relays and transistor switches, whereas in digital
Applications, the multiplexers are built from standard logic gates. When the multiplexer is
used for digital applications, it is called a digital multiplexer.
Standard ICs are available for. 2:1 MUX, 4:1 MUX, 8:1 MUX and 16:1 MUX.

Multiplexer Types
Multiplexers are classified into four types:
 2:1 Multiplexer ( 1select line)
 4:1 Multiplexer (2 select lines)
 8:1 Multiplexer(3 select lines)
 16:1 Multiplexer (4 select lines)
Designing Of 2:1 Multiplexer:-
A multiplexer (or MUX) is a common digital circuit used to mix a lot of signals into
just one. If you want multiple sources of data to share a single, common data line, you’d use a
multiplexer to run them into that line. Multiplexers come in all sorts of shapes and sizes, but
they’re all made out of logic gates.
A 2:1 multiplexer consists of two inputs I 0 and I 1, one select input S and one output Y.
Depends on the select signal, the output is connected to either of the inputs. Since there are
two input signals only two ways are possible to connect the inputs to the outputs, so one
select is needed to do these operations.
If the select line is low, then the output will be switched to I 0 input, whereas if select line is
high, then the output will be switched to I 1input.
The truth table of the 2-to-1 multiplexer is shown below. Depending on the selector switching
the inputs are produced at outputs, i.e. I 0, I 1 and are switched to the output for S=0 and S=1
respectively . Thus, the Boolean expression for the output becomes I 0 when S=0 and output is
I 1 when S=1.

Input Output
S Y

0 I0
1 I1

The Truth Table Of 2:1 MUX

From the truth table the Boolean expression of the output is given as
Y =I 0 S + I 1 S

From the above output expression, the logic circuit of 2-to-1 multiplexer can be implemented
using logic gates as shown in figure. It consists of two AND gates, one NOT gate and one OR
gate. When the select line, S=0, the output of the upper AND gate is zero, but the lower AND
gate is I 0.

Thus, the output generated by the OR gate is equal to I 0. Similarly, when S=1, the output of
the lower AND gate is zero, but the output of upper AND gate is I 1. Therefore, the output of
the OR gate is I 1. Thus, the above given Boolean expression is satisfied by this circuit.

(c) Truth Table

Fig.(a) Shows Functional Block Diagram And Fig.(b) is Logic Diagram Of 2:1 Multiplexer
Designing Of 4:1 Multiplexer:-
In 4:1 Multiplexer consists are four data input lines I 0 , I 1 , I 2∧I 3 two select lines as S0
and S1 and a single output line Y. The select lines S0 ∧S 1 select one of the four input lines to
connect the output line. The particular input combination on select lines selects one of input (
I 0 through I 3) to the output. Here two select inputs are required as 22= 4 where and each
number of select lines
i.e. n=2. To construct
The Boolean expression for this 4-to-1 Multiplexer with inputs I 0 ¿ I 3 and data select lines
S0 , S 1 is given as:
Y =S 1 S0 I 0+ S 1 S0 I 1 + S1 S 0 I 2 +S 1 S 0 I 3
At any one instant in time only ONE of the four analogue switches is closed, connecting only
one of the input lines I 0 ¿ I 3 to the single output at Y. As to which switch is closed depends
upon the addressing input code on lines S0 and S1
The block diagram and the truth table of a 4-to-1 multiplexer is shown below in which four
input combinations 00, 10, 01 and 11 on the select lines respectively switches the inputs
I 0 , I 1 , I 2∧I 3 to the output. That means when S1=0 and S0 =0, the output at Y is I 0, similarly Y
is I 1 if the select inputs S1=0 and S0= 1 and so on

From the above expression of the output, a 4-to-1 multiplexer can be implemented by using
basic logic gates. The below figure shows the logic circuit of 4:1 MUX which is implemented
by four 3-inputs AND gates, two 1-input NOT gates, and one 4-inputs OR gate.

In this circuit, each data input line is connected as input to an AND gate and two select lines
are connected as other two inputs to it. The AND gate output is connected to with inputs of
OR gate so as to produce the output Y.

Adding more control address lines, (n) will allow the multiplexer to control more inputs as it
can switch 2n inputs but each control line configuration will connect only ONE input to the
output.

4:1 Multiplexer using Logic Gates

Designing Of 8:1 Multiplexer:-

The 8:1 multiplexer consists of 8 input lines I 0 , I 1 , … I 7, Three selection lines S0 , S 1 , S2 and
one output line Y. Depending on the select lines combinations, multiplexer decodes the
inputs.

The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that
enable or disable the multiplexer. Since the number data bits given to the MUX are eight then
3 bits (23=8) are needed to select one of the eight data bits.

The truth table for an 8-to1 multiplexer is given below with eight combinations of inputs so
as to generate each output corresponds to input.

For example, if S0 =0 , S 1=1 and S2=0 then the data output Y is equal to I 2. Similarly the
data outputs I 0 to I 7 will be selected through the combinations of S2 , S 1∧S 0as shown in below
figure.
From the above truth table, the Boolean equation for the output is given as

Y =I 0 S 2 S1 S 0 + I 1 S2 S 1 S0 + I 2 S 2 S1 S 0+ I 3 S 2 S 1 S0 + I 4 S 2 S1 S 0 + I 5 S2 0 dataoutputs D isequal ¿ D2 ng on selected input combin

For the combination of selection input, the data line is connected to the output line.
The circuit shown below is an 8:1 multiplexer. The 8:1 multiplexer requires 8 AND gates,
one OR gate and 3 selection lines. As an input, the combination of selection inputs are giving
to the AND gate with the corresponding input data lines.
In a similar fashion, all the AND gates are given connection. In this 8:1 multiplexer, for any
selection line input, one AND gate gives a value of 1 and the remaining all AND gates give 0.
And, finally, by using OR gate, all the AND gates are added and, this will be equal to the
selected value.

Application of Multiplexer

In all types of digital system applications, multiplexers find its immense usage. Since these
allows multiple inputs to be connected independently to a single output, these are found in
variety of applications including data routing, logic function generators, control sequencers,
parallel-to-serial converters, etc.

Introduction to Demultiplexers:-
The action or operation of a demultiplexer is opposite to that of the multiplexer. As
inverse to the MUX, demux is a one-to-many circuit. With the use of a demultiplexer, the
binary data can be bypassed to one of its many output data lines.

Demultiplexers are mainly used in Boolean function generators and decoder circuits.
Different input/output configuration demultiplexers are available in the form of single
integrated circuits (ICs).Also, the facility of cascading two or more IC circuit’s helps to
generate multiple output demultiplexers. Let us get a brief idea of demultiplexers and its
types.

The process of getting information from one input and transmitting the same over one
of many outputs is called demultiplexing. A demultiplexer is a combinational logic circuit
that receives the information on a single input and transmits the same information over one of
2n possible output lines.

The bit combinations of the select lines control the selection of specific output line to be
connected to the input at given instant. The below figure illustrates the basic idea of
demultiplexer, in which the switching of the input to any one of the four outputs is possible at
a given instant.

Demultiplexers are also called as data distributors, since they transmit the same data which is
received at the input to different destinations.
Thus, a demultiplexer is a 1-to-N device where as the multiplexer is an N-to-1 device. The
figure below shows the block diagram of a demultiplexer or simply a DEMUX.

It consists of 1 input line, m output lines and n select lines. In this, n selection lines are
required to produce 2n possible output lines (consider 2n = m). For example, a 1-to-4
demultiplexer requires 2 (22) select lines to control the 4 output lines.

There are several types of demultiplexers based on the output configurations such as 1:2, 1:4,
and 1:8.

Demultiplexer Types
Demultiplexers are classified into four types:
 1:2 Demultiplexer ( 1select line)
 1:4 Demultiplexer (2 select lines)
 1:8 Demultiplexer (3 select lines)
 1:16 Demultiplexer (4 select lines)

Designing Of 1:2 Demultiplexer:-

A 1:2 demultiplexer consists of one input line, two output lines and one select line.
The signal on the select line helps to switch the input to one of the two outputs. The figure
below shows the block diagram of a 1:2 demultiplexer with additional enable input.

In the figure, there are only two possible ways to connect the input to output lines, thus only
one select signal is enough to do the demultiplexing operation. When the select input is low,
then the input will be passed to Y 0 and if the select input is high then the input will be passed
to Y 1.
The truth table of a 1:2 demultiplexer is shown below in which the input is routed to Y 0 and
Y 1depends on the value of select input S. In the table output Y 1 is active when the
combination of select line and input line are active high

From the above truth table, the logic diagram of this demultiplexer can be designed by using
two AND gates and one NOT gate as shown in below figure. When the select lines S=0,
AND gate A1is enabled while A2 is disabled.

Then, the data from the input flows to the output line Y 1. Similarly, when S=1, AND gate A2
is enabled and AND gate A1 is disabled, thus data is passed to the Y 0 output.

Designing Of 1:4 Demultiplexer:-

A 1-to-4 demultiplexer has a single input (D), two selection lines ( S1∧S 0) and four
outputs (Y 0 ¿ Y 3). The input data goes to any one of the four outputs at a given time for a
particular combination of select lines.

This demultiplexer is also called as a 2-to-4 demultiplexer which means that two select lines
and 4 output lines. The block diagram of 1:4 DEMUX is shown below.
The truth table of this type of demultiplexer is given below. From the truth table it is clear
that, when S1=0∧S0 =0, the data input is connected to output Y 0 and when S1= 0 and S0=1,
then the data input is connected to output Y 1.

Similarly, other outputs are connected to the input for other two combinations of select lines.

From the table, the output logic can be expressed as min terms and are given below.
Y 0=S 1 S0 D
Y 1=S1 S 0 D
Y 2 = S1 S 0 D
Y 3=S 1 S0 D
Where D is the input data, Y 0 to Y 3 are output lines and S0 ∧S 1 are select lines.
From the above Boolean expressions, a 1:4 demultiplexer can be implemented by using four
3-input AND gates and two NOT gates as shown in figure below. The two selection lines
enable the particular gate at a time.
So depends on the combination of select inputs, input data is passed through the selected gate
to the associated output

Designing Of 1:8 Demultiplexer:-

The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of
single input D, three select inputs S2 , S 1∧S 0and eight outputs from Y 0 ¿ Y 7.

It is also called as 3-to-8 demultiplexer due to three select input lines. It distributes one input
line to one of 8 output lines depending on the combination of select inputs.

The truth table for this type of demultiplexer is shown below. The input D is connected with
one of the eight outputs from Y 0 ¿ Y 7 based on the select lines S2 , S 1∧S 0.

For example, if S2 , S 1 , S 0=000, then the input D is connected to the output Y 0 and so on.
From this truth table, the Boolean expressions for all the outputs can be written as follows.

Y 0= D S2 S 1 S 0
Y 1=D S2 S 1 S0
Y 2=D S2 S 1 S0
Y 3=D S2 S 1 S0
Y 4 =D S 2 S1 S 0
Y 5=D S2 0 data outputs D isequal ¿ D2 ng on selected input combinations ¿ S1 S 0
Y 6= D S2 S 1 S 0
Y 7= D S2 S 1 S 0
From these obtained equations, the logic diagram of this demultiplexer can be implemented
by using eight AND gates and three NOT gates as shown in below figure. The different
combinations of the select lines , select one AND gate at given time , such that data input will
appear at a particular output.
Encoders:-
A binary encoder has 2ninput lines and n output lines, hence it encodes the
information from 2n inputs into an n-bit code. From all the input lines, only one of an input
line is activated at a time, and depending on the input line, it produces the n bit output code.

The figure below shows the block diagram of binary encoder which consists of 2n input lines
and n output lines. It translates decimal number to binary number.

The output lines of an encoder correspond to either true binary equivalent or in BCD coded
form of the binary for the input value. Some of these binary encoders include decimal to
binary encoders, decimal to octal, octal to binary encoders, decimal to BCD encoders, etc
Decimal to BCD Encoder

This type of encoder usually consists of ten input lines and 4 output lines. Each input
line corresponds to the each decimal digit and 4 outputs correspond to the BCD code.

This encoder accepts the decoded decimal data as an input and encodes it to the BCD output
which is available on the output lines.

The figure below shows the basic logic symbol of decimal to BCD encoder along with its
truth table. The truth table represents the BCD code for each decimal digit.

From this we can formulate the relationship between the BCD bit and decimal digit. It is
important to note that there is no explicit input line for decimal zero. When this condition
occurs, i.e., decimal inputs 1 to 9 all are zero, then the BCD output is 0000.

From the above table, we get the expressions as

D = D8 + D9

C = D4 + D5 + D6 + D7

B = D2 + D3 + D6 + D7

A = D1 + D3 + D5 + D7 + D9

From the above expressions, the decimal to BCD encoder logic circuit can be implemented
by using set of OR gates as shown in below figure.
Priority Encoder:-
The Priority Encoder solves the problems mentioned above by allocating a priority
level to each input. The priority encoders output corresponds to the currently active input
which has the highest priority. So when an input with a higher priority is present, all other
inputs with a lower priority will be ignored.

The priority encoder comes in many different forms with an example of an 8-input priority
encoder along with its truth table shown below.

Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit
priority encoder which has eight active LOW (logic “0”) inputs and provides a 3-bit code of
the highest ranked input at its output.
Priority encoders output the highest order input first for example, if input lines “D2“, “D3”
and “D5” are applied simultaneously the output code would be for input “D5” (“101”) as this
has the highest order out of the 3 inputs. Once input “D5” had been removed the next highest
output code would be for input “D3” (“011”), and so on.
The truth table for a 8-to-3 bit priority encoder is given as:
Where X equals “don’t care”, that is logic “0” or a logic “1”.

From this truth table, the Boolean expression for the encoder above with data inputs D0 to D7
and outputs Q0, Q1, Q2 is given as:

Priority Encoder Output Expression

BCD to Decimal decoder
BCD is an abbreviation for binary-coded decimal. The BCD code expresses each digit
in a decimal number
by its nibble equivalent. For instance, decimal number 429 is changed to its BCD form as
follows:

The circuit of Fig. 4.18 is called a l-of-10 decoder because only 1 of the 10 output lines is
high. For instance, when ABCD is 0011, only the Y3 AND gate has all high inputs; therefore,
only the Y3 output is high, If ABCD changes to 1000, only the Y8 AND gate has all high
inputs; as a result, only the Y8 output goes high. If you check the other ABCD possibilities
(0000 to 1001), you will find that the subscript of the high output always equals the decimal
equivalent of the input BCD digit. For this reason, the circuit is also called a BCD-to-decimal
converter.
BCD to Seven segment decoder

In Binary Coded Decimal (BCD) encoding scheme each of the decimal numbers(0-9) is
represented by its equivalent binary pattern(which is generally of 4-bits).

Whereas, Seven segment display is an electronic device which consists of seven Light
Emitting Diodes (LEDs) arranged in a some definite pattern (common cathode or common
anode type), which is used to display Hexadecimal numerals(in this case decimal numbers, as
input is BCD i.e., 0-9).

Two types of seven segment LED display:

 1. Common Cathode Type: In this type of display all cathodes of the seven LEDs are
connected together to the ground or -Vcc(hence, common cathode) and LED displays
digits when some ‘HIGH’ signal is supplied to the individual anodes.
2. Common Anode Type: In this type of display all the anodes of the seven LEDs are
connected to battery or +Vcc and LED displays digits when some ‘LOW’ signal is
supplied to the individual cathodes.

But, seven segment display does not work by directly supplying voltage to different segments
of LEDs. First, our decimal number is changed to its BCD equivalent signal then BCD to
seven segment decoder converts that signals to the form which is fed to seven segment
display.

This BCD to seven segment decoder has four input lines (A, B, C and D) and 7 output lines
(a, b, c, d, e, f and g), this output is given to seven segment LED display which displays the
decimal number depending upon inputs.

Truth Table – For common cathode type BCD to seven segment decoder: