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Module 4
Syllabus:
Flip-flops: SR, JK, T and D. Triggering of flip-flops- Master slave flip- flops, Edge- triggered flip- flops.
Excitation table and characteristic equation.
Registers: register with parallel load.
Counter design: Asynchronous counters- Binary and BCD counters, timing sequences and state
diagrams. Synchronous counters- Binary Up- down counter, BCD counter.

1. Combinational Logic Circuits

 Digital electronics is classified into combinational logic and Sequential Logic Circuits.
 Combinational logic output depends on the present inputs levels, whereas sequential logic
output not only depends on the input levels, but also stored levels (previous output history).

Fig. Block Diagram of Combinational Circuit

 Sequential circuit is a combination of a combinational circuit with memory

 The memory elements are devices capable of storing binary information within them.
 The binary information stored in the memory elements at any given time defines the state
of the sequential circuit.
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 Comparison of Combinational Logic Circuits and Sequential Logic Circuits

 There are two types of sequential circuits. Their classification depends on the timing of their
signals:
1. Synchronous Sequential Circuits
2. Asynchronous Sequential Circuits

 Synchronous Sequential Circuit

 A sequential circuit whose output behavior depends on the input at a discrete-time is called
synchronous sequential circuits.
 Synchronous sequential circuits that use clock pulses in the inputs of memory elements are
called clocked sequential circuits.
 In which the feedback to the input for next output generation is governed by clock signals.
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 Asynchronous Sequential Circuits
 The sequential circuit whose output depends on the sequence in which the input changes are
called asynchronous sequential circuits.

2. Flip Flops
 Asynchronous sequential circuit This is a system whose outputs depend upon the order in
which its input variables change and can be affected at any instant of time.
 Flip-flop is a circuit that maintains a state until directed by input to change the state.
 A circuit that has two stable states is treated as a flip flop.
 These stable states are used to store binary data that can be changed by applying varying
inputs.
 The flip flops are the fundamental building blocks of the digital system.
 Types of flip-flops:
a) SR Flip Flop
b) D Flip Flop
c) JK Flip Flop
d) T Flip Flop
a) S-R Flip Flop
 The S-R flip flop is the most common flip flop used in the digital system.
 In SR flip flop, when the set input "S" is true, the output Y will be high, and Y' will be
low.
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Excitation Table
 During the design process we usually know the transition from present state to next state and
wish to find the latch input conditions that will cause the required transition.
 For this reason, we need a table that lists the required inputs for a given change of state. Such
a table is called an excitation table, and it specifies the excitation behavior of the sequential
circuits.
 The excitation of the SR flip flop is as follows:

b) D Flip Flop
 D flip flop is a slight modification of SR flip-flop.
 From the figure you can see that the D input is connected to the S input and the complement
of the D input is connected to the R input.

 If CLK '0', the flip flop switches to the CLEAR state.

 The D input is passed on to the flip flop when the value of CLK is '1'.
 If D = 1, the Q output goes to 1. If D = 0, the Q output goes to 0.
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c) J-K Flip Flop

 A J-K flip-flop is improved version of the SR Flip Flop and prevents the circuit from going
in an invalid state.
 The JK flip-flop is named after his inventor known as Jack Kilby from Texas Instruments.
 The JK Flip-flop is also widely known as a programmable flip-flop as it can disguise other
flip-flops based on the inputs applied.
 It is nothing more than an S-R flip-flop with an added layer of feedback.
 This feedback selectively enables one of the two set/reset inputs so that they cannot both
carry an active signal to the output, thus eliminating the invalid condition.
 The letter J stands for SET and the letter K stands for CLEAR.
 When both the inputs J and K have a HIGH state, the flip-flop switches to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1.
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d) T Flip Flop
 This is a much simpler version of the J-K flip flop.
 Both the J and K inputs are connected together and thus are also called a single input J-K flip
flop.
 When clock pulse is given to the flip flop, the output begins to toggle.


 The next sate of the T flip flop is similar to the current state when the T input is set to 0.
 If toggle input is set to 0 and the present state is also 0, the next state will be 0.
 If toggle input is set to 0 and the present state is 1, the next state will be 1.
 The next state of the flip flop is opposite to the current state when the toggle input is set to 1.
 If toggle input is set to 1 and the present state is 0, the next state will be 1.
 If toggle input is set to 1 and the present state is 1, the next state will be 0.
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 Timing Diagram of JK Flip Flop

Race Around Condition

 For J-K flip-flop, if J=K=1, and if CLK=1 for a long period of time, then Q output will
toggle as long as CLK is high, which makes the output of the flip-flop unstable or uncertain.
 This problem is called race around condition in J-K flip-flop.
 This problem can be avoided by ensuring that the clock input is at logic “1” only for a very
short time.
 This introduced the concept of Master Slave JK flip flop.

3. Master Slave JK flip flop

 The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected
together in a series configuration.
 Out of these, one acts as the “master” and the other as a “slave”.
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 The output from the master flip flop is connected to the two inputs of the slave flip flop whose
output is fed back to inputs of the master flip flop
 When the clock makes a positive transition the master section is triggered but the slave section is
not because its clock is inverted. Ie when the clock pulse is 1, the slave flip flop will be in the
isolated state.

Figure : Timing Diagram of Master Slave JK Flip Flop

4. Triggering of Flip Flops

 The state of a flip-flop is changed by a change in the input signal.
 This change is called a trigger and the transition it causes is said to trigger the flip-flop.
 This small change can be brought with the help of a clock pulse or commonly known as a
trigger pulse.
 There are mainly four types of pulse-triggering methods.
a) High Level Triggering
b) Low Level Triggering
c) Positive Edge Triggering
d) Negative Edge Triggering

a) High Level Triggering

 When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is
used.
 It is mainly identified from the straight lead from the clock input.
 Take a look at the symbolic representation shown below.
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b) Low Level Triggering

 When a flip flop is required to respond at its LOW state, a LOW level triggering method is
used.
 It is mainly identified from the clock input lead along with a low state indicator bubble.
 Take a look at the symbolic representation shown below.

c) Positive Edge Triggering

 When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE
edge triggering method is used.
 It is mainly identified from the clock input lead along with a triangle.
 Take a look at the symbolic representation shown below.

d) Negative Edge Triggering

 When a flip flop is required to respond during the HIGH to LOW transition state, a
NEGATIVE edge triggering method is used.
 It is mainly identified from the clock input lead along with a low-state indicator and a
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triangle.
 Take a look at the symbolic representation shown below.

5. Binary Counter
 A Counter is a device which stores the number of times a particular event or process has
occurred, often in relationship to a clock signal.
 Counters are sequential circuit that count the number of pulses can be either in binary code or
BCD form.
 Counters are used in digital electronics for counting purpose, they can count specific event
happening in the circuit.
 They can also be designed with the help of flip flops.
 The main properties of a counter are timing, sequencing, and counting.
 Counter works in two modes Up counter and Down counter.
 Counters are broadly divided into two categories depending upon clock pulse applied.
1. Asynchronous counter
2. Synchronous counter
 In Asynchronous Counter is also known as Ripple Counter, different flip flops are triggered
with different clock, not simultaneously. While in Synchronous Counter, all flip flops are
triggered with same clock simultaneously.
 Synchronous Counter is faster than asynchronous counter in operation.
 Depending on the way in which the counting progresses, the synchronous or asynchronous
counters are classified as follows –
1. Up counters
2. Down counters
3. Up/Down counters
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Comparison of Synchronous Counter and Asynchronous Counter

Sl.No. Synchronous Counter Asynchronous Counter

In synchronous counter, all flip flops In asynchronous counter, different flip flops
1 are triggered with same clock are triggered with different clock, not
simultaneously. simultaneously.
Synchronous Counter is faster than Asynchronous Counter is slower than
2
asynchronous counter in operation. synchronous counter in operation.
Synchronous Counter does not Asynchronous Counter produces decoding
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produce any decoding errors. error.
Synchronous Counter is also called Asynchronous Counter is also called Serial
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Parallel Counter. Counter.
Synchronous Counter designing as
Asynchronous Counter designing as well as
5 well implementation are complex due
implementation is very easy.
to increasing the number of states.
Synchronous Counter will operate in Asynchronous Counter will operate only in
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any desired count sequence. fixed count sequence (UP/DOWN).
In synchronous counter, propagation In asynchronous counter, there is high
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delay is less. propagation delay.
Synchronous Counter examples are: Asynchronous Counter examples are: Ripple
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Ring counter, Johnson counter. UP counter, Ripple DOWN counter.

1. Asynchronous Counter

Asynchronous counter basics:

Figure : 1 bit asynchronous/ripple counter

 When -ve edge clock pulse is applied and input is given to FF logic 1 then the output state of
FF will toggle for every falling edge.
 It is known as binary or mod -2 counter or bit ripple counter.
 It has 2 unique output states (0 and 1).
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Up Counter:

 When two FFs are connected in series and output of one FF is act as clock for 2nd FF.
 When the output state (i.e. Q) of previous FF is feed as clock to next FF then the counter will
perform up counting.

Figure : 2 bit asynchronous Up counter.

 The state of 2nd FF will change only when output of the 1st FF is logic 0
 It can generate 4 different unique states. This is known as divide by 4 circuits or mod 4
ripple counter.
 The first negative-going edge of CLK (clock pulse) causes the Q0 output of FF1 to go
HIGH but it has no effect on FF2
After first negative-going edge - Q1Q0 is 01
 In the second negative-going edge of CLK causes Q0 to go LOW and triggers FF2, causing
Q1 to go HIGH.
After second negative-going edge - Q1Q0 is 10
 In the third negative-going edge of CLK causes Q0 to go HIGH again, it has no effect on
FF2.
After third negative-going edge - Q1Q0 is 11
 In the fourth negative-going edge of CLK causes Q0 to go LOW, and triggers FF2 causing
Q1 to go LOW.
After fourth negative-going edge - Q1Q0 is 00
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Down Counter:

 When the complemented output state (i.e. Q’) of previous FF is feed as clock to next FF then
the counter will perform down counting

 The state of 2nd FF will change only when output of the 1st FF is logic 1
 The first negative-going edge of CLK (clock pulse) causes the Q0 output of FF1 to go
HIGH and Q0’ goes to LOW , it triggers FF2 causing Q1 to toggle from 0 to 1.
After first negative-going edge - Q1Q0 is 11
 In the second negative-going edge of CLK causes Q0 to go LOW and Q0’ goes to HIGH, it
has no effect on FF2.
After second negative-going edge - Q1Q0 is 10
 In the third negative-going edge of CLK causes Q0 to go HIGH and Q0’ goes to LOW , it
triggers FF2 causing Q1 to toggle from 1 to 0.
After third negative-going edge - Q1Q0 is 01
 In the fourth negative-going edge of CLK causes Q0 to go LOW, and Q0’ goes to HIGH, it
has no effect on FF2.
After fourth negative-going edge - Q1Q0 is 00
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3 Bit Asynchronous UP Counter

Three FFs are connected in series and output of one FF is act as clock for next FF.

When the output state (i.e. Q) of previous FF is feed as clock to next FF then the counter will perform up
counting.

Truth Table for 3 bit UP counter

Logic Diagram for 3 bit UP counter

 When the first clock pulse is applied, the FF1 changes state on its negative edge.
Therefore, Q2Q1Q0 = 001
 On the negative edge of second clock pulse flip flop FF1 toggle, its output changes from 1 to 0.
This triggers the FF2 and it changes state.
Therefore, Q2Q1Q0 = 010
 Similarly, the output of flip flop FF3 changes only when there is negative transition at its input
when fourth clock pulse is applied.
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Timing Diagram for 3 bit UP counter

Exercise :

3 Bit Asynchronous DOWN Counter

Asynchronous Up/Down counter:

 Up/Down counter is the combination of both the counters in which we can perform up or
down counting by changing the Mode control input.
Design of 3 bit Asynchronous up/down counter:

 In this a mode control input (say M) is used for selecting up and down mode.
 A combinational circuit is required between each pair of flip-flop to decide whether to do up
or do down counting.
n n
 For n = 3, i.e for 3 bit counter Maximum count = 2 -1 and number of states are 2

Steps involve in design are :

Step 1 : Decision for Mode control input

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When M = 0, then Y= Q, therefore it will perform Up counting.
When M = 1, then Y= Q’ therefore it will perform Down counting
So the all possible combinations are:

K-map for finding output Y that will be given as clock to next FF

Step 2 : Insertion of Combinational logic between every pair of FFs

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Timing diagram :
Initially Q3 = 0, Q2 = 0, Q1 = 0.

Case 1 – When M=0, then M’ =1

Put this in Y= M’Q + MQ’= Q So Q is acting as clock for next FFs.
Therefore; the counter will act as Up counter.
Explanation of Up counter –
 The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
 The 2nd FF input is connected to Q1.Therefore it changes its state when Q 1= 1 and there
is falling edge of clock.
 Similarly, 3rd FF is connected to Q 2. Therefore, it changes its state when Q 2= 1 and there
is falling edge of clock.
 By this we can generate counting states of Up counter.
 After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
Case 2 – When M=1, then M’ =0
Put this in Y= M’Q + MQ’= Q’ So Q’ is acting as clock for next FFs.
Therefore, the counter will act as Down counter.
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Explanation of Down counter –

 The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
 The 2nd FF input is connected to Q’1.Therefore it changes its state when Q’1= 1 and there
is falling edge of clock.
 Similarly, 3rd FF is connected to Q’ 2. Therefore, it changes its state when Q’ 2= 1 and
there is falling edge of clock.
 By this we can generate counting states of down counter.
 After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.

1. Synchronous Counter

 Unlike the asynchronous counter, synchronous counter has one global clock which drives
each flip flop so output changes in parallel.
 The one advantage of synchronous counter over asynchronous counter is, it can operate on
higher frequency than asynchronous counter as it does not have cumulative delay because of
same clock is given to each flip flop.
 For synchronous counters, all the flip-flops are using the same CLOCK signal.
 Thus, the output would change synchronously.
 Procedure to design synchronous counter are as follows:-
Step 1: Determine number of FF used and types of Flip Flops
Step 2: Write excitation table of Flip Flop
Step 3: Draw the State Transition Diagram and Circuit Excitation Table
Step 4: Find a simplified equation for each FF input using K- Map.
Step 5: Draw the circuit diagram
3bit Synchronous Up Counter

Step 1: Decide the number of Flip flops

N number of Flip flop (FF) required for N bit counter.

For 3 bit counter we require 3 FF.

n
Maximum count = 2 -1, where n is a number of bits.
For n= 3, Maximum count = 7.
Here T FF is used.
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Step 2: Write excitation table of Flip Flop

Step 3: Draw the State Transition Diagram and Circuit Excitation Table

3
For n= 3, 2 =8 states and Maximum count = 7

State Transition Diagram :

Circuit Excitation Table :

The circuit excitation table represents the present states of the counting sequence and the next states
after the clock pulse is applied and input T of the flip-flops. By seeing the transition between the
present state and the next state, we can find the input values of 3 Flip Flops using the Flip Flops
excitation table. The table is designed according to the required counting sequence.
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Here T = 1, then there is output state (next state changes from previous state) changes i.e Q changes
from 0 to 1 or 1 to 0
T= 0 then, there is no state output state changes i.e Q remains same
Step 4: Find a simplified equation for each FF input using K- Map.

Step 5: Draw the circuit diagram

The clock is provided to every Flip flop at same instant of time.

The toggle(T) input is provided to every Flip flop according to the simplified equation of K map.

Exercise : Synchronous 3 bit Down counter

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Synchronous 3 bit Up/Down counter

 Procedure to design synchronous counter are as follows:-

Step 1: Determine number of FF used and types of Flip Flops
Step 2: Write excitation table of Flip Flop
Step 3. Decision for Mode control input M
Step 4: Draw the State Transition Diagram and Circuit Excitation Table
Step 5: Find a simplified equation for each FF input using K- Map.
Step 6: Draw the circuit diagram
Step 1: Decide the number of Flip flops

Here we are performing 3 bit or mod-8 Up or Down counting,

so 3 Flip Flops are required, which can count up to 23-1 = 7.
Here T Flip Flop is used.

Step 2: Write excitation table of Flip Flop

Step 3. Decision for Mode control input M

When M=0 ,then the counter will perform up counting.

When M=1 ,then the counter will perform down counting.
Step 4: Draw the State Transition Diagram and Circuit Excitation Table

State Transition Diagram:

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Circuit Excitation Table :

The circuit excitation table represents the present states of the counting sequence and the next states
after the clock pulse is applied and input T of the flip-flops. By seeing the transition between the
present state and the next state, we can find the input values of 3 Flip Flops using the Flip Flops
excitation table. The table is designed according to the required counting sequence.

If there is a change in the output state of a flip flop (i.e. 0 to 1 or 1 to 0), then the corresponding T
value becomes 1 otherwise 0.
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Step 5: Find a simplified equation for each FF input using K- Map.

Step 6: Draw the circuit diagram

The simplified expression for Flip Flops is used to design circuit diagrams.
Here all the connections are made according to simplified expressions for Flip Flops.
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Timing Diagram

BCD Counter (Decade Counter)

 A binary coded decimal (BCD) counter is a serial digital counter that counts ten digits .
 it is also called as “Decade counter”.
 A BCD Counter counts ten different states and then reset to its initial states.

Step 1: Decide the number of Flip flops

N number of Flip flop (FF) required for N bit counter.

For 4 bit counter we require 4 FF.

Here T FF is used.

Step 2: Write excitation table of Flip Flop

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Step 3: Draw the State Transition Diagram and Circuit Excitation Table

State Transition Diagram :

Circuit Excitation Table :

The circuit excitation table represents the present states of the counting sequence and the next states
after the clock pulse is applied and input T of the flip-flops. By seeing the transition between the
present state and the next state, we can find the input values of 4 Flip Flops using the Flip Flops
excitation table. The table is designed according to the required counting sequence.

Here T = 1, then there is output state (next state changes from previous state) changes i.e Q changes
from 0 to 1 or 1 to 0
T= 0 then, there is no state output state changes i.e Q remains same
Step 4: Find a simplified equation for each FF input using K- Map.
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Step 5: Draw the circuit diagram

The clock is provided to every Flip flop at same instant of time.

The toggle(T) input is provided to every Flip flop according to the simplified equation of K map.

The applications of BCD counters are

 Clock production
 Clock division
 United oscillator
 Used in minimal power CMOS circuits
 TTL consistent inputs
 Implemented in frequency counting circuits