MOD1MCES
MOD1MCES
RISC:-
* a design philosophy
*delivering simple but powerful instructions, that execute within a single cycle at
high clock speed.
*reducing the complexity of instructions performed by the hardware - it is easier to
provide greater flexibility and intelligence in software rather than hardware
*places greater demands on the compiler.
*wheras in cisc machine(complex instruction set computer) - relies more on the
hardware for instruction functionallity and hese instructions are more complicated.
RISC DESIGN RULES:- (Instructons,Pipeline,Registers,Load-Store Architecture)
1.Instructions:-
*reduced number of instruction classes
*simple operations
* each instruction can execute in a single clock cycle.
* compiler programmer synthesizes complicated operations
* each instruction is having fixed length - allows pipeline to fetch future
instructions
*in cisc processors,the instructions are often of variable sizes and take many cycles
to execute
2.Pipelines:- (pipeline is a set of data processing elements connected in series,
where the output of one data processing element is input to a new element. )
*processing of instructions is broken down into smaller units
*instuctions are executed in parallel by pipelines.
*pipeline advances by one step on each cycle for maximum throughput.
*there is no need for an instruction to be executed by a mini-program called
microcode as on CISC processors.
3.Registers:-(data storing units)
*large general-purpose register set
* any register can contain either data or an address.
*registers act as the fast local memory store for all data processing
operations.
*cisc processors have dedicated registers for specific purposes.
4.Load-Store Architecture:-
*processor operates on data held in registers
*seperate load and store instructions transfer data between the register bank
and external memory
*seperating memory accesses from data processing provides an advantage
because ypu can use data items held in the
reisters bank multiple times without needing multiple memory accesses.
* in a cisc design the data processing can act on memory directly.
Design rules allow a Risc processor to be simpler, and the core can operate at
higher clock frequencies.
In contrast, traditional Cisc processors are more complex and operate at lower
frequencies.