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Accessing Io Devices in System Memory

I/O devices can be connected to a computer's memory using memory-mapped I/O. With this approach, I/O devices are assigned unique addresses and the processor can access the devices using load and store instructions. When an I/O device needs service, it can trigger an interrupt that causes the processor to save its state and begin executing an interrupt service routine to handle the I/O request before returning to the original program. Interrupts allow asynchronous events to be processed efficiently with low overhead.

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34 views

Accessing Io Devices in System Memory

I/O devices can be connected to a computer's memory using memory-mapped I/O. With this approach, I/O devices are assigned unique addresses and the processor can access the devices using load and store instructions. When an I/O device needs service, it can trigger an interrupt that causes the processor to save its state and begin executing an interrupt service routine to handle the I/O request before returning to the original program. Interrupts allow asynchronous events to be processed efficiently with low overhead.

Uploaded by

rohit sharma
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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ACCESSING I/O DEVICES IN SYSTEM MEMORY

A simple arrangement to connect I/O devices to a computer is to use a single bus


arrangement. The bus enables all the devices connected to it to exchange information.
Typically, it consists of three sets of lines used to carry address, data, and control signals.
Each I/O device is assigned a unique set of addresses. When the processor places a
particular address on the address line, the device that recognizes this address responds to
the commands issued on the control lines. The processor requests either a read or a write
operation, and the requested data are transferred over the data lines, when I/O devices and
the memory share the same address space, the arrangement is called memory-mapped
I/O.
With memory-mapped I/O, any machine instruction that can access memory can
be used to transfer data to or from an I/O device. For example, if DATAIN is the address
of the input buffer associated with the keyboard, the instruction

Move DATAIN, R0
Reads the data from DATAIN and stores them into processor register R0. Similarly, the
instruction
Move R0, DATAOUT

Sends the contents of register R0 to location DATAOUT, which may be the output data
buffer of a display unit or a printer.
Most computer systems use memory-mapped I/O. some processors have special
In and Out instructions to perform I/O transfers. When building a computer system based
on these processors, the designer had the option of connecting I/O devices to use the
special I/O address space or simply incorporating them as part of the memory address
space. The I/O devices examine the low-order bits of the address bus to determine
whether they should respond.
The hardware required to connect an I/O device to the bus. The address decoder
enables the device to recognize its address when this address appears on the address lines.
The data register holds the data being transferred to or from the processor. The status
register contains information relevant to the operation of the I/O device. Both the data
and status registers are connected to the data bus and assigned unique addresses. The
address decoder, the data and status registers, and the control circuitry required to
coordinate I/O transfers constitute the device’s interface circuit.
I/O devices operate at speeds that are vastly different from that of the processor.
When a human operator is entering characters at a keyboard, the processor is capable of
executing millions of instructions between successive character entries. An instruction
that reads a character from the keyboard should be executed only when a character is
available in the input buffer of the keyboard interface. Also, we must make sure that an
input character is read only once.
This example illustrates program-controlled I/O, in which the processor
repeatedly checks a status flag to achieve the required synchronization between the
processor and an input or output device. We say that the processor polls the device. There
are two other commonly used mechanisms for implementing I/O operations: interrupts
and direct memory access. In the case of interrupts, synchronization is achieved by
having the I/O device send a special signal over the bus whenever it is ready for a data
transfer operation. Direct memory access is a technique used for high-speed I/O devices.
It involves having the device interface transfer data directly to or from the memory,
without continuous involvement by the processor.
The routine executed in response to an interrupt request is called the interrupt-
service routine, which is the PRINT routine in our example. Interrupts bear considerable
resemblance to subroutine calls. Assume that an interrupt request arrives during
execution of instruction i in figure 1
Program 1 Program 2
COMPUTER routine PRINT routine

2
....
Interrupt i
Occurs i+1
here
…
M

Figure 1. Transfer of control through the use of interrupts

The processor first completes execution of instruction i. Then, it loads the


program counter with the address of the first instruction of the interrupt-service routine.
For the time being, let us assume that this address is hardwired in the processor. After
execution of the interrupt-service routine, the processor has to come back to instruction
i +1. Therefore, when an interrupt occurs, the current contents of the PC, which point to
instruction i+1, must be put in temporary storage in a known location. A Return-from-
interrupt instruction at the end of the interrupt-service routine reloads the PC from the
temporary storage location, causing execution to resume at instruction i +1. In many
processors, the return address is saved on the processor stack.
We should note that as part of handling interrupts, the processor must inform the
device that its request has been recognized so that it may remove its interrupt-request
signal. This may be accomplished by means of a special control signal on the bus. An
interrupt-acknowledge signal. The execution of an instruction in the interrupt-service
routine that accesses a status or data register in the device interface implicitly informs
that device that its interrupt request has been recognized.
So far, treatment of an interrupt-service routine is very similar to that of a
subroutine. An important departure from this similarity should be noted. A subroutine
performs a function required by the program from which it is called. However, the
interrupt-service routine may not have anything in common with the program being
executed at the time the interrupt request is received. In fact, the two programs often
belong to different users. Therefore, before starting execution of the interrupt-service
routine, any information that may be altered during the execution of that routine must be
saved. This information must be restored before execution of the interrupt program is
resumed. In this way, the original program can continue execution without being affected
in any way by the interruption, except for the time delay. The information that needs to
be saved and restored typically includes the condition code flags and the contents of any
registers used by both the interrupted program and the interrupt-service routine.
The task of saving and restoring information can be done automatically by the
processor or by program instructions. Most modern processors save only the minimum
amount of information needed to maintain the registers involves memory transfers that
increase the total execution time, and hence represent execution overhead. Saving
registers also increase the delay between the time an interrupt request is received and the
start of execution of the interrupt-service routine. This delay is called interrupt latency.

Source : http://elearningatria.files.wordpress.com/2013/10/cse-iv-
computer-organization-10cs46-notes.pdf

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