Microchip Tech MCP1827S 5002E EB - C641174

MCP1826/MCP1826S
1000 mA, Low-Voltage, Low Quiescent Current

LDO Regulator
Features Description
• 1000 mA Output Current Capability The MCP1826/MCP1826S is a 1000 mA Low Dropout
• Input Operating Voltage Range: 2.3V to 6.0V (LDO) linear regulator that provides high-current and
• Adjustable Output Voltage Range: 0.8V to 5.0V low-output voltages. The MCP1826 comes in a fixed or
(MCP1826 only) adjustable output voltage version, with an output
voltage range of 0.8V to 5.0V. The 1000 mA output cur-
• Standard Fixed Output Voltages:
rent capability, combined with the low-output voltage
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V capability, make the MCP1826 a good choice for new
• Other Fixed Output Voltage Options Available sub-1.8V output voltage LDO applications that have
Upon Request high current demands. The MCP1826S is a 3-pin fixed
• Low Dropout Voltage: 250 mV Typical at 1000 mA voltage version.
• Typical Output Voltage Tolerance: 0.5% The MCP1826/MCP1826S is stable using ceramic
• Stable with 1.0 µF Ceramic Output Capacitor output capacitors that inherently provide lower output
• Fast Response to Load Transients noise and reduce the size and cost of the entire
regulator solution. Only 1 µF of output capacitance is
• Low Supply Current: 120 µA (typ)
needed to stabilize the LDO.
• Low Shutdown Supply Current: 0.1 µA (typ)
(MCP1826 only) Using CMOS construction, the quiescent current
consumed by the MCP1826/MCP1826S is typically
• Fixed Delay on Power Good Output
less than 120 µA over the entire input voltage range,
(MCP1826 only)
making it attractive for portable computing applications
• Short Circuit Current Limiting and that demand high-output current. The MCP1826
Overtemperature Protection versions have a Shutdown (SHDN) pin. When shut
• TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5 down, the quiescent current is reduced to less than
Package Options (MCP1826) 0.1 µA.
• TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3 On the MCP1826 fixed output versions the
Package Options (MCP1826S) scaled-down output voltage is internally monitored and
• Pass Automotive AEC-Q100 Reliability Testing a power good (PWRGD) output is provided when the
output is within 92% of regulation (typical). The
Applications: PWRGD delay is internally fixed at 200 µs (typical).
• High-Speed Driver Chipset Power The overtemperature and short circuit current-limiting
provide additional protection for the LDO during system
• Networking Backplane Cards
Fault conditions.
• Notebook Computers
• Network Interface Cards
• Palmtop Computers
 2007-2021 Microchip Technology Inc. DS20002057C-page 1

MCP1826/MCP1826S
Package Types
MCP1826 MCP1826S
DDPAK-5 TO-220-5 DDPAK-3 TO-220-3
Fixed/Adjustable
1 2 3
1 2 3
1 2 3 4 5
1 2 3 4 5
SOT-223-5 SOT-223-3
6 4
1 2 3 4 5 1 2 3
Pin Fixed Adjustable Pin
1 SHDN SHDN 1 VIN

2 VIN VIN 2 GND (TAB)
3 GND (TAB) GND (TAB) 3 VOUT

4 GND (TAB)
4 VOUT VOUT
5 PWRGD ADJ
6 GND (TAB) GND (TAB)
DS20002057C-page 2  2007-2021 Microchip Technology Inc.

MCP1826/MCP1826S
Typical Application
MCP1826 Fixed Output Voltage
PWRGD
R1
On 100 k
Off SHDN
1 VOUT = 1.8V @ 1000 mA
VIN = 2.3V to 2.8V VIN VOUT
GND
C1
C2
4.7 µF 1 µF
MCP1826 Adjustable Output Voltage
VADJ
R2
R1 20 k
On 40 k
Off SHDN
1 VOUT = 1.2V @ 1000 mA
VIN = 2.3V to 2.8V VIN VOUT
C1
C2
4.7 µF 1 µF
GND

MCP1826/MCP1826S
Functional Block Diagram – Adjustable Output
PMOS
VIN VOUT
Undervoltage
Lockout
(UVLO)
ISNS Cf Rf
SHDN ADJ/SENSE
+
Driver w/limit
and SHDN EA
Overtemperature
Sensing –
SHDN
VREF
V IN
SHDN Reference
Soft-Start
Comp TDELAY
GND
92% of VREF

MCP1826/MCP1826S
Functional Block Diagram – Fixed Output (3-Pin)
PMOS
VIN VOUT
Undervoltage Sense
Lockout
(UVLO)
ISNS Cf Rf
SHDN
+
Driver w/limit
and SHDN EA
Overtemperature
Sensing –
SHDN
VREF
V IN
SHDN Reference
Soft-Start
Comp TDELAY
GND
92% of VREF

MCP1826/MCP1826S
Functional Block Diagram – Fixed Output (5-Pin)
PMOS
VIN VOUT
Undervoltage Sense
Lockout
(UVLO)
ISNS Cf Rf
SHDN
+
Driver w/limit
and SHDN EA
Overtemperature
Sensing –
SHDN
VREF
V IN
SHDN Reference
Soft-Start
PWRGD
Comp TDELAY
GND
92% of VREF

MCP1826/MCP1826S
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings † operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
VIN ....................................................................................6.5V affect device reliability.
Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V
Maximum Power Dissipation......... Internally-Limited (Note 6)
Output Short Circuit Duration ................................ Continuous
Storage temperature .....................................-65°C to +150°C
Maximum Junction Temperature, TJ ........................... +150°C
ESD protection on all pins (HBM/MM)   4 kV;  300V
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output,
IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C
Parameters Sym. Min. Typ. Max. Units Conditions
Input Operating Voltage VIN 2.3 6.0 V Note 1

Input Quiescent Current Iq — 120 220 µA IL = 0 mA, VOUT = 0.8V to
5.0V
Input Quiescent Current for ISHDN — 0.1 3 µA SHDN = GND
SHDN Mode
Maximum Output Current IOUT 1000 — — mA VIN = 2.3V to 6.0V
VR = 0.8V to 5.0V, Note 1
Line Regulation VOUT/ — ±0.05 ±0.20 %/V (Note 1) VIN 6V
(VOUT x VIN)
Load Regulation VOUT/VOUT -1.0 ±0.5 1.0 % IOUT = 1 mA to 1000 mA,
(Note 4)
Output Short Circuit Current IOUT_SC — 2.2 — A RLOAD < 0.1, Peak Current
Adjust Pin Characteristics (Adjustable Output Only)
Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 V VIN = 2.3V to VIN = 6.0V,
IOUT = 1 mA
Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ = 0V to 6V
Adjust Temperature Coefficient TCVOUT — 40 — ppm/°C Note 3
Fixed-Output Characteristics (Fixed Output Only)
Voltage Regulation VOUT VR - 2.5% VR ±0.5% VR + 2.5% V Note 2
Note 1: The minimum VIN must meet two conditions: VIN2.3V and VIN VOUT(MAX)VDROPOUT(MAX).
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * Temperature). VOUT-HIGH is the highest voltage measured over the
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is
tested over a load range from 1 mA to the maximum specified output current.
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX).
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, JA). Exceeding the maximum allowable power
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained
junction temperatures above 150°C can impact device reliability.
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the
ambient temperature is not significant.

MCP1826/MCP1826S
AC/DC CHARACTERISTICS (CONTINUED)

Dropout Characteristics
Dropout Voltage VDROPOUT — 250 400 mV Note 5, IOUT = 1000 mA,
VIN(MIN) = 2.3V
Power Good Characteristics
PWRGD Input Voltage Operat- VPWRGD_VIN 1.0 — 6.0 V TA = +25°C
ing Range 1.2 — 6.0 TA = -40°C to +125°C
For VIN < 2.3V, ISINK = 100 µA
PWRGD Threshold Voltage VPWRGD_TH %VOUT Falling Edge
(Referenced to VOUT) 89 92 95 VOUT < 2.5V Fixed,
VOUT = Adj.
90 92 94 VOUT >= 2.5V Fixed
PWRGD Threshold Hysteresis VPWRGD_HYS 1.0 2.0 3.0 %VOUT
PWRGD Output Voltage Low VPWRGD_L — 0.2 0.4 V IPWRGD SINK = 1.2 mA,
ADJ = 0V
PWRGD Leakage PWRGD_LK — 1 — nA VPWRGD = VIN = 6.0V
PWRGD Time Delay TPG — 125 — µs Rising Edge
RPULLUP = 10 k
Detect Threshold to PWRGD TVDET-PWRGD — 200 — µs VOUT = VPWRGD_TH + 20 mV
Active Time Delay to VPWRGD_TH - 20 mV
Shutdown Input
Logic High Input VSHDN-HIGH 45 — — %VIN VIN = 2.3V to 6.0V
Logic Low Input VSHDN-LOW — — 15 %VIN VIN = 2.3V to 6.0V
SHDN Input Leakage Current SHDNILK -0.1 ±0.001 +0.1 µA VIN = 6V, SHDN =VIN,
SHDN = GND
AC Performance
Output Delay From SHDN TOR — 100 — µs SHDN = GND to VIN
VOUT = GND to 95% VR
Output Noise eN — 2.0 — µV/Hz IOUT = 200 mA, f = 1 kHz,
COUT = 10 µF (X7R Ceramic),
VOUT = 2.5V

MCP1826/MCP1826S
AC/DC CHARACTERISTICS (CONTINUED)
Power Supply Ripple Rejection PSRR — 60 — dB f = 100 Hz, COUT = 4.7 µF,
Ratio IOUT = 100 µA,
VINAC = 100 mV pk-pk,
CIN = 0 µF
Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
Thermal Shutdown Hysteresis TSD — 10 — °C IOUT = 100 µA, VOUT = 1.8V,
VIN = 2.8V
TEMPERATURE SPECIFICATIONS

Temperature Ranges
Operating Junction Temperature Range TJ -40 — +125 °C Steady State
Maximum Junction Temperature TJ — — +150 °C Transient
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 3L-DDPAK JA — 31.4 — °C/W 4-Layer JC51 Standard
JC — 3.0 — °C/W Board
Thermal Resistance, 3L-TO-220 JA — 29.4 — °C/W 4-Layer JC51 Standard
Thermal Resistance, 3L-SOT-223 JA — 62 — °C/W EIA/JEDEC JESD51-751-7
JC — 15.0 — °C/W 4 Layer Board
Thermal Resistance, 5L-DDPAK JA — 31.2 — °C/W 4-Layer JC51 Standard
Thermal Resistance, 5L-TO-220 JA — 29.3 — °C/W 4-Layer JC51 Standard
Thermal Resistance, 5L-SOT-223 JA — 62 — °C/W EIA/JEDEC JESD51-751-7
JC — 15.0 — °C/W 4 Layer Board

MCP1826/MCP1826S
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA,
Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output.
140 0.10
VOUT = 1.2V Adj IOUT = 1 mA VOUT = 1.2V Adj
IOUT = 0 mA
Quiescent Current (μA)
0.09 VIN = 2.3V to 6.0V
Line Regulation (%/V)

130
0.08 IOUT = 100 mA
120 130 CC
+130 IOUT = 50 mA
0.07
110 +90
+90 C
C
0.06
+25
+25 C
C
100 0.05 IOUT = 250 mA
0C
90 -45 C 0.04
IOUT = 1000 mA
0.03
80 -45 -20 5 30 55 80 105 130
2 3 4 5 6
Input Voltage (V) Temperature (°C)
FIGURE 2-1: Quiescent Current vs. Input FIGURE 2-4: Line Regulation vs.
Voltage (Adjustable Version). Temperature (Adjustable Version).
180 0.15
IOUT = 1.0 mA to 1000 mA
VOUT = 1.2V Adj
170 VOUT = 3.3V
0.10
Ground Current (μA)
Load Regulation (%)
160
0.05
150 VOUT = 1.8V
VIN = 5.0V
140 0.00
VIN = 3.3V VOUT = 0.8V
VOUT = 5.0V
130
-0.05
120
-0.10
110 VIN = 2.3V
100 -0.15
0 250 500 750 1000 -45 -20 5 30 55 80 105 130
Load Current (mA) Temperature (°C)
FIGURE 2-2: Ground Current vs. Load FIGURE 2-5: Load Regulation vs.
Current (Adjustable Version). Temperature (Adjustable Version).
140 0.411
VOUT = 1.2V Adj VOUT = 1.2V
135
IOUT = 0 mA VIN = 6.0V IOUT = 1.0 mA

Adjust Pin Voltage (V)
130 0.410
125
VIN = 5.0V
120 VIN = 6.0V 0.409
115
110
0.408 VIN = 2.3V
105 VIN = 5.0V
100 VIN = 4.0V
95 0.407
VIN = 3.0V
90 VIN = 2.3V
85 0.406
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
Temperature (°C) Temperature (°C)
FIGURE 2-3: Quiescent Current vs. FIGURE 2-6: Adjust Pin Voltage vs.
Junction Temperature (Adjustable Version). Temperature (Adjustable Version).

MCP1826/MCP1826S
0.30 150
VOUT = 0.8V
IOUT = 0 mA

0.25 140
Dropout Voltage (V)
0.20 VOUT = 5.0V Adj 130 +130°C

0.15 120 +90°C
VOUT = 2.5V Adj
0.10 110 +25°C
0°C
0.05 100 -45°C
0.00
90
0 200 400 600 800 1000
2 3 4 5 6
Load Current (mA) Input Voltage (V)
FIGURE 2-7: Dropout Voltage vs. Load FIGURE 2-10: Quiescent Current vs. Input
Current (Adjustable Version). Voltage.
0.34 150
IOUT = 1.0A VOUT = 2.5V

140 IOUT = 0 mA
0.31
Dropout Voltage (V)
130 +130 C
0.28 VOUT = 5.0V Adj 120 +90 C
110 +25 C
0.25 0C
VOUT = 2.5V Adj 100 -45 C
0.22
90
0.19 80
-45 -20 5 30 55 80 105 130 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Temperature (°C) Input Voltage (V)
FIGURE 2-8: Dropout Voltage vs. FIGURE 2-11: Quiescent Current vs. Input
Temperature (Adjustable Version). Voltage.
170 200
Power Good Time Delay (µS)
VOUT = 2.5V VIN = 2.3V for VR=0.8V

160 IOUT= 0 mA
180 VIN = 3.9V for VR=3.3V
Ground Current (μA)
150 VIN = 6.0V 160

VOUT=3.3V
140 140
130 120
VOUT=0.8V
120 VIN = 5.0V 100
110 VIN = 3.9V 80

VIN = 3.1V
100 60
-45 -20 5 30 55 80 105 130 0 250 500 750 1000
Temperature (°C) Load Current (mA)
FIGURE 2-9: Power Good (PWRGD) FIGURE 2-12: Ground Current vs. Load
Time Delay vs. Temperature. Current.

MCP1826/MCP1826S
130 0.040
IOUT = 0 mA VR = 2.5V
125
IOUT = 1 mA VIN = 3.1 to 6.0V

0.035
120
115 0.030
IOUT = 50 mA
110 VOUT = 2.5V
105 0.025
IOUT = 250 mA
100
0.020
95 VOUT = 0.8V IOUT = 1000 mA
IOUT = 500 mA
90 0.015
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Line Regulation vs.
Temperature. Temperature.
0.50
VR = 0.8V 0.30
VOUT = 0.8V
0.40
0.20 VIN = 2.3V
Load Regulation (%)

IOUT = 1 mA to 1000 mA
ISHDN (μA)
0.30 VIN = 6.0V VIN = 4.0V 0.10
VIN = 3.0V 0.00

0.20
VIN = 5.0V VIN = 2.3V -0.10
0.10 -0.20
0.00 -0.30
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
FIGURE 2-14: ISHDN vs. Temperature. FIGURE 2-17: Load Regulation vs.
Temperature (VOUT < 2.5V Fixed).
0.10 0.00
IOUT = 1 mA VOUT = 0.8V
IOUT = 1 mA to 1000 mA
VIN = 2.3V to 6.0V -0.05
0.08 VOUT = 2.5V

Load Regulation (%)
IOUT = 50 mA -0.10
0.06 IOUT = 100 mA -0.15
-0.20
0.04 VOUT = 5.0V
-0.25
IOUT = 1A
0.02 -0.30
IOUT = 500mA
-0.35
0.00 -0.40
-45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130
FIGURE 2-15: Line Regulation vs. FIGURE 2-18: Load Regulation vs.
Temperature. Temperature (VOUT 2.5V Fixed).

MCP1826/MCP1826S
0.30 10.000
VR=0.8V, VIN=2.3V COUT=1 μF ceramic X7R
CIN=10 μF ceramic
0.25
Dropout Voltage (V)
VOUT = 2.5V
Hz)
0.20 1.000 IOUT=200 mA
PV/
0.15
Noise (P
VR=3.3V, VIN=4.1V
VOUT = 5.0V
0.10 0.100
0.05
0.00 0.010
0 200 400 600 800 1000 0.01 0.1 1 10 100 1000
Load Current (mA) Frequency (kHz)
FIGURE 2-19: Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage
Current. Density vs. Frequency.
0.34 0
IOUT = 1000 mA
0.32 -10
Dropout Voltage (V)
0.30 VOUT = 2.5V -20
PSRR (dB)
0.28 -30
0.26 -40 VR=1.2V Adj

-50 COUT=10 μF ceramic X7R
0.24 VOUT = 5.0V VIN=3.1V
-60 CIN=0 μF
0.22 IOUT=10 mA
-70
0.20
-80
-45 -20 5 30 55 80 105 130
0.01 0.1 1 10 100 1000
Temperature (°C) Frequency (kHz)
FIGURE 2-20: Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple
Temperature. Rejection (PSRR) vs. Frequency (Adjustable).
0
2.00
VOUT = 0.8V -10
1.80
Short Circuit Current (A)
1.60 -20
1.40
PSRR (dB)
-30
1.20
1.00 -40 VR=3.3V Fixed
0.80 -50 COUT=22 μF ceramic X7R
0.60 VIN=3.9V
-60 CIN=0 μF
0.40
0.20 -70 IOUT=10 mA
0.00 -80
0 1 2 3 4 5 6 0.01 0.1 1 10 100 1000
Input Voltage (V) Frequency (kHz)
FIGURE 2-21: Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple
Input Voltage. Rejection (PSRR) vs. Frequency.

MCP1826/MCP1826S
FIGURE 2-25: 2.5V (Adj.) Start-up from FIGURE 2-28: Dynamic Line Response.
VIN.
FIGURE 2-29: Dynamic Load Response

FIGURE 2-26: 2.5V (Adj.) Start-up from (10 mA to 1000 mA).
Shutdown.
FIGURE 2-30: Dynamic Load Response

FIGURE 2-27: Power Good (PWRGD) (100 mA to 1000 mA).
Timing.

MCP1826/MCP1826S
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3-Pin Fixed 5-Pin Fixed Adjustable
Name Description
Output Output Output
— 1 1 SHDN Shutdown Control Input (active-low)
1 2 2 VIN Input Voltage Supply
2 3 3 GND Ground
3 4 4 VOUT Regulated Output Voltage
— 5 — PWRGD Power Good Output
— — 5 ADJ Voltage Adjust/Sense Input
Exposed Pad Exposed Pad Exposed Pad EP Exposed Pad of the Package (ground potential)
3.1 Shutdown Control Input (SHDN) 3.5 Power Good Output (PWRGD)
The SHDN input is used to turn the LDO output voltage The PWRGD output is an open-drain output used to
on and off. When the SHDN input is at a logic-high indicate when the LDO output voltage is within 92%
level, the LDO output voltage is enabled. When the (typically) of its nominal regulation value. The PWRGD
SHDN input is pulled to a logic-low level, the LDO threshold has a typical hysteresis value of 2%. The
output voltage is disabled. When the SHDN input is PWRGD output is delayed by 200 µs (typical) from the
pulled low, the PWRGD output also goes low and the time the LDO output is within 92% + 3% (max hystere-
LDO enters a low quiescent current shutdown state sis) of the regulated output value on power-up. This
where the typical quiescent current is 0.1 µA. delay time is internally fixed.
3.2 Input Voltage Supply (VIN) 3.6 Output Voltage Adjust Input (ADJ)
Connect the unregulated or regulated input voltage For adjustable applications, the output voltage is
source to VIN. If the input voltage source is located connected to the ADJ input through a resistor divider
several inches away from the LDO, or the input source that sets the output voltage regulation value. This
is a battery, it is recommended that an input capacitor provides the user the capability to set the output
be used. A typical input capacitance value of 1 µF to voltage to any value they desire within the 0.8V to 5.0V
10 µF should be sufficient for most applications. range of the device.
3.3 Ground (GND) 3.7 Exposed Pad (EP)

Connect the GND pin of the LDO to a quiet circuit The DDPAK and TO-220 package have an exposed tab
ground. This will help the LDO power supply rejection on the package. A heat sink may be mounted to the tab
ratio and noise performance. The ground pin of the to aid in the removal of heat from the package during
LDO only conducts the quiescent current of the LDO operation. The exposed tab is at the ground potential of
(typically 120 µA), so a heavy trace is not required. the LDO.
For applications have switching or noisy inputs tie the
GND pin to the return of the output capacitor. Ground
planes help lower inductance and voltage spikes
caused by fast transient load currents and are
recommended for applications that are subjected to
fast load transients.
3.4 Regulated Output Voltage (VOUT)

The VOUT pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1826/MCP1826S is
stable with ceramic, tantalum and aluminum-electro-
lytic capacitors. See Section 4.3 “Output Capacitor”
for output capacitor selection guidance.

MCP1826/MCP1826S
4.0 DEVICE OVERVIEW EQUATION 4-2:
V OUT – V ADJ
The MCP1826/MCP1826S is a high output current, R 1 = R 2  --------------------------------
 V ADJ 
Low Dropout (LDO) voltage regulator. The low dropout
Where:
voltage of 300 mV typical at 1000 mA of current makes
it ideal for battery-powered applications. Unlike other VOUT = LDO Output Voltage
high output current LDOs, the MCP1826/MCP1826S VADJ = ADJ Pin Voltage
only draws a maximum of 220 µA of quiescent current. (typically 0.41V)
The MCP1826 has a shutdown control input and a
power good output.
4.2 Output Current and Current
4.1 LDO Output Voltage Limiting
The 5-pin MCP1826 LDO is available with either a fixed The MCP1826/MCP1826S LDO is tested and ensured
output voltage or an adjustable output voltage. The to supply a minimum of 1000 mA of output current. The
output voltage range is 0.8V to 5.0V for both versions. MCP1826/MCP1826S has no minimum output load, so
The 3-pin MCP1826S LDO is available as a fixed the output load current can go to 0 mA and the LDO will
voltage device. continue to regulate the output voltage to within
tolerance.
4.1.1 ADJUST INPUT
The MCP1826/MCP1826S also incorporates an output
The adjustable version of the MCP1826 uses the ADJ current limit. If the output voltage falls below 0.7V due
pin (pin 5) to get the output voltage feedback for output to an overload condition (usually represents a shorted
voltage regulation. This allows the user to set the load condition), the output current is limited to 2.2A
output voltage of the device with two external resistors. (typical). If the overload condition is a soft overload, the
The nominal voltage for ADJ is 0.41V. MCP1826/MCP1826S will supply higher load currents
Figure 4-1 shows the adjustable version of the of up to 2.5A. The MCP1826/MCP1826S should not be
MCP1826. Resistors R1 and R2 form the resistor operated in this condition continuously as it may result
divider network necessary to set the output voltage. in failure of the device. However, this does allow for
With this configuration, the equation for setting VOUT is: device usage in applications that have higher pulsed
load currents having an average output current value of
EQUATION 4-1: 1000 mA or less.
R1 + R2 Output overload conditions may also result in an
V OUT = V ADJ  ------------------ over-temperature shutdown of the device. If the junc-
 R2 
Where: tion temperature rises above 150°C, the LDO will shut
down the output voltage. See Section 4.8 “Overtem-
VOUT = LDO Output Voltage perature Protection” for more information on
VADJ = ADJ Pin Voltage overtemperature shutdown.
(typically 0.41V)
4.3 Output Capacitor
MCP1826-ADJ
The MCP1826/MCP1826S requires a minimum output
capacitance of 1 µF for output voltage stability. Ceramic
VOUT
capacitors are recommended because of their size,
On R1
cost and environmental robustness qualities.
Off 1 2 3 4 5 C2
SHDN ADJ 1 µF Aluminum-electrolytic and tantalum capacitors can be
VIN
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
C1 R2
4.7 µF GND must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
FIGURE 4-1: Typical adjustable output acceptable ESR range required. A typical 1 µF X7R
voltage application circuit. 0805 capacitor has an ESR of 50 milli-ohms.
The allowable resistance value range for resistor R2 is
from 10 k to 200 k. Solving the equation for R1
yields the following equation:

MCP1826/MCP1826S
Larger LDO output capacitors can be used with the When the LDO is put into Shutdown mode using the
MCP1826/MCP1826S to improve dynamic SHDN input, the power good output is pulled low
performance and power supply ripple rejection immediately, indicating that the output voltage will be
performance. A maximum of 22 µF is recommended. out of regulation. The timing diagram for the power
Aluminum-electrolytic capacitors are not recom- good output when using the shutdown input is shown in
mended for low-temperature applications of  -25°C. Figure 4-3.
The power good output is an open-drain output that can
4.4 Input Capacitor be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
Low input source impedance is necessary for the LDO
1.2 mA (VPWRGD < 0.4V maximum).
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum VPWRGD_TH
of 1.0 µF to 4.7 µF is recommended for most
applications. VOUT
For applications that have output step load TPG
requirements, the input capacitance of the LDO is very

important. The input capacitance provides the LDO VOH
with a good local low-impedance source to pull the TVDET_PWRGD
transient currents from in order to respond quickly to
the output load step. For good step response PWRGD
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor. VOL
The capacitor should be placed as close to the input of
the LDO, as is practical. Larger input capacitors will
also help reduce any high-frequency noise on the input
FIGURE 4-2: Power Good Timing.
and output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
VIN
4.5 Power Good Output (PWRGD) TOR
The PWRGD output is used to indicate when the output 70 µs

voltage of the LDO is within 92% (typical value, see 30 µs
Section 1.0 “Electrical Characteristics” for Minimum
and Maximum specifications) of its nominal regulation SHDN TPG
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
VOUT
value. Once this threshold has been exceeded, the
power good time delay is started (shown as TPG in the
Electrical Characteristics table). The power good time
delay is fixed at 125 µs (typical). After the time delay
period, the PWRGD output will go high, indicating that PWRGD
the output voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition FIGURE 4-3: Power Good Timing from
low. The power good circuitry has a 200 µs delay when Shutdown.
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.

MCP1826/MCP1826S
4.6 Shutdown Input (SHDN) 4.7 Dropout Voltage and Undervoltage
The SHDN input is an active-low input signal that turns
Lockout
the LDO on and off. The SHDN threshold is a Dropout voltage is defined as the input-to-output
percentage of the input voltage. The typical value of voltage differential at which the output voltage drops
this shutdown threshold is 30% of VIN, with minimum 2% below the nominal value that was measured with a
and maximum limits over the entire operating VR + 0.5V differential applied. The
temperature range of 45% and 15%, respectively. MCP1826/MCP1826S LDO has a very low dropout
The SHDN input will ignore low-going pulses (pulses voltage specification of 250 mV (typical) at 1000 mA of
meant to shut down the LDO) that are up to 400 ns in output current. See Section 1.0 “Electrical Charac-
pulse width. If the shutdown input is pulled low for more teristics” for maximum dropout voltage specifications.
than 400 ns, the LDO will enter Shutdown mode. This The MCP1826/MCP1826S LDO operates across an
small bit of filtering helps to reject any system noise input voltage range of 2.3V to 6.0V and incorporates
spikes on the shutdown input signal. input Undervoltage Lockout (UVLO) circuitry that keeps
On the rising edge of the SHDN input, the shutdown the LDO output voltage off until the input voltage
circuitry has a 30 µs delay before allowing the LDO reaches a minimum of 2.00V (typical) on the rising
output to turn on. This delay helps to reject any false edge of the input voltage. As the input voltage falls, the
turn-on signals or noise on the SHDN input signal. After LDO output will remain on until the input voltage level
the 30 µs delay, the LDO output enters its soft-start reaches 1.82V (typical).
period as it rises from 0V to its final regulation value. If Since the MCP1826/MCP1826S LDO undervoltage
the SHDN input signal is pulled low during the 30 µs lockout activates at 1.82V as the input voltage is falling,
delay period, the timer will be reset and the delay time the dropout voltage specification does not apply for
will start over again on the next rising edge of the output voltages that are less than 1.8V.
SHDN input. The total time from the SHDN input going
For high-current applications, voltage drops across the
high (turn-on) to the LDO output being in regulation is
PCB traces must be taken into account. The trace
typically 100 µs. See Figure 4-4 for a timing diagram of
resistances can cause significant voltage drops
the SHDN input.
between the input voltage source and the LDO. For
applications with input voltages near 2.3V, these PCB
TOR trace voltage drops can sometimes lower the input
400 ns (typ) voltage enough to trigger a shutdown due to
70 µs undervoltage lockout.
30 µs
SHDN 4.8 Overtemperature Protection

The MCP1826/MCP1826S LDO has tempera-
ture-sensing circuitry to prevent the junction tempera-
ture from exceeding approximately 150°C. If the LDO
junction temperature does reach 150°C, the LDO
VOUT
output will be turned off until the junction temperature
cools to approximately 140°C, at which point the LDO
output will automatically resume normal operation. If
FIGURE 4-4: Shutdown Input Timing
the internal power dissipation continues to be
Diagram.
excessive, the device will again shut off. The junction
temperature of the die is a function of power dissipa-
tion, ambient temperature and package thermal
resistance. See Section 5.0 “Application Cir-
cuits/Issues” for more information on LDO power
dissipation and junction temperature.

MCP1826/MCP1826S
5.0 APPLICATION In addition to the LDO pass element power dissipation,
there is power dissipation within the
CIRCUITS/ISSUES MCP1826/MCP1826S as a result of quiescent or
ground current. The power dissipation as a result of the
5.1 Typical Application ground current can be calculated using the following
The MCP1826/MCP1826S is used for applications that equation:
require high LDO output current and a power good
output. EQUATION 5-2:
P I  GND  = V IN  MAX   I VIN
VOUT = 2.5V @ 1000 mA Where:
MCP1826-2.5
On R1 PI(GND) = Power dissipation due to the
Off 1 2 3 4 5 10 k C2 quiescent current of the LDO
SHDN 10 µF
VIN(MAX) = Maximum input voltage
3.3V VIN
IVIN = Current flowing in the VIN pin
C1
4.7 µF with no LDO output current
GND PWRGD (LDO quiescent current)
The total power dissipated within the

FIGURE 5-1: Typical Application Circuit. MCP1826/MCP1826S is the sum of the power dissi-
pated in the LDO pass device and the P(IGND) term.
5.1.1 APPLICATION CONDITIONS Because of the CMOS construction, the typical IGND for
Package Type = TO-220-5 the MCP1826/MCP1826S is 120 µA. Operating at a
maximum VIN of 3.465V results in a power dissipation
Input Voltage Range = 3.3V ± 5%
of 0.12 milli-Watts for a 2.5V output. For most
VIN maximum = 3.465V applications, this is small compared to the LDO pass
VIN minimum = 3.135V device power dissipation and can be neglected.
VDROPOUT (max) = 0.400V The maximum continuous operating junction
VOUT (typical) = 2.5V temperature specified for the MCP1826/MCP1826S is
+125°C. To estimate the internal junction temperature
IOUT = 1000 mA maximum
of the MCP1826/MCP1826S, the total internal power
PDISS (typical) = 0.965W dissipation is multiplied by the thermal resistance from
Temperature Rise = 28.27°C junction-to-ambient (RJA) of the device. The thermal
resistance from junction to ambient for the TO-220-5
package is estimated at 29.3°C/W.
5.2 Power Calculations
5.2.1 POWER DISSIPATION EQUATION 5-3:
T J  MAX  = P TOTAL  R JA + T A  MAX 
The internal power dissipation within the
MCP1826/MCP1826S is a function of input voltage,
output voltage, output current and quiescent current. TJ(MAX) = Maximum continuous junction
Equation 5-1 can be used to calculate the internal temperature
power dissipation for the LDO. PTOTAL = Total device power dissipation
RJA = Thermal resistance from junction to
EQUATION 5-1: ambient
P LDO =  V IN  MAX  – V OUT  MIN    I OUT  MAX  TA(MAX) = Maximum ambient temperature
Where:
PLDO = LDO Pass device internal
power dissipation
VIN(MAX) = Maximum input voltage
VOUT(MIN) = LDO minimum output voltage

MCP1826/MCP1826S
The maximum power dissipation capability for a 5.3 Typical Application
package can be calculated given the
junction-to-ambient thermal resistance and the maxi- Internal power dissipation, junction temperature rise,
mum ambient temperature for the application. junction temperature and maximum power dissipation
Equation 5-4 can be used to determine the package is calculated in the following example. The power
maximum internal power dissipation. dissipation as a result of ground current is small
enough to be neglected.
EQUATION 5-4:
5.3.1 POWER DISSIPATION EXAMPLE
 T J  MAX  – T A  MAX  
P D  MAX  = ---------------------------------------------------
R JA Package
Package Type = TO-220-5
PD(MAX) = Maximum device power dissipation
Input Voltage
TJ(MAX) = Maximum continuous junction
VIN = 3.3V ± 5%
temperature
LDO Output Voltage and Current
TA(MAX) = Maximum ambient temperature
VOUT = 2.5V
RJA = Thermal resistance from junction to
ambient IOUT = 1000 mA
Maximum Ambient Temperature
TA(MAX) = 60°C
EQUATION 5-5:
T J  RISE  = P D  MAX   R JA Internal Power Dissipation
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)
TJ(RISE) = Rise in device junction temperature PLDO = ((3.3V x 1.05) – (2.5V x 0.975))
over the ambient temperature x 1000 mA
PD(MAX) = Maximum device power dissipation PLDO = 1.028 Watts
RJA = Thermal resistance from junction to 5.3.1.1 Device Junction Temperature Rise
ambient
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
EQUATION 5-6: from junction to ambient for the application. The
thermal resistance from junction-to-ambient (RJA) is
T J = T J  RISE  + T A
derived from EIA/JEDEC standards for measuring
thermal resistance. The EIA/JEDEC specification is
TJ = Junction temperature
JESD51. The standard describes the test method and
TJ(RISE) = Rise in device junction temperature board specifications for measuring the thermal
over the ambient temperature resistance from junction to ambient. The actual thermal
TA = Ambient temperature resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an Appli-
cation” (DS00792), for more information regarding this
subject.
TJ(RISE) = PTOTAL x RJA

TJ(RISE) = 1.028 W x 29.3°C/W
TJ(RISE) = 30.12°C

MCP1826/MCP1826S
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
TJ = TJ(RISE) + TA(MAX)
TJ = 30.12°C + 60.0°C
TJ = 90.12°C
5.3.1.3 Maximum Package Power

Dissipation at 60°C Ambient
Temperature
TO-220-5 (29.3° C/W RJA):
PD(MAX) = (125°C – 60°C) / 29.3°C/W
PD(MAX) = 2.218W
DDPAK-5 (31.2°C/Watt RJA):
PD(MAX) = (125°C – 60°C)/ 31.2°C/W
PD(MAX) = 2.083W
From this table, you can see the difference in maximum
allowable power dissipation between the TO-220-5
package and the DDPAK-5 package.

MCP1826/MCP1826S
6.0 PACKAGING INFORMATION
6.1 Package Marking Information

3-Lead DDPAK (MCP1826S) Example:
XXXXXXXXX MCP1826S
XXXXXXXXX 08EEB^^
e3
YYWWNNN 0730256
1 2 3 1 2 3
3-Lead SOT-223 (MCP1826S) Example:
XXXXXXX 1826S08
XXXYYWW EDB0730
NNN 256
3-Lead TO-220 (MCP1826S) Example:
XXXXXXXXX MCP1826S
XXXXXXXXX 12EAB^^
e3
YYWWNNN 0730256
1 2 3 1 2 3
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP1826/MCP1826S
Package Marking Information (Continued)
5-Lead DDPAK (MCP1826) Example:
XXXXXXXXX MCP1826
XXXXXXXXX e3
10EET^^
YYWWNNN 0730256
1 2 3 4 5 1 2 3 4 5
5-Lead SOT-223 (MCP1826) Example:
XXXXXXX 1826-08
XXXYYWW EDC0730
NNN 256
5-Lead TO-220 (MCP1826) Example:
XXXXXXXXX MCP1826
XXXXXXXXX e3
08EAT^^
YYWWNNN 0730256
1 2 3 4 5 1 2 3 4 5
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP1826/MCP1826S

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

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3-Lead Transistor Outline Package (AB) - [TO-220]
A E B
SEATING
E2
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E
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Microchip Technology Drawing C04-034-AB Rev B Sheet 1 of 2

MCP1826/MCP1826S
3-Lead Transistor Outline Package (AB) - [TO-220]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Terminals N 3
Terminal Pitch e .100 BSC
Overall Terminal Pitch e1 .200 BSC
Overall Height A .160 - .190
Tab Thickness A1 .045 - .055
Base to Lead A2 .090 - .115
Terminal Width b .025 .033 .040
Shoulder Width b2 .045 - .060
Terminal Thickness c .015 - .022
Overall Length D .560 - .590
Molded Package Length D1 .330 - .355
Exposed Pad Length D2 .474 - .507
Overall Width E .385 - .415
Exposed Pad Width E1 .300 REF
Allowable Stamping Irregularities Zone E2 - - .030
Tab Length H1 .234 - .258
Terminal Length L .540 - .560
Terminal Shoulder Length L1 .243 REF
Mounting Hole Diameter ØP .146 - .156
Mounting Hole Center Q .103 - .113
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-034-AB Rev B Sheet of 2

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MCP1826/MCP1826S
APPENDIX A: REVISION HISTORY
Revision C (May 2021)

• Updated the Features section.
• Updated Section 6.0 “Packaging Information”.
• Updated the Product Identification System section
to include Automotive representation.
• Minor editorial corrections.
Revision B (February 2013)

• Updated the value of VDROPOUT (max) in
Section 5.1 “Typical Application”.
Revision A (August 2007)

• Original Release of this Document.

MCP1826/MCP1826S
NOTES:

MCP1826/MCP1826S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX X X X/ XX Examples:

a) MCP1826-0802E/XX: 0.8V LDO Regulator
Device Output Feature Tolerance Temp. Package
b) MCP1826-1002E/XX: 1.0V LDO Regulator
Voltage Code
c) MCP1826-1202E/XX: 1.2V LDO Regulator
d) MCP1826-1802E/XX 1.8V LDO Regulator
Device: MCP1826: 1000 mA Low Dropout Regulator e) MCP1826-2502EXX: 25V LDO Regulator
MCP1826T: 1000 mA Low Dropout Regulator f) MCP1826-3002E/XX: 3.0V LDO Regulator
Tape and Reel g) MCP1826-3302E/XX 3.3V LDO Regulator
MCP1826S: 1000 mA Low Dropout Regulator
MCP1826ST: 1000 mA Low Dropout Regulator h) MCP1826-5002E/XX: 5.0V LDO Regulator
Tape and Reel i) MCP1826-ADJE/XX: ADJ LDO Regulator
a) MCP1826S-0802E/XX:0.8V LDO Regulator

Output Voltage *: 08 = 0.8V “Standard”
12 = 1.2V “Standard” b) MCP1826S-1002E/XX:1.0V LDO Regulator
18 = 1.8V “Standard” c) MCP1826S-1202E/XX 1.2V LDO Regulator
25 = 2.5V “Standard”
d) MCP1826S-1802E/XX 1.8V LDO Regulator
30 = 3.0V “Standard”
33 = 3.3V “Standard” e) MCP1826S-2502E/XX 2.5V LDO Regulator
50 = 5.0V “Standard” f) MCP1826S-2502E/XX 3.0V LDO Regulator
ADJ = Adjustable Output Voltage ** (MCP1826 only) g) MCP1826S-3302E/XX 3.3V LDO Regulator
*Contact factory for other output voltage options h) MCP1826S-5002E/XX 5.0V LDO Regulator
** When ADJ is used, the “extra feature code” and
“tolerance” columns do not apply. Refer to examples.
Extra Feature Code: 0 = Fixed XX = AB for 3LD TO-220 package
= AT for 5LD TO-220 package
= DB for 3LD SOT-223 package
Tolerance: 2 = 2.0% (Standard)
= DBVAO for 3LD SOT-223 package,
Automotive
Temperature: E = -40C to +125C = DC for 5LD SOT-223 package
= EB for 3LD DDPAK package
Package Type: AB = Plastic Transistor Outline, TO-220, 3-lead = ET for 5LD DDPAK package
AT = Plastic Transistor Outline, TO-220, 5-lead
DB = Plastic Transistor Outline, SOT-223, 3-lead
DBVAO= Plastic Transistor Outline, SOT-223, 3-lead,
Automotive
DC = Plastic Transistor Outline, SOT-223, 5-lead
EB = Plastic, DDPAK, 3-lead
ET = Plastic, DDPAK, 5-lead
Note: ADJ (Adjustable) only available in 5-lead version.

MCP1826/MCP1826S
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
• Microchip is willing to work with any customer who is concerned about the integrity of its code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole Trademarks

purpose of designing with and using Microchip products. Infor- The Microchip name and logo, the Microchip logo, Adaptec,
mation regarding device applications and the like is provided AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
only for your convenience and may be superseded by updates. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
It is your responsibility to ensure that your application meets LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
with your specifications. Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
MICROCHIP MAKES NO REPRESENTATIONS OR WAR- SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
WRITTEN OR ORAL, STATUTORY OR OTHERWISE, other countries.
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NON- AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
PARTICULAR PURPOSE OR WARRANTIES RELATED TO Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-
ITS CONDITION, QUALITY, OR PERFORMANCE. Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, WinPath, and ZL are registered
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI- trademarks of Microchip Technology Incorporated in the U.S.A.
RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-
TIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
WHATSOEVER RELATED TO THE INFORMATION OR ITS Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,
BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,
USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES Dynamic Average Matching, DAM, ECAN, Espresso T1S,
ARE FORESEEABLE. TO THE FULLEST EXTENT EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
FOR THE INFORMATION. Use of Microchip devices in life sup- Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,
port and/or safety applications is entirely at the buyer's risk, and simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,
the buyer agrees to defend, indemnify and hold harmless SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total
Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
Microchip from any and all damages, claims, suits, or expenses ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
resulting from such use. No licenses are conveyed, implicitly or of Microchip Technology Incorporated in the U.S.A. and other
otherwise, under any Microchip intellectual property rights countries.
unless otherwise stated.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2021, Microchip Technology Incorporated, All Rights

Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality. ISBN: 978-1-5224-8121-8

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02/28/20

Microchip Tech MCP1827S 5002E EB - C641174

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MCP1826/MCP1826S

1000 mA, Low-Voltage, Low Quiescent Current

 2007-2021 Microchip Technology Inc. DS20002057C-page 1

Pin Fixed Adjustable Pin

1 SHDN SHDN 1 VIN

3 GND (TAB) GND (TAB) 3 VOUT

DS20002057C-page 2  2007-2021 Microchip Technology Inc.

MCP1826 Fixed Output Voltage

MCP1826 Adjustable Output Voltage

 2007-2021 Microchip Technology Inc. DS20002057C-page 3

DS20002057C-page 4  2007-2021 Microchip Technology Inc.

 2007-2021 Microchip Technology Inc. DS20002057C-page 5

DS20002057C-page 6  2007-2021 Microchip Technology Inc.

Parameters Sym. Min. Typ. Max. Units Conditions

Input Operating Voltage VIN 2.3 6.0 V Note 1

 2007-2021 Microchip Technology Inc. DS20002057C-page 7

Parameters Sym. Min. Typ. Max. Units Conditions

DS20002057C-page 8  2007-2021 Microchip Technology Inc.

Parameters Sym. Min. Typ. Max. Units Conditions

Parameters Sym. Min. Typ. Max. Units Conditions

 2007-2021 Microchip Technology Inc. DS20002057C-page 9

0.09 VIN = 2.3V to 6.0V

Line Regulation (%/V)

Load Regulation (%)

IOUT = 0 mA VIN = 6.0V IOUT = 1.0 mA

Temperature (°C) Temperature (°C)

DS20002057C-page 10  2007-2021 Microchip Technology Inc.

Quiescent Current (μA)

0.20 VOUT = 5.0V Adj 130 +130°C

Quiescent Current (μA)

Temperature (°C) Input Voltage (V)

VOUT = 2.5V VIN = 2.3V for VR=0.8V

150 VIN = 6.0V 160

110 VIN = 3.9V 80

 2007-2021 Microchip Technology Inc. DS20002057C-page 11

IOUT = 1 mA VIN = 3.1 to 6.0V

Line Regulation (%/V)

Load Regulation (%)

0.30 VIN = 6.0V VIN = 4.0V 0.10

VIN = 3.0V 0.00

Temperature (°C) Temperature (°C)

0.08 VOUT = 2.5V

DS20002057C-page 12  2007-2021 Microchip Technology Inc.

0.30 VOUT = 2.5V -20

0.26 -40 VR=1.2V Adj

 2007-2021 Microchip Technology Inc. DS20002057C-page 13

FIGURE 2-29: Dynamic Load Response

FIGURE 2-30: Dynamic Load Response

DS20002057C-page 14  2007-2021 Microchip Technology Inc.

3.3 Ground (GND) 3.7 Exposed Pad (EP)

3.4 Regulated Output Voltage (VOUT)

 2007-2021 Microchip Technology Inc. DS20002057C-page 15

DS20002057C-page 16  2007-2021 Microchip Technology Inc.

requirements, the input capacitance of the LDO is very

The PWRGD output is used to indicate when the output 70 µs

 2007-2021 Microchip Technology Inc. DS20002057C-page 17

SHDN 4.8 Overtemperature Protection

DS20002057C-page 18  2007-2021 Microchip Technology Inc.

The total power dissipated within the

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

Microchip Technology Drawing C04-034-AB Rev B Sheet of 2

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