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Course 2

This document provides an overview of sequential logic circuits and two types of flip-flops: 1) The D-type (delay) flip-flop transfers the digital level from its input D to its output Q on the rising edge of a clock pulse, memorizing the input until the next clock pulse. It can also be used as a frequency divider by connecting its D input to its Q output. 2) The JK flip-flop is another type of flip-flop that is described but not explained in detail.

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10 views1 page

Course 2

This document provides an overview of sequential logic circuits and two types of flip-flops: 1) The D-type (delay) flip-flop transfers the digital level from its input D to its output Q on the rising edge of a clock pulse, memorizing the input until the next clock pulse. It can also be used as a frequency divider by connecting its D input to its Q output. 2) The JK flip-flop is another type of flip-flop that is described but not explained in detail.

Uploaded by

Mada
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Course 2 Acquisition and treatment of experimental data

1. Sequential Logic Circuits


The sequential logic circuits differ from the combinatorial logic circuits in two main
respects:
 The output of the system depends not only on the present external input(s) but also on the
previous inputs state;
 The same external input(s) state can give a different output response.
An important feature of sequential logical circuits, not present in combinatorial logic
circuits, is the presence of feedback connection(s), where the output from one or more logic gates
is fed back into the input(s) of the logic circuits.

1.1. The D-type (delay) Flip-Flop


The delay flip-flop (DFF) has one data input (D) and a clock input (CLK). As can be seen
from Figure 1, the DFF circuit may include also two asynchronous inputs, PRESET and CLEAR,
able to set the flip-flop in a predetermined state, independent on the CLOCK value.

a) b) c)
Figure 4. The DFF: (a) Symbol; (b) equivalent circuit; (c) working diagram

The DFF transfers the digital level from the input D to the output Q, bur this does not
happen immediately and only happens on an rising clock pulse (i.e. as CLK goes from 0 to 1). The
input is thus delayed by up to a clock pulse before appearing at the output. This is illustrated in the
Figure 1.c. The DFF is an edge-triggered device which means that the change of state occurs only
on a clock transition (in this case the rising clock pulse as it goes from 0 to 1). The data
transferred from the D input to the Q output is memorized until the next rising clock pulse.
Additional to the function of elemental memory cell, the DFF may be also used as
frequency divider by connecting, as indicated in Figure 2, the D input to the Q output.

a) b)
Figure 2. Use of the DFF as frequency divider: (a) electronic schematic; (b) signals diagram

It can be seen that for every two input clock pulses only one output clock pulse appears, the
circuit is therefore performing division by 2. It should be noted that this behaviour only takes
places when the clock pulses are reasonably short (but at least long enough for the output to change
state). If the clock pulse is long then oscillation may occur.

1.2. The JK Flip-Flop


The JK flip-flop (JKFF) symbol and a possible internal structure are presented in Figure 3.

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