An optimal algorithm for area / delay trade-off at high level behavioral specification of a digital circuit

SYNOPSIS
SUBMITTED FOR THE DEGREE OF

MASTER OF TECHNOLOGY IN VLSI DESIGN

BY

ANUBHAV SINGHAL

IMS ENGINEERING COLLEGE, GHAZIABAD,

2011-2012
INDEX

1. Introduction 2. Description about synthesis 3. High level synthesis or behavioral synthesis 4. Importance of Behavioral synthesis over RTL logic design 5. Stages of the behavioral synthesis process 6. Proposed Problems 7. Conclusion

Introduction:-

Electronics design automation (EDA or ECAD)is a

category of software tools for designing electronics system such as printed circuit boards and integrated circuits. the tools work together in a design flow the chip designers use to design and analyze entire semiconductor chips. Design flows are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. Moores law has driven the entire IC implementation RTL to GDS ll design flow from one which uses primarily standalone Synthesis ,Placement, Routing algorithms to an integrated construction and analysis flow for design closure. The three main eras of development of Electronic design automationThe Age of Invention: During the invention era, routing, placement, static timing analysis and logic synthesis were invented. The Age of Implementation: In the age of implementation, these steps were drastically improved by designing sophisticated data structures and advanced algorithms. This allowed the tools in each of these design steps to keep pace with the rapidly increasing design sizes. However, due to the lack of good predictive cost functions, it became impossible to execute a design flow by a set of discrete steps, no matter how efficiently each of the steps was implemented. The Age of Integration: This led to the age of integration where most of the design steps are performed in an integrated environment, driven by a set of incremental cost analyzers. Description about synthesis:Logic Synthesis:- Logic synthesis is a process by which an abstract from of desired circuit behavior ,typically register transfer level (RTL)is turned into a design implementation interms of logic gates.

High level synthesis or Behavioral Synthesis:High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior The starting point of a high-level synthesis flow is ANSI C/C++/System C code. The code is analyzed, architecturally constrained, and scheduled to create a register transfer level hardware design language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of tools while the tool does the RTL implementation. Verification of the RTL is an important part of the process. Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register transfer level (RTL), and algorithmic level. While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and Ansi C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the microarchitecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation.The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation. Behavioral synthesis:-Behavioral synthesis is the enabling technology for implementing a practical methodology for high-level design. It fits in with existing design flows and can be selectively applied to portions of a design that will derive the greatest benefit from the using a higher level of abstraction and the automation that it provides. Behavioral synthesis

allows design at higher levels of abstraction by automating the translation and optimization of a behavioral description, or high-level model, into an RTL implementation. It transforms un-timed or partially timed functional models into fully timed RTL implementations. Because a microarchitecture is generated automatically, designers can focus on designing and verifying the module functionality. Design teams create and verify their designs in an order of magnitude less time because it eliminates the need to fully schedule and allocate design resources with existing RTL methods. This behavioral design flow increases design productivity, reduces errors, and speeds verification.

Flow diagram of behavioral synthesis

The behavioral synthesis process incorporates a number of complex stages. This process starts with a high-level language description of a module's behavior, including I/O actions and computational functionality. Several algorithmic optimizations are performed to reduce the complexity

of a result and then the description is analyzed to determine the essential operations and the dataflow dependencies between them. The other inputs to the synthesis process are a target technology library, for the selected fabrication process, and a set of directives that will influence the resulting architecture. The directives include timing constraints used by the algorithms, as they create a cycle-by-cycle schedule of the required operations. The allocation and binding algorithms assign these operations to specific functional units such as adders, multipliers, comparators, etc.

Importance design:Current

of Behavioral

synthesis over RTL logic

RTL design and refinement is time-consuming and error-prone transistors are now

with the decreses in device geometries. More

available but the resources to evaluated multiple architectural choices and their respective RTL configurations manually architectural choices and their respective RTL configuration manually are prohibitive. its becoming impossible to design effectively and meet project deadlines.As a result ,designers risk locking into architectural and RTL design description that cannot be implemented ,or do not meet the design objectives. Behavioural sysnthesis allows designers to quickly create hardware from untimed high level models. these models accurately describe the function but do not specifically schedule or allocated hardware resources as required when using traditional RTL logic synthesis tools,with behavioral synthesis ,design teams create and verify designs in an order of magnitude less time because it eliminates the need to fully schedule and allocate design resources with existing RTL methods.

Stages of the behavioral synthesis process:The behavioral synthesis process consists of a number of activities .various behavioral synthesis tools perform these activities in different orders using different algorithms.some on the desired solution. behavioural synthesis tools combine some of these activities or perform them iteratively to converge

Lexical processing:Behavioral synthesis is begin swith an algorithmic description of the desired behavior expressed in ahigh level language.Lexical processing parses the high-level souce code and transforms it into an internal representation. Algorithm optimization :Optimizations that can be performed on the algorithm itself include common subexpression elimination and constant folding.Many of these optimizations are commonly used in high-level language compilers or parallelizing compilers. Control/dataflow analysis:The inputs,outputs,and operations of the algorithm are identified and the data dependencies between them are determined.theresukt of this process is usually a control/dataflow graph (CDFG). Library processing:The RTL implementation produced by behavioural synthesis will depend on the capabilities and characteristics of the library parts avialable for the specific implementation technology to be used.Library processing reads the available libraries and determines the functional,timingand area characteristics of the aviable parts. Resource allocation:Resource allocation establishe a set of functional units that will be adequate to implement the design .in many behavioral synthesis system ,an intial resource allocation is performed and subsequently modified during scheduling and/or binding. Scheduling :Scheduling introduces parallelism and the concept of the time .it tranforms the library. Functional unit binding:the algorithm into an FSM representation .Using the data dependencies of the algorithm and the latencies of the functional units in

Binding assigns the operations of the algorithm to specific instances of functional units from the library. Register binding:In cases where values are produced in one clock cycle and consumed in another ,these values must be stored in roasters or memory.the register binding process allocates registers as needed and assigns each value to a physical register. Output processing:The datapath and finite state machine resulting from all of the previous steps are written out as RTL source code in the target language.this code can be structured in a number of ways to optimize the downstream logic synthesis process or to enhance the readability of the code.

Proposed Problems:
Behavioral Synthesis is an automated design process that interprets an algorithmic description of a desired behavior and creates a hardware that implements that behavior. The first step in behavioral synthesisis to compile a specification into an internal representation. The second step is to apply high-level transformations with the goal of optimizing the behavior. Finally, scheduling and allocation converts the behavior into a structure. Scheduling determines the time at which each operation is executed, while allocation synthesizes the necessary hardware to perform the operations. The structure is then passed to other tools for logic synthesis. In this project, initially we will review of various behaviourial synthesis approaches along with their result. Then we will develop a mathematical model that will take user input for area and delay requirement for the given design description at high level language like C or VHDL and calculate best possible trade-off between delay and area based on possible optimization of the given design done at various level like algorithm optimization, scheduling, register binding etc. Secondly, we develop efficient algorithms for algorithmic code optimization, scheduling and register binding while taking care of user requirement of delay and

area. This tool will try to meet the user requirement of delay and area iteratively. Thus, objective of the project is to develop an efficient mathematical model to cater the users need of delay and area at behavioral description level of the design along with generating efficient algorithms/techniques for code optimization, scheduling and register binding.

Conclusion:We have taken a look at the relatively new behavioral methodology, and at the synthesis process that makes it possible. We described about advantages of behavioral synthesis over RTL logic synthesis and discussed different stages of behavioral synthesis. Behavioral synthesis improves productivity improvements this enables will be necessary to face the challenges of designing upcoming systems that are expected to exceed one hundred million gates.