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Combinational Circuit2

The document provides VHDL code to design a circuit that implements the logic equation "res = ( (not(A and B)) and (not(A or B)) ) and C". The code defines an entity with inputs A, B, C and outputs O1, O2, out1, out2, res. It uses O1, O2, out1, out2 as intermediate signals to calculate the logic expression and assign the result to res. A testbench is also provided to simulate the circuit with different input combinations.

Uploaded by

Rinki Kar
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
27 views

Combinational Circuit2

The document provides VHDL code to design a circuit that implements the logic equation "res = ( (not(A and B)) and (not(A or B)) ) and C". The code defines an entity with inputs A, B, C and outputs O1, O2, out1, out2, res. It uses O1, O2, out1, out2 as intermediate signals to calculate the logic expression and assign the result to res. A testbench is also provided to simulate the circuit with different input combinations.

Uploaded by

Rinki Kar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Q.

Write VHDL code & design Circuit for the given equation “res = ( (not(A and B)) and (not(A or
B)) ) and C ”

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity combi2_entity is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

O1 : inout STD_LOGIC;

O2 : inout STD_LOGIC;

out1 : inout STD_LOGIC;

out2 : inout STD_LOGIC;

res : out STD_LOGIC);

end combi2_entity;

architecture Behavioral of combi2_entity is

begin

--res = ( (not(A and B)) and (not(A or B)) ) and C

O1 <= A and B;

O2 <= A or B;

out1 <= not O1;

out2 <= not O2;

res <= (not(O1)) and (not(O2)) and c;

end Behavioral;
-- Module Name: /home/ise/comb2/comb2_tb.vhd

-- Project Name: comb2

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY comb2_tb IS

END comb2_tb;

ARCHITECTURE behavior OF comb2_tb IS

COMPONENT combi2_entity

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

O1 : INOUT std_logic;

O2 : INOUT std_logic;

out1 : INOUT std_logic;

out2 : INOUT std_logic;

res : OUT std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';


--BiDirs

signal O1 : std_logic;

signal O2 : std_logic;

signal out1 : std_logic;

signal out2 : std_logic;

--Outputs

signal res : std_logic;

BEGIN

uut: combi2_entity PORT MAP (

A => A,

B => B,

C => C,

O1 => O1,

O2 => O2,

out1 => out1,

out2 => out2,

res => res

);

-- Stimulus process

stim_proc: process

begin

wait for 1 ps;

A <= '0';

B <= '0';

C <= '0';
wait for 1 ps;

A <= '0';

B <= '0';

C <= '1';

wait for 1 ps;

A <= '0';

B <= '1';

C <= '0';

wait for 1 ps;

A <= '0';

B <= '1';

C <= '1';

wait for 1 ps;

A <= '1';

B <= '0';

C <= '0';

wait for 1 ps;

A <= '1';

B <= '0';

C <= '1';

wait for 1 ps;

A <= '1';

B <= '1';

C <= '0';

wait for 1 ps;

A <= '1';

B <= '1';

C <= '1';

wait for 1 ps;

end process;
END;

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