Topic 2 Comp Sci
Topic 2 Comp Sci
Topic 2 Comp Sci
1 Overview
CPU -the central processing unit contains:
Registers; MAR, MDR, ACC and PC.
MAR - memory address register s purpose is to contain the ram address of
the next instruction. The CPU will want it.
MDR - memory data register purpose is to hold data that will be written to the
RAM or that was read from RAM
CU- the control unit which maintains the system clock speed, coordinates
machine instruction cycles (aka the FED cycle), decodes instructions sent
from the ram and controls the data flow.
ALU- is the arithmetic logic unit and this carries out mathematical operations.
PC - the program counter stores memory instructions.
ACC - accumulator stores the data/results from the ALU
Cache levels
Level 1 - smallest, fastest level. The most expensive is kept inside the CPU
Level 2 - in the middle between the 2. Faster than level 3 but slower than LVL
1. Also in the middle in price and size.
Level 3 - slowest and biggest level of cache. Cheapest and is kept outside but
close to the CPU.
Usually, memory is kept inside the hard disk but decreasing the time it takes
to get the information requires the cache is introduced. A cache hit occurs
when the CPU looks for info and finds it in the cache. If not in the cache it'll
search the RAM. If not present there, it'll search the hard disk drive for the
data required.
Firstly the address of the next instruction is copied from the PV to the MAR
through the address bus.
Next, the Address of the current instruction is copied from the MAR to the
RAM through the address bus.
Now, Data from the RAM is copied to the MDR through the data bus.
Then the PC increments one by one.
The CU decodes.
The ALU executes
Finally, the ALU stores result in the Accumulator.