29/06/2023, 22:54 Commonly Asked DFT Interview Questions (With Answers) | Indeed.

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Interviewing Commonly Asked DFT Interview Questions (With Answers)

Commonly Asked DFT Interview

Questions (With Answers)
Indeed Editorial Team

Updated 8 March 2023

The design for testing or DFT is a procedure that software professionals use to ensure
maximum efficiency in the development process under a resource-limited or reliability
driven scheme. IT professionals use the technique of DFT to remove malfunctioned parts
from a system as much as the time and money allow. If you aim to become a software
professional, learning about the commonly asked DFT questions can help you prepare
effectively for your interview. In this article, we discuss some commonly asked DFT
interview questions and share sample answers alongside tips to help guide your
preparation process.

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Common DFT interview questions

Here are some common DFT interview questions to help you prepare for your interview
efficiently:

Can you explain the scan insertion steps?

Employers can ask you this question to assess your fundamental understanding of the
DFT procedure since the scanning process plays an essential role in implementing
testing successfully. They may also want to test your critical awareness and
comprehension abilities as they carefully analyse how you explain the basic steps. When
answering this question, consider describing the vital stages of the scan insertion
process, and you can also give examples to add more clarity to your answers.

Example: 'Engineers, developers and other software professionals often face issues ensuring
the smooth functioning of chip designs and circuits. For any chip design that contains a large
portion of logic, DFT and scan testing are mandatory procedures of the design process that
can help reduce the complexity of testing various sequential circuits. The underlying concept
of a scan test is to connect several memory elements like flip-flops or latches that form chains
so that the shifting through scan chains can help control the states of DUT.

When software professionals want to enable a scan test for a chip design, they can insert
additional test logic, called scan insertion. Scan insertion primarily comprises two steps. The
first is to replace the plain memory cells, like flip-flops or latches, using the scan cells. The
second step is to connect these cells to form one or more chains. You can use the scan cells in
two different modes, the functional or mission mode that one can use during normal
operations and the scan mode that allows a user to shift through various scan chains.'

Related: What Is The Tree Data Structure? (With Advantages And Types)

What is test point insertion? Can you explain its

scenario?
Employers can ask you this question to assess your subject knowledge and expertise to
determine if you are a good fit for this position. They may want to analyse your
comprehension and speaking abilities to determine if you can explain complex
procedures concisely. When answering this question, consider describing the meaning
and importance of test point insertion alongside sharing its process.

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Example: 'Test point insertion refers to the technique of improving a design's testability and
its test coverage by adding some controllable and straightforward logic to the system.
Whenever there is a complex application-specific integrated circuit or ASIC design, there is
usually some uncontrollable or unobservable logic. Since the designers and engineers cannot
precisely control or observe these logics, it becomes almost impossible to test them for
efficiency. This reason is exactly why the need for a test point insertion technique arises.

While there are several techniques to change the pattern generator in test point insertion,
changing the circuit-under-test or CUT by inserting test points is one way. Test points are
efficient in improving the fault coverage of a system. The process of test point insertion
involves adding control and observation points to the CUT. The observation points help make
a node observable by making it a primary output and sampling it in a scan cell. Engineers and
other software professionals routinely rely on the circuit restructuring during the layout
process to consider the additional delay caused by metal wires.'

Related: Top Data Structure Interview Questions With Example Answers

What is scan compression, and how does it work?

Employers can ask you this question to assess your foundational understanding of the
core concepts. They may want to identify if you have the right skill set to perform scan
compression efficiently. Through this question, they may also want to analyse if you can
contribute to this job role, so consider sharing the meaning and importance. In your
answer, you can also give an example to add more depth to your response and impress
the employers with your range of subject understanding.

Example: 'One of the most common DFT architectures is the scan compression method that
software professionals use to reduce the automatic test pattern generation or ATPG test
application time and data volume. A traditional compression structure uses three distinct
blocks: a decompressor, a compressor, and an X-tolerance or X-mask. This structure helps the
professionals connect the design logic through scan chains. Here, one can compose a
decompressor using a broadcast or spreader network of the scan input pins and the
compressor using the multiple input signature register or MISR logic on the scan output pins.

We can break the existing long scan chains between the scan input and the scan output pins,
also known as FULLSCAN, into smaller scan channels or stumps and connect to the
compression logic interface. We get the target compression ratio when we divide the total
number of scan channels by the external FULLSCAN chains. You can reduce the test time and
the test data volume close to the target ratio when you correctly balance the scan chains. One
of the most significant advantages of using an exemplary DFT architecture is that DFT
engineers can expect more efficiency.'

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Related: All You Need To Know About Data Warehouse Architecture

Can you explain some uses of clock gating in design?

This question tests your practical and technical understanding of the DFT process. Since
clock gating forms an essential part of the entire testing procedure, employers can ask
you this question to determine if you have the technical exposure and skill set to know
about fundamental concepts in a detailed manner. They may also want to assess your
suitability for this job role. When answering this question, consider describing the
meaning and the process of clock gating in an elaborate way, and you can also share
examples to add more depth to your response.

Example: 'Clock gating in design is an essential method that designers and other technical
professionals use to turn off the clock to certain digital design parts when they are not
required. Given that power budgets highly restrict most of the systems on chips or SOCs, it is
imperative to reduce the power consumption as much as possible, and clock gating is one of
the most efficient ways. The operational aspect and the foundational concept of clock gating
are easy.

Because all you need to do as a software professional is to turn off the design when you do
not need it without affecting its functionality. When you turn off the clock to the
design/system, you are essentially reducing the switching activity of the design and, therefore,
its dynamic power. As a design professional, you can also apply clock gating to the smallest
part of digital design or up to the complete subsystems or the entire SOCs. One of the primary
uses of clock gating is that it helps designers reduce the dynamic power dissipation alongside
saving power.'

Related: What Is The Open Group Architecture Framework (TOGAF)?

What is the purpose of implementing DFT?

Employers can ask you this question to see how much you have engaged with DFT
principles to know its underlying importance and uses. They may also want to assess if
you have practical knowledge and exposure to describe its purpose to a layperson. When
answering this question, consider sharing the primary purposes for which professionals
use DFT and its overall importance in design to convey your subject understanding.

Example: 'The DFT process or techniques are essential in the overall design process. They help
designers and engineers reduce the high cost of time and effort needed to generate test vector
sequences for very large-scale integration or VLSI circuits. Using DFT, you can also simplify the
identification process of faulty chips, especially if you have designed them for testability. When
deciding what specific DFT technique to use for a particular circuit, you can consider the

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advantages, such as more straightforward test vector generation, higher fault coverage and
potentially reduced test application time.

Every situation requires different interventions, so you may want to know that not every DFT
technique can yield the best results in every case. Once you have decided on a DFT technique
to access its many benefits, consider applying it consistently throughout the design cycle, from
the inception to the completion process. Another critical use of DFT is that it enables technical
professionals to ensure that they have designed the chip according to the blueprint. It is also
cost-effective as it allows them to test a chip by adding circuitry and improving the
observability of internal nodes.'

Related: 8 VLSI Interview Questions (With Sample Answers And FAQs)

Additional DFT interview questions

Here are some additional DFT interview questions you can expect in your interview:

Why do you use a latch in a clock gating cell?

How do you remove glitches through latch?

How do you decide the number of scan chains for your core?

What do you mean by manufactured defects?

What is the meaning of clock latency?

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