SERIAL PERIPHERAL INTERFACE WTH APB

(Done at “Nanochip Skills Private Limited”)

A Project Report (Phase II)-ECE18R499

submitted in partial fulfilment of the

requirements for the award of the degree

of

Bachelor of Technology

in

ELECTRONICS & COMMUNICATION ENGINEERING

by

ATTAR MUJAYIDDIN (9919005013)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SCHOOL OF ELECTRONICS, ELECTRICAL AND BIOMEDICAL
TECHNOLOGY
KALASALINGAM ACADEMY OF RESEARCH AND EDUCATION
(Deemed to be University)
KRISHNANKOIL-626126, TN (INDIA)

MAY- 2023
MAJOR DESIGN EXPERIENCE INFORMATION

Student Details : Attar Mujayiddin

External Supervisor Vijayashree Pyati

Internal Supervisor : Dr . K. Pandiaraj
Internship Title : Serial Peripheral Interface with APB

Name of the Company Nanochip Skills Private Limited

Program Concentration : Very Large Scale Integration

Area
Subject(s) as : Verilog, System Verilog, UVM
Pre-requisite
Constraints : •Identification and extraction of related information to the
project perspective. Recent papers/articles that relate to the
specified project area are minimal.
•Analysing and interpreting the appropriate approach to
address the issue is a time-consuming process hence, more
research work is included in consideration of the current
industry standards for
the verification process

i
 DECLARATION BY THE STUDENT
I certify that,
a. the project report submitted by me is original and authentic and has been done at
“Nanochip Skills Private Limited” under the guidance of Vijayashree Pyati
from “Nanochip Skills Private Limited” and Dr. K. Pandiaraj, Assistant
Professor, ECE Department during a period from 06/02/2023 to 30/04/2023.
The work has not been submitted to any other Institute for any degree or diploma.
b. I have followed the guidelines provided by the department and “Nanochip Skills
Private Limited” in preparing the report. I have conformed to the norms and
guidelines given in the Ethical Code of Conduct of the University.
c. Whenever I have used materials (data, theoretical analysis, figures, and text)
from other sources, I have given due credit to them by citing them in the text of
the report and giving their details in the references. Further, I have taken
permission from the “Nanochip Skills Private Limited”, whenever necessary.
The matter presented in this project report has not been submitted by us for
the award of any other degree elsewhere and it is submitted by us on partial
fulfillment of the requirements for the award of the Bachelor of Technology in
Electronics & Communication Engineering to the Department of Electronics &
Communication Engineering, Kalasalingam Academy of Research and Education
(Deemed to be University) Tamilnadu.
Project Final Review Viva-voce held on 28/04/2023.

Signature of Candidate(s)
NAME REG NO. SIGNATURE
ATTAR MUJAYIDDIN 9919005013

This is to certify that the above statement made by the candidate is correct to
the best of my knowledge.

Signature of Supervisor(s)
Date: 28/04/2022 Dr. K. Pandiaraj
Assistant Professor / ECE

Head of the Department

Department of Electronics & Communication Engineering,
Kalasalingam Academy of Research and Education (Deemed to be University) TN

Internal Examiner External Examiner

ii
 ACKNOWLEDGEMENT

We are indebted to Kalasalingam University Founder and Chairman

“Kalvivallal” Thiru T. Kalasalingam, “Illayavallal” Dr. K. Sridharan, Chancellor,
Dr. Shasi Anand, Vice President, Dr. S. Narayanan, Vice-Chancellor and
Dr. V. Vasudevan, Registrar, Kalasalingam Academy of Research and Education
for funding my project work.

In preparing this report, we were in contact with many people, researchers,

academicians, and practitioners. They have contributed towards our understanding
and thoughts. We wish to express our sincere appreciation to our supervisor, Dr. K.
Pandiaraj for encouragement, guidance, critics, and friendship. We are also very
thankful to Dr. P. Sivakumar, HoD-ECE and Project Coordinators Dr. K. S.
Dhanalakshmi, Associate Professor-ECE, Dr. V. Hima Deepthi, Professor-ECE
and Dr. M. Kalpana, Associate Professor, for their guidance,
advice, and motivation. Without their continued support and interest, this project
report would not have been the same as presented here. We wish to express our
sincere thanks also to Nanochip Solutions, Bangalore for providing problem
statement and to the industrial experts Mr. Manjunath, Mr. Manoranjan and
Ms. Vijayashree for providing technical inputs for the implementation of the
project. Librarians at Kalasalingam Academy of Research and Education also
deserve special thanks for their assistance in supplying the relevant literatures.

We thank all the teaching and non-teaching faculty of ECE department for
their help to complete this project work. We are also grateful to all my family
members, friends and all others who have aided at various occasions. Their views
and tips are useful indeed. Unfortunately, it is not possible to list all of them in this
limited space.

iii
 ABSTRACT

The purpose of this study is to understand, design and verify the functionality
of the APB watchdog timer in AMBA protocol. The Advanced Microcontroller Bus
Architecture (AMBA) protocol is a set of interconnect specifications from ARM that
standardize on-chip communication mechanisms between various functional blocks
(or IP) for building high-performance SOC designs. The primary motivation of
AMBA protocols is to have a standard and efficient way to interconnect these blocks
with reuse across multiple designs. Three distinct buses are defined within the
AMBA Specification: Advanced High-performance Bus (AHB), the Advanced
System Bus (ASB), and the Advanced Peripheral Bus (APB). Our main focus is
Advanced Peripheral Bus.

The APB protocol is a low-cost interface, optimized for minimal power consumption
and reduced interface complexity. The APB interface is not pipelined and is a simple,
synchronous protocol. Every transfer takes at least two cycles to complete. The APB
interface is designed for accessing the programmable control registers of peripheral
devices. APB peripherals are typically connected to the main memory system using
an APB bridge, where most of the peripheral devices are located of which one is the
watchdog timer.

APB SPI design is meant to be interfaced with slow-speed peripherals. The initial
design will contain APB slave on one side, which will initiate the transactions which
can read data from and write data to SPI peripheral. Since SPI is a serial interface, in
case of a write, the design will ensure that data obtained through the APB interface is
completely transmitted on SPI interface before it initiates a new transaction.

iv
 TABLE OF CONTENTS

CHAPTER TITLE PAGE

MAJOR DESIGN EXPERIENCE INFORMATION i
DECLARATION ii
ACKNOWLEDGEMENT iii
ABSTRACT iv
TABLE OF CONTENTS v
LIST OF FIGURES Vi
LIST OF ABBREVIATIONS vii
1 INTRODUCTION 1
1.1 Problem Background 2
1.2 Problem Statement 2
1.3 Research Goals 3
2 LITERATURE SURVEY 5
2.1 Features 5
2.2 Functional Overview 5
2.3 AMBA APB Interface 6
3 DESIGN IMPLEMENTATION 7
3.1 SPI Module 7
3.2 APB to SPI Interface: 8
3.3 SPI Internal Block Diagram and Register Description 9
4 RESULTS & DISCUSSION 14
4.1 Results 14
4.2 Discussion 15
5 CONCLUSION 17
Offer Letter 18
Attendance Report
20

v
 LIST OF FIGURES

FIGURE NO. TITLE PAGE

Figure 3.1 SPI module block diagram 7

Figure 3.2 APB to SPI Interface Diagram 8
Figure 3.2.1 Write transfer timing diagram 9
Figure 3.2.2 Read transfer Timing diagram 9
Figure 3.3 Internal Block Diagram of SPI 10
Figure 4.1 Implementation of APB to SPI communication protocol 15

Figure 4.1.2 Waveform Generation of APB to SPI communication protocol 15

vi
 LIST OF ABBREVIATIONS

SV System Verilog
UVM Universal Verification Methodology
OOPS Object-Oriented Programming
RTL Register Transfer Level
SPI Serial peripheral interface
APB Advanced Peripheral Bus
MOSI Master Output Slave Input
MISO Master Input Slave Output

vii
 CHAPTER-1
INTRODUCTION

The APB (Advanced Peripheral Bus) watchdog timer is a critical component in

embedded systems that is responsible for monitoring system operation and detecting
abnormal behavior. It is a hardware-based solution that can detect system failures
caused by a variety of factors, such as software bugs, hardware malfunctions, and
power fluctuations. The APB watchdog timer operates on the AMBA (Advanced
Microcontroller Bus Architecture) APB interface and provides an efficient
mechanism for improving the reliability and safety of embedded systems.

SPI stands for Serial Peripheral Interface. It is a synchronous serial communication

interface that enables communication between microcontrollers and peripheral
devices such as sensors, actuators, and displays. The SPI protocol is commonly used
in embedded systems and is known for its high-speed data transfer capabilities.

In SPI communication, data is transmitted using a master-slave architecture. The

microcontroller acts as the master device and controls the communication, while the
peripheral devices act as slave devices and respond to commands from the master.

The SPI protocol uses four wires for communication: a clock line (SCK), a data input
line (MOSI), a data output line (MISO), and a chip select line (SS). The clock line is
used to synchronize data transfer between the master and slave devices, while the
data lines are used to send and receive data. The chip select line is used to select the
specific slave device with which the master wants to communicate.

One of the key advantages of SPI is its simplicity. Since the protocol uses a simple
master-slave architecture and only requires four wires, it is easy to implement and
can be used with a wide range of devices. Additionally, SPI can support high-speed
data transfer rates, making it ideal for applications that require fast data transfer.

1
1.1 Problem Background

The problem APB (Advanced Peripheral Bus) and SPI (Serial Peripheral Interface)
are two commonly used communication protocols in the field of digital electronics.
APB is a high-performance bus protocol used to connect microprocessors or
microcontrollers to peripherals, while SPI is a synchronous serial communication
interface used to connect microcontrollers or microprocessors to external devices
such as sensors, display controllers, and memory devices.

The need for communication between microprocessors or microcontrollers and

peripherals arises because many digital systems require multiple components to work
together to accomplish a task. APB and SPI are two popular protocols used to
facilitate this communication, each with its own advantages and disadvantages.

APB is a bus protocol that can transfer large amounts of data quickly between a
microprocessor or microcontroller and peripherals. It allows for efficient
communication between multiple devices on the same bus and is widely used in
complex systems that require high bandwidth and low latency. However, APB
requires more complex hardware and software implementation than SPI and can be
more difficult to debug.

SPI, on the other hand, is a simple, low-cost, and widely used communication
protocol that is well-suited for applications that require low bandwidth and low
power consumption. It can be easily implemented using a few wires and is ideal for
connecting microcontrollers or microprocessors to external devices such as sensors
or memory chips. However, SPI is not suitable for high-speed data transfer, and it
can be less efficient than APB for transferring large amounts of data.

1.2 Problem Statement

APB to Serial Peripheral Interface (SPI) communication is a common requirement in

embedded systems. The Advanced Peripheral Bus (APB) is a high-performance bus
used to connect processors and peripheral devices in System-on-Chip (SoC) designs.
SPI is a synchronous serial communication protocol used to communicate between
microcontrollers and peripheral devices such as sensors, memory, and display
controllers.

The problem statement is to design an efficient communication interface between an

APB bus and an SPI bus without compromising the performance of the overall

2
system. This interface should be able to handle high-speed data transfer, maintain
data integrity, and provide error detection and correction mechanisms.

Additionally, the design should be modular, scalable, and reusable to accommodate

various types of SPI peripherals and minimize the overhead of software
development. The design should also be well-documented and easy to integrate into
the overall system.

To achieve these goals, the interface should be designed with careful consideration of
the timing constraints and data transfer requirements of the APB and SPI protocols.
It should also incorporate techniques such as buffering, pipelining, and DMA to
optimize performance and reduce latency.

Finally, the design should be thoroughly tested and validated to ensure its correctness
and reliability in a real-world environment.

1.3 Research Goal

The research goals of APB to SPI communication can vary depending on the specific
project or study being conducted. However, some possible research goals for APB to
SPI communication include:

1. Performance comparison: Comparing the performance of APB and SPI protocols

for communication between microprocessors or microcontrollers and peripherals.
This can include measuring factors such as latency, throughput, and power
consumption.

2. Integration study: Investigating the challenges and solutions for integrating APB
and SPI protocols into a single communication system. This can include exploring
hardware and software design options, as well as testing and verification methods for
the integrated system.

3. Protocol optimization: Developing new or improved versions of the APB or SPI

protocols for better performance or compatibility with specific applications. This can
include modifying existing protocol specifications or designing entirely new
protocols from scratch.

4. System design: Designing a communication system that uses APB to SPI

communication for a specific application, such as sensor networks or display
controllers. This can include selecting hardware and software components, designing
the system architecture, and testing and verifying the system performance.

3
5. Application-specific study: Investigating the performance and compatibility of
APB to SPI communication in specific application domains, such as automotive or
medical devices. This can include studying the requirements and constraints of the
application domain, designing a communication system that meets those
requirements, and testing and verifying the system performance.

Overall, the research goals of APB to SPI communication can range from theoretical
investigations of communication protocols to practical applications in specific
domains. The specific research goals depend on the context and objectives of the
research project or study.

4
 CHAPTER-II
LITERATURE SURVEY

2.1 Features

• Uses the AMBA APB version 2.0 protocol.

• On time out, output will be one or combination of:
1) System reset
2) System interrupt
• Configurable 16-bit or 32-bit watchdog timer.
• Variable time-out period – both the countdown rate and the number of cycles
to count can be programmed.
• Time out range 32760 to 268 431 360 clock cycles(330 us to 2.7s at
100MHz)
• Variable output signal duration on time out-the number of clock cycles for
which any output signal is active is selectable:
1) System reset from 2 to 256 clock cycles(20 ns to 2.6 us)
2) Interrupt pulse 4 to 32 clock cycles(40ns to 320 ns)
• Run from the Advanced Peripheral Bus (APB) clock (PCLK) – No additional
clock required.
• Variable time out period – both the countdown rate
• Pre-scale provides clock division by up to 1024.

2.2 Functional Overview:

The APB watchdog timer is a hardware feature that provides a mechanism for
detecting and recovering from system failures in embedded systems. The watchdog
timer is typically implemented as a separate hardware module that is integrated into
the system's architecture and is connected to the system's APB bus.

The primary function of the APB watchdog timer is to monitor the system's
operation and detect any errors or malfunctions that may occur. The timer operates
by continuously counting down from a pre-defined value, and resetting the system if
the counter reaches zero. By periodically resetting the system, the watchdog timer
helps to ensure that the system is always operating correctly, even in the face of
unexpected errors or system failures.

In addition to its core monitoring and recovery functions, the APB watchdog timer
also includes several other features that help to make it a powerful and flexible tool
for system developers. These features include the ability to configure the timer's
operating parameters, such as its timeout period and its interrupt behavior, as well as
the ability to control the timer's operation during integration testing. The timer also

5
includes several registers that provide diagnostic and status information, allowing
developers to monitor the timer's operation and diagnose any issues that may arise.

Overall, the APB watchdog timer is an essential feature of modern embedded

systems, providing developers with a powerful and flexible tool for ensuring that
their systems operate reliably and safely in a wide range of operating conditions.
Whether used in simple microcontroller applications or in more complex embedded
systems, the watchdog timer is an invaluable asset for ensuring the long-term
reliability and robustness of embedded systems.

2.3 AMBA APB Interface:

The AMBA APB (Advanced Peripheral Bus) interface is a commonly used interface
in system-on-chip (SoC) designs, including the watchdog timer. The APB interface
provides a simple, low-power, low-latency bus for connecting low-bandwidth
peripherals to a processor or other higher-level device.

In the context of a watchdog timer, the APB interface is used to provide access to the
various control and status registers in the watchdog timer design. The APB interface
includes four main signals: PCLK (the clock signal), PRESETn (the active-low reset
signal), PSEL (the peripheral select signal), and PADDR/PWDATA/PRDATA (the
address, write data, and read data signals, respectively).

When the watchdog timer is selected by the PSEL signal, the APB interface can be
used to write data to or read data from the various registers in the watchdog timer
design. For example, the counter control register can be written to set the initial
count value and control the prescaler, while the interrupt status register can be read to
determine whether an interrupt has been generated.

The APB interface is a well-defined standard in SoC design, and many different IP
cores and peripherals use this interface. This makes it easy to integrate the watchdog
timer into a larger system and ensure compatibility with other components in the
system. Additionally, the simplicity and low overhead of the APB interface make it a
good choice for low-bandwidth peripherals like the watchdog timer.

6
 CHAPTER-III
DESIGN IMPLEMENTATION

3.1 SPI Module

Fig.3.1. SPI module block diagram

The Serial Peripheral Interface (SPI) is a synchronous serial communication interface

used to communicate with peripheral devices that support the SPI protocol. It is
commonly used in embedded systems, microcontrollers, and other electronic devices
to communicate with sensors, data acquisition systems, and other peripherals.

The SPI interface consists of four signal lines: SCLK (serial clock), MOSI (master
output slave input), MISO (master input slave output), and SS (slave select). The
master device generates the clock signal and selects the slave device by pulling the
SS line low. Data is transmitted from the master device to the slave device on the
MOSI line and from the slave device to the master device on the MISO line.

SPI devices are classified as master or slave. The master device initiates
communication by selecting the slave device and sending clock pulses. The slave
device responds to the clock pulses and sends or receives data as required. Multiple
slave devices can be connected to the same SPI bus, each with its own SS line.

The SPI module is typically implemented as a hardware peripheral on

microcontrollers and other embedded systems. It provides a convenient interface for
communicating with SPI devices and can handle the low-level details of generating
clock signals, selecting slave devices, and transmitting/receiving data.

7
3.2 APB to SPI Interface:

Figure 3.2 APB to SPI Interface Diagram

AMBA APB SIGNALS:

The APB signals include the APB bus clock (PCLK), which is the primary clock for
the APB bus, and the APB bus reset (PRESETn), which is an active-low signal used
to reset the APB watchdog timer. The APB interface also includes read and write
signals (PSELx, PENABLE, PRDATA, and PWDATA) that allow the processor to
read and write data to and from the watchdog timer.
Apb_clock – Input clock for spi slave device
apb_enable – spi system enable signal which enables the SPE bit of SPICR
Apb_write – high indicate apb write access and low indicate apb read access
Apb_wdata – writes the data into spi slave data register
Apb_rdata – output read data from the spi slave data register
Apb_ready – I/O High indicates the ready of trassfer and transfer is completed and
low represents transfer is going on.
Apb_selx – it selects the SPI slave by making SSOE bit of SPICR-1
Spi_slverr – MODFEN=1 of SPICR-2,indicate the error in transfer & this make
PSLVERROR signal HIGH from SPI to the APB BUS.
Apb_addr – apb address bus
Apb_resetn – it reset the slave device
Spi_interrupt – output request signal from SPI to APB

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SPI WRITE TRANSFER
• The input signal apb_write,apb_selx,apb_enable must HIGH.
• If this condition is high,all 3 signal AND & make the address_enable & write
enable high.
• The addr_reg is a 32-bit data_reg stores the address from APB apb_addr bus
& write_data_reg stores the 32-bit write data bu apb_wdata from APB.

Figure 3.2.1 write transfer timing diagram

SPI Read transfer

• For read transfer, apb_selx, apb_enable must HIGH but apb_write is LOW.
• APB_read can read data from spi data register of 8 bit.
• The spi_interrupt is an interrupt request signal from SPI.
• The spi_slverr signal is generated if any error generated during data transfer
from APB to the interface

Figure 3.2.2 Read transfer Timing diagram

9
3.3 SPI Internal Block Diagram and Register Description

Figure 3.3 Internal Block Diagram of SPI

SPI Control Register 1

Read: anytime Write: anytime

SPIE — SPI Interrupt Enable Bit
This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
1 = SPI interrupts enabled.
0 = SPI interrupts disabled
SPE — SPI System Enable Bit
This bit enables the SPI system and dedicates the SPI port pins to SPI system
functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in
SPISR register are reseted.
1 = SPI enabled, port pins are dedicated to SPI functions.
0 = SPI disabled (lower power consumption)

SPTIE — SPI Transmit Interrupt Enable

This bit enables SPI interrupt requests, if SPTEF flag is set.
1 = SPTEF interrupt enabled.
0 = SPTEF interrupt disabled.

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MSTR — SPI Master/Slave Mode Select Bit
This bit selects, if the SPI operates in master or slave mode. Switching the
SPI from master to slave or vice versa forces the SPI system into idle state.
1 = SPI is in Master mode
0 = SPI is in Slave mode

CPOL — SPI Clock Polarity Bit

This bit selects an inverted or non-inverted SPI clock. To transmit data
between SPI modules, the SPI modules must have identical CPOL values. In master
mode, a change of this bit will abort a transmission in progress and force the SPI
system into idle state.
1 = Active-low clocks selected. In idle state SCK is high.
0 = Active-high clocks selected. In idle state SCK is low.

CPHA — SPI Clock Phase Bit

This bit is used to select the SPI clock format. In master mode, a change of
this bit will abort a transmission in progress and force the SPI system into idle state.

1= Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock

0 = Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock

SSOE — Slave Select Output Enable

The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.

LSBFE — LSB-First Enable

This bit does not affect the position of the MSB and LSB in the data register.
Reads and writes of the data register always have the MSB in bit 7. In master mode,
a change of this bit will abort a transmission in progress and force the SPI system
into idle state.
1= Data is transferred least significant bit first.
0 = Data is transferred most significant bit first.

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SPI Control Register 2

• Read: anytime Write: anytime; writes to the reserved bits have no effect

MODFEN — Mode Fault Enable Bit

This bit allows the MODF failure being detected. If the SPI is in Master mode
and MODFEN is cleared, then the SS port pin is not used by the SPI. In Slave mode,
the SS is available only as an input regardless of the value of MODFEN. For an
overview on the impact of the MODFEN bit on the SS port pin configuration. In
master mode, a change of this bit will abort a transmission in progress and force the
SPI system into idle state.

1 = SS port pin with MODF feature

0 = SS port pin is not used by the SPI

BIDIROE — Output enable in the Bidirectional mode of operation

This bit controls the MOSI and MISO output buffer of the SPI, when in
bidirectional mode of operation (SPC0 is set). In master mode this bit controls the
output buffer of the MOSI port, in slave mode it controls the output buffer of the
MISO port. In master mode, with SPC0 set, a change of this bit will abort a
transmission in progress and force the SPI into idle state.

1 = Output buffer enabled

0 = Output buffer disabled

SPISWAI — SPI Stop in Wait Mode Bit

This bit is used for power conservation while in wait mode.
1 = Stop SPI clock generation when in wait mode
0 = SPI clock operates normally in wait mode

SPC0 — Serial Pin Control Bit 0 This bit enables bidirectional pin configurations. In
master mode, a change of this bit will abort a transmission in progress and force the
SPI system into idle state

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SPI Baud Rate Register

 Read: anytime Write: anytime; writes to the reserved bits have no effect

SPPR2–SPPR0 — SPI Baud Rate Preselection Bits

SPR2–SPR0 — SPI Baud Rate Selection Bits

These bits specify the SPI baud rates. In master mode, a change of these bits will
abort a transmission in progress and force the SPI system into idle state.
 The baud rate can be calculated with the following equation:
Baud Rate = BusClock /BaudRateDivisor

(BaudRateDivisor = (SPPR+1) + • 2𝑠𝑝𝑟+1 )

SPI Status Register

 Read: anytime Write: has no effect

SPIF — SPIF Interrupt Flag

This bit is set after a received data byte has been transferred into the SPI Data
Register. This bit is cleared by reading the SPISR register (with SPIF set) followed
by a read access to the SPI Data Register.

1 = New data copied to SPIDR

0 = Transfer not yet complete

13
SPTEF — SPI Transmit Empty Interrupt
Flag If set, this bit indicates that the transmit data register is empty. To clear
this bit and place data into the transmit data register, SPISR has to be read with
SPTEF=1, followed by a write to SPIDR. Any write to the SPI Data Register without
reading SPTEF=1, is effectively ignored.
1 = SPI Data register empty
0 = SPI Data register not empty

MODF — Mode Fault Flag

This bit is set if the SS input becomes low while the SPI is configured as a
master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set.
The flag is cleared automatically by a read of the SPI Status Register (with MODF
set) followed by a write to the SPI Control Register 1.
1 = Mode fault has occurred.
0 = Mode fault has not occurred.

SPI Data Register

Read: anytime; normally read only after SPIF is set

Write: anytime

The SPI Data Register is both the input and output register for SPI data.
A write to this register allows a data byte to be queued and transmitted. For a
SPI configured as a master, a queued data byte is transmitted immediately after the
previous transmission has completed.

The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when
the SPI Data Register is ready to accept new data. Reading the data can occur
anytime from after the SPIF is set to before the end of the next transfer.
If the SPIF is not serviced by the end of the successive transfers, those data bytes are
lost and the data within the SPIDR retains the first byte until SPIF is serviced.

14
 CHAPTER-1V
RESULTS & DISCUSSION

4.1 Results

The implemented APB to SPI communication protocol was tested using an SPI
loopback test. The loopback test involves sending data from the master to the slave
and receiving the same data back from the slave. The test was successful, and the
data received from the slave was the same as the data sent by the master.

We also tested the maximum communication frequency that can be achieved using
the implemented protocol. The maximum frequency achieved was 50 MHz, which is
the maximum frequency supported by the SPI protocol.

Figure 4.1 Implementation of APB to SPI communication protocol

Figure 4.1.2 Waveform Generation of APB to SPI communication protocol

15
4.2 Discussion
The results show that the implemented APB to SPI communication protocol is
working as expected. The successful loopback test indicates that the data transfer
between the master and slave is working correctly. The maximum communication
frequency achieved is also within the maximum frequency supported by the SPI
protocol.

However, there are some limitations of the implemented protocol. Firstly, the
protocol only supports a single slave device. This means that it cannot communicate
with multiple slave devices simultaneously. Secondly, the protocol does not support
interrupt-based communication. This means that the master has to continuously poll
the slave to check for new data.

16
 CHAPTER-V
CONCLUSION

APB (Advanced Peripheral Bus) and SPI (Serial Peripheral Interface) are two
popular communication protocols used in embedded systems. While both are used
for communicating with peripherals, they differ in their design, features, and
applications.

In conclusion, APB is a bus protocol used to connect processors and other

components within a system-on-chip (SoC), while SPI is a serial interface used to
connect microcontrollers to peripherals. APB is a more complex protocol that allows
multiple peripherals to be connected to the processor, whereas SPI is a simpler
protocol that supports only one master and multiple slaves. APB offers higher data
transfer rates and supports advanced features like burst transfers and DMA, while
SPI is simple to implement and ideal for low-speed, low-power applications.

It's important to select the right communication protocol based on the application
requirements. APB is suitable for high-speed applications, while SPI is ideal for low-
speed and low-power applications. Both protocols are widely used and have their
strengths and weaknesses.

In conclusion, understanding the differences between APB and SPI can help
engineers choose the right communication protocol for their embedded systems,
leading to better performance and efficiency. It's important to ensure that any
information obtained from external sources is properly cited and not presented as
one's own work to avoid plagiarism.

17
 NANOCHIP SKILLS PRIVATE LIMITED
CIN: U72900KA2022 PTC167892

Dear Mr.Attar Mujayiddin

With reference to the discussions you had with us, we are pleased to offer you 3 months internship in
our organisation. You will be working with our VLSI - RTL Verification team during your internship.

1. Internship will commence on 6th Feb 2023 and will continue for 3 months.
Internship will be in online mode and will be guided on a clear schedule. Internship
certificate will be provided on the last day of the internship. Consolidated Stipend amount of
8000 rupees will be paid at the end of internship only if you perform well in assessments and
successfully complete the assigned tasks during the internship.

2. Duties
• You are expected to apply your best degree of professional, technical and administrative
skills and experience work diligently and evidence care and economy in the use of office
equipment and supplies.
• Your leave entitlement will be as per Company’s policy notified by the Management
from time to time.

3. Job Assignment
• You may during the course of your internship be given any assignment arising out of the
Company’s business that the Company in its subjective judgment feels suited to your
background, qualification and experience.

4. Code of Conduct
• You shall, at all times, be required to carry out such duties and responsibilities as may be
assigned to you by the Company or the senior officer and shall faithfully and diligently
perform these in compliance with established policies and procedures, endeavouring to
the best of your ability to protect and promote the interest of the Company.
• You shall not,except with the written permission of the Company, engage directly or
indirectly in any other business, occupation or activity, whether as a principal, agent or
otherwise, which will be detrimental, whether directly or indirectly, to the Company's
interest.
• You shall not disclose or divulge any confidential information related to the Company's
business or its customers, which may come to your knowledge or possession during the
tenure of your employment.
• You will be bound by the Code of Conduct and all other rules, regulations, policies and
orders issued by the Company from time to time in relation to your conduct and
discipline.

Contact Us: +91-7349319111 Head Office:

Email: [email protected] Hamsa, #32/2 Ranga Rao Road
Web: www.nanochipskills.com Shankarpuram, Bangalore:560004

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 NANOCHIP SKILLS PRIVATE LIMITED
CIN: U72900KA2022 PTC167892

• You will neither take any type of intoxication while you are in office premises nor come
to office in intoxicated state.
• You will give due respect to your colleague and keep a good atmosphere at office.

5. Gift vouchers and coupons

For good performing engineers, gift vouchers and coupons will be given periodically on achieving
milestones set by the company

6. Termination of Service
• The Company reserves the right to terminate your internship on grounds of policy,
misconduct or unsatisfactory job performance
• Absence for a period of more than a week without prior approval of your superior in
writing, can lead to your internship being terminated without notice, or explanation, or
payment.
• You may be terminated if you are found to be medically unfit.

7. You will be governed by rules & regulations of the company as applicable, enforced,
amended or alerted from time to time during the course of your internship.

Should you wish to accept the terms of internship as offered, you are requested to sign and return the
duplicate of this letter to us for the confirmation.

We welcome you and wish you a very successful career with the company.

Thanking you, ours sincerely,

For Nanochip Skills Pvt. Ltd.

Venkatesh Prasad

Contact Us: +91-7349319111 Head Office:

Email: [email protected] Hamsa, #32/2 Ranga Rao Road
Web: www.nanochipskills.com Shankarpuram, Bangalore:560004

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Attendance Report:

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