{ “ny THE FUNDANENTALS OF DIGITAL SEMICONDUCTOR TESTING \OZ CMosTable of Contents >2.:| Table of Contents The Basics ........060eeeeeee ‘Objectives Scientific / Engineering Notation 5 Voltage Current Resistance Using Ohm's Law to Test Device Speatations : Digital Numbers ....... : Digital Logic ..... Overview of Semiconductors and ATE ......... wee 2d Objectives .. biseeteseseeseeteaeeesesiseenees ATE Automated Test Equipment Semiconductor Technologies Digital and Analog Circuits ‘Types of ATE Systems .. Tester Loadboards ..... Wafer Probing ...- Probe Cards ...... Device Handlers viens ‘Temperature Forcing Units .... Introduction to Test . Objectives ..... Basic Terms .... What is The Correct Way to Test? The Test System ‘The PMU ce The Pin Electronics .. Basic Rules of Test Engineering, Device Specifications Objectives : Basic Terms .. : ‘The Design Specification - The Test Specification .. ‘The Device Specification ‘Test Conditions and Limits . Parameters that Apply to Parametric Testing (DC) - Parameters that Apply to Functional and AC Testing G Logical Functions . Reading Device Specifications... 256 x 4 RAM Specifications ...... Interpreting the Device Specification .. Device Specifications and Test Conditions ‘The Fundamentals of Digital Semiconductor Testing iFONG raste of Contents Opens and Shorts - PMU Method . Objectives .. _ ‘Why Test for Opens and Shorts? ..... ‘Opens and Shorts Serial Static Method 61 Verifying DC Parameters ....... Objectives ........2.+ Basic Terms Binning .. Program Flow Test Summary. DC Tests and the Hidden Resistance Ohm's Law : YOH/IOH VOL/IOL : IDD Gross Current IDD Static Current TDDQ «....--+ IDD Dynamic Current . Input Currents (IIL/IH) ..... Resistive Inputs—Pull-ups and Pull-downs . +615 +619 2 627 Output Fanout . 6-35 High Impedance 2637 Input Clamp (VJ) : 2642 Output Short Circuit Current (105) 2645 Verifying Functional Parameters 7A Objectives: : : Basic Terms Functional Testing ‘The Test Cycle . Input Data . Input Signal Formats - Developing Input Signal Timings ..... Output Data eo Testing Outputs Developing Output Signal Timing Vector Data Executing a rest... Functional Specifications Gross Functional Tests, Equation Based Timing Testing a Device ‘Sample Device Specification —— Specification Test Conditions locked Inverter Gross Functional Test Conditions for the Clocked Inverter Test Program Statements ...... Standard Functional Tests. Opens and Shorts - Functional Method VIL/VIH VOL/IOL il ‘The Fundamentals of Digital Semiconductor TestingTable of Contents Resistive Output Loading . Functional Z-State— High Impedance Testing Open Drain / Open Source Outputs ....... Testing AC Parameters ..........0secceeeseseceeeeeeeeenneeeeees Objectives: ... AC Parametric Testing - Read & Record . Go-Nogo Testing . Compromises Standard AC Parameters . Setup Time Hold Time Propagation Delay Measurements - Minimum Pulse Widths ......... Maximum Frequency ..... Output Enable Time Output Disable Time ..... AC Specifications from 256 x 4 Static RAM Data Sheet Developing Functional Timing Write Cycle Timing ...... Read Cycle Timing . Bit B12 8:13 Device Characterization ........ Objectives: . ‘Test Vectors and Characterization ‘The Binary Search .... Binary Search Test Applications . ‘The Linear Search . : ‘Common Characterization Parameters « ‘The Test System Datalogger Use of Test System Tools ‘Shmoo Plots ‘Threshold/Level Test Vector Development .. Objectives: . Test Vectors . : Example Vector File «... Working with the Design Engineer Creating Vectors by Hand . Tester Options (Memory Considerations) « Test Vector Examples... Simulation Data .. Simulation for Test Test Program Development Issues . Objectives: Whatis the Primary Purpose of the Test Program? Other Considerations ........ Initializing the Program ‘The Fundamentals of Digital Semiconductor Testing, iiiSoft] @ = “de Table of Contents Verifying the Test Setup ....... Power-on Sequencing ....... Power-off Sequencing . Creating a Test Program . Objectives: .... Developing the Test Plan from the Device Speciation Designing the Test Hardware ... : Writing the Test Program Loadboard Tests Tester Diagnostics =. Running the Program Time Verifying the Functional Test Setup . A Brief Discussion on Test Vectors Troubleshooting «..+..-+.-++++ Objectives conco00 Where to Begin : : Example: IIL/IIH Test Failures .. 2B Debug Tools . -BS veeee 4D “Ma 7M Qualifying and Documenting the Test Program .. Objectives Qualification - Verify testing on handlers and probers 142 Documenting the Test Program ...... Vee CMOS Device Latch-up .......00eseseseeeeeeee seeeees 151 Objectives: 15-4 What is Latch-up? = 154 Latch-up Testing « 1153 Test Patterns ...-.. 11584 Test Procedure Summary 1155 Applying Test Stimulus . 1. 156 Principles of Scan Testing .... ++ 16-1 Objectives: 216-41 What is Scan Testing? ..- 2161 LSSD Technique... 64 ‘Scan Test Equipment 16-4 Glossary . Beene ceeeseeeeeess Glossory-1 Answers to Review Questions . . Answers-1 Section 3 - Introduction to Test : Section 4 - Workbook Exercise . Section 4 - Device Specification - Section 5 - Opens and Shorts . Section 6 - DC Tests . iv ‘The Fundamentals of Digital Semiconductor Testing,ma Table of Contents Section 7 - Functional Test - Answers-8 Section 8 - AC Testing “Answers-11 Section 9 - Device Characterization . “Answers-12 Section 10 - Test Vector Development + Answers-13, Section 11 - Test Program Development issues + Answers-1d Section 12 - Creating a Test Program ... Answers-16 Section 13 - Troubleshooting Answers-17 Section 14 - Qualifying and Documenting the Tes Answers-19 ‘The Fundamentals of Digital Semiconductor Testing vSoft|& = Test 83 (Table of Contents vi ‘The Fundamentals of Digital Semiconductor TestingObjectives This section explains: ‘Number formats ‘+ What is: Voltage, Current, Resistance ‘+ Various methods to measure resistance ‘Digital Logic Pulses + Simple’ ital Circuits The Basics ‘his section is intended to be a short refresher for those who have not used their electronics training recently. It is not, however, intended to be a replacement for a complete basic electronics course. Scientific / Engineering Notation Itmay be necessary to express very large numbers or very small numbers when dealing with test issues. To simplify ‘writing these numbers they are often expressed in scientific notation format. This format uses the mathematical properties of the powers of 10. In engineering texts and writing, abbreviations are used to represent levels of 1000. The following. table shows the scientific notation the computer notation, the abbreviation and names for commonly used numbers in the test industry, ‘Computer Power of 10 Number Name Notation Equivalent Abbreviation 1,000,000,000 | __ Giga 10E+9 1x10? G 1,000,000 | __ Mega 1E+6 1xl0° M 1,000 Kilo 1E3 1x10 K 10| Deka EH 1x10® da 1] Unity 1E+0 1x10" 1 Dect 1E-1 1x10? a 01 Milli 1E3 1x10? m 900001 | Micro 1E6 1x10 2@) ‘000000001 ‘Nano’ 1E-9 1x10? a ‘The Fundamentals of Digital Semiconductor Testing LiSoft| & = Test| a Gn The Basics Voltage ‘Voltage isthe electrical difference of potential between two points. In a power supply the negative terminal has an ‘accumulation of negative charge (a surplus of electrons), while the positive terminal has a positive charge (an accumulation of positive ions). This potential difference can be measured as voltage. “Vis the unit abbreviation for voltage, as in 5.0V (named for Alessandro Volta, an Italian physicist who first measured it). You sometimes create a voltage, called static electricity, when you walk across a carpet in a room with dry air. The formula symbol for voltage is E, short for EMF, short for ElectroMotive Force (which is probably what Volta called it). Some texts also use “V" as the formula symbol for voltage. Current Current isthe flow of charge through a conductor. Ifa conductor (e.g, copper wire) is connected between the positive and negative terminals of a power supply, current will flow in an effort to balance the potential difference (the voltage) between the two points. This flow can be measured and is described in units called amperes or amps (named for André M. Ampere, a French physicist and contemporary of Volta who studied electricity). “A” is the unit abbreviation for current, as in 2.5mA (milliAmps). “T” is the formula symbol for current. Resistance Resistance is the opposing force to current flow, similar to friction which opposes mechanical force. The unit of ‘measurement used to describe the amount of resistance a material offers is the obm, (named after George Simon Ohm, « German physicist who did research on electricity). The unit abbreviation for obm is the Greek letter omega (@). The formula symbol for resistance is R, for the obvious reason. Different materials have different amounts of resistance. The table below shows the typical resistance found in one foot of ‘wire which is one mil (0.001 inches) in diameter, at room temperature, for some common conductors. ‘Material ohms at 25C Silver 9.90) Copper 10.37 Gold 14.70 ‘Aluminum 17.00) Nickel 47.00 Tron 74.00 ‘Carbon 21,000.00 Note: the resistance of most materials changes with temperature, Some materials become more resistive at higher temperatures, called a Positive Temperature Coefficient of resistance (positive TC) and some become less resistive at higher temperatures (negative TC). 12 ‘The Fundamentals of Digital Semiconductor TestingUsing Ohm's Law to Test Device Specifications ‘Ohm's law defines the relationship between current, voltage and resistance as: < = resistance a ‘This indicates that voltage is equal to the current multiplied by the resistance. When voltage and resistance are known, ccurrent can be found using the formu T=E/R ‘When current and resistance are known, voltage can be found using the formula: E-r+R ‘When current and voltage are known, resistance can be found using the formula: R=E/I A test system is capable of supplying voltage and measuring current or supplying current and measuring voltage, therefore ‘many tests are performed to determine the resistance of the device being tested. It may seem odd but the results of tests are not normally measured directly in ohms. The value of a resistor can be found by applying a voltage across the resistor and ‘measuring the current flow through it. Once the voltage and current are known the resistance can be calculated using Ohm's law. ‘The Fundamentals of Digital Semiconductor Testing 13The Basics Measuring Resistance Power Supply Current Meter MEASURE CURRENT >>" o} PATTER Range FORCE VOLTAGE 25 noe | Flow =END= 0v Resistance is measured by forcing a known voltage (E) and measuring the resultant current (), then calculating R=E/I. Note that the resistance of the current meter must be very small compared to the resistance being measured. Figure 1-1 In the example above, the test system's power supply provides 5.0V. The current meter measures the amount of current flow through the resistor and reports its findings. Let's say the current meter indicates a current flow of 2.5 x 10-3 amps (2.5mA). The resistance can be found using the following formula: R=E/1 R= 5 / 2.5m R = 20000, ‘This works out to 2000, so the unknown resistor must be 20000 Using Current Limits to Verify Resistance Semiconductors are designed with certain specifications in mind, so rather than finding the value of an unknown resistor, a tests made to insure thatthe resistor vale is within the design specification range. Ite design specification sates that the resistor value must be 20000 + 10%, the test an be made as follows: ‘The smallest acceptable value of resistance is 18000 (2000 - 2000 * 10%). When 5.0V is applied across an 18000 resistor, 2.7mA of current will flow. This can be determined using the following formula: 14 ‘The Fundamentals of Digital Semiconductor Testing7R / 1800 T= 2.77mA ‘The largest acceptable value of resistance is 2,2000 (2000 + 2000 * 10%). When 5.0V is applied across a 2,2008 resistor 2.27mA of current will flow. ‘To perform the test, an upper current limit of 2.7mA and a lower limit of 2.27mA is set or programmed into the test system. When the tes is performed, the current measured by the current meter is compared to the programmed limits and ‘pass/fail decision is made. Using Voltage Limits to Verify Resistance In the example shown in Figure 1-1 a voltage was applied across the resistor and the resulting current was measured. The test can also be performed by forcing a known current through the resistor and measuring the resultant voltage as seen in Figure 1-2. If the resistor is exactly 20000 and a current of 2.5mA is forced through the resistor a voltage drop equal to '5.0V will appear across the resistor. Measuring Resistance Power Supply Voltage Meter MEASURE VOLTAGE é | Resistance is measured by forcing a known current (I) and measuring the resultant voltage (E), then calculating R=E/. Note that the resistance of the voltmeter must be very high compared to the resistor being measured. Figure 1-2 ‘The Fundamentals of Digital Semiconductor Testing 15rms a Me Basics In order to perform the test using this method the voltage limits must be defined. The lowest acceptable value of resistance, 18000, will produce a voltage drop of 4.5V from this formula: E=I+R E = 2.5x10-3 * 1800 E= 4.5 ‘The highest value of resistance, 22000, will product a voltage drop of 5.5V. The test can be performed by forcing 2.5mA of current and comparing the measured voltage against the upper and lower voltage limits. Ifthe measured value is within the limits the result of the testis pass otherwise itis fail. ‘Since most semiconductor devices operate between 3V and SY, the value of current forced can be adjusted to yield a voltage within this range. For example, ifthe expected resistance value is 50008 (or SKQ) a current of ImA can be forced through the resistor to produce a voltage drop of SV across it. Digital Numbers Most computers in use today are digital computers. Digital refers to the way computers perform their various functions or operations by manipulating digits or numbers. Humans using the Arabic number system also began by manipulating a Me Basics ‘When output data is produced by a circuit, alogic 1 is a voltage of 2.4V or greater and a logic Os a voltage of O.4V or less. (iypical TTL values). Voltages between 0.4V and 2.4V do not represent valid output levels; a circuit receiving an invalid level will not know if tis receiving a 0 or a 1 ‘With an output low guaranteed to be less than 0.4V and an input which recognizes anything up to 0.8V asa low, there is a 0.4V noise margin (0.8 - 0.4). This allows up 0.4V of noise to occur on the signal and still have it correctly recognized as a logic 0. The same noise margin exists with logic 1 levels—2.4V output level and 2.0V input level. Pulse Levels Input Pulse Output Pulse Levels represent normal min/max TTL specification values. Figure 1-4 A logic 0 input level is refered to as VIL. (Voltage In Low). A logic 1 input level is referred to as VIH, (Voltage In High). A logic 0 output level is referred to as VOL (Voltage Out Low). A logic 1 output evel is referred to as VOH (Voltage Out High). 1410 ‘The Fundamentals of Digital Semiconductor TestingThe Basics Inverter ‘The inverter is the most basic of logic gates. With one input and one output, it changes a logic 1 toa logic O and vice versa. Inverters have a single input and a single output. An inverter is shown in Figure 1-5, with its input and output logic shown as a waveform in Figure 1-6. Inverter lparall* 2 TA Truth Table * Our: Input Output 12 4 4 10 = GND Logle 0 in = Logie 1 out Logie 1 in = Logic 0 out For VDD = 5.0V: Any input voltage between 0.0V and 0.8V is a logic 0. Any input voltage between 2.0V and VDD is a logic 1 Any output voltage between 0.0V and 0.4V is a logic 0. Any output voltage between 2.4V and VDD is a logic 1. Figure 1-5 ‘The Fundamentals of Digital Semiconductor Testing Mu‘The Basics Inverter Truth Table Figure 1-6 shows the waveforms for four test cycles. Each cycle begins at “TO” (time zero). In the frst cycle, a logic one {is applied to the input and a logic zero is expected on the output. In the second cycle a logic zero is applied to the input and. a logic one is expected on the output. The patter then repeats. The test period is the time duration of one cycle. VIL and VIF represent the voltage levels that will be applied to the input pin. VOL and VOH represent the expected output levels. Inverter via 1 vou ouput2| o [+ fo fa | FS Period Functional Diagram of Inverter Truth Table Figure 1-6 112 ‘The Fundamentals of Digital Semiconductor TestingThe Basics (Sc AND Gate ‘The AND gate provides a function in which the output value depends on the combination of all input values as given by the statement “The output is logic 1 only if ALL inputs are logic 1; the output is a logic 0 if ANY input is logic 0.” AND gates have 2 or more inputs and one output. See Figure 1-7. Note: Logic consisting of only basic gates such as AND, OR, etc. is sometimes called combinational logic. Truth Table Inputs Output secccccel Logic 0 on ANY input Logic 1 on ALL inputs = Logic 1 out 5 a a ° 2 & Figure 1-7 ‘The Fundamentals of Digital Semiconductor Testing, 113NAND Gate ‘The NAND gate provides a function in which the output value depends on the combination of all input values as given by the statement “The output is a logic 0 only if ALL inputs are logic 1; the output isa logic 1 if ANY input is @ logic 0.” AND gates have 2 or more inputs and one output. See Figure 1-8, This logic function is equivalent to an AND gate followed by an inverter. It exists because itis generally easier to build a semiconductor NAND gate than an AND gate and because itis often used to decrease total gate count when optimizing logic circuits NAND Gate Truth Table: Inputs Output aoncsenel Logic 0 on ANY input Logic 1 on ALL inputs = Logic 0 out Figure 1-8 114 ‘The Fundamentals of Digital Semiconductor Testing& OR Gate ‘The OR gate provides a function in which the output value depends on the combination of all input values as given by the statement “The output is a logic O only if ALL inputs are logic 0; the output isa logic 1 if ANY input is a logie 1." OR ales have 2 or more inputs and one output. See Figure 1-9. OR Gate fs ‘Truth Table Inputs Output 4 123 4 Inputs 2 output = 8 000 3 oo1 4 oro 4 O11 4 100 4 101 4 at 140 4 ‘eND 4444 Logic 0 on ALL inputs = Logic 0 out Logic 1 on ANY input = Logic 1 out Figure 1-9 ‘The Fundamentals of Digital Semiconductor Testing 115sq= wt. The Basics NOR Gate ‘The NOR gate provides a function in which the output value depends on the combination of all input values as given by the statement “The output is a logic 1 only if ALL inputs are logic 0; the output is a logic 0 if ANY input is logic 1." NOR gates have 2 or more inputs and one output. See Figure 1-10. i aescsene| eccccce! Logic 0 on ALL inputs = Logic 1 out Logic 1 on ANY input = Logic 0 out Figure 1-10 his logic function is equivalent to an OR gate followed by an inverter. It exists because itis generally easier to build a semiconductor NOR gate than an OR gate and because itis often used to decrease total gate count when optimizing logic circuits. 1-16 ‘The Fundamentals of Digital Semiconductor TestingThe Basics D Flip Flop Flip flops are so named because the output changes (flips and flops) when a clock signal occurs. There are both level triggered and edge triggered flipflops. The most common and most useful is edge triggered, which means that its output only changes when a clock edge, or transition, occurs. The example in Figure 1-11 shows a D flip flop which is triggered by the positive going edge of the input clock signal. Flip flops have one or more data inputs, one clock input and one output. They may also have a Preset and/or Clear input and an inverted (Q) output. D Flip-Flop vob ’ Truth Table Inputs Output 0 4 No change Clockin—jok__ we change _— fo change No change GND cookin IF LE LILI 1 patain LS Le aor LJ L__ aor I L_IJ A positive clock edge causes the Data In logic level to be latched at the Q output. Figure 1-11 On the D type flip flop, the logic level which gets clocked to the output is the level which is present on the D input when the positive clock edge occurs. You can think of “D” as meaning Duplicate because the output duplicates the input after a clock edge triggers it. The D flip flop is the essence of a 1 bit memory, since whatever gets clocked to the Q output is remembered until the next clock occurs, no matter what logic level occurs on the D input in the meantime. Other types of flip flops (not discussed here) are the T and the J-K. ‘The Fundamentals of Digital Semiconductor Testing 17Soft Test! Sc “eta ‘The Fundamentals of Digital Semiconductor Testing| Soft] |= Overview of Semiconductors and ATE Fc?| m=) Os Overview of Semiconductors and ATE Objectives This section explains: ‘+ Wafers, Dice and Packages + Basic concepts of Automatic Test Equipment ‘+ Overview of Analog, Digital and Memory test systems ‘+ Overview of Loadboards, Probers, Handlers and Temperature units Wafers, Dice and Packages ‘The birth of the transistor in 1947 represents the start of the semiconductor industry. Since then, semiconductor ‘manufacturing and fabrication techniques have advanced significantly. Many individual transistors can now be fabricated and interconnected to form complex “integrated circuits.” Semiconductors called VLSI (Very Large Scale Integration) circuits, often containing millions of transistors, are presently being manufactured. A.wafer has a flat spot or notch (top of wafer) Which is used to insure proper orientation during the fabrication and testing process. ‘Wafers often have process monitor dice which are the same on all wafers regardless of the product. Because these process monitor dice are the same on all wafers, their electrical characteristics are known and checked at specific points during the fabrication process to verify that the process is being performed correctly. Ink dots mark bad dice. Figure 2-1 A wafer after It has been tested and inked photo courtesy Intemational Microelectronic Products, Inc. ‘Semiconductor circuits are initially manufactured in what is called wafer form. A wafer is a circular slice of silicon used as a foundation upon which many individual circuits are built. An individual circuit within a wafer is called a die, with dice being the plural form of the word. Each die is isolated from, and completely independent of, all other dice contained within the wafer. ‘The Fundamentals of Digital Semiconductor Testing, aBond Pads The light colored rectangles around the periphery of this die are bond pads. Probes make contact with the bond pads during wafer test. During the assembly process, bond wires are used to make ‘electrical contact between a die and the pins of a package. Probe Marks Notice the small dark spot on each bond pad. These are probe marks. The bond. pads are made of soft aluminum, so when a probe makes electrical contact with the aluminum pad a small puncture, called a probe mark, is left behind. Probe ‘marks can be used by the probe operator as visual verification that contact is being made to all die pads. ere i an anlae ‘asl Figure 2-2 A single die sawed from a wafer photo courtesy Intemational Microelectronic Products, inc. When the manufacturing process is complete, each die must be thoroughly tested. Testing a wafer is called wafer probing or die sort. During this process, each die is tested to insure that it properly meets its device ‘specification. This involves yerifying voltages, currents, timings and functionality. When a die does not meet its specification, itis marked to indicate that it has failed the test process. Failures are typically indicated by placing an ink dot on defective dice. After all dice on the wafer are probed, the wafer is cut to separate the dice. This is known as sawing the wafer. Any defective dice shown by an ink dot are scrapped (thrown away). Figure 2-2 shows an uninked die that has been sawed from a wafer. This die is now ready to be assembled into a package. 22 ‘The Fundamentals of Digital Semiconductor Testing,‘This picture shows a die mounted in a ie CERDIP package (Ceramic Dual Inline Package). The die is located in the center of the package. This area is called the die cavity. Notice the small bond wires which make the electrical connection between the bond. pads of the die and the pins of the package. ‘The metal lid is used to seal the die inside the package. i Figure 2-3 Tested die mounted in a package Photo courtesy International Microelectronic Products, Inc. ‘Once a dice is assembled into a package, itis tested again in the process called package test or final test. If the probe card or wafer test equipment limits the speed or performance of the circuit, the package test may need to be more rigorous than the wafer test. The packaged device may be tested several times at various temperatures to guarantee parameters which are temperature sensitive. Commercial devices may be tested at 0° C, 25°C and again at 70° C. Military devices may be tested at -55° C, 25° C and 125° C ‘The black lines seen in this photo are bond wires. Bond wires make electrical ‘connection between the bond pads of the die and the pins of a package. ‘The probes on the probe card make contact with the bond pads during wafer test. When viewed through a microscope during wafer test the probes appear similar to the bond wires in this picture. Figure 2-4 A die with bond wires attached to each bond pad photo courtesy Intemational Microelectronic Products, Inc. Figure 2-4 shows a close-up view of a die and bond wires in the die cavity of a device package. ‘The Fundamentals of Digital Semiconductor Testing, 238Overview of Semiconductors and ATE Figure 2-5 Several types of packages Photos courtesy Intemational Microelectronic Products, Inc. and Amkor Electronics Inc, Device packages are available in many different styles, figure 2-5 shows a few examples. Some common package types are listed below. DIP Dual Inline Package (dual indicates the package has pins on two sides) CerDip Ceramic Dual Inline Package PDIP _ Plastic Dual Inline Package PGA PinGrid Array BGA Ball Grid Array SOP Small Outline Package TSOP Thin Small Outline Package TSSOP Thin Shrink Small Outline Package (this one is really getting small!) SIP Single Inline Package SIMM Single Inline Memory Modules (like the memory inside of a computer) QFP Quad Flat Pack (quad indicates the package has pins on four sides) TQFP Thin version of the QFP MQFP Metric Quad Flat Pack MCM — Multi Chip Modules (packages with more than 1 die (formerly called hybrids) 24 ‘The Fundamentals of Digital Semiconductor TestingOverview of Semiconductors and ATE Figure 2-6 A digital test system with two test heads Photo courtesy Schlumberger Technologies inc. ATE - Automated Test Equipment ‘As the complexity of integrated circuits has grown, the complexity of testing them has also grown. For some devices, the largest portion of manufacturing cost is testing. VLSI devices can require hundreds of voltage, uments ate Milfons of ancBotal steps may be tests. Millions of functional steps may be required to insure complete functionality of a ‘VLSI device. To perform such complex testing, Automated Test Equipment (ATE) is used. ATE isa collection of high performance computer controlled test instruments. A test system is the result of this, ‘merging of test instrumentation with a computer. The computer controls the test hardware by executing a set of instructions called the test program. Test systems typically produce very consistent test results which can be repeated quickly and reliably. To keep results correct and consistent, test systems are periodically calibrated, to verify (and adjust if necessary) the accuracy of forcing and measuring instruments. When a test system is used to verify correct operation of an individual die within a wafer, a probe card physically and electrically connects the test system to the die. An interface circuit board called a load board or performance board connects the probe card to the instruments in the test system. The load board and probe card work together to enable electrical signals to pass back and forth between the test system and the die. After dice are assembled into packages, they must be tested again. Testing packaged circuits may be done by manually inserting individual circuits into a device socket on the loadboard. This is called hand test. A faster way to test packaged circuits uses an automatic device handler. A handler has a set of contacts which connect the pins of the package to the loadboard. This provides a complete electrical path between the tester electronics and the die located inside the package. A handler can quickly pick up an untested device, insert it into the test site, then remove the tested device and place it in a particular bin location based on the pass/fail test results. Semiconductor Technologies Various methods are used to fabricate and manufacture digital semiconductor circuits. These methods are known as technologies. Some common technologies are: TTL (Iransistor-Transistor Logic a.k.a. bipolar logic), ECL (Emitter Coupled Logic), SOS (Silicon on Sapphire), and CMOS (Complimentary Metal-Oxide Semiconductor). Although all technologies require testing, this text focuses on digital TTL and CMOS circuits. ‘The Fundamentals of Digital Semiconductor Testing 25wan | 2b UL, Overview of Semiconductors and ATE Digital and Analog Circuits In the past there was a clear distinction between analog and digital circuit designs. Digital circuits manipulate electrical signals represented by zero and one logic levels. A zero is defined as a specific amount of voltage and a one is defined as another specific but different amount of voltage. All valid digital data is represented as either zero or a one. A single one or zero level represents a bit of data. Any number can be represented by assigning weighted values to each data bit within a sequence of zeros and ones. The larger or more precise the value, the more data bits are required to represent the value. A byte is a group of eight bits. Digital values are often processed in bytes. Unlike two level (zero/one) digital data, analog signals are continuous—an infinite number of values exists between any 2 signal levels. Analog circuits may use either voltage or current to represent data values. The ‘most common analog circuit building block is the operational amplifier, or op amp. ‘To help understand the fundamental difference between analog and digital values, think of a clock. The hands ‘on an analog clock move continuously, therefore any and all time values can be determined and the precision of the reading is based to some degree upon the observer. (Ona digital clock only incremental values are displayed. Any values of time which are less than the smallest incremental value (e.g, one minute or one second) are not displayed. When more precision is required of a digital clock, more digits are added, with each new digit representing a smaller incremental time value. Some circuits contain both digital and analog circuitry. An A to D converter changes analog values to digital values; aD to A converter changes digital values to analog. Devices that. both digital and analog circuitry are known as mixed signal devices. Another way of describing circuits is based upon how much of the circuit is analog and how much is digital. The phrase Big D Little A indicates that the circuit consists primarily of digital circuitry. The phrase Big A Little D indicates that the circuit consists primarily of analog circuitry. 26 ‘The Fundamentals of Digital Semiconductor TestingSoft|% == Overview of Semiconductors and ATE Fa} Ss & Types of ATE Systems Although some ATE is considered to be general purpose, most test systems are designed to test a particular class or family of integrated circuits. Some of the more common classes of devices are memories, analog, mixed signal and digital. Each of these classes can also be subdivided, but for this discussion only four classes are considered. Figure 2-7 A Memory Tester Photo courtesy of Teradyne Incorporated. Memory Devices Memory devices are considered digital and many DC test parameters are common to both memory and non— memory digital devices. Memory devices, however, require certain types of functional test procedures that are ‘unique to memories. ATE memory test systems use an algorithmic pattern generator (APG) to generate the functional test patterns. The APG is capable of producing complex functional test sequences from hardware so they do not have to be stored as test vectors. Typical functional test patterns for a memory device are checkerboard, inverted checkerboard, walking ones, walking zeros, and butterfly, to name but a few. The APG generates these patterns each time a device is tested, unlike a non-memory tester which stores pre-generated patterns in vector memory then accesses the data during each test Memory devices typically require long test_ {mes to exercise al of the required test patterns. In an effort to reduce test costs and increase test throughput Memory test systems often test numerous devices in parallel. ‘The Fundamentals of Digital Semiconductor Testing 27Figure 2-8 A Linear Tester Photo courtesy LTX Inc. Analog or Linear Devices Analog device testing requires precise generation and measurement of both voltage and current. Force and measurement accuracy in the range of microvolts and picoamps are sometimes necessary. Analog devices require little if any) digital stimuli in comparison to digital devices. The DC test parameters of analog circuits. are also quite different from digital circuits. Verification of analog parameters requires specific test instrumentation. Analog test systems are often designed using rack mount instrumentation which is custom selected to test a specific device. Examples of analog test parameters are gain, input offset current and voltage, linearity, common mode rejection, power supply rejection, dynamic response, frequency response, settling time, overshoot, harmonic distortion, signal to noise ratio, response time, cross-talk, adjacent channel interference, accuracy and noise. 28 ‘The Fundamentals of Digital Semiconductor TestingSoft] & = Overview of Semiconductors and ATE Fa ws) hw Figure 2-9 A Mixed Signal Tester Photo courtesy Hewiet-Packard. Mixed Signal Devices Mixed signal devices contain both digital and analog circuitry and thus required test systems which have ‘equipment for testing both types of circuitry. Mixed signal testers come in two flavors: Big D Little A testers are designed for circuits that are primarily digital. They do DC and functional tests very effectively but support uly minimal analog testing Big A LtleD tester are designed fr circuits that ae primarily analog, They accurately fest analog parameters but are very limited in functional ‘The Fundamentals of Digital Semiconductor Testing 29Figure 2-10 A Digital Tester Photo courtesy Schlumberger Technologies Inc. Digital Devices Devices with only digital circuitry are tested with digital test systems. These vary greatly in price, performance, size and options, Bench-top testers are available on the low end of the price/ performance scale. ‘They are designed for testing small pin count, low complexity devices. They typically run at a maximum speed of 20MHz and store only a limited number of test patterns. These testers are used to test small scale (SSI) and medium scale (MSI) integrated circuits. At the high end of the digital tester scale are the super fast, super high pin count systems. These high performers may operate at test frequencies to 400MHz and offer up to 1024 tester channels. These systems have highly accurate timing resources and can store millions of functional test patterns. They are often used to characterize new VLSI circuits but their cost may prohibit their use in production testing. In the middle of the tester scale we find the work horses of the semiconductor test industry. These testers are designed to provide the right mix of performance versus cost. The semiconductor industry is extremely sensitive to the cost of test, which can add substantially to the total manufactured cost of a device. Mid— performance testers operate from 50MHz to 100MHz and can be purchased with up to 256 tester channels. A variety of options are available on this type of test system. ‘To control the cost of test, itis critically important that the performance of the test system match the test requirements of the device. Using a high performance test system that offers more features than necessary to test a device will result in test costs which are too high. Using a low performance test system may result in inadequate test coverage. Finding the right balance between equipment cost and performance is essential to controlling the cost of test. 240 ‘The Fundamentals of Digital Semiconductor Testing,Soft] % == Overview of Semiconductors and ATE 5.,| Figure 2-11 Tester Loadboards Photo courtesy ESH Inc. Tester Loadboards A loadboard or performance-board is a mechanical and electrical interface that connects the test system’s test hhead to the device under test. The loadboard often mates to a wafer prober, device handler or other test hardware. The loadboard routes electrical from the pi i t During wafer test, the loadboard interfaces with the probe card. When testing devices by hand, the test socket is mounted on the loadboard. For high volume production testing, the loadboard interfaces with a device handler. Because there are many different types of equipment that the tester must mechanically and electrically mate with, there are a wide variety of loadboards. When testing high speed or high current devices, a custom loadboard is required. These high performance custom circuit boards must be impedance matched to insure signal integrity; they often have matched line lengths (signal paths) to insure timing integrity. Custom loadboards can be very expensive and often take months to design and manufacture. 2aSo me Festl 3 {Overview of Semiconductors and ATE and camera used to view the die to set probe "alignment. When the test head is down the microscope goes through its center. ‘The test head (far let) supplies all the resources for testing the die. The test head is linked to the tester via acable. —A torsion bar manipulator (under the test head) allows the test head to be gently lowered onto the prober. -A white boat of wafers sits at right center under the TV monitor ‘The wafer chuck (to the left of the boat) holds the ‘wafer and positions each die underneath the probe card. ‘Manual alignment controls including a joy stick are visible in the foreground. Figure 2-12 Wafer prober and a test head on a Torsion Bar manipulator Photo courtesy Electroglas Inc. Wafer Probing During Wafer Test, the test head is mated directly to the wafer prober. The test head is flipped upside-down and connects with a prober interface assembly which contains the probe card (this type of testing is often called flip head sort). A single wafer is placed onto the chuck and the wafer is aligned with the probe card to insure a perfect fit. The probe card is then used to make contact with each die on a wafer. The probe card is not visible in Figure 2-12, but itis located in the center of the prober (near the chuck). In the early years, wafers were loaded one at a time onto the chuck, and the alignment of the wafer was performed manually by a skilled probe operator. The probing area was open, as seen in Figure 2-12, allowing both light and contamination to reach the wafers. We now know that some test parameters can be affected by light, which may cause a device to fail. In recent years, contamination has become a larger concern due to the smaller geometry of the components on a die. Contamination can cause parameters to drift, devices to fail and in general, shorten the life of a device. 242 ‘The Fundamentals of Digital Semiconductor Testing,soft] Ge mm Ovarvow of Semiconductors andar 9OH| Sy ge Figure 2-13 Fully Enclosed Prober with Test Head Photo courtesy Electroglas Inc. and Credence Systems Inc. ‘Wafer probers are now designed so that light and contamination can no longer reach the wafers. The wafers are fully enclosed and protected the during the testing process. ‘When the wafers leave the fabrication area they are placed in a protective container called a boat. A boat typically holds about 25 wafers. During the testing process the boat of wafers is placed inside the prober and all wafer handling and alignment functions are performed automatically by the prober. ‘Modem probers can ink defective dice, but many companies prefer to create wafer maps that store the locations of good and bad dice electronically. These maps are then used during the assembly process to separate the good dice from the defective dice. Electronic wafer mapping eliminates problems associated with prober inking attachments. Moder probers are highly reliable and require very little attention. They have greatly eliminated the need for skilled probe operators. ‘The Fundamentals of Digital Semiconductor Testing 2413ss ed. Overview of Semiconductors and ATE Probe Cards Probe cards connect the test head electronics to the individual pads of a die. In Figure 2-14, the probe card is physically part of the load board. In some cases the probe card attaches to the loadboard via a socket. ‘The probe card mechanically attaches to the test head. Tester resources are routed through springy pogo pins that make electrical connection to the bottom of the probe card. Signals then travel through traces within the circuit board to the individual probes. Figure 2-14 High Probe Count Probe Card Photo courtesy Cerprobe inc. Interconnect wires (outside of the white area) route the tester resources to the individual probes. Each probe (inside the white area) ‘makes electrical contact with a bond pad on the die. Figure 2-15 Probes of a High Probe Count Probe Card Photo courtesy Cerprobe Inc. 214 ‘The Fundamentals of Digital Semiconductor TestingOverview of Semiconductors and ATE lS & Untested devices are loaded into the top of the handler using rails or tubes. Devices slide into a thermal chamber, which brings the devices up or down to the proper temperature. ‘One device at a time is loaded into the contactor mechanism (left middle), where electrical contact is made to the test head (not shown). ‘A.user station allows handler setup and control. ‘Tested devices are loaded into specific bins or tubes (lower right) based on the results ofthe testing (called binning). Figure 2-16 Device Handler with thermal chamber Photo courtesy Daymark Ino. Device Handlers Just as there are a wide variety of semiconductor package types, there are as many different styles of handlers to accommodate them. Figure 2-16 illustrates a handler which tests DIP packages (dual in-line package). After device assembly is complete, packaged devices are placed in tubes or trays so that they can be taken to the test area. During production testing, untested devices are loaded into the handler storage bin. The handler then selects an untested device, moves it to the contact area, which interfaces to the test head, and inserts the device in the contactors. Ona signal from the handler that all is ready, the test system performs the required tests and makes a pass/fail decision. Information is sent from the test system to the handler regarding the proper bin assignment and the device is ‘moved and stored in the appropriate bin location. Bins are used to group devices together based on their test results. A device handler must have a minimum of three bins: an untested hin, a good device bin and a reject. ‘bin, Other bins are also useful—for instance, itis convenient to separate rejects into categories such as: DC rejects, AC rejects and Functional rejects. There may also be various grades of good devices based on a Parameter such as operating speed, e.g. 100MHZ, 166MHZ. and 200MHZ devices. The maximum number of bins a handler supports is limited by its physical size. Many handlers also offer environmental chambers for testing devices at temperatures different from room. ‘temperature. ‘The Fundamentals of Digital Semiconductor Testing 245sts 3 (L, Overview of Semiconductors and ATE A.user control station allows temperature setting. When the thermal chamber (the clear round chamber at the end of the tube at left) is placed over a device, the fe device is heated or cooled to a set temperature. Figure 2-17 Temperature forcing system Photo courtesy Thermonics Inc. Temperature Forcing Units ‘Some devices must be tested at various temperatures. For example, a device specifications may state that the circuit must perform properly between -55° C and +125° C. In the past, small hand held thermal probes were used to heat devices to 70° C or 125° C. This method was time consuming and troublesome because the handle of the thermal probe would become excessively hot and it ‘was often difficult to make good thermal contact with the device under test. Hand held probes also do not accurately control device temperature. For low temperature testing, dry ice or liquid nitrogen was often used to cool a device. Using dry ice is not an accurate method of cooling a device because the temperature of dry ice is approximately -60° C and device specifications typically call for -55° C or 0° C. Another problem with dry ice was simply having it available when it was needed, ‘Temperature forcing systems are generally the best method of heating or cooling devices when testing in a +hand socket. Temperature forcing systems are programmable, accurate and fully self contained, requiring only external electrical power. 216 ‘The Fundamentals of Digital Semiconductor TestingIntroduction to Test Introduction to Test Objectives This section explains: + The purpose of testing + Terms used to describe testing + Basic rules of test engineering + The components of a basic test system + The functions of the PMU and Pin Electronics card ‘+ The functions of a simple device and test program Basic Terms There are many terms used to describe semiconductor testing. Some basic terms are defined here, other terms are defined throughout this text. A complete list of terminology is located in the Glossary. The DUT ‘The semiconductor device being tested is often called the DUT (Device Under Test). Itis also sometimes called a UUT (Unit Under Test). Terms that Apply to the DUT Nw? eS tuple Specie pi ‘Signals pass to and from the DUT via connection points called pins. A list of the various pin types, that can be found on digital devices follows: signal Pins Input, output, Tri-State® and bi-directional pins (power and ground pins are not tpt Pi included in this definition). Signal pins have a structure which is different from Power pins. Input Pin A device pin that acts as a butffer between external signals and the internal logic of a device. The input senses the voltage applied to it and transmits a logic 0 or logic 1 level to the internal logic of the device. i; tum A device pin that acts as a buffer between the internal logic of a device and the as we te a environment. An output pin provides the correct voltages to produce a crs 0 or logic 1Jeyel and also supplies the IOL/IOH current. A bo oppiefion ahtae dda “earn MRE farts ee et ween, mudtiple °/P ‘ThreeState output Ore functions as an output pit and has of turning off ‘amingot Gringo ahi a igh inpedaes state) Also called Hs Sane op ‘output. Sie sh fo per pent ee Bi-directional Pin A device pin 1 fomelods aaa input, dx output eis alo capable of taming “TH Pe off (going toa high impedance state). hone, everything We ouwmed, $F dual pis cout ‘The Fundamentals of tal Semiconductor Testing 34De ~iqushea rattuye , ure Introduction to Test Fortonal way ps! 4eo | @ i a fst ped Power Pin A device pin that is connected toa power supply or ground. VDDand VCCare 5" bth typical examples of a power pins, VSS and ground are also identified as power ‘4 pins. that is different from signal pins. vec. ‘The power pin that supplies voltage for a TTL device. yop ‘The power pin that supplies voltage for.a CMOS device. vss ‘The power pin that provides a retum path for the power supplied to the VDD or CC pin, Ground T connect signal pn orater electri node othe test system refermce noe or to VSS, On a device with only one power supply voltage, VSS is often called und. . Sr apply © whey Ae E Be The Test Program fp wily Yost peweneles ‘The purpose of a semiconductor test program is to control the test hardware in a manner that will guarantee that the DUT meets or exceeds all of its design parameters. The design parameters are defined in detail in the dence pegs ‘The test program is often segmented into various parts such as DC tests, functional tests and AC tests, DC testing verifies voltage and current parameters. Functional testing verifies correct operation of the various logical functions of the device. AC testing verifies that the device can perform the logical operations within specified timing constraints. ‘The test program controls the test system hardware so that each test gives a pass or fail result If the test result is a pass, the device meets or exceeds the design specifications. If the result is a failure, the device does not operate within its specifications and should not be used in its intended application. The test program may also separate devices into categories based on theit performance. This is.called binning. A microprocessor that can function correctly at 150Mhz might be categorized as the best part or a “bin one.” A microprocessor that can function correctly at 100Mhz is not as good as the one that works at 150Mhz, but it’s not one that should be thrown away. It might be categorized as a “bin two” and sold to a different customer than the 150MHz device. The test program must also be capable of controlling external hardware such as device handlers or wafer probers. It must collect test results and present the results in a summarized format. The test results provide valuable information to the test and product engineers and can be used to help increase yields. Gree fohy = make perf jail deuovey bat not big 6 % SPCC What is The Correct Way to Test? roed an Tr ‘The question has been asked many times “What is the right way to create a test program?” Unfortunately, there is no single definition of the right way or the best way to test. What is correct for one situation may not be the best for another. Many factors influence the way a test program is constructed. Lets look at some of the ‘more influential factors. ‘+ Whatis the purpose of the test? The following lst illustrates the most common uses of semiconductor test programs. Each of the items listed has unique requirements thus needs a unique test program. rmaanton Wy gon neerou Ble + Wafer Test — The testing of individual devices when they are still in wafer form. This is the first attempt at separating good dice from bad. This activity is also called wafer sort ar die sort. + Package Test — Wafers are cut into individual dice and each die is assembled into a package. The packaged device is then tested to insure that the assembly process was correctly performed and to verify that the device still meets its design specifications. Package testis also called final test. 32 ‘The Fundamentals of Digital Semiconductor Testing,eye mie | SR A a semiuodudar Introduction to Test booed mE seiiay PA FE Semen 0 Guurdband * Quality Assurance Test — Performed on a sample basis to insure that the package test was . performed correctly. Solty fo not emurad abt Spread - dip. fr. produduy tat + Device Characterization — Devic# Characterization i the process of determining the operating, extremes of individual device parameters. + PROPOst Bum=In— The TSENG OF devices before and after they are “bumed in” to verify that the process did not cause certain parameters to drift. This process weeds out infant mortality devices (those which have a defect that causes them to fail soon after they are first used).. + Military Testing — Involves performing rigorous testing over a temperature range and documenting the results. + Incoming Inspection — Testing of devices by a customer to insure the quality ofthe devices purchased before using them in an application. + Assembly Verification — Verifies that the devices survived the assembly process and that they were assembled correctly. The tests performed during assembly verification are similar to that of package testing and may be a subset of package testing. This activity is usually performed offshore. +( Failure Analysis — The process of analyzing device failures to determine why the device failed. Dete the gause of a failure yields information that can improve device reliabilit See wage by adem am i ‘What are the capabilities of the test system? Test programs are designed to take full advantage of the test system’s capabilities. Various test methods may be used depending on the hardware and software capabilities ofthe test system. High performance testers Highly sort fe of accurate high speed measurements + Large vector slemory —tlimihate¥the ned to reload test patterns + Multiple PMUs — capable of parallel measurements, reducing test time on DC tests * Programmable current loads — simplifies test hardware, adds flexibility * Timing and levels per pin — eases program development, reduces test times Lower cost testers ‘+ Low speed / low accuracy — may be inadequate to match device specifications ‘Small vector memory — may require reloading test vectors, increases test times Single PMU —can only make serial DC measurements, requires long test times Shared resources (timing / levels) — increases complexity of test program, increases test times ‘What are the financial considerations? This is probably the single most important factor in deciding ‘what needs to be tested and what is the best way to meet those needs. Testing can add significantly to ‘the manufacturing cost of a device, therefore many decisions regarding test are based solely on the selling price vs. test costs. For example, a device might be used in a game and sell for $0.15. The same device may also be used in a satellite and sell for $350.00. A unique specification will exist for each use, requiring two unique test programs. $350.00 selling price per device can support expensive test costs $0.15 selling price per device can support only minimal test costs ‘What is the test philosophy of the company developing the test program? A test philosophy is a ‘consensus of opinion of what is the best method of testing within a given company. Itis based on their particular requirements, the selling price of their devices and often itis influenced by past experiences. ‘The Fundamentals of Digital Semiconductor Testing, 33= Te iby Introduction to Test Before test program development begins the test engineer must thoroughly consider each of the items mentioned above to determine the best solution. Developing test programs is not a matter of right or wrong, it is more of identifying the best solution for a give set of circumstances The Test System ‘The test system js electronic and mechanical hardware used to simulate the operating conditions that a DUT will experience when used in an application, 50 that defective devices can be found. The test system is offen 8 known as ATE or Automated Test Equipment. ‘The test system hardware is controlled by a computer which executes a set of instructions (the test program). ‘The tester must present the correct voltages, currents, timings and functional states to the DUT and monitor the response from the device for each test. The test system then compares the result of each test to pre-defined limits and a pass/fail decision is made. A test system is actually a collection of power supplies, meters, signal generators, pattern generators and other ‘hardware items which all work collectively under one main controller. What's in a Test System? ‘Figure 3-1 shows the basic blocks that all digital test systems contain. Many new test systems contain far more hardware than what is shown here, but this diagram is a good starting point. ‘The CPU is the system controller. It contains the computer which controls the test system and provides a ‘means of moving data into and out of the test system. Most new test systems offer a network interface as well ‘as magnetic media for data transfers. The hard disk and CPU memory are used to store information locally; the video display and keyboard are used by the test operator to interact with the test system. 34 ‘The Fundamentals of Digital Semiconductor Testing,Introduction to Test % stl aD Ge Abe Mgsnthn pattan rts, Pater HHE_Henay Tok Ophaay Memory taki Basic Test System Components here We me Patten angered Memory Timing, for Parallel Formatting, Special %, Pin Electronics Drivers, aie eS Extomal Curent Loads, Contoler Power © Reforenan | sttument Sra” serie SY et (tor VDD, vi. “Eset Savi vor vor tpl mainframe fee Figure 3-1 prod pore spp aoe ah ‘The DC subeystem contains the Device Eni Supplies (DPS), the Referencd Voltage Supplies (RVS) and the Precision Measurement Unit (PMU). The DPS supplies voltage and current to the DUT power pins (VDD/ VCC). The RVS supplies voltage references for logic 0 and logic 1 levels to the driver and comparator circuitry located on the pin electronic cards. These voltages set VIL, VIH, VOL and VOH. Less expensive and older test systems may have a limited number of RVS supplies, so only a limited number of input and output levels can bbe programmed at one time. When tester pins share a resource such as the RVS, that resource is considered a shared resource. Some test systems are said to have a tester per pin architecture which means that they have the ability to set input and output levels and timing independently for each pin. A tester pin, also called tester channel, is circuitry on the pin electronics card which supplies and /or detects voltage, current and timing for one DUT pin. ‘The DC subsystem also contains EMU circuitry (Precision Measurement Unit) to make accurate DC ‘measurements, Some systems have a PMU per pin, located in the test head. Each test system has high speed memory, called pattern memory or vector memory to store test vectors or test pattems, Test patterns, also known as the truth table, represent the Sates of inputs and outputs for the various __Togical functions that the device is designed to perform. Input, or drive, pattems are supplied to the DUT by the test system from pattern me Output, or expect, patterns are compared against the response from the ‘output pins of the DET During a functional test, vector patterns are applied to the DUT and the DUT’s ‘The Fundamentals of Digital Semiconductor Testing 35Soft] & a= 1G Introduction to Test responses are monitored. If the expected response data does not match the output data from the DUT, a functional failure occurs. There are two types of test vectors—parallel vectors and scan vectors. Many test systems support both types. ~~ ‘The timing subsection has memory to store formatting, masking and timeset data for use during functional testing, The signal formats (wave shapes) and timing edge markers are used for DUT input signals and strobe ‘timing for sampling DUT output signals. The timing subsection receives drive patterns from pattern memory and combines them with timing and signal format information to create formatted data which is sent to the driver section of the pin card and then to the DUT. Special Options includes a variety of possiblities such a algorithmic pattern generators for memory est or specialized hardware modules used to perform analog tests. The System Clocks provide a means of synchronizing the movement of information throughout the test system. These clocks often run at much higher frequencies than the functional test rate. Many test systems have calibration circuitry which can automatically verify and calibrate the system timing. ‘The External Interface communicates with other hardware such as wafer probers, device handlers or special test instruments. This interface typically uses a serial or GPIB (IEEE-488) protocol. ‘The test head contains pin electronics cards and interfaces to the DUT test hardware or loadboard. ‘The Loadboard is the physical interface between the test system and the DUT. It connects to the DUT through a test socket, a probe card or a device handler. It holds interface components required to test the DUT, such as relays, resistive loads or power supply decoupling capacitors. ‘Near the test head is the test box or bin box. The bin box typically contains Start and Reset buttons and displays pass/fail results. The PMU ‘The Precision Measurement Unit (PMU) is used to make accurate DC measurements. It can force current and measure voltage or force voltage and measure current, Some test systems have only one central PMU that must bbe shared across all pin channels of the tester. Others have more than one PMU which accesses multiple channels, typically in groups of eight or sixteen. High end test systems have PMU per pin capability, which has a PMU on every tester channel. 36 ‘The Fundamentals of Digital Semiconductor TestingIntroduction to Test Precision Measurement Unit (PMU) sang teat x made 2 whee 3 sets Fo. De tahay Fore, \ enue, ‘avdveg, Ohm's lows Ui vettaye, Water, aitabee pur Pin SH KEM Stay E feng — he Spce: Shab Iams J Sink Utrenb ~ OM Dual Limits [2 ts teat ~ erat ew tf ype then ca he fant opiten, © the bait Upper Limit ap Ire tate rg oo ee S) aa! mrkiny ony measuremeh Lower Limit aowa ware ~ wr redftio ¥ E dee opp pie Figure 3-2 ut wtem Neyet Me sgitem) Force and Measurement Modes In ATE, the term force (as in force voltage or force current) describes the application of a certain value of voltage ‘or current by the test system. Apply can be substituted for the word force. ‘When programming the PMU, the force function is selected as either current ot voltage. If current is forced, the ‘measurement mode is automatically set to voltage. If voltage is forced, the measurement mode is automatically set to current. Once the force function is selected, the force value must be set. Force and Sense Lines ‘To improve the voltage forcing accuracy of the PMU, a four wire system is used. Four wire systems use 2 lines ery caren and sone Hs to monitor the llageat the point of in ‘he DUT ORS at the point of interest (usually Taw states that a voltage is produced across a resistance when current flows through the resistance. All wire has resistance so, depending on the current through the force lines, the voltage at the DUT is different from the voltage at the PMU force unit output. ‘The Fundamentals of Digital Semiconductor Testing 37sass (Introduction to Test Using 2 separate (non-current carrying) sense wires to measure the voltage at the DUT keeps the voltage drop caused by current flow through the force lines from causing an error or offset in the voltage. The point at which the force and sense line are connected together is called the Kelvin Connect Point. Range Settings A PMU force range and measurement range must be selected. Proper range selection insures the most accurate test result. Be aware that the force and measure ranges have a limiting effect on the PMU. The force range will determine the maximum forcing capability of the PMU, so if the PMU is programmed to force 5 Volts and the 2 Volt force range has been selected, only 2 Volts will be forced. Likewise, ifthe ImA measurement range is selected, the maximum current that can be measured is ImA regardless of the actual current flow. It is important to note that neither the force nor the measurement range of the PMU should be changed while it is connected to a DUT. Changing the range causes noise spikes that may damage the DUT. A noise spike is ‘when a signal level abruptly changes its voltage level for a very short time. A noise spike is also called a glitch. Limit Settings ‘The PMU has two programmable measurement limits—an upper and a lower limit. The limits may be used. individually (one limit enabled while the other is disabled) or they : may be used together (both limits enabled). ‘The upper limit is used to make a Fail Greater Than comparison and the lower limit to make a Fail Less Than comparison. Failing the “Fail Greater Than” limit means the measured value was more positive than the upper limit setting. Failing the “Fail Less Than” limit means the measured value was more negative than the lower limit setting. Clamp Settings ‘Most Precision Measurement Units have voltage and current clamps which are set from within a test program. A clamp crc hat limits the amount of altage or curent thats supplied bythe PMU during atest in order to protect the fest operator, the testhardwareand the DUT. Vou = MAX av Lut Foul GT A mt Fol FLT 90 38 ‘The Fundamentals of Digital Semiconductor Testing,Introduction to Test F< | 9) Un Current Clamp rect ciruk the is tipah & 2Sbmf Far oy Pr clump the oppsate. Of what you ore py] . y Ea MEASURE +)‘ : . RL ETA ware — vss=0v Nelo @ hint ts When forcing 5V and current limit is 20mA, set Iclamp at 25.01 Cloewp al When Ri. = 2509, lout = 20mA When Ri. <= 2000, IquT = 25mA (clamp current) Figure 3-3 When the PMU is used in Force Voltage mode, a current clamp must be set to limit the maximum current which flows during the test. When forcing voltage, a PMU delivers as much current as necessary to sustain the voltage. Ifa DUT pin is shorted to ground (or another supply), the forcing unit will increase the current to try to force the pin to the programmed voltage. This may result in a large enough current flow through the DUT pin to bum probe cards, circuit traces, pin electronics components, fingers, adjacent DUTs, ete. ‘When forcing voltage, the PMU measures current. Because the current clamp limits the amount of current supplied by the PMU, the current clamp value must be set outside of the test limits otherwise the current ‘lamp will prevent a “too much current” failure. Figure 3-3 shows the PMU forcing 5.0V across a 250 Ohm load. In actual testing, the DUT is the resistive load. From Ohm’s Law (I=E/R) we know that the 250 Ohm load will restrict the current flow to 20mA during this test. The device specification may state that the maximum acceptable current is 25mA. This means the fail limit ‘would be set to Kail GT 25mA and the current clamp could be set to 30mA. Ifa defective DUT presents a load of 10 Ohms, the resulting current will be 500mA unless a current clamp is programmed to limit the current. A current flow of 500mA may cause damage to the test system, the interface hardware or the DUT. However, ifa current clamp is programmed to 30mA the maximum current flow would ‘The Fundamentals of Digital Semiconductor Testing, 39‘| mmm beod Uy Introduction to Test be limited by the clamp circuit to a much safer value. “Why 30mA?” you may ask. 30mA is greater than the fail limit of 25mA, allowing the test to fail when a defective device is encountered, but the current will be limited toa safe value. The clamp value must always be set outside of the fail limits; if not, the test will never fail Voltage Clamp join Carcass Wage eonp Po Chonp Reng aug (euereat dew 1250mv ty 30V ack Receseny pie, For Iforce = 10.0 mA: When Ry = 5000, Vout = 5. When Ri = open, VouT = COMPLIANCE or CLAMP voltage. . Figure 3-4 When the PMU is used in the Force Current mode, a voltage clamp must be programmed to limit the maximum voltage that is produced during the test. When forcing current, a PMU will increase the voltage at its output to try and force the programmed current. Ifthe pin is an open circuit, the voltage may increase to a value that is dangerous to the DUT, the hardware, the operator, etc. When a test is made with the PMU in the current forcing mode we expect to measure a voltage within a certain defined limit range. If the DUT is defective, the actual voltage measured may be far greater than the expected voltage. To be sure that the voltage produced by the PMU stays within safe limits, a voltage clamp should be programmed. | ‘The voltage clamp will limit the amount of voltage supplied by the PMU, so the voltage clamp value must be | set outside of the test limits to make sure the voltage can reach the value required by the DUT. When forcing ) current a voltage clamp must always be set. 340 ‘The Fundamentals of Digital Semiconductor TestingSe Figure 3-4 shows the PMU forcing 10mA through a 500 ohm load. In actual testing, the DUT will present the resistive load. Based on Ohms law (E=1/R) we know that 10mA flowing through a 500 Ohm load will develop a voltage drop of 5 volts. In this example, assume the device specification states that the maximum acceptable voltage is 5.25 volts. This requires a fail limit of “Fail GT 5.25 volts” and the voltage clamp could be set to 6 volts. In the course of device testing, a defective DUT may present a high resistance or worse yet, an open circuit. When the PMU attempts to force current into an open crcl (or a Very Nigh Weistance) the result will be the ‘maximum voltage that the PMU is capable of producing. Think of it this way, if 10ma is forced into 500 Oams the result is 5 Volts; if 10mA is forced in 5000 Ohms the result is 50 Volts; if 10mA is forced into an open circuit (infinite Ohms) the result is an infinitely high voltage. In this example, if a voltage clamp is programmed to 6 Volts, the test will fail when the measured voltage is greater than 5.25 Volts but the PMU voltage will be imited to the programmed value of the clamp. Introduction to Test veaR pr Nery hgh wttaye, The Pin Electronics “The pin electronics (also called the Pin Card, PE, PEC or 1/O card) is the interface between the test system resources and the DUT. It supplies input signals to the DUT and receives output signals from the DUT. Each test system has its own unique design but generally the PE circuitry will contain: + Driver circuitry to supply input signals. + 1/0 switching circuitry for turning drivers and current loads on and off. + Voltage Comparator circuitry for, detecting output levels. ‘+ Aconnection point to the PMU. ‘¢ Programmable current loads. + Possibly additional circuitry for making high speed current measurements. + Possibly a per pin PMU ‘Although there are many variations of this design, Figure 3-5 represents a single tester channel on a typical pin. electronics card for a digital test system. ‘The Fundamentals of Digital Semiconductor Testing 341| Ge introduction to Test FET Pin Electronic sustch VIH (Logie 1) \‘E “wet, Current ea Load geal utes) 3 stds hig Voltage — yout iS | Receiver Lmparators Wi ~stete (Outputs) PMU per pin Comparators The Driver The driver circuitry receives formatted signals, called FDATA, from the high speed section of the test system. As the signal passes through the driver, the VIL/VIH references from the Reference Voltage Supplies (RVS) are applied to the formatted data. If the FDATA instructs the driver to drive to a logic 0, the driver will drive to the YIL reference. VIL (Voltage In Low) represents the maximum guaranteed voltage value that can be applied to an input and still be recognized as a logic 0 by the DUT circuitry. If the FDATA instructs the driver to drive to a logic 1, the driver will drive to the VIH reference. VIH (Voltage In High) represents the guaranteed minimum voltage value that can be applied to an input and still be recognized as a logic 1 by the DUT circuitry. When the tester channel is programmed as an input, F1 FET turns on and the KI relay is closed allowing the signal from the driver to pass through to the DUT. When the tester channel is programmed as an output or is in “don’t care” mode the Fl FET is turned off and the signal from the driver will not pass through to the DUT. The Fi FET is a Field Effect Transistor used as a very high speed switch. It isolates the driver circuitry from the device under test. The FI FET is used during IO switching, which is when the DUT alternates between 312 The Fundamentals of Digital Semiconductor Testing,q= Introduction to Test 7.35; Sa receiving data from the test system (reading data) and supplying data to the test system (writing data). The same pins function as both inputs and outputs. Ifthe tester channel is programmed as an input, the FET is on. If the tester channel is not programmed as an input the F1 FET is off, which prevents the driver signal from reaching the device under test. It is important to insure that the DUT and the driver are not trying to drive a voltage onto the same tester channel at the same time. This is called an I/O conflict or bus contention. Current Loads ‘The Current Loads, also known as Dynamic Loads or Programmable Current Loads, act as a load to the DUT ‘outputs during functional tests and can be programmed to supply positive and negative currents. Positive current flows from the test system into the device and negative current flows from the DUT into the test system. ‘The dynamic loads provide both IOH (Current Out High), which is the amo f current thata-DUT output must source when driving a logic T, and JOL current (Current Out Low), whichis the amountof current that ‘After the IOL and JOH current values are set by thé fest prograiiy the VREF voltage is used to set the switching point of the IOL and IOH currents. The switching point is the output voltage above which IOH flows and ‘below which IOL flows. When the output voltage from the device under test is more negative than VREF, IOL current flows. When the output voltage from the device under test is more positive than VREF, IH current flows. The current loads are also used during the functional Tri-State® tests and the functional opens and fost oS ‘The F2 FET is also a field effect transistor used as a high speed switch. The F2 FET isolates the current load circuitry from the device under test and is used during IO switching. Ifthe tester channel is programmed as an ‘output, F2 is on, allowing current to flow to and from the device under test. If the tester channel is programmed as an input, F2 is off. The Voltage Comparators ‘The Voltage Comparators are used during functional testing to compare the output voltage of the device under test to reference voltages supplied by the RVS. The RVS supplies a reference for a valid logic 1 (VOH) and a valid logic 0 (VOL). If the DUT output voltage is equal to or less than VOL, itis recognized as a logic zero. If the DUT output voltage is equal to or greater than VOH, it is recognized as a logic one. If the output voltage is, ¢ggeater than VOL but ess than VOH, itis considered to be aTri-State® level or a bad output. ~ in bw The PMU Connection When the PMU connects to a device pin, the K1 relay is opened first, then the K2 relay is closed. This sequence isolates the PMU from the I/O circuitry of the pin electronics card. ‘The High Speed Current Comparators ‘Some test systems offer a way to measure smalll currents quickly as an alternative to having a PMU for each tester channel. Current comparators are used to make high speed leakage measurements. The K3 relay ‘connects the current comparators to the pin under test. Ifthe test system has PMU per pin capability, the current comparators are not necessary. ‘The Fundamentals of Digital Semiconductor Testing 313| Q, mm Su Introduction to Test The PPPMU ‘Some test systems offer a per pin PMU (PPPMU) that allows the test system to measure either voltage or current on every pin simultaneously. Like the PMU the PPPMU can force current and measure voltage or force voltage and measure current. PPPMUs typically lack all the capability of the standard system PMU. Basic Rules of Test Engineering The following set of rules will apply in most instances. They are defined here because they seem to be recurring problems found in many test programs. If you should ever feel a need to intentionally violate these rules, make certain that you fully understand the consequences. Some of these rules may seem obvious, but it is easier than you think to violate these rules, depending upon the exact test hardware being used. + Never functionally test an input pin as if it were an output. This can be accomplished by accidentally setting the output compare mask on an input pin. Remember, inputs are not directly tested for pass fail results during functional testing. Signals are applied to inputs, outputs are tested. ‘+ Never connect a tester pin driver to an output pin of a DUT. The result of this action will cause the test system and the device pin to both drive voltage and current at the same point, at the same time. ‘+ Never float an input pin. A valid logic 0 or 1 level must always be supplied to an input pin. Floating. CMOS inputs may result in device latch-up, an SCR effect which can destroy the device by drawing too much current. ‘+ Never supply a voltage which is above VDD or below ground to an input pin or output pin. This may cause a CMOS device fo latch up. > ‘+ Always, when forcing voltage, seta current clamp to limit the amount of current provided by the test system. ‘+ Always, when forcing current, set a voltage clamp to limit the amount of voltage provided by the test system. + Never change a force range of the tester when connected to a device pin. Never change the forcing mode (voltage/current) of the PMU when connected to a device pin. oy onjopp erdibonmech cad net yond reunesly 314 ‘The Fundamentals of Digital Semiconductor TestingIntroduction to Test Introduction to Test — Review Digital test programs are often segmented into three separate sections. These sections are: Positive current flow is defined as: a) Current flowing from the test system into the DUT 1b) Current flowing from the DUT into the test system ©) Current flowing from a higher voltage to a lower voltage ‘A device pin that functions as both an input and output is called a: Which resource of the test system hardware is used to provide voltage and current to power the DUT? a) RVS b) DPS ©) Driver Which resource of the test system hardware is used to perform very accurate voltage and current ‘measurements? Which type of testing verifies correct operation of the various logical operations or functions of the device? ‘When using the PMU to force current, which clamp should be used? a) Acurrent clamp b) A voltage clamp ©) Neither, clamps are not used when forcing current When using the PMU to force voltage, which clamp should be used? a) Acurrent clamp b) A voltage clamp ©) Neither, clamps are not used when forcing current ‘The Fundamentals of Digital Semiconductor Testing, 35Soft} Test} 3:16 = > (Introduction to Test ‘The Fundamentals of Digital Semiconductor Testing,Device Specifications Device Specifications Objectives ‘This section explains: ‘Why a device specification is written. ¢ How to read a device specification. ‘+ How to determine limits for each test + How to determine which tests to perform. Semiconductor testing is based upon a specification created specifically for each unique device design. The specification will define the intended functions and operational parameters of the device. To understand the various tests defined in the following chapters, itis first necessary to gain a basic understanding of device specifications. ‘Some type of device specification must exist before a plan for the test program can be developed. A test specification, a design specification or a data book specification may be used as a reference when developing the test plan. The specification is the foundation upon which the test plan is developed. Test program development should not begin until a specification and test plan have first been defined. Basic Terms As we begin to discuss the various types of specifications, there are a few terms related to testing a device that ‘we need to understand: tard onto = 4 the etuel Teoh Preconditioning Setting a device into the proper logic state so that a test may be performed. A functional vector sequence is often required to prepare the DUT for a DC test. Static ‘The DUT is in a fixed state of operation, with no input or output signals changing. Dynamic ‘The DUT is actively changing states. Dynamic tests are associated with executing functional test vectors. The Design Specification ‘The term design specification describes a document which defines the intended functions and performance characteristics of a new circuit design. The specification includes voltages, currents, timings and a description _ of the device functions. The design specification may be created by the sales and marketing department, the design engineering department or in some cases the end user. The creation of the design specification precedes the manufacturing of the silicon; after the device is produced it must be characterized and the actual _Berformance of the device can be compared with the intended design requirements. ‘The Fundamentals of Digital Semiconductor Testing 41| St Device Specifications The Test Specification ‘The term test specification describes a document which shows step-by-step the process required to fully test the circuit. The test specification is normally produced by the semiconductor manufacturer for its own internal ‘use through a cooperative effort of the design, test and product engineering departments. It defines the exact conditions (voltages, currents, timings and test patterns) to be used in program development and production testing. These conditions, when applied to the device under test, will guarantee that the device meets the intended design specification. If during the course of test development, it becomes necessary to modify a test parameter in order to get the device to function properly, the test/ product engineer will immediately notify all appropriate parties of the modification (in writing). This modification will then be reflected in the published device specification. The Device Specification The terms device specification or data book specification refers to a published document which describes the functionality of a device along with its performance characteristics. Device specifications can normally be found in semiconductor device catalogs (also called data books). These specifications will define voltages, currents and timings but are often very general and lack the detail required to develop a complete test program. The device specification also serves as a contract between the seller and buyer, in that the semiconductor manufacturer guarantees that the device will perform as defined in the specification. ‘The device specification as it appears in a semiconductor device catalog is often used for program development. A typical device specification for a 256.x4 static RAM will be used throughout this manual as an example. Test Conditions and Limits When testing a digital semiconductor device three types of tests are performed: DC, Functional and AC. The conditions and limits for each test must be determined. The device specification is reviewed and used as a starting point for test program development. Not all test conditions Will be detailed in the specification. Also, conditions may exist in a device specification which can not be reproduced on a digital test system or may not apply to digital testing, Itis important to understand the “intent” of each parameter and the standard procedures used to verify individual parameters. Standard procedures for each test will be presented in detail in the following chapters. Parameters that Apply to Parametric Testing (DC) When developing the DC test plan the following information must be determined. This information should be defined in the device specification. ‘Input voltages and currents (VIL, VIH, IIL, ITH) ‘¢ Output voltages and currents (VOL, VOH, IOL, IOH, IOZH, JOZL) ‘+ Power supply currents and voltages (VCC, VDD, VDDMIN, VDDNOM, VDDMAX, ICC, IDD) + Pass fail limits for each parameter Note: Many DC tests require that the device be properly preconditioned. For example, in order to perform the VOH test (voltage out high) the device but first be preconditioned so that the outputs are set to the logic one 42 ‘The Fundamentals of Digital Semiconductor Testing,\q= Device Specifications Se state. The device specification will typically not include preconditioning information. The information in the following chapters which describes each DC test will however specify all required preconditioning. Parameters that Apply to Functional and AC Testing ‘When developing the AC test plan the following information must be determined. This data should be defined in the device specification. + Input conditions (VIL, VIH) + Output conditions (VOL, VOH, IOL, IH) + Power supply settings (VDDMIN, VDDNOM, VDDMAX) ‘+ Timings (frequency, pulse widths, setup and hold times, delays) + Pass /fail limits for each parameter Note: It may be possible to take a quick look at the AC (timing) specification and determine whether or not the target test system will be adequate to test the device. For example, if the device specification defines the ‘operating frequency at 50MH2z and the test system operates at a maximum of 20MHz, compromises will need to be made, or another test system may be selected for use. Other considerations are: minimum pulse widths and timing accuracies needed to make setup, hold and delay time measurements, Logical Functions The functionality of the device may be shown within the device specification as a truth table for simple logic devices. For complex devices the general functionality or behavior of the device may be described in written’ “form. Complex devices may take many thousands or millions of instructions (input combinations) to fully test the device. Detailed test patterns for complex devices are most often developed by aang OmUUT ‘using computer aided _design tools during the design process and are not included as part of the device specification. Reading Device Specifications By working through the following pages you will begin to gain an understanding of how the various parameters are defined in a device specification and used within the test program. Review the device specification for the 256 x 4 static RAM. On the pages immediately following the specification you will find a brief description of each DC test listed in the specification. Read the device specifications carefully and determine the correct values to be used within the test program. Although the complete device specification is shown, only the DC section will be considered at this time. The AC section will be discussed in a later chapter. ‘The Fundamentals of Digital Semiconductor Testing 43Uk 256 x 4 Static RAM adires eT Eoch ddr — 4 ya bogie Diagram D3 D2 D1 DO cs2 { west E spats Si WE Writ Gr, ne igo DE ops fiche = tal & het te « a 3 9 8 a a 3 & Figure 4-1 Functional Description ‘The 256 x 4 static RAM is a high speed CMOS 256 word by 4 bit static RAM. CMOS technology provides excellent performance at low power consumption. Flexible design makes it easy to use the 256 x 4 static RAM and expand to larger memory sizes. Very low access time makes the RAM useful in CPU caching applications and others which require fast data access. Writing to the device is done by taking CS1/ and WE/ low and CS2 high. Data on DO-D3 is written into the ‘memory location specified by the address on A0-A7. Outputs 00-O3 are in a high impedance state during the write cycle. ‘The RAM is read by making CS1/ and OE/ low and CS2 and WE/ high. Data at the address set by AO-A7 appears on outputs 00-03 within the maximum access time. When CS1/ or OE/ are high or WE/ ot CS2 are low, the output pins are in a high-impedance state. 44 ‘The Fundamentals of Digital Semiconductor Testing|, Device specications 5":| Sb, 256 x 4 RAM Specifications Maximum Ratings Storage Temperature “BB°C to 125°C |] DC Input Voltage” “OSV to7.0V “Ambient Temperature with 7 ‘Output Current into Power Applied SSC 0 125°C | Gusputs (Low) 20mA Supply Voltage to Ground Potential (Pins 24 and 18 to Pins 7 -05V to7.0V 200mA and 12) Latch-Up Current DC Voltage applied to Outputs in menzeae O5V to7.0V Operating Range” Range Ambient Temperature” vDD Commercial | Ct 70°C BVES% Miltary SECO SC BVEIO% Paso Fal Fok D.C. Characteristics (Over the Operating Range) lrent we cee gory RL Fares Parameter Description “Test Conditions Min Max | Units VOH | Output HIGH Voltage | VDD=Min, IOH=-52mA 24 ; Vv re fe VOL | Output LOW Voltage | VDD=Min, IOL=80mA oa Vv] tp pte VIH__| Input HIGH Voltage 22 | Vpp v oe Fel VIL | Input LOW Voltage! 00 | 08 V nuts TIL, HH | Input Load Current | Vass Vins VDD =10_ [+10 [HA ‘Output Current ‘Vas = Vout VDD, 10Z | qighz) Outputs Disabled ao] Ho] ua VDD = Max Commercial i20_| mA IDD__| Power Supply Current | Iout = OmA f= fax Military 150 | mA Capacitance? Parameters Description "Test Conditions Max | Units Gin Input Capacitance ‘Ta = 250C, f= IMHz, VDD =5.0V 8 pF Cout ‘Output Capacitance | same as above 8 pF tac T jeder Pottery? Logic Table# eet @ Compete Trath Rb] at & Inputs ‘Outputs Mode OE ar [ce WE | Dos | 00-03 x H x x x Zz Not Selected Xx x L Xx x Zz Not Selected TL L Ht i x T/H__ | Read Stored Data x TL H cL L Z Waite 0" x L Ht cL H Z___| Write “17 H L Ht H X Z Output Disabled ‘The Fundamentals of Digital Semiconductor Testing, 45Device Specifications 256 x 4 Static RAM A.C. Characteristics ADDR +}— we ESE ADDR CSi acs2 os oo CSI acs2 We a yecs* }—ts5—4 tuo DATA IN an) ewe] | ffawe DATA OUT KK pas) DATA OUT Figure 4-2 Read Timing® Figure 4-3 Write Timing* READ Cyde Parameter Description Min | Max | Unite tre Read Cycle time 5 nsec tha ‘Address to Data Valid 15 _[ nsec tacs ‘Chip Select to Data Valid 10_[ nsec toe ‘GE Low to Data Valid 10_| nsec tuzes® | Chip Select to HighZ 8 [nsec tyzor ‘OE High to High Z 8 nsec izes | Chip Select to Low Z 2 nsec tizoE OE Low to Low Z 2 nsec WRITE Cyde Parameter Description Min | Max | Units two Write Cycle time 5 nsec tazwe | WE Low to HighZ 3 [nsec tizwe WE High to Low Z 2 nsec ‘ewe ‘WE Pulse Width 1 msec ts Data Set-up to Wiite End a nsec ti Data Hold from Write End T nsec ta ‘Address Set-up to Write Start 2 nsec tua Address Hold from Write End_ 2 nsec tscs. GS Low to Write End ay msec tow "Addiress Set-up to Write End B = 46 ‘The Fundamentals of Digital Semiconductor Testing,Device Specifications vee=s0v fn All Input Pulses Dg = 3.0v D1 D2 pa — x ans ‘<—