Chapter 4

Hardware Architecture of 8086/8088

Introduction
In the preceding chapters we have read about the 8086/8088 microprocessors internal archi-
tecture. However to design an 8086/8088 microprocessor based system we should have
Comprehensive knowledge about the 8086 and 8088 microprocessor IC module. In addition the
8086 microprocessor requires a few dedicated IC's to function as a complete computer. In this
chapter we shall introduce to you the 8086 and 8088 microprocessor IC pin outs, their pin
assignments and functions. We shall also study the 8284 clock generator IC. Data sheets are
available that contain comprehensives manufacturer data sheets enabling students who want to
work on project based on the 8086 microprocessor and to be able to properly design such
systems. Here we shall also attempt to provide you knowledge of the 8086 based system, a
minimum and maximum mode configuration and its operation. However a reference to an 8086
microprocessor will be valid to the 8088 microprocessor due to internal similarities which exist.

The 8086/8088 CPU Module Pin-Out

On the first glance the 8086 or the 8088 microprocessor may appear to be a very complex IC.
Figure 4.1(a) shows the pin out of an 8086 microprocessor while fig. 4.1(b) shows the pin out
of the 8088 microprocessor. You may at the first glance observe no difference between the two
microprocessor IC packages.
Both microprocessors are packaged in a 40 pin dual in line package (DIP). As discussed earlier
the 8086 microprocessor has a 16 bit data bus while the 8088 has an 8 bit microprocessor,
though both are very similar to each other.

DC Characteristics
Both the 8086 and 8088 microprocessors require a supply voltage of + 5V with a tolerance ±
10%. The 8086 and 8088 can be operated at a supply voltage of 5V with a tolerance of ± 5%.
These microprocessors can be operated in temperature ranging from 0°C to 70°C. Since this
range is insufficient for certain applications there are extended temperature versions of both
these microprocessor which can be operated between temperature ranges from - 40°C to 140°C.
Both these microprocessors draw a maximum supply current of 340 mA. The 8086
draws a maximum supply current of 360 mA. These microprocessors have an average power
dissipation value of about 2.5W.

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Input and Output Characteristics
The input characteristics are shown in figure 4.2 where the input voltage and current
requirements required to drive the microprocessor as shown.
Symbol Parameters Min Max Units
VIL Input low voltage -0.5 0.8 V
VIH Input high voltage 2.0 Vcc + 0.5 V
IIL Input low current — ±10μA μA
IIH Input high current — ±10μA μA
Figure 4.2. Input characteristics for the 8086 and 8088 microprocessors
Output characteristics are shown in figure 4.3. However the 8086 and 8088 microprocessor have
low noise immunity due to which a 8086 buffered system is preferred when drawing large
number of loads. Buffered 8086 system is discussed in detail later.
Symbol Parameters Min Max Units
VOL Output low voltage — 0.45 V
VOH Output high voltage 2.4 — V
IOL Output low current — 2.0 mA
IOH Outpur high current — -400 μA
Figure 4.3. Output characteristics for the 8086 and 8088 microprocessors
Here we shall briefly explain the 8086 and 8088 microprocessor IC pins, their functions and
names as well as a brief description of their purpose. The following section lists the pin

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definition as given by Intel Corporation.
Pins Signal Assignments (8086)
Here we shall briefly explain the 8086 and 8088 microprocessor IC pins, their functions and
names as well as a brief description of their purpose
Pin Assignment Pin No. Description
AD15-AD0 39, 2-16 This is the multiplexed data and address bus. These bits contain
16 bits of data or address depending on the ALE logic value.
When ALE = 0, these pins contain 16 bits of data where AD0 is
LSB bit and AD15 is MSB bit of data. When ALE = 1, these pin
contain the right most 16 bits of the memory address. For I/O
operations AD7-AD0 contains the port address when ALE = 1.
A19/S6—A16/S3 35-38 This is the upper order address bus bits multiplexed with status
bits. Initially, these pins contain the upper order address bits
(when ALE = 1). During the next clock after ALE goes, low
these pins contains the status bits as shown in figure 4.4 which
shows the truth table for S6-S3 status bits.
RD 32 This is the 8086 read control signal. The read signal is active
when it goes low. When RD goes low the microprocessor re-
ceives data on AD15-AD0 from memory or I/O devices.
RESET 21 When the RESET pin is held high for four more clock periods, if
resets the microprocessor. This clears all registers and loads the
CS register with FFFFH and the IP register with 0000H. This
also resets the IF flag to zero.
CLK 19 This Pin is used to provide the clock signal for processor
synchronization. The clock signal must have a duty cycle of 33%
as specified by Intel for proper operation.
Vcc 40 This Pin is used to supply the+5.0 V input supply voltage.
GND 1,20 These are the 8086 ground pins. For reliable operation both these
pins must be grounded.

S3 S4 Decoded Function
0 0 Extra Segment being accessed
0 1 Stack Segment being accessed
1 0 Code segment being accessed
1 1 Data segment being accessed
S6 = l(Always)
S5 = IF (Interrupt flag status bit)
Figure 4.4. Function of S3, S4, S5, S6 Status bits

Pin Assignment Pin No. Description

MN/ M X 33 The voltage level at this Pin determines whether the 8086 or
8088 microprocessor will operate in minimum or maximum
mode. For minimum mode operation of the microprocessor this

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 Pin should be connected to + Vcc and for maximum mode
operation this pin should be connected to GND voltage levels.
NMI 17 This is Non-maskable Interrupt Pin. This is a positive edge
triggered input and cannot be disabled.
INTR 18 This is Interrupt Request Pin used for interrupting the 8086.
When the INTR Pin is held high the 8086 checks the interrupt
flag bit in the 8086 flag register (IF), if IF = 1 then the current
instruction execution is completed and then the INTA Pin
becomes active. The processor is then said to have been
interrupted and program execution is relocated to memory
address specified by the interrupt request.
READY 22 This is an input that is used to control 8086 operation. This Pin is
used to synchronize slower peripheral devices to the 8086
microprocessor. When READY = 0, the 8086 microprocessor
enters a wait state where it remains idle, (performing no
operation) when READY = 1, the microprocessor functions
normally.
TEST 23 The TEST Pin is used in conjunction with the WAIT
instruction. On execution of a wait instruction, the 8086
microprocessor checks the TEST pin status. If TEST = 0 the
wait instruction executes as a NOP (No operation) instruction. If
TEST = 1, the wait instruction will cause the microprocessor to
becomes idle until TEST goes low and becomes zero.
BHE /S7 34 The bus high enable Pin is an active low and used to enable the
higher order 8 bits of data bus during a memory operation. The
S7 status bit is always 1.

Minimum Mode Pins Signal Assignment

We have earlier referred to a term minimum mode and maximum mode operation of the 8086
microprocessor. The 8086 or 8088 is mode to operate in minimum mode when the MN/ M X pin
is connected directly to + 5V while the maximum mode operation occurs when the MN/ M X pin
is connected directly to ground.

Pin Assignment Pin No. Description

M/ IO 28 this output Pin is used to select memory or I/O devices. When the
address in the 8086/8088 refers to an I/O device then this Pin is
driven low while if it is accessing a memory location then this
Pin is in high (1) state.
WR 29 This is the write signal output Pin. When this Pin goes low it
indicates that the data bus contains valid data that is to be stored

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 in memory or outputted to an I/O device.
INTA 24 Interrupt Acknowledge Signal. When the INTR goes high the
microprocessor responds to this by issuing low in this pin. This
pin is normally used to gate the interrupt vector number onto the
data bus in response to an interrupt request.
ALE 25 Address Latch Enable Pin goes high when the 8086/8088
multiplexed data bus contains valid address bits i.e., when ALE
is 1, the multiplexed address data bus contains address bits.
When ALE = 0, the multiplexed address data bus is used as a
data bus i.e., the multiplexed address data bus will behave as a
data bus and the data that is presently present on this bus is valid
data bits.
DT/ R 27 Data Transmit/Receive signal: When the 8086 microprocessor is
transmitting data on its bus then DT/ R = 1 and when
microprocessor is receiving data on its buses then DT/ R = 0.
This is used as an enable signal for data buffers that may be used
in an 8086/8088 based system.
DEN 26 Data bus enable signal goes low when the microprocessor
address data bus is to be used as a data bus. It is can be used to
enable buffers for buffering the data bus.
HOLD 31 When the external peripherals request a DMA (Direct Memory
Access), they do so by placing a high signal on this Pin. When
HOLD is 1 the microprocessor stops execution and relinquishes
control of the address, data and control bus by placing them in a
high impedance state. It also tristates AD15 - AD0, A19/S6 -
A16/S3, RD , M/ IO , IO/ M , WR Pins. After doing so HLDA is
set to 1. If Hold = 0, the microprocessor executes normally.
HLDA 30 Hold Acknowledge bit is placed 1 when the processor enters the
DMA state. All Pin that have tri stated remain so till the HOLD
Pin becomes 0.

Maximum Mode Pin Assignment

When the MN/MX Pin is grounded the microprocessor (8086/8088) enters maximum mode
operation. This mode is used for multiprocessor systems or systems containing the 8087 numeric
coprocessor when interfaced to 8086 or 8088 microprocessor
Pin Assignment Pin No. Description
LOCK 29 This Pin is placed low when the LOCK instruction is used. It is
interfaced to active high chip enable Pins of peripherals so as to
lock them out of the system (therefore disabling them)
QS1, QS0 24, 25 These are the queue status bits. Figure 4.6 shows the truth table
and are used by the 8087 coprocessor.

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 RQ / GT0 & RQ / GT1 30,31 When DMA transfer mode is required during maximum mode
operation then these request/grant Pin are used. They are bi-
directional pins and are used for requesting a DMA. When the
processor grants a DMA it is also conveyed through these bits.
S2 , S1 & S0 26-28 The status bits are used by the bus controller for the current bus
cycle decoding. Their truth table is shown in figure 4.5.

S2 S1 S0 Control Function
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
Figure 4.5. Status Bit function

QS1 QS0 Decoded Function

0 0 Queue is idle
0 1 First byte of opcode
1 0 Queue empty
1 1 Subsequent byte of opcode
Figure 4.6. Instruction Queue Status Bit Function

Pin Signal Assignments (8088)

As discussed earlier there are only few differences between the 8086 and 8088 microprocessor.
(The major difference being that the 8088 has an 8 bit external data bus. This in effect qualifies if
as an 8 bit CPU. Though in the true sense the 8088 is not really a 8 bit CPU because internally it
can handle 16 bit of data just like the 8086. It should be clearly understood that internally the
8088 works exactly as an 8088 microprocessor. Here we discuss only the Pins that are different
from 8086 such as the address and data Pins, SSO Pin and IO/M Pin.
Pin Assignment Pin No Description
AD7 - ADO 9-16 The 8088 multiplexed address data bus. It is 8 bits wide and
carries the lowest 8 bits of the address of memory or 1/0 port
address when ALE = 1, when ALE = 0 this bus functions as a
data bus and can carry 8 bits of data.
A15 - A8 39, 2-8 These carry the next 8 bits of address and the remain constant;
.throughout the bus cycle.
IO/ M 28 The memory/IO port selection Pin. If this Pin is high it selects an
I/O device and low it is used to select a memory chip. This Pin is
directly connected to chip enable of a memory chip or port
device.
SSO 34 The status line output pin out is a status bit which is sent by 8088

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 microprocessor. The IO/ M , DT/ R and SSO together carry the
function of the current bus cycle the truth table shown in figure
4.7.

IO/ M , DT/ R and SSO Function

0 0 0 Interrupt acknowledge
0 0 1 Memory Read
0 1 0 Memory Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 I/O Read
1 1 0 I/O Write
1 1 1 Passive
Figure 4.7. 8088 decoded status bits for 8088 bus synchronization

Clock Generation
Before we attempt to design an 8086 based computer, we will obviously have to provide basic
input signals such as clock and reset synchronization. The intel designers with the 8086 released
the 8284 clock and Reset synchronization IC. The advantages of using the 8284 clock generator
shall become clear as you go along. It is an important IC and reduces the number of devices
required for generation of a stable clock signal. It also provides RESET and READY
synchronization signals which are required for proper operation of the 8088 and 8086 micro-
processors. Figure 4.8 shows the pin out of the 8284 clock generator IC. The 8284 clock
generator is available in an 18-pin integrated circuit and is for use specifically with the 8086 and
8088 microprocessor. We shall now list each pin and its function.

The 8284A Clock Generator Pin Functions

CSYNC : This is the clock synchronization input. When an external frequency input
is used for clock generation this Pin must be held high. If this Pin is
grounded, the internal crystal oscillator is used for timing.
PCLK : The PCLK output is basically used for peripheral clock synchronization.
Since peripherals generally are much slower than the microprocessor, the
8284 supplies the PCLK signal at one sixth the frequency of the EFI or
crystal clock frequency. This signal is half that of the CLK output that is
provided to the microprocessor and has a 50 percent duty cycle.
AEN1 & AEN2 : These are the address enable Pins. These Pins are used in conjunction with

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 the RDY1 and RDY2 input pins to cause wait states in the microprocessor.
The wait states also require the READY Pin of the 8086 microprocessor to
be attached to the 8284.
RDY1 & RDY2 : The bus ready input pins which cause wait states in an 8086/8088 system,
when synchronized with AEN1 and AEN2 as well as READY output pin
of 8086.
CLK : The clock output Pin which is directly connected to the 8086/8088 CLK Pin
for clock timing. The clock output is one third the crystal or EFI input
frequency that is a 9 MHz EFI input will give an output signal of 3 MHz at
CLK Pin. The output signal has a 33 percent duty cycle as required by the
8086/8088 processor.
GND : This connects to the system ground for the clock generator IC grounding.
RESET : This RESET output pin connects to the 8086 RESET and provide a
synchronized RESET output signal which resets the 8086/8088
microprocessor.
RES : The reset input is an active low input to the 8284 A. It is generally
connected to an RC coupling network which resets the 8086
microprocessor when the complete system is switched on. When the RES
input pin goes low it effectively will send a synchronized reset signal to the
8086 microprocessor and hence reset it.
OSC : The oscillator output Pin is a TTL level signal that is at the same frequency
as the EFI input or crystal frequency and is used to provide EFI input to
other 8284 IC's in a multiprocessor based system.
F/ C : This is a Pin for selection of whether to use an external frequency circuit or
the crystal frequency of the 8284 clock generator to produce the clock out-
put. If this Pin is low the internal cystal oscillator network provides the
signal that is used for timing and when F/C is pulled high the EFI input is
used.
EFI : External frequency input Pin. When F/ C is pulled high the signal that is
supplied to this Pin is used for the 8284 clock output as well as internal
timing of the 8284 IC.
ASYNC : This Pin also called ready synchronization decision input and selects the
number of synchronization levels for RDY1 and RDY2. If this Pin is high
one level of synchronization is chosen for RDY1 and RDY2 signals.
READY : The READY output directly connects to the 8086 microprocessor ready
input pin and is used as output signal which allows the 8086
microprocessor to enter wait states.
X1 and X2 : The crystal oscillator input Pins. These are used to connect a quartz crystal
of thrice the desired clock frequency output i.e., for a 5 MHz clock, a 15
MHz crystal will be connected. This crystal is used as the resonating clock
source for the 8284 clock register and to synchronize all its internal
circuitry.
Vcc : The power supply pin which connects to +5.0V ±10% power source.

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Operations of 8284
Internally the 8284 clock generator can be divided into three sections as shown in figure 4.9.
These sections are:
1. Reset Section
2. Clock Section
3. Ready Synchronization
Clock Section
When a crystal is attached to terminals X1 and X2 it makes the 8284 internal oscillator
oscillate at the same frequency as the crystal. This generated square wave it fed to an AND
gate which is controlled by the state of F/ C . If F/ C is zero this signal is fed to the divide by
three counter and if F/ C is one, the EFI signal is fed to the counter. The divide by three
counter simply converts the frequency of the square wave to one by third of the input
frequency (crystal or EFI frequency). This signal is buffered and fed to the CLK output giving
us the required clock frequency for driving 8086 microprocessor system. It can be seen the
output of the divide by three counter is referred to a divide by two counter, whose output will
be one sixth the input signal frequency. This is our PCLK signal.
Reset Section
This section is extremely simple to comprehend. It consists of a Schmitt trigger buffer and a D
type flip flop (negative edge trigger). Since the D flip flop is negative edge triggered and is
triggered by the negative transition of the CLK signal it will apply the RESET signal during a
1 to 0 clock transition of the CLK output. Since the 8086 samples the RESET pin on a 0 to 1
(+ve edge) transition of the clock thus this signal will be meet the requirements of the 8086
processor. The figure 4.10 shows an 8086 interfaced with an 8284 IC with RESET and CLK
signal connected. An RC coupling circuit is attached with a time constant 10 msec. This RC
coupling circuit is coupled to RES Pin. When the system is switched on RES signal is low
there by ensuring that the 8284 clock generator resets the 8086/8088. After about 10 ms (the
time constant of the RC circuit) the RES will rise to logic one therefore ensuring that the 8086
RESET Pin goes low thereby enabling normal operation of 8086.

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Since the RESET Pin of the 8086 require the input to remain at l for at least 50 ms the above
circuit ensures this criteria which is met due to a large time constant of the RC network. Since
the RC network has a time constant of 10 ms the RESET output of 8284 clock generator will
remain high for 10 ms therefore ensuring proper resetting of 8086. An operator reset switch is
also provided. On pressing the switch the capacitor shall discharge therefore repeating the above
process in turn resetting the 8086/8088 microprocessor.

Bus Demultiplexing and Buffering

As we have earlier discussed that the 8086/8088 has a multiplexed address and data bus
we first must therefore separate these two for proper operation with interfacing device. At
this point, the question might arise why exactly is the address and data bus multiplexed.

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The reason is because of reduction of external pins that shall be now present on the 8086
IC. The 8086 will first send the address of the external device on this multiplexed. Also
the data that must be sent by the device to the 8086 will also be sent on the same bus;
therefore it is obvious that the bus changes state. Therefore, buffering is required if we
want this bus to hold valid data for greater time intervals than what, actually is given.

Demultiplexing the 8086/8088 Buses

Demultiplexing the 8088
Figure 4.11 illustrates the basic model for 8088 bus demultiplexing and shows the components
required. Two 74373 eight bit latches are used. One is required to demultiplex the
address/data bus pin AD0–AD7. The control signal used to trigger the latches is the ALE
signal. The 74373 latch has a latch enable pin which is wired to the 8086 ALE signal pin.
When the 8088 multiplex address/data bus contains a valid address ALE turns 1 enabling
both the latches. After one time state ALE is driven to 0. At this point the 8088 is enabling
the multiplexed address/data bus to run as a data bus. However, since the ALE = 0. This
disables the latches from changing their output. (Which are the address bits). These latches
therefore have stored the address bits A7–A0 and A19–A16. It is clear now that when data is
sent/received from memory/IO obviously they will not effect the address bits (which will
remain static as long as ALE = 0).
Demultiplexing the 8086
The concept discussed above shall remain same for 8086 except for the addition of another
74373 octal latch. The 8088 and 8086 processors differ in terms of number of pin multiplexed.
In the 8086 the multiplexed pins include AD15–AD0, A19/S6–A16/S3, BHE /S7. All these
must be demultiplexed for proper operation. Observing the figure 4.12, we will now notice
that the I/O devices observe this 8086 with a 20 bit address bus, 16 bit data bus and a 3
bit control bus ( WR , RD , M/ IO ). The demultiplexing ensures proper operation even
during times when data glitches and changes on the 8086 data/address bus.
Buffering
Demultiplexing the 8086 or 8088 microprocessor address bus does not solve the problems
encountered during practical operations of the 8086 based system. We do require the
microcomputer to be able to drive TTL loads. Also most devices have an input
capacitance therefore all the 8086 microprocessor signals must have sufficient drive
capability to drive external output loads.
A solution to this problem would be to buffer the 8086 or 8088 microprocessor buses so that
they may be able to drive high capacitive loads. The demultiplexed address bus does not
require buffering as the octal latch will buffer it (as shown in figure 4.11 and 4.12). However
the data bus must be buffered. Secondly the control signal such as WR , RD and IO/ M (or
M/ IO ) must also be provided with sufficient drive ratings therefore should also be buffered.
An 8086 or 8088 microprocessor which has all its buses (address and data bus) as well as
its control signals buffered is called a fully buffered 8086 system. The data bus must use a
bidirectional buffer such as 74245 as it allows data signals to flow in both directions.

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12
13
14
Fully buffered 8086 and 8088 systems are shown in figure 4.13 and 4.14. The octal
transceiver are used for buffering the data bus and has its direction signal pin controlled
by the DT/ R . As usual DT/ R is low when a read operation is to take place enabling the
74245 latches to direct data toward the 8086 microprocessor. During write cycles the DT/ R
goes high enabling the 74245 latch to transmit data towards devices. The 74245 is also

15
enabled or disabled by the DEN pin. The use of the 74244 buffer IC's is also required for
control signals because if we use the 8 bit 74373 octal IC that is connected to the upper order
address bus then the control signals will not be able to be transmitted to the devices on this
latch because it will be disabled after the first cycle by the ALE signal. ( RD , WR signals
undergo changes much later).
The 74373 attached to the address bits A8 to A15 in figure 4.13 can be replaced by the 74244 IC
as these bits do not carry any information except the address bits for the 8088 microproces-
sor.

Read and Write Cycle Timing

All the hardware that we have discussed till now is obviously sequential logic circuitry.
All sequential logic circuitry is synchronized with respect to a synchronization signal
which we call the clock signal (CLK). However bus timing is more complicated than simple
sequential circuit synchronization as we have to synchronize a large number of signals. Take
for example the ALE has to be synchronized correctly so that the system designer may be
able to correctly separate the address and data bits that the microprocessor is inputting.
Similarly other signals such as RD (or WR ), status bits (S7, S6, S5, S4 and S3, S2, S1),
IO/ M (8088 microprocessor) are sent out at predetermined intervals of time with respect to
the basic synchronizing signal (i.e., CLK). Due to the above reasons it becomes necessary
for a hardware designer to understand bus timing so that he/she can chose the necessary
devices (which have to obviously be compatible to the 8086 or 8088 bus timing) so as to
form a system of use. However, we shall here discuss only the minimum mode read and
write cycles.
Simplified Read and Write Timing \
The 8086 and 8088 microprocessor when accessing memory and I/O devices do operations
that are performed in time intervals that remain constant. These constant time intervals or
periods are called bus cycles. Each bus cycle is divided into exactly four clock periods. Let us
assume that we are operating an 8086 microprocessor at 5MHz. Therefore
Microprocessor clock frequency = f  5 MHz
1 1
Microprocessor clock period =   200 ns
f 5 MHz

(or time state)

1 bus cycle = 4 time states = 4 × 200 ns = 800 ns
Thus an 8086 or 8088 microprocessor will access memory or I/O devices in periods of 800ns.
Thus the maximum rate with which an 8086 microprocessor can read or write data to and
from memory (or I/O devices) is 1.25 million transfers per second (At 5 MHz).
Now let us discuss the read and write bus cycles. We know that a bus cycle is composed of
four time state but then what exactly happens during these four time states. Simplified
read and write cycles are shown in figure 4.15 and 4.16. We shall name the four time states T1, T2,
T3, and T4 and now discuss (with great simplicity) what would be the basic operations performed
by the microprocessor.

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 During the first time state T1, the microprocessor sends out the 20 bit address of the memory
or I/O locations through the address bus. Control signals such as ALE, DT/ R and IO/ M (or
M/ IO ) are also sent out so that the microprocessor can synchronize the required circuitry for
demultiplexing the address data bus as well as provide sufficient delay time for external devices
to be enabled before the access signals are sent (such as RD , WR etc.).

In the next time state T2, the processor sends out control signals such as RD , WR and
DEN so that the external devices may be caused to perform the operation requested. During
a write cycle the data to be written to memory (or I/O) is also output so that the data bits are
set up on the input pins of the devices as the write ( WR ) signal is listed (Therefore avoid
conflicts of setup time). The READY signal is sampled towards the end of T2 and if the
READY signal is low the microprocessor enters a wait state (i.e., T3 becomes a no operation
time state or wait state. This is used to synchronize slower devices).
During a read bus cycle the data bus is sampled at the end of T3 and the data held on the
bus is transferred to the microprocessor.
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The T4 time state is the bus reset time state. During this time state all the buses are
deactivated in preparation for the next bus cycle. During this period, the data bus is also in
the process being read (sampled) if the current bus cycle is a read cycle. Also the transition
on the WR , signal (from low to high) is used to activate external devices to be written to (in
case of the write cycle).
The 8086 Read Bus Cycle
Now we shall discuss the read bus cycle which is shown in figure 4.17. It might seem slightly
complicated but on close observation with figure 4.18 (a) and (b) we will start to get a
clearer picture. Fig. 4.18 lists the names of the various time divisions that the read bus cycle
has been broken down into.
Here the procedure for calculating the maximum access time that is allowed for accessing
(read operation) a memory device is described. All memory devices must be able to operate
well within this time frame for proper operation of the 8086 based system.
Now let us calculate the maximum time that can be made available for memory access.
Now we have earlier read that the microprocessor samples the data bus at the end of time
state T3. However in figure 4.17 if you see you shall find a line going straight down at T3.
Observe the data bus you find at this point a time TCLDX which is the Data in hold time
(figure 4.18(a). Therefore, this is the hold time required so that the proper sampling of the
data bus may occur. Now this point which is at the end of T3 is exactly 3 Time states (i.e.,
600ns) from the start of T1.
Now a memory address appears on the address bus after a time TCLAV after the start the
start of time state Tl. Now the memory should be allowed an access time from the time
the address has appeared on the bus to the time it will be sampled. Memory access time =
600ns - TCLAV
However the data must be setup before the sampling period by the microprocessor. Again
observe figure 4.17. Where you shall find the TDVCL or data setup time which is the setup
time required before sampling of data bus. Now the memory obviously has to place its data
before this setup time required by the processor. Therefore the maximum memory access
time allowed will be
Maximum memory access time = 600ns - TCLAV - TDVCL
= 600 - 110 - 30 (From fig. 4.18(a) and (b)) at 5MHz clock)
= 460 ns
Now a memory chip that is to be interfaced to an 8086 microprocessor should have an
access time much lower than the calculated 460 ns. In the buffered system, the buffers too
will introduce a propagation delay therefore ideally memory chips interfaced to the 8086
should have access times well below 400 ns.

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The 8086 Write Bus Cycle
Figure 4.19 illustrates the 8086 minimum mode write cycle. There are very few differences between
the read and write bus cycles. The RD strobe signal has been here replaced by the WR strobe
while the data bus contains valid data which has to be written to memory. The DT/ R signal
remains at VOH (logic 1) throughout the write bus cycle. The data is written to memory device at
the low to high transition of the WR strobe (during end of T3).
Observe figure 4.19 where we observe that the memory write time has to less than the total time
between the time of the WR strobe transition and the total data hold time after this transition.
Thus memory devices must be able to transfer data in the limiting time period TWHDX which
is equal to TCLCH- 30 = 118 - 30 = 88ns (Figure 4.18(a) and 4.18(b). Therefore memory devices must
be able to written to in times less than 88ns when the 8086 microprocessor is operated at 5 MHz
clock. Most memory IC's available have hold times which range from 1 to 10 ns which is within the
limiting value of 88ns.

A.C. CHARACTERISTICS
(8086: TA - 0°C to 70°C, Vcc = 5V ±10%)
(8086-1: TA - 0°C to 70°C, Vcc = 5V ±5%)
(8086-2: TA - 0°C to 70°C, Vcc = 5V ±5%)

19
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS
8086 8086-1 8086-2
Symbol Parameter Min. Max. Min. Max. Min. Max. Units Test Conditions
TCLCL CLK Cycle Period 200 500 100 500 125 500 ns
TCLCH CLK Low Time 118 53 68 ns
TCHCL CLK High Time 69 39 44 ns
TCH1CH2 CLK Rise Time 10 10 10 ns
From 1.0V to 3.5V
TCL2CL1 CLK Fall Time 10 10 10 ns
From 3.5V to 1.0V
TDVCL Data in Setup Time 30 5 20 ns

TCLDX Data in Hold Time 10 10 10 ns

TR1VCL RDY Setup Time into 8284 (See 35 35 35 ns

Notes 1, 2)
TCLR1X ROY Hold Time into 8284 (See 0 0 0 ns
Notes 1, 2)
TRYHCH READY Setup Time into 8088 118 53 68 ns

TCHRYX 30 20 20 ns
REAOY Hold Time Into 8088

TRYLCL -8 -10 -8 ns
READY Inactive to CLK (See Note 3)

THVCH HOLD Setup Time 35 20 20 ns

TINVCH 30 15 15 ns
INTR, NMI. TEST Setup Time (See
Note 2)
TILIH Input Rise Time (Except CLK) 20 20 20 ns From 0.8V to 2.0V

TIHIL Input Fall Time (Except CLK) 12 12 12 ns From 2.0V to 0.8V

Figure 4.18 (a) Timing Responses (8086/8088)

20
 A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES

8086 8086-1 8086-2

Symbol Parameter Mln. Min. Max. Max. Mln. Max. Units Test Conditions
TCLAV Address Valid Delay 10 110 10 50 10 60 ns
TCLAX Address Hold Time 10 10 10 ns
TCLAZ Address Float Delay TCLAX 80 10 40 TCLAX 50 ns
TLHLL ALE Width TCLCH-20 TCLCH-10 TCLCH-10 ns
TCLLH ALE Active Delay 80 40 50 ns
TCHLL ALE Inactive Delay 85 45 55 ns
TLLAX Address Hold Time to TCHCL-10 TCHCL-10 TCHCL-10 ns
ALE Inactive

TCLDV Data Valid Delay 10 110 10 50 10 60 ns

TCHDX Data Hold Time 10 10 10 ns
TWHDX Data Hold Time After TCLCH-30 TCLCH-25 TCLCH-30 ns
WR

TCVCTV Control Active Delay 1 10 110 10 50 10 70 ns

CL-20-100 pF for
TCHCTV Control Active Delay 2 10 110 10 45 10 60 ns all 8088 Outputs
in addition to
TCVCTX Control inactive Delay 10 110 10 50 10 70 ns internal loads

TAZRL Address Float to READ 0 0 0 ns

Active
TCLRL RD Active Delay 10 165 10 70 10 100 ns

TCLRH RD Inactive Delay 10 150 10 60 10 80 ns

TRHAV RD Inactive to Next TCLCL-45 TCLCL-35 TCLCL-40 ns

Address Active
TCLHAV HLDA Valid Delay 10 160 10 60 10 100 ns

TRLRH RD Width 2TCLCL-75 2TCLCL-40 2TCLCL-50 ns

TWLWH WR Width 2TCLCL-60 2TCLCL-35 2TCLCL-40 ns

TAVAL Address Valid to ALE TCLCH-60 TCLCH-35 TCLCH-40 ns

Low
TOLOH Output Rise Time 20 20 20 ns From 0.8V to 2.0V

TOHOL Output Fall Time 12 12 12 ns From 2.0V to 0.8V

Figure 4.18 (b) Timing Responses (8086/8088)

21
Ready and Wait State Cycle Synchronization
As we have read earlier the microprocessor can be made to enter wait states so as to
interface to slower memory and I/O devices. Suppose we have to design a system based
on the 8086 microprocessor and have to interface a memory device where access time is
560ns. Obviously this is not achievable by the normal 8086 read bus cycle (as the time
allocated for a maximum memory access time of 460 ns). However the use of ready input can
cause the microprocessor to enter wait states (which is the insertion of an extra clock period
between T2 and T3) thereby Allowing a memory access time of 600ns (460ns + 200ns due
to extra clock). This is not achievable by the normal 8086 read bus cycle (as the time
allocated for a maximum memory access time of 460 ns). However the vise of ready input can
cause the microprocessor to enter wait states (which is the insertion of an extra clock period
between T2 and T3) thereby allowing a memory access time of 600ns (460ns + 200ns due to
extra clock).
The Ready Input is sampled at the end of T2 time state and again, if applicable, in the

22
middle of TW. If the ready input is a logic zero at this sampling time, T3 is delayed and TW is
inserted between T2 and T3. Again in the middle of TW, the ready input is re-sampled to
determine whether the next clock period is TW or T3 time state. It is tested for a logic 0
during the high to low transition of the clock at the end of T2, and for a logic 1 during the low
to high transition of the 8086 clock as shown in figure 4.20.

Observe figure 4.20 (which can be seen in figure 4.17) the ready input signal has to match
very stringent requirements and must not occur earlier than 35ns before the end of T2
time state nor later than 8ns after T2 time state so as to cause the microprocessor to
enter wait states. Ready input synchronization can be achieved by using the 8284H clock
generator internal ready synchronization circuitry and the RDY1 and RDY2 ready input
pins.
The 8284 clock generator based ready synchronization
The RDY1 and RDY2 are synchronized ready input pins to the ready synchronization cir-
cuitry of the 8284 A as shown in figure 4.9. The time diagram can be observed from figure
4.17 and redrawn as shown in figure 4.21.

We show you the internal functional diagram of 8284 A clock generator in figure 4.22
where the lower half is ready synchronization circuitry. We see that the RDY1 and AEN1
are ANDed and fed to one input of the OR gate while the second input of the OR gate is fed
by the RDY2 and AEN2 signal which are fed to the second AND gate. In order to present a
logic 1 to either of the D-Flip Flop we require either the RDY1 and AEN1 signals to be
active or the RDY2 and AEN2 signals to be active.

23
Now if ASYNC is logic one then the ready synchronization stage is enabled. Figure 4.23
shows simple READY synchronization circuit for introducing single wait states.

We use a T flip flop to generate the RDY1 input the flip flop is set to 1 when the three
control signals are high (till T2 all are high). Therefore the T flip flop can toggle only after
T2 time state when the output of the NAND gate goes low. The T flip flop will toggle when
the positive edge of T2 occurs thereby generating the desired RDY1 input which will
cause the 8284A to generate the synchronized ready signal to the 8086. The OR gate is used
so that only selected devices that require the ready signal will cause the 8284A circuit to
perform the operation.

The 8086/8088 Minimum Mode Operation

24
The 8086 or 8088 microprocessor can be made to operate in two basic configurations: minimum
mode and maximum mode. The 8086 microprocessor operate in minimum mode when the
MN/ MX pin is pulled directly to the + Vcc power supply. The minimum mode operation is the
simplest way to use a 8086 microprocessor as all the control signal to access I/O or memory are
generated by the microprocessor. Minimum Mode also allows eight bit peripherals to be used
without any problems. The minimum configuration is shown in figure 4.24.

The 8086/8088 Maximum Mode Operation

Maximum mode operation differs greatly from the 8086 minimum mode operation. This
mode of operation is entered when the MN/ MX pin is tied to ground. Some control signals
such as RD , WR etc must now be externally generated. The 8288 bus controller is
designed to be used with the 8086 and generates all external control signals for the 8086
based system as shown in figure 4.25. Maximum mode operation is designed for the 8086
system which requires the 8087 coprocessor to be interfaced.

25
The 8288 Bus Controller
An 8086/8088 system when operated in maximum mode must have an 8288 bus controller to
provide the signals eliminated from the 8086/8088 by the maximum mode operation. The 8288 is
a high performance CMOS Bus Controller manufactured using a self-aligned silicon gate CMOS
process. The 8288 provides the control and command timing signals for 8086, 8088, 80186, and
80188 based systems. The high output drive capability of the 8288 eliminates the need for
additional bus drivers. Static CMOS circuit design insures low operating power.

Figure 4.26 pin out of 8288

Figure 4.25 shows the maximum operation of 8086 using the 8288 IC. Notice the control bus
developed by 8288 bus controller contains separate signals for I/O ( IORC and IOWC ) and
memory ( MRDC and MWTC ). It also contains advanced memory ( AMWC ) and I/O

26
( AIOWC ) write strobes, and the INTA signal. These signals replace the minimum mode ALE,
WR , IO/ M , DT/ R , DEN , INTA , which are lost when the 8086/8088 microprocessors are
operated in the maximum mode.

Figure 4.27 Functional diagram of 8288

Pin Description
PIN NO TYPE DESCRIPTION
SYMBOL
Vcc 20 Vcc:The+5V power supply pin. A 0.1 nF capacitor between pins 10 and 20 is
recommended for decoupling.
GND 10 GROUND.

S0 , S1 , S2 19,3, I STATUS INPUT PINS: These pins are the input pins from the 8086/88 processors.
18 The 8288 decodes these inputs to generate command and control signals at the
appropriate time. When Status pins are not in use (passive), command outputs are
held HIGH (See Table).
CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the
8284A or 8285 clock generator and serves to establish when command/control
signals are generated.
ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the
address latches. This signal is active HIGH and latching occurs on the falling (HIGH
to LOW) transition. ALE is intended for use with transparent D type latches, such as
the 8282 and 8283H.
DEN 16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local
or system data bus. This signal is active HIGH.
DT/ R 4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow
through the transceivers. A HIGH on this line indicates Transmit (write to I/O or
memory) and a LOW indicates Receive (read from I/O or memory).
AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 8288 Bus Controller a
minimum of 110ns (250ns maximum) after it becomes active (LOW). AEN going
inactive immediately three-states the command output drivers. AEN does not affect
the I/O command lines if the 8288 is in the I/O Bus mode (IOB tied HIGH).
CEN 15 I COMMAND ENABLE: When this signal is LOW all 8288 command outputs and
the DEN and PDEN control outputs are forced to their Inactive state. When this
signal is HIGH, these same outputs are enabled.

27
 IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 8288
functions in the I/O Bus mode. When it is strapped LOW, the 8288 functions in the
System Bus mode (See I/O Bus and System Bus sections).
AIOWC 12 O ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write
Command earlier in the machine cycle to give I/O devices an early indication of a
write instruction. Its timing is the same as a read command signal. AIOWC is active
LOW.
IOWC 11 O I/O WRITE COMMAND: This command line instructs an I/O device to read the
data on the data bus. The signal is active LOW.
IORC 13 O I/O READ COMMAND: This command line instructs an I/O device to drive its data
onto the data bus. This signal is active LOW.

AMWC 8 O ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory

write command earlier in the machine cycle to give memory devices an early
indication of a write instruction. Its timing is the same as a read command signal.
This signal is active LOW.
MWTC 9 O MEMORY WRITE COMMAND: This command line instructs the memory to
record the data present on the data bus. This signal is active LOW.

MRDC 7 O MEMORY READ COMMAND: This command line instructs the memory to drive
its data onto the data bus. This signal is active LOW.

INTA 14 O INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device

that its interrupt has been acknowledged and that it should drive vectoring
information onto the data bus. This signal is active LOW.

MCE/ PDEN 17 O This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable
occurs during an interrupt sequence and serves to read a Cascade Address from a
master 8259A Priority Interrupt Controller onto the data bus. The MCE signal is
active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables the data
bus transceiver for the I/O bus that DEN performs for the system bus. PDEN signal
is active LOW.

Functional Description
The command logic decodes the three 8086, 8088, 80186, 80188 status lines ( S0 , S1 , S2 ) to
determine what command is to be issued.

S2 S1 S0 PROCESSOR STATE 82C88 COMMAND

0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC , AIOWC
0 1 1 Halt None
1 0 0 Code Access MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC , AMWC
1 1 1 Passive None

I/O Bus Mode

The 8288 is in the I/O Bus mode if the IOB pin is strapped HIGH. In the I/O Bus mode, all I/O
command lines IORC , IOWC , AIOWC , INTA ) are always enabled (i.e., not dependent on

28
 AEN ). When an I/O command is initiated by the processor, the 8288 immediately activates the
command lines using PDEN and DT/ R to control the I/O bus transceiver. The I/O command
lines should not be used to control the system bus in this configuration because no arbitration is
present. This mode allows one 8288 Bus Controller to handle two external busses. No waiting is
involved when the CPU wants to gain access to the I/O bus. Normal memory access requires a
"Bus Ready" signal ( AEN LOW) before it will proceed. It is advantageous to use the IOB mode
if I/O or peripherals dedicated to one processor exist in a multi-processor system.
System Bus Mode
The 8288 is in the System Bus mode if the IOB pin is strapped LOW. In this mode, no command
is issued until a specified time period after the AEN line is activated (LOW). This mode
assumes bus arbitration logic will inform the bus controller (on the AEN line) when the bus is
free for use. Both memory and I/O commands wait for bus arbitration. This mode is used when
only one bus exists. Here, both I/O and memory are shared by more than one processor.
Command Outputs
The advanced write commands are made available to initiate write procedures early in the
machine cycle. This signal can be used to prevent the processor from entering an unnecessary
wait state.
INTA (Interrupt Acknowledge) acts as an I/O read during an interrupt cycle. Its purpose is to
inform an interrupting device that its interrupt is being acknowledged and that it should place
vectoring information onto the data bus.
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
Control Outputs
The control outputs of the 8288 are Data Enable (DEN), Data Transmit/Receive (DT/ R ) and
Master Cascade Enable/ Peripheral Data Enable (MCE/ PDEN ). The DEN signal determines
when the external bus should be enabled onto the local bus and the DT/ R determines the
direction of data transfer. These two signals usually go to the chip select and direction pins of a
transceiver.
The MCE/ PDEN pin changes function with the two modes of the 8288. When the 8288 is in the
IOB mode (IOB HIGH), the PDEN signal serves as a dedicated data enable signal for the I/O or
Peripheral System bus.

29
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge cycle if the 8288 is in the System Bus
mode (IOB LOW). During any interrupt sequence, there are two interrupt acknowledge cycles
that occur back to back. During the first interrupt cycle no data or address transfers take place.
Logic should be provided to mask off MCE during this cycle. Just before the second cycle begins
the MCE signal gates a master Priority Interrupt Controller's (PIC) cascade address onto the
processor's local bus where ALE (Address Latch Enable) strobes it into the address latches. On
the leading edge of the second interrupt cycle, the addressed slave PIC gates an interrupt vector
onto the system data bus where it is read by the processor.
If the system contains only one PIC, the MCE signal is not used. In this case, the second
Interrupt Acknowledge signal gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each machine cycle and serves to strobe the current
address into the 8282/8283H address latches. ALE also serves to strobe the status ( S0 , S1 , S2 )
into a latch for halt state decoding.
Command Enable
The Command Enable (CEN) input acts as a command qualifier for the 8288. If the CEN pin is
high, the 8288 functions normally. If the CEN pin is pulled LOW, all command lines are held in
their inactive state (not three-state). This feature can be used to implement memory partitioning
and to eliminate address conflicts between system bus devices and resident bus devices.
8282 Address Latch (Working Same as 74LS373)
The 8282 is a high performance CMOS Octal Latching Buffer manufactured using a self-
aligned silicon gate CMOS process. The 8282 provides an eight-bit parallel latch/buffer in a 20
pin package. The active high strobe (STB) input allows transparent transfer of data and latches
data on the negative transition of this signal. The active low output enable ( OE ) permits simple
interface to state-of-the-art microprocessor systems.

30
 Figure 4.28 pin out and truth table of 8282
Functional Diagram

Gated Inputs
During normal system operation of a latch, signals on the bus at the device inputs will become high
impedance or make transitions unrelated to the operation of the latch. These unrelated input
transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS
devices by creating a low resistance path between VCC and GND when the signal is at or near the
input switching threshold. Additionally, if the driving signal becomes high impedance ("float"
condition), it could create an indeterminate logic state at the input and cause a disruption in device
operation.

31
The 828X Series of bus drivers eliminates these conditions by turning off data inputs when data is
latched (STB = logic zero for the 8282/83H) and when the device is disabled ( OE = logic one for
8286H/87H). These gated inputs disconnect the input circuitry from the VCC ground power supply
pins by turning off the upper P-channel and lower N-channel (see Figure 4.29). No new current
flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs
are not transmitted. The next stage is held to a valid logic level internal to the device.
DC input voltage levels can also cause an increase in ICC if these input levels approach the
minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in
its linear operating region (partially conducting state). The 828X series gated inputs mean that
this condition will occur only during the time the device is in the transparent mode (STB = logic
one). ICC remains below the maximum ICC standby specification of 10mA during the time
inputs are disabled, thereby, greatly reducing the average power dissipation of the 828X series
devices

Figure 4.29 The CMOS circuitry of 8282

8286 Transceiver (Working Same as 74LS245)
The Harris 8286H is a high performance CMOS Octal Transceiver manufactured using a self
aligned silicon gate CMOS process (Scaled SAJI IV). The 82C86H provides a full eight bit
bidirectional bus interface in a 20 lead package. The Transmit (T) control determines the data
direction. The active low output enable ( OE ) permits simple interface to the 8086, 8088 and
other microprocessors. The 8286H has gated inputs, eliminating the need for pull-up/pull-down
resistors and reducing overall system operating power dissipation.

32
 Figure 4.30 pin out and truth table of 8286
Functional Diagram

Gated Inputs
During normal system operation of a latch, signals on the bus at the device inputs will become
high impedance or make transitions unrelated to the operation of the latch. These unrelated input
transitions switch the input circuitry and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between VCC and GND when the signal is at or
near the input switching threshold. Additionally, if the driving signal becomes high impedance
(“float” condition), it could create an indeterminate logic state at the inputs and cause a
disruption in device operation.
The Harris 828X series of bus drivers eliminates these conditions by turning off data inputs when
data is latched (STB = logic zero for the 8282/83H) and when the device is disabled ( OE = logic

33
one for the 8286H/87H). These gated inputs disconnect the input circuitry from the VCC and
ground power supply pins by turning off the upper P-channel and lower N-channel (See Figure
4.31). No current flow from VCC to GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held to a valid logic level internal to
the device.
D.C. input voltage levels can also cause an increase in ICC if these input levels approach the
minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in
its linear operating region (partially conducting state). The 828X series gated inputs mean that
this condition will occur only during the time the device is in the transparent mode (STB = logic
one). ICC remains below the maximum ICC standby specification of 10mA during the time
inputs are disabled, thereby greatly reducing the average power dissipation of the 828X series
devices.

Figure 4.31 The CMOS circuitry of 8286

Address Decoding Techniques
The 8086 microprocessor provides a 20-bit memory address that allows up to 1MB of main
memory. Most memory interfaces, however, do not fill this entire range. This means that for a
given memory design, several of the address lines are going to be “unused”. However, these
unused lines are very important because they determine the range of addresses the memory
interface will occupy.
An address decoder is a circuit that examines these extra address lines and enables the memory
for a specified range of address. This is an important part of any memory design, as one block of
memory must not be allowed to overlap another.
Another reason for requiring address decoding is the fact that the microprocessor and memory
devices may have different number of address lines. For example the 8086 microprocessor has
20 address lines while the 8 KB memory has 13 address lines. This in effect means that how we
would access a memory device which has 13 address lines to a microprocessor having 20 address
lines. Secondly if we connect only 13 address lines of the microprocessor to the 8 KB memory
then microprocessor would be able to access only 8KB of memory; however 8086 can access
1MB of memory. If 8086 can access 1MB of memory can we connect different memory blocks
of same or different size summing up to the maximum address limit of microprocessor. We will
discuss some address decoding techniques used with the microprocessor based systems.
Decoder is a digital circuit that recognizes different binary patterns on its input lines and
produces an active output at a unique output line. For a three input decoder the possible input
patterns are 23. That means for a 3 input decoder there can be eight outputs. Depending upon

34
each unique pattern only one output of the decoder becomes active at one time. Using this fact
we can decode different memory blocks with the use of the decoders. (You have already read
about the decoders in your digital logic course. Please revise it)
Logic Gate Decoders
The decoder which recognizes a particular binary pattern and become active on that particular
input pattern is a logic decoder. For example a two input AND gate produces an active high
output if both of the inputs are high. Similarly a two input NAND gate produces an active-low
output if both of the inputs are high.
Suppose we were to interface an EEPROM of size 8 KB to 8088 microprocessor. Since this is a
memory chip it has its own internal address decoder. The memory has the input address lines
only. Since the size of this memory chip is 8 KB there should be log2(8 * 1024)=log2(213)=13
address input lines. So this means the address inputs A0 to A12 of this memory chip is to be
connected with the A0 to A12 of 8088 microprocessor. If we leave the rest address lines of 8088
microprocessor as it is then this memory device is selected irrespective of the content of the other
address lines. For example since this memory chip is addressed in the range 0 to 1FFFH we can
address another chip in the range 2000H to 3FFFH. Among these two chips, if A13 is 0 first chip
is selected and if A13 is 1 the second chip is selected. But if we ignore the upper lines for the first
chip the first chip is selected even when the second chip is selected. But this situation should not
occur in address decoding. In address decoding only one memory location is to be selected for a
particular binary pattern in the address bus. The address decoding using the fewer address lines
of the microprocessor than the actual lines generates the conflicting situations. The address
decoding scheme using fewer address lines is called non unique address decoding.
So for the first memory chip to be selected in the range 00000H to 01FFFH we also have to
consider the higher address lines A13 to A19 of the microprocessor so that it will not generate the
conflicting situations. So the remaining 7 lines (A13 to A19) are fed to the NAND gate decoder
which is again fed to another NAND gate whose another input is fed with IO/ M allowing the
EEPROM to be selected only when the 8088 wants to read the memory but not I/O. Output of
this NAND is fed to one of the chip enable input. The other chip enable is connected with RD .

Figure 4.32: NAND Gate Decoder Circuit to select the 2864 for memory location 00000K to 01FFFH
In the figure you may observe that the NAND gate output would go low when all the inputs
are low. This would in effect cause the EEPROM device to be accessed for memory
address ranging from 00000H to 1FFFH. The NAND gate output goes low when all the

35
inputs are low and the second NAND gate goes low when the output from the first gate is
low and IO/ M is low the second NAND gate generates low active signal selecting the
EEPROM chip. The EEPROM device is selected in the address of above as it is connected
to the CE pin of the 2864. The address range can be calculated as:
Lower address 0000 0000 0000 0000 0000 = 00000H
Higher address 0000 0001 1111 1111 1111 = 01000H
To NAND decoder
If it is desired that the EEPROM be placed at the last address of 8088 address space then the
address ranges from FEFFFH to FFFFFH. The EEPROM at the last address is decoded as
follows.

Figure 4.33 NAND Gate Decoder Circuit to select the 2864 for memory location FEFFFH to FFFFFH.
Observe that the NAND gate decoder circuit will give a low output when all inputs are high. This is
due to the inverters attached after the address lines and before the NAND gate. Therefore the
EEPROM would be selected when the inputs A13 – A19 are high and IO/ M is low.
Interfacing RAM for 8088 is easy because the bus of memory is of 8-bit and that of the 8088
microprocessor is 8-bit. But interfacing memory with 8086 is different than interfacing memory
with 8088 because the bus for a memory consists of 8-bit while the bus for 8086 consists of 16-
bit.
So let’s take example of interfacing HM62864 SRAM memory chip. This is a 64 K Byte
memory chip. This ram has three active-low control inputs labeled CS1 (chip select 1), WE
(write enable), OE (output enable) and one active-high control input labeled CS2 (chip select 2).
Since the input/output pins of the SRAM are 8-bit and the data bus of 8088 microprocessor is 8-bit
so all the data pins of the 8088 are connected directly and the memory read and write lines to OE
and WE pins respectively.

36
 Figure 4.34 64 KB SRAM interface with 8088 (only a single memory chip is required)
The 8088 has a 20-bit address bus; the HM62864, however, has only 16 address pins. If we
connect address lines A0-A15 to the memory, what is to be done with the four remaining
address lines—A16-A19? The Figure shows these lines connected to a box labeled decoder. The
decoder is shown in the following figure using NAND gate and inverter. Notice, however, that
the output of this NAND gate drives the CS1 input of the RAM chip. Because the RAM is
enabled only when this input is low and CS2 high, we can conclude that the memory will be
enabled only when A16 is low and A17-A19 are high.

Figure 4.35 elaborated decoder of figure 4.34

Exercise: Try to interface the memory at the address starting at A0000H. Design the address
decoding circuit for the same SRAM.
As we know that the data bus of the 8086 microprocessor is of 16bit interfacing the HM82864
will not work with the direct connection. So we require two RAM modules, one interfacing at the
odd address and the other at the even address. So the interface provides 128KB of memory.

37
 Figure 4.36 8086 SRAM interface with two RAM modules
A0 address line is used to select even or the odd memory banks. To allow the processor to access
the individual bytes as well as 16-bit words BHE is used. When this line is low, the processor is
accessing a word or an odd memory byte. In both these cases, the high order part of the data bus
(D8-D15) is involved. On the other hand, when A0 is low the processor is either accessing a
word or an even memory byte. In this case the low-order part of the data bus (D0-D7) is
involved. This is clearly shown in the figure 4.36 above. The decoder verifies the high-order
address lines mathc the addresss assigned to this circuit. A0 and BHE are then used to enable
the even (A0=0) or odd ( BHE =0) SRAM chip. Both chips are enabled for a word access. Note
that this implies that words must befin at an even memory address (that is address with A0=0).
Words that begin at an odd address will require two memory cycles; one to access the odd byte
and the second to access the even byte.
Exercise: Design the address decoding circuit for the figure in 4.36 to interface at address
E0000H.
Block Decoders
In a practical microcomputer the memory array often consists of several blocks of memory chips.
This will require a separate decoder for each memory block unless a special block decoder is
built.
A 256K-byte memory array is shown in Fig. 4.37. It consists of four 64K-byte blocks of memory
and a 74LS138 (Intel part number 8205) 3-to-8-line decoder. The low- order address lines AB0-
AB15 select one of 64K bytes in each memory bank. However, the decoder allows only one bank
to be enabled at a time. For example, output 0 will be active when AB19 = 0 (enabling the
decoder) and AB18-AB16 = 000 (selecting the 0 output). This corresponds to the address range
00000-OFFFFH.

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 Figure 4.37 The 74LS138 3-to-8 decoder to select different memory blocks
The decoder in Fig. 4.37 provides eight block select outputs and thus can be used to decode up to
512K bytes of memory. So with the use of the 4-to-16 decoders we can decode 16 blocks of
memory.
To decode the address of the memory for 8086 for the same type of the memory chip BHE and
address A0-to-A16 are used by the memory blocks for their internal decoding and the even and
odd memory address decoding. The output from the block decoder are connected to the even and
odd memory as a single chip and the chip select of the both the even and odd memory are
connected together. The even and odd are selected according to the value of A0 and BHE as
discussed above.
PROM Decoders
It is somewhat dissimilar to have the 50,000-transistor 8086 microprocessor sitting beside
several SSI and MSI TTL devices providing address decoding and other miscellaneous gating
functions. These chips, with 15 to 100 transistors per package, may collectively require as much
board space as the more complex processor they support. There ought to be a better way.
And, of course, there is. One solution is to replace all of this combinational TTL logic with a
high-speed PROM. After all, a PROM is nothing more than an elaborate truth-table generator. As
you have already studied in your digital logic, it stores one w-bit output word for each of its 2n
input combinations.
As an example, consider the design of an address decoder to implement the 8086 system whose
memory is mapped in Fig. 4.38. What makes the design of this decoder difficult is the three
different block sizes—IK, 16K, and 64K. A block decoder is impractical because the smallest
block size—IK bytes—would require a decoder with 10 inputs and therefore 210, or 1024
outputs! It appears that we are stuck having to build three separate decoder circuits.

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 Figure 4.38: memory map for 8086 microcomputer system featuring three different block sizes
But now consider using a PROM with 10 inputs. Assuming an 8-bit word size, a lK-byte PROM
would be required, not a particularly exotic or expensive component. The 77/87S180 series of
fusible-link PROMs of 1K-byte could be used for this purpose.
Selecting the 87S181A with tri-state outputs, the memory interface in Fig. 4.39 can be drawn.
The low-order address lines are connected to the memory chips, with the PROM used to decode
the 1024 1K-byte block boundaries. Q1-Q4 have arbitrarily been selected to provide the four
memory select signals.
These outputs should be programmed so that each is low when its address range is applied to the
PROM. For example, Q4, the RAM0 select signal, should be low for addresses in the range
00000H-0FFFFH. Over this range, AB19-AB10 vary from 0000000000B to 0000111111B, that is,
location 0 to location 63D in the PROM. This corresponds to the first 64 IK blocks. Addresses
outside this range should cause Q4 to be high (inactive). Similar calculations can be made for
the other three blocks.

The PROM decoder offers several advantages over its discrete logic TTL counterpart. Most
important, it replaces several TTL packages with one 24-pin package. It also offers the
versatility of allowing the system's memory map to be programmable. A new memory
configuration can be obtained by simply inserting a new PROM. Finally, the circuit is fast.
Typical access time (decoder delay) is 25 ns—probably faster than the TTL gates it replaces.

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 Figure 4.39: Using a PROM to provide four different address select signals

PLAs and PALs

The PROM decoder in 4.39 uses 64 + 64 + 16 + 1 = 145 of the 1024 possible memory locations.
The remaining 879 locations store a memory disable code. This seems rather wasteful, as each of
these4 879 bytes stores exactly the same binary code 0000XXXXH. Could we devise a
component that has the decoding capability of the PROM but not the wasted storage space?
Before answering this question, let's develop an equivalent circuit for a PROM (or ROM) when
it is used to replace combinational logic. Because the ROM develops all 2n possible
combinations of its inputs, we think of it as a truth-table generator. We also know that using the
rules of Boolean algebra, any truth-table function can be expressed as a combinational logic
circuit in standard sum-of-products form. Thus we might visualize a ROM as an array of AND
gates (developing all possible product terms) driving one OR gate. ROMs with multiple outputs
(i.e., word sizes greater than one bit) have several OR gates. This is shown in Fig. 4.40.
A ROM has certain restrictions. Each AND gate must develop one of the 2n product terms, no
simplifications are possible. For example, if the function to be implemented is
X = ABCD + ABC D = ABC (D + D ) = ABC
it will still be implemented as ABCD + ABCD by the ROM. This is where the "wasted" space
comes from. This restriction also has another negative effect. If the D input in the example
above switches from a 1 to a 0, a different AND gate (the one developing the product
ABCD) will be enabled. This may cause a "glitch" (momentary pulse) in the ROM's output as
one AND gate switches OFF and the other switches ON.

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 Figure 4.40: PROMs, PLAs and PALs can be used to implement logic functions expressed in standard sum-of-
products form. Each device consists of an AND array whose outputs can be used to drive an OR array
There are two alternatives to the ROM. They are called the PL A and PAL (for "programmable
logic array" and "programmable array logic"): The PLA is the most versatile. It allows the entire
AND array (see fig. 4.40) to be programmed. Thus the term ABC required in the example above
could be programmed. The PLA also allows the OR array to be programmed. This means that
each OR gate has as many inputs as there are product terms.
A PAL is similar to a PLA but its OR array is limited so that each OR gate has a fixed number of
inputs. The "wasted" storage space of the ROM is reduced in the PLA and PAL by limiting each
to fewer than 2n product terms.
Electrically, PALs and PLAs are available with TTL-compatible inputs and outputs. The
PAL10L8 has a maximum propagation delay of 35 ns. A FAST series is available with typical
delays of only 15 ns.
PALs are programmed using a fusible-link technique similar to that of a bipolar PROM. This
makes the parts extremely I versatile. A designer can quickly design and fabricate his or her own
"custom" integrated circuit in a matter of hours. And there need not be a high volume to justify
the part, as would be the case in the conventional four-to eight-month custom IC development
cycle.
PLAs and PALs are now the choice of most designers for replacement of combinational (and
sequential) logic. PLAs are the most versatile but also the most expensive. They require special
programmers, whereas PALs can be programmed with a conventional (fusible-link) PROM
programmer. PROMs are chosen when all 2n product terms are required—microprocessor
memory applications, primarily.

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