LG 65eg960t, 65eg960t-Ta

Internal Use Only
North/Latin America http://aic.lgservice.com

Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
OLED TV
SERVICE MANUAL
CHASSIS : EB53E
MODEL : 65EG960T 65EG960T-TA

65EG960Y 65EG960Y-TA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL69302301 (1505-REV00) Printed in Korea

CONTENTS
CONTENTS ............................................................................................... 2
SAFETY PRECAUTIONS ......................................................................... 3
SERVICING PRECAUTIONS..................................................................... 4
SPECIFICATION........................................................................................ 6
ADJUSTMENT INSTRUCTION............................................................... 13
BLOCK DIAGRAM................................................................................... 23
EXPLODED VIEW ................................................................................... 34
SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX
TROUBLE SHOOTING GUIDE.................................................. APPENDIX
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.
IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.
Fuse and Conventional Resistor

Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range 3. Test method

This specification is applied to the OLED TV used EB53E 1) Performance: LGE TV test method followed
chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC specification
2. Requirement for Test - Wireless : Wireless HD Specification (Option)
Each part is tested as below without special notice
1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 20 minutes prior to
the adjustment.
4. Model General Specification

No. Item Specification Remarks
1 Market Asia, Oceania, Africa, Middle East(PAL/DVB Market)
1) PAL-BG/DK/I/I’
2 Television system 2) SECAM L/L’, DK, BG, I
3) DVB-T/T2, C, S/S2
3 Channel Storage ATV / DTV - 1500EA
► DVB-T
- Guard Interval(Bitrate_Mbit/s): 1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne
16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
Digital : COFDM(DVB-T) Only DVB-T Model
4 Receiving system 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
Digital : COFDM(DVB-T/T2) Only DVB-T2 Model
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
Digital : QAM
► DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s
- Modulation :
16QAM, 64-QAM, 128-QAM and 256-QAM
► DVB-S/S2
- Symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s
- Viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode: 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
5 Video Input RCA PAL, SECAM, NTSC 4 System : PAL, SECAM, NTSC, PAL60
6 Component Input Y/Pb/Pr
Antenna, AV1, Component, HDMI1, HDMI2, HDMI3,
7 Head phone out
USB1, USB2, USB3
8 HDMI Input HDMI1-DTV,HDMI2-DTV, HDMI3-DTV PC(HDMI Ver. 1.4), Support HDCP
9 Audio Input DVI Audio, Component, AV1
10 SPDIF out SPDIF out
11 USB Input For My Media(Movie/Photo/Music List) or For SVC
5. External Input Support Format
5.1. Standard Level For Input Signal (Video, Audio, Y/C, Component)
No Item Min Typ Max Unit Remarks
1. Video Input Level 0.9 1 1.1 Vpp
2. S Video Input Level(Y) 0.85 1 1.15 Vpp
3. S Video Input Level(C-Burst) 0.143 0.286 Vpp
4. Audio Input Level 0.4 0.5 0.6 Vrms PAL,SECAM, AV1(SCART), AV2, Component
Component Video Input Level
5. 0.6 0.7 0.8 Vpp
(Y, CB/PB, CR/PR)
5.2. 2D Mode
(1) CVBS input
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed Remarks
1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I) NTSC-M
2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I) NTSC-M
3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz PAL-BDGHI
(2) Component (Y, CB/PB, CR/PR)

No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I)
2 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I)
3 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz
4 720*480p 31.47 59.94 27.00 SDTV 480P
5 720*480p 31.50 60.00 27.03 SDTV 480P
6 720*576p 31.25 50.00 27.00 SDTV 576P 50Hz
7 1280*720 44.96 59.94 74.18 HDTV 720P
8 1280*720 45.00 60.00 74.25 HDTV 720P
9 1280*720 45.00 50.00 74.25 HDTV 720P 50Hz
10 1920*1080 28.13 50.00 74.25 HDTV 1080I 50Hz,
11 1920*1080 33.72 59.94 74.18 HDTV 1080I
12 1920*1080 33.75 60.00 74.25 HDTV 1080I
13 1920*1080 56.25 50.00 148.50 HDTV 1080P
14 1920*1080 67.50 60.00 148.50 HDTV 1080P
(3) HDMI (DTV)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 640*480 31.47 59.94 25.13 SDTV 480P
2 640*480 31.50 60.00 25.13 SDTV 480P
3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I)
4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I) Spec. out but display
5 720*576 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz
6 720*480 31.47 59.94 27.00 SDTV 480P
7 720*480 31.50 60.00 27.03 SDTV 480P
8 720*576 31.25 50.00 27.00 SDTV 576P
9 1280*720 44.96 59.94 74.18 HDTV 720P
10 1280*720 45.00 60.00 74.25 HDTV 720P
11 1280*720 37.50 50.00 74.25 HDTV 720P
12 1920*1080 28.13 50.00 74.25 HDTV 1080I
13 1920*1080 33.72 59.94 74.18 HDTV 1080I
14 1920*1080 33.75 60.00 74.25 HDTV 1080I
15 1920*1080 26.97 23.98 63.30 HDTV 1080P
16 1920*1080 27.00 24.00 63.36 HDTV 1080P
17 1920*1080 33.71 29.97 79.12 HDTV 1080P
18 1920*1080 33.75 30.00 79.20 HDTV 1080P
19 1920*1080 56.25 50.00 148.50 HDTV 1080P
20 1920*1080 67.43 59.94 148.35 HDTV 1080P
21 1920*1080 67.50 60.00 148.50 HDTV 1080P
22 3840*2160 53.95 23.98 297.00 UDTV 2160P
23 3840*2160 54.00 24.00 297.00 UDTV 2160P
24 3840*2160 56.25 25.00 297.00 UDTV 2160P
25 3840*2160 61.43 29.97 297.00 UDTV 2160P
26 3840*2160 67.50 30.00 297.00 UDTV 2160P
27 3840*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0
28 3840*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0
29 3840*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0
30 4096*2160 53.95 23.98 297.00 UDTV 2160P
31 4096*2160 54.00 24.00 297.00 UDTV 2160P
32 4096*2160 56.25 25.00 297.00 UDTV 2160P
33 4096*2160 61.43 29.97 297.00 UDTV 2160P
34 4096*2160 67.50 30.00 297.00 UDTV 2160P
35 4096*2160 112.50 50.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0
36 4096*2160 135.00 59.94 593.41 UDTV 2160P 8 bit / YCbCr 4:2:0
37 4096*2160 135.00 60.00 594.00 UDTV 2160P 8 bit / YCbCr 4:2:0
(4) HDMI Input (PC)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed Remarks
1 640*350 31.47 70.09 25.17 EGA
2 720*400 31.47 70.08 28.32 DOS
3 640*480 31.47 59.94 25.17 VESA(VGA)
4 800*600 37.88 60.32 40.00 VESA(SVGA)
5 1024*768 48.36 60.00 65.00 VESA(XGA)
6 1360*768 47.71 60.01 84.75 VESA(WXGA)
7 1152*864 54.35 60.05 80.00 VESA
8 1280*1024 63.98 60.02 109.00 SXGA
9 1920*1080 67.50 60.00 158.40 WUXGA(Reduced Blanking)
10 3840*2160 54.00 24.00 297.00 UDTV 2160P
11 3840*2160 56.25 25.00 297.00 UDTV 2160P
12 3840*2160 67.50 30.00 297.00 UDTV 2160P
13 4096*2160 53.95 23.97 297.00 UDTV 2160P
14 4096*2160 54.00 24.00 297.00 UDTV 2160P
5.3. 3D Mode
(1) RF input
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed Remarks
1 1280*720 37.50 50 74.25 HDTV 720P 2D to 3D, Side by Side, Top & Bottom
2 1920*1080 28.13 50 74.25 HDTV 1080I 2D to 3D, Side by Side, Top & Bottom
(2) HDMI input

1) HDMI1.4/2.0 (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock(MHz) Proposed 3D input proposed mode
1 720*480 31.50 60.00 27.03 SDTV 480P
2 720*576 31.25 50.00 27.00 SDTV 576P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Frame Sequential, Row Inter-
45.00 60.00 74.25 HDTV 720P leaving, Column Interleaving
3 1280*720
37.50 50.00 74.25 HDTV 720P
33.75 60.00 74.25 HDTV 1080I
2D to 3D, Side by Side(Half), Top & Bottom
28.13 50.00 74.25 HDTV 1080I
27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
4 1920*1080 28.12 25.00 74.25 HDTV 1080P Checker Board, Row Interleaving, Column
33.75 30.00 74.25 HDTV 1080P Interleaving
67.50 60.00 148.50 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,
Checker Board, Single Frame Sequential, Row
56.25 50.00 148.50 HDTV 1080P Interleaving, Column Interleaving
53.95 23.98 297.00
54.00 24.00 296.70
56.25 25.00 297.00 HDTV 2160P 2D to 3D, Top & Bottom(half), Side by Side(half)
3840*2160
5 61.43 29.97 297.00
4096*2160
67.50 30.00 296.70
112.50 50.00 594.00 2D to 3D, Top & Bottom(half), Side by Side(half)
HDTV 2160P
135.00 60.00 594.00 (8 bit, YCbCr 4:2:0)
2) HDMI 1.4b (3D supported mode automatically)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) VIC 3D input proposed mode Proposed
Top-and-Bottom Secondary(SDTV 480P)
31.47 / 31.50 59.94/ 60.00 25.13/25.20 1
Side-by-side(half) Secondary(SDTV 480P)
1 640*480 31.47 / 31.50 59.94/ 60.00 50.35/50.40 1 Side-by-side(Full) (SDTV 480P)
Frame packing Secondary(SDTV 480P)
62.94 / 63.00 59.94/ 60.00 50.35/50.40 1
Line alternative (SDTV 480P)
31.47 / 31.50 59.94 / 60.00 27.00/27.03 2,3
2 720*480 31.47 / 31.50 59.94 / 60.00 54.00/54.06 2,3 Side-by-side(Full) (SDTV 480P)
62.94 /63.00 59.94 / 60.00 54.00/54.06 2,3
Line alternative (SDTV 480P)
31.25 50.00 27.00 17,18
31.25 50.00 54.00 17,18 Side-by-side(Full) (SDTV 576P)
62.50 50.00 54.00 17,18
3 720*576 Line alternative (SDTV 576P)
Secondary(SDTV 576I)
Frame packing
(SDTV 576I
Side-by-side(Full)
15.63 50.00 27.00 21 (SDTV 576I
Top-and-Bottom
Side-by-side(half)
Top-and-Bottom Primary(HDTV 720P)
37.50 50.00 74.25 19
Side-by-side(half) Primary(HDTV 720P)
37.50 50.00 148.50 19 Side-by-side(Full) (HDTV 720P)
44.96 / 45.00 59.94 / 60.00 74.17/74.25 4
4 1280*720
44.96 / 45.00 59.94 / 60.00 148.35/148.50 4 Side-by-side(Full) (HDTV 720P)
75.00 50.00 148.50 19
Side-by-side(half) (HDTV 720P)
Frame packing Primary(HDTV 720P)
89.91/90.00 59.94 / 60.00 148.35/148.50 4
Line alternative (HDTV 720P)
Top-and-Bottom Secondary(HDTV 1080I)
28.13 50.00 74.25 20
Side-by-side(half) Primary(HDTV 1080I)
28.13 50.00 148.50 20 Side-by-side(Full) (HDTV 1080I)
Top-and-Bottom Secondary(HDTV 1080I)
33.72 / 33.75 59.94 / 60.00 74.17/74.25 5
Side-by-side(half) Primary(HDTV 1080I)
33.72 / 33.75 59.94 / 60.00 148.35/148.50 5 Side-by-side(Full) (HDTV 1080I)
Primary(HDTV 1080I)
56.25 50.00 148.50 20 Frame packing
(HDTV 1080I)
Primary(HDTV 1080I)
67.43/67.50 59.94 / 60.00 148.35/148.50 5 Frame packing
(HDTV 1080I)
26.97 / 27.00 23.97 / 24.00 74.17 / 74.25 32
26.97 / 27.00 23.97 / 24.00 148.35 / 148.50 32 Side-by-side(Full) (HDTV 1080P)
Top-and-Bottom Secondary(HDTV 1080P)
28.12 25.00 74.25 33
5 1920*1080 Side-by-side(half) Secondary(HDTV 1080P)
28.12 25.00 148.50 33 Side-by-side(Full) (HDTV 1080P)
33.72 / 33.75 29.98 / 30.00 74.18/74.25 34
Side-by-side(half) Secondary(HDTV 1080P)
33.72 / 33.75 29.98 / 30.00 148.35/148.50 34 Side-by-side(Full) (HDTV 1080P)
43.94/54.00 23.97 / 24.00 148.35/148.50 32
Frame packing Secondary(HDTV 1080P)
56.25 25.00 148.50 33
67.43 / 67.5 29.98 / 30.00 148.35/148.50 34
56.25 50.00 148.50 31
67.43 / 67.50 59.94 / 60.00 148.35/148.50 16
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
(3) HDMI-PC Input (3D) (3D supported mode manually)
1 1024*768 48.36 60.00 65.00 HDTV 768P 2D to 3D, Side by Side(half), Top & Bottom
2D to 3D, Side by Side(half), Top & Bottom,
2 1920*1080 67.500 60 148.50 HDTV 1080P Checker Board, Single Frame Sequential,
Row Interleaving, Column Interleaving
54.00 24.00 296.70
2D to 3D, Top & Bottom(half), Side by
3 3840*2160 56.25 25.00 297.00 HDTV 2160P
Side(half),
67.50 30.00 296.70
2D to 3D,
4 4096*2160 54 24.00 297.00 HDTV 2160P
Top & Bottom(half), Side by Side(half),
640*350
720*400
5 Others - - - 640*480 2D to 3D, Side by Side(half), Top & Bottom
800*600
1152*864
(4) Component Input ( 3D) (3D supported mode manually)

4 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(half), Top & Bottom
(5) USB
1) Movie (3D) (3D supported mode manually)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode
1 Under 704x480 - - - 2D to 3D
Over 704x480
2 Under 1080P - - - 2D to 3D, Side by Side(Half), Top & Bottom
interlaced
2D to 3D, Side by Side(Half), Top & Bottom, Checker
Over 704x480 - 50 / 60 - Board, Row Interleaving, Column Interleaving, Frame
3 Under 1080P Sequential
progressive 2D to 3D, Side by Side(Half), Top & Bottom, Checker
- others -
Board, Row Interleaving, Column Interleaving
4 Over 2160P - 24/25/30 - 2D to 3D, Side by Side(Half), Top & Bottom
2) DLNA - Photo (3D) (3D supported mode manually)

1 Under 320x240 - - - 2D to 3D
2 Over 320x240 - - - 2D to 3D, Side by Side(Half), Top & Bottom
3) DLNA (3D) (3D supported mode automatically)

1 1080p 33.75 30.00 74.25 Side by Side(Half), Top & Bottom, Checker Board
2 2160p 67.50 30.00 297.00 MPO(Photo), JPS(Photo)
(6) Miracast, Widi (3D supported mode manually)

1 1024*768p - 30/60 -
2 1280*720p - 30/60 - 2D to 3D, Side by Side(Half), Top & Bottom
3 1920*1080p - 30/60 -
4 Others - - - 2D to 3D
■ Remark: 3D Input mode

Single Frame Frame Row Column
No. Side by Side Top & Bottom Checker board 2D to 3D
Sequential Packing Interleaving Interleaving
1
ii. iii. iv. v. vi.
ADJUSTMENT INSTRUCTION
1. Application Range 3.2. LAN Inspection
This specification sheet is applied to all of the OLED TV with 3.2.1. Equipment & Condition
EB53E chassis. ▪ Each other connection to LAN Port of IP Hub and Jig
2. Designation
(1) Because this is not a hot chassis, it is not necessary to
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) The adjustment must be performed in the circumstance of
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative
3.2.2. LAN inspection solution
▪ LAN Port connection with PCB
humidity if there is no specific designation.
▪ Network setting at MENU Mode of TV
(4) The input voltage of the receiver must keep AC 100-240
▪ Setting automatic IP
V~, 50/60 Hz.
▪ Setting state confirmation
(5) The receiver must be operated for about 5 minutes prior to
- If automatic setting is finished, you confirm IP and MAC
the adjustment when module is in the circumstance of over
Address.
15 °C.
In case of keeping module is in the circumstance of 0 °C, it 3.2.3. WIDEVINE key Inspection
should be placed in the circumstance of above 15 °C for 2 - Confirm key input data at the "IN START" MENU Mode.
hours.
In case of keeping module is in the circumstance of below

-20 °C, it should be placed in the circumstance of above 15
°C for 3 hours.
[Caution]
When still image is displayed for a period of 20 minutes or
longer (Especially where W/B scale is strong. Digital pattern
13ch and/or Cross hatch pattern 09ch), there can some
afterimage in the black level area.
3. Automatic Adjustment
3.1. MAC address D/L, CI+ key D/L(Option),
Widevine key D/L, ESN D/L, HDCP20 D/L 3.3. LAN PORT INSPECTION(PING TEST)
Connect: USB port Connect SET → LAN port == PC → LAN Port
Communication Prot connection SET PC
▪ Com 1,2,3,4 and 115200(Baudrate)
Mode check: Online Only
▪ Check the test process 3.3.1. Equipment setting
: DETECT→MAC→ESN→Widevine→CI(option)→HDCP20 (1) Play the LAN Port Test PROGRAM.
▪ Play: Press Enter key (2) Input IP set up for an inspection to Test Program.
▪ Result: Ready, Test, OK or NG *IP Number : 12.12.2.2
▪ Printer Out (MAC Address Label)
3.3.2. LAN PORT inspection(PING TEST)
(1) Play the LAN Port Test Program.
(2) Connect each other LAN Port Jack.
(3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.
3.4. Model name & Serial number Download 3.5. CI+ Key checking method
3.4.1. Model name & Serial number D/L Check whether the key was downloaded or not at ‘In Start’
▪ Press "P-ONLY" key of service remote control. menu. (Refer to below).
(Baud rate : 115200 bps)
▪ Connect RS-232C Signal to USB Cable to USB.
▪ Write Serial number by use USB port.
▪ Must check the serial number at Instart menu. => Check the Download to CI+ Key value in LGset.
3.5.1. Check the method of CI+ Key value
3.4.2. Method & notice (1) Check the method on Instart menu
(1) Serial number D/L is using of scan equipment. (2) Check the method of RS232C Command
(2) Setting of scan equipment operated by Manufacturing 1) Into the main ass’y mode(RS232: aa 00 00)
Technology Group. CMD 1 CMD 2 Data 0
(3) Serial number D/L must be conformed when it is produced A A 0 0
in production line, because serial number D/L is mandatory
by D-book 4.0. 2) Check the key download for transmitted command
(RS232: ci 00 10)
* Manual Download (Model Name and Serial Number) CMD 1 CMD 2 Data 0
If the TV set is downloaded by OTA or service man, sometimes C I 1 0
model name or serial number is initialized.(Not always)
It is impossible to download by bar code scan, so It need 3) Result value
Manual download. - Normally status for download : OKx
1) Press the "Instart" key of Adjustment remote control. - Abnormally status for download : NGx
2) Go to the menu "7.Model Number D/L" like below photo.
3) Input the Factory model name(ex 47LB650V-ZA) or Serial 3.5.2. Check the method of CI+ key value(RS232)
number like photo. 1) Into the main ass’y mode(RS232: aa 00 00)
CMD 1 CMD 2 Data 0
A A 0 0
2) Check the mothed of CI+ key by command
4) Check the model name Instart menu. → Factory name (RS232: ci 00 20)
displayed. (ex 47LB650V-ZA) CMD 1 CMD 2 Data 0
5) C heck the Diagnostics.(DTV country only) → Buyer
C I 2 0
model displayed. (ex 47LB650V-ZA)
3) Result value
i 01 OK 1d1852d21c1ed5dcx
CI+ Key Value
3.6. WIFI MAC ADDRESS CHECK

(1) Using RS232 Command
H-freq(kHz) V-freq.(Hz)
Transmission [A][I][][Set ID][][20][Cr] [O][K][X] or [NG]
(2) Check the menu on in-start
4. Manual Adjustment (1) EDID for 3D Model
1) DTS
4.1. EDID(The Extended Display Identification # HDMI 1(C/S : A0 9E) - HDMI UHD Deep On Case
Data)/DDC(Display Data Channel) download EDID Block 0, Bytes 0-127 [00H-7FH]
4.1.1. Overview 0 1 2 3 4 5 6 7 8 9 A B C D E F
0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
It is a VESA regulation. A PC or a MNT will display an optimal
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
resolution through information sharing without any necessity
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
of user input. It is a realization of "Plug and Play".
30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
4.1.2. Equipment 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
- Since embedded EDID data is used, EDID download JIG, 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
HDMI cable and D-sub cable are not need. 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
- Adjustment remote control
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.1.3. Download method 80 02 03 55 F1 58 10 9F 04 13 05 14 03 02 12 20 21
(1) Press "ADJ" key on the Adjustment remote control, then 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06
select "12.EDID D/L", By pressing "Enter" key, enter EDID A0 C0 15 07 50 09 57 07 7C 03 0C 00 10 00 B8 3C 20
D/L menu. B0 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10
For HDMI EDID C0 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 C0 00
D0 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36
DVI-D to HDMI or HDMI to HDMI
E0 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E
F0 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 9E
# HDMI 1(C/S : E6 F4) - HDMI UHD Deep Off Case

EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
(2) S elect "Start" button by pressing "Enter" key, HDMI1/ 0 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
HDMI2/ HDMI3 are writing and display OK or NG. 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
4.1.4. EDID DATA 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
▪ Reference 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
- HDMI1 ~ HDMI3 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
- In the data of EDID, bellows may be different by Input mode. 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
0 1 2 3 4 5 6 7 8 9 A B C D E F
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
0x00 00 FF FF FF FF FF FF 00 1E 6D ⓐ ⓑ EDID Block 1, Bytes 128-255 [80H-FFH]
0x01 ⓒ 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
0 1 2 3 4 5 6 7 8 9 A B C D E F
0x02 0F 50 54 A1 8 00 31 40 45 40 61 40 71 40 81 80
0x03 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
80 02 03 46 F1 54 10 9F 04 13 05 14 03 02 12 20 21
0x04 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50
0x05 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A A0 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02
0x06 3E 1E 53 10 00 0A 20 20 20 20 20 20 ⓓ B0 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10
0x07 ⓓ 01 ⓔ1 C0 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C
0x00 02 03 3A F1 4E 10 9F 04 13 05 14 03 02 12 20 21 D0 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
0x01 22 15 01 29 3D 06 C0 15 07 50 ⓕ
E0 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
0x02 ⓕ
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F4
0x03 ⓕ 10 28 10 E3 05 03 01 02 3A 80 18 71 38
0x04 2D 40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 # HDMI 2(C/S : A0 8E) - HDMI UHD Deep On Case
0x05 71 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 01 1D
0x06 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 00 00 1E
0x07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ⓔ2 0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
ⓐ Product ID 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
ⓑ Serial No: Controlled on production line. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
ⓒ Month, Year: Controlled on production line: 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
ex) Monthly : ‘01’ → ‘01’, Year : ‘2015’ → ‘19’ 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
ⓓ Model Name(Hex): LGTV 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
ⓔ Checksum(LG TV): Changeable by total EDID data. 60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
ⓕ Vendor Specific(HDMI) 70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
EDID Block 1, Bytes 128-255 [80H-FFH] 2) AC3
0 1 2 3 4 5 6 7 8 9 A B C D E F # HDMI 1(C/S : A0 A7) - HDMI UHD Deep On Case
80 02 03 55 F1 58 10 9F 04 13 05 14 03 02 12 20 21 EDID Block 0, Bytes 0-127 [00H-7FH]
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 29 3D 06 0 1 2 3 4 5 6 7 8 9 A B C D E F
A0 C0 15 07 50 09 57 07 7C 03 0C 00 20 00 B8 3C 20 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
B0 C0 8E 01 02 03 04 01 4F 3F FC 08 10 18 10 06 10 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
C0 16 10 28 10 67 D8 5D C4 01 78 80 03 E3 05 C0 00 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
D0 E4 0F 00 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
E0 00 40 84 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
F0 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 8E 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
# HDMI 2(C/S : E6 E4) - HDMI UHD Deep Off Case
EDID Block 0, Bytes 0-127 [00H-7FH] EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 80 02 03 52 F1 58 10 9F 04 13 05 14 03 02 12 20 21
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 26 15 07
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 A0 50 09 57 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C B0 02 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 C0 10 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A D0 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC E0 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 F0 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 A7

0 1 2 3 4 5 6 7 8 9 A B C D E F # HDMI 1(C/S : E6 FD) - HDMI UHD Deep Off Case
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 0 1 2 3 4 5 6 7 8 9 A B C D E F
A0 09 57 07 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 02 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
B0 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
C0 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
D0 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
E0 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E4 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
# HDMI 3(C/S : E6 D4) - HDMI UHD Deep Off Case
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 A0 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02 03 04 01
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C B0 4F 3F FC 08 10 18 10 06 10 16 10 28 10 E5 0E 60
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 C0 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A D0 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC E0 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 FD

0 1 2 3 4 5 6 7 8 9 A B C D E F # HDMI 2(C/S : A0 07) - HDMI UHD Deep On Case
90 22 15 01 5D 5E 5F 62 63 64 29 3D 06 C0 15 07 50 0 1 2 3 4 5 6 7 8 9 A B C D E F
A0 09 57 07 7C 03 0C 00 30 00 B8 3C 20 C0 8E 01 02 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
B0 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
C0 E5 0E 60 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
D0 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
E0 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D4 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
* Checksum (HDMI 1/2/3)
HDMI Deep Color On HDMI Deep Color Off
Input
FFh (Checksum) FFh (Checksum)
HDMI1 A0 9E E6 F4
HDMI2 A0 8E E6 E4
HDMI3 E6 D4 E6 D4
EDID Block 1, Bytes 128-255 [80H-FFH] 3) PCM
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 26 15 07 0 1 2 3 4 5 6 7 8 9 A B C D E F
A0 50 09 57 07 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
B0 02 03 04 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
C0 10 67 D8 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
D0 C0 18 66 21 50 B0 51 00 1B 30 40 70 36 00 40 84 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
E0 63 00 00 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
F0 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 97 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
# HDMI 2(C/S : E6 ED) - HDMI UHD Deep off Case
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 80 02 03 4F F1 58 10 9F 04 13 05 14 03 02 12 20 21
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 23 09 57
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 A0 07 7C 03 0C 00 10 00 B8 3C 20 C0 8E 01 02 03 04
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C B0 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 67 D8
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 C0 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 C0 18 66
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A D0 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 00 00
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC E0 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 F0 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 00 19

0 1 2 3 4 5 6 7 8 9 A B C D E F # HDMI 1(C/S : E6 6F) - HDMI UHD Deep off case
90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07 0 1 2 3 4 5 6 7 8 9 A B C D E F
A0 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 02 03 04 01 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
B0 4F 3F FC 08 10 18 10 06 10 16 10 28 10 E5 0E 60 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
C0 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
D0 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
E0 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ED 50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
# HDMI 3(C/S : E6 DD) - HDMI UHD Deep off Case
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 7C 03 0C
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 A0 00 10 00 B8 3C 20 C0 8E 01 02 03 04 01 4F 3F FC
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C B0 08 10 18 10 06 10 16 10 28 10 E5 0E 60 61 65 66
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 C0 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A D0 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC E0 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 00
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6F
EDID Block 1, Bytes 128-255 [80H-FFH

90 22 15 01 5D 5E 5F 62 63 64 26 15 07 50 09 57 07 0 1 2 3 4 5 6 7 8 9 A B C D E F
A0 7C 03 0C 00 30 00 B8 3C 20 C0 8E 01 02 03 04 01 00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
B0 4F 3F FC 08 10 18 10 06 10 16 10 28 10 E5 0E 60 10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
C0 61 65 66 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
D0 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 30 01 01 01 01 01 01 08 E8 00 30 F2 70 5A 80 B0 58
E0 00 40 84 63 00 00 1E 00 00 00 00 00 00 00 00 00 40 8A 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D 40
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DD 50 58 2C 45 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 88 3C 00 0A 20 20 20 20 20 20 00 00 00 FC
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 A0
Input
HDMI1 A0 A7 E6 FD
HDMI2 A0 97 E6 ED
HDMI3 E6 DD E6 DD
EDID Block 1, Bytes 128-255 [80H-FFH] 4.2. White Balance Adjustment
0 1 2 3 4 5 6 7 8 9 A B C D E F
4.2.1. Overview
80 02 03 4F F1 58 10 9F 04 13 05 14 03 02 12 20 21
▪ W/B adj. Objective & How-it-works
90 22 15 01 60 61 5D 5E 5F 65 66 62 63 64 23 09 57
(1) Objective: To reduce each Panel's W/B deviation
A0 07 7C 03 0C 00 20 00 B8 3C 20 C0 8E 01 02 03 04
B0 01 4F 3F FC 08 10 18 10 06 10 16 10 28 10 67 D8
(2) How-it-works : When R/G/B gain in the OSD is at 192, it
C0 5D C4 01 78 80 03 E3 05 C0 00 E4 0F 00 C0 18 66 means the panel is at its Full Dynamic Range. In order to
D0 21 50 B0 51 00 1B 30 40 70 36 00 40 84 63 00 00 prevent saturation of Full Dynamic range and data, one
E0 1E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 63 of R/G/B is fixed at 192, and the other two is lowered to
F0 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 00 09 find the desired value.
(3) Adjustment condition : normal temperature
1) Surrounding Temperature : 25 °C ± 5 °C
# HDMI 2(C/S : E6 5F) - HDMI UHD Deep off case
2) Warm-up time: About 5 Min
3) Surrounding Humidity : 20 % ~ 80 %
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
4.2.2. Equipment
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 (1) Color Analyzer: CA-210 (LED Module : CH 14)
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C (2) Adjustment Computer(During auto adj., RS-232C protocol
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 is needed)
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A (3) Adjustment Remote control
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC (4) Video Signal Generator MSPG-925F 720p/216-Gray
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6 (Model: 204, Pattern: 49)
EDID Block 1, Bytes 128-255 [80H-FFH] → Only when internal pattern is not available
• Color Analyzer Matrix should be calibrated using CS-100.
0 1 2 3 4 5 6 7 8 9 A B C D E F
80 02 03 40 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 7C 03 0C 4.2.3. Equipment connection MAP
A0 00 20 00 B8 3C 20 C0 8E 01 02 03 04 01 4F 3F FC
B0 08 10 18 10 06 10 16 10 28 10 E5 0E 60 61 65 66 Co lo r Analyzer
C0 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00 Probe RS -232C
D0 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84 Co m p ut er
E0 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 00 RS -232C
RS -232C
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5F
Pat t ern Generat o r
Signal Source
# HDMI 3(C/S : E6 4F) - HDMI UHD Deep off case * If TV internal pattern is used, not needed
0 1 2 3 4 5 6 7 8 9 A B C D E F
00 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01 4.2.4. Adj. Command (Protocol)
10 01 19 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 <Command Format>
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80 START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS STOP
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30 - LEN: Number of Data Byte to be sent
50 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A - CMD: Command
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC - VAL: FOS Data value
70 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E6
- CS: Checksum of sent data
EDID Block 1, Bytes 128-255 [80H-FFH] - A: Acknowledge
0 1 2 3 4 5 6 7 8 9 A B C D E F Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]
80 02 03 40 F1 54 10 9F 04 13 05 14 03 02 12 20 21
90 22 15 01 5D 5E 5F 62 63 64 23 09 57 07 7C 03 0C
A0 00 30 00 B8 3C 20 C0 8E 01 02 03 04 01 4F 3F FC
B0 08 10 18 10 06 10 16 10 28 10 E5 0E 60 61 65 66
C0 01 1D 80 18 71 1C 16 20 58 2C 25 00 40 84 63 00
D0 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00 40 84
E0 63 00 00 1E 00 00 00 00 00 00 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4F

Input
HDMI1 A0 19 E6 6F
HDMI2 A0 09 E6 5F
HDMI3 E6 4F E6 4F
▪ RS-232C Command used during auto-adjustment. 4.2.5. Adj. method
RS-232C COMMAND
Explanation
(1) Auto adj. method
[CMD ID DATA] 1) Set TV in adj. mode using POWER ON key.
wb 00 00 Begin White Balance adjustment 2) Zero calibrate probe then place it on the center of the
wb 00 10 Gain adjustment(internal white pattern) Display.
wb 00 1f Gain adjustment completed 3) Connect Cable.(RS-232C to USB)
wb 00 20 Offset adjustment(internal white pattern) 4) Select mode in adj. Program and begin adj.
wb 00 2f Offset adjustment completed 5) When adj. is complete (OK Sign), check adj. status pre
End White Balance adjustment
mode. (Warm, Medium, Cool)
wb 00 ff 6) Remove probe and RS-232C cable to complete adj.
(internal pattern disappears)
Ex) wb 00 00 → Begin white balance auto-adj. ▪ W/B Adj. must begin as start command “wb 00 00” , and
wb 00 10 → Gain adj. finish as end command “wb 00 ff”, and Adj. offset if need.
ja 00 ff → Adj. data
jb 00 c0 (2) Manual adjustment. method
... 1) Set TV in Adj. mode using POWER ON.
... 2) Zero Calibrate the probe of Color Analyzer, then place it
wb 00 1f → Gain adj. completed on the center of LCD module within 10 cm of the surface.
*(wb 00 20(Start), wb 00 2f(end)) → Off-set adj. 3) Press ADJ key → EZ adjust using adj. R/C → 7. White-
wb 00 ff → End white balance auto-adj. Balance then press the cursor to the right(key ►).
(When right key(►) is pressed 216 Gray internal pattern
▪ Adj. Map will be displayed)
Command Data Range 4) One of R Gain / G Gain / B Gain should be fixed at 192,
(lower case ASCII) (Hex.) Default
Adj. item
(Decimal) and the rest will be lowered to meet the desired value.
CMD1 CMD2 MIN MAX 5) Adjustment is performed in COOL, MEDIUM, WARM 3
R Gain j g 00 C0 modes of color temperature.
G Gain j h 00 C0
B Gain j i 00 C0 ** G-fix adjustment
Cool
R Cut Adjust modes (Cool), Fix the G gain to 172 (default data)
G Cut and change the others (G/B Gain).
B Cut Adjust two modes(Medium / Warm), Fix the one of R/G/B
R Gain j a 00 C0 gain to 192(default data) and decrease the others.
G Gain j b 00 C0 ▪ If internal pattern is not available, use RF input. In EZ Adj.
B Gain j c 00 C0 menu 7.White Balance, you can select one of 2 Test-
Medium pattern: ON, OFF. Default is inner(ON). By selecting OFF,
R Cut
you can adjust using RF signal in 216 Gray pattern.
G Cut
B Cut
▪ Adjustment condition and cautionary items
R Gain j d 00 C0
1) Lighting condition in surrounding area
G Gain j e 00 C0
Surrounding lighting should be lower 10 lux. Try to
Warm B Gain j f 00 C0
isolate adj. area into dark surrounding.
R Cut 2) Probe location
G Cut : Color Analyzer(CA-210) probe should be within 10 cm
and perpendicular of the module surface (80° ~ 100°)
3) Aging time
- After Aging Start, Keep the Power ON status during 5
Minutes.
- In case of LCD, Back-light on should be checked
using no signal or Full-white pattern.
4.2.6. Reference (White balance Adj. coordinate and 4.3. Local Dimming Function Check
color temperature) (1) Turn on TV.
▪ Luminance : 206 Gray (2) A t the Local Dimming mode, module Edge Backlight
▪ Standard color coordinate and temperature using CS-1000 moving right to left Back light of IOP module moving.
(over 26 inch) (3) Confirm the Local Dimming mode.
Coordinate (4) Press “exit” Key.
Mode Temp ∆uv
x y
Cool 0.271 0.270 13000 K 0.0000
Medium 0.286 0.289 9300 K 0.0000
Warm 0.313 0.329 6500 K 0.0000
▪ Standard color coordinate and temperature using CA-210(CH 14)

Coordinate
Mode Temp ∆uv
x y 4.4. Magic Motion Remote control test
Cool 0.271 ± 0.002 0.270 ± 0.002 13000 K 0.0000 - E quipment : RF Remote control for test, IR-KEY-Code
Remote control for test
Medium 0.286 ± 0.003 0.289 ± 0.003 9300 K 0.0000 - You must confirm the battery power of RF-Remote control
Warm 0.313 ± 0.002 0.329 ± 0.002 6500 K 0.0000 before test(recommend that change the battery per every lot)
- Sequence (test)
1) If you select the ‘start key(OK)’ on the Adjustment remote
4.2.7. LED White balance table control, you can pairing with the TV SET.
▪ Edge & ALEF LED module change color coordinate because 2) You can check the cursor on the TV Screen, when select
of aging time. the "OK" key on the Adjustment remote control.
▪ Apply under the color coordinate table, for compensated 3) You must remove the pairing with the TV Set by select
aging time. ‘Mute + OK Key’ on the Adjustment remote control.
▪ (Normal line) White balance table
Model : (normal line)
Cool Medium Warm
4.5. 3D function test
Aging (Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4])
time x y x y x y * HDMI mode NO. 872 , pattern No.83
(Min) 271 270 286 289 313 329 (1) Please input 3D test pattern like below.
1 0-2 285 296 300 315 327 355
2 3-5 284 294 299 313 326 353
3 6-9 283 293 298 312 325 352
4 10-19 283 292 298 311 325 351
5 20-35 281 288 296 307 323 347
6 36-49 279 286 294 305 321 345
7 50-79 278 284 293 303 320 343
8 80-119 277 282 292 301 319 341 (2) When 3D OSD appear automatically, then select green key.
9 Over 120 271 270 286 289 313 329
▪ AUO, INX, Sharp, CSOT, BOE (Cool :13000 K)

Cool Medium Warm
x y x y x y
271 270 285 293 313 329
Target 278 280 293 299 320 339
(3) Don't wear a 3D Glasses, Check the picture like below.
4.6. Option selection per country 5. GND and Internal Pressure check
4.6.1. Overview 5.1. Method
- Option selection is only done for models in AJ/JA/IL (1) GND & Internal Pressure auto-check preparation
- Check that Power Cord is fully inserted to the SET. (If
4.6.2.Method loose, re-insert)
(1) Press "ADJ" key on the Adjustment remote control, then (2) Perform GND & Internal Pressure auto-check
select Country Group Menu. - Unit fully inserted Power cord, Antenna cable and A/V
(2) Depending on destination, select Country Group Code or arrive to the auto-check process.
Country Group then on the lower Country option, select - Connect D-terminal to AV JACK TESTER
US, CA, MX. Selection is done using +, - or ►◄ KEY. - Auto CONTROLLER(GWS103-4) ON
- Perform GND TEST
4.7. HDMI ARC Function Inspection - If NG, Buzzer will sound to inform the operator.
(1) Test equipment - If OK, changeover to I/P check automatically.
- Optic Receiver Speaker (Remove CORD, A/V form AV JACK BOX.)
- MSHG-600 (SW: 1220 ↑) - Perform I/P test
- HDMI Cable (for 1.4 version) - If NG, Buzzer will sound to inform the operator.
- If OK, Good lamp will lit up and the stopper will allow the
(2) Test method pallet to move on to next process.
1) Insert the HDMI Cable to the HDMI ARC port from the
master equipment. (HDMI 2)
5.2. Checkpoint
▪ TEST voltage
- GND: 1.5 KV / min at 100 mA
- SIGNAL: 3 KV / min at 100 mA
▪ TEST time: 1 second
▪ TEST POINT
- GND TEST = POWER CORD GND & SIGNAL CABLE
METAL GND
- Internal Pressure TEST = POWER CORD GND & LIVE &
NEUTRAL
▪ LEAKAGE CURRENT: At 0.5 mArms
6. Audio
No. Item Min Typ Max Unit
Audio practical max 10 12 W EQ Off
1 Output, L/R (Distortion AVL Off
= 10 % max Output) 8.10 10.8 Vrms Clear Voice Off
2) Check the sound from the TV Set. EQ On
Speaker
2 10 12 W AVL On
(6 Ω Impedance)
Clear Voice On
Measurement condition:
(1) RF input: Mono, 1 KHz sine wave signal, 100 % Modulation
(2) CVBS, Component: 1 KHz sine wave signal 0.5 Vrms
3) Check the Sound from the Speaker or using AV & Optic

TEST program (It’s connected to MSHG-600)
4.8. Ship-out mode check (In-stop)

- After final inspection, press In-Stop key of the Adjustment
remote control and check that the unit goes to Stand-by
mode.
7. USB S/W Download(Service only) 8. Tool Option selection
(1) Put the USB Stick to the USB socket. ▪ Method: Press Adj. key on the Adjustment remote control,
(2) Automatically detecting update file in USB Stick. then select Tool option.
- If your downloaded program version in USB Stick is Model Tool 1 Tool 2 Tool 3 Tool 4 Tool 5 Tool 6 Tool 7 Tool 9
Older, it didn't work. But your downloaded version is 65EG960*-T* 34409 37912 697 64794 18598 2474 44683 512
Newer, USB data is automatically detecting.(Download
Version High & Power only mode, Set is automatically
Download)
(3) Show the message "Copying files from memory".
(4) Updating is starting.

(5) Updating Completed, The TV will restart automatically.
(6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
* If downloading version is more new than your TV have, TV
can lost all channel data. In this case, you have to channel
recover. if all channel data is cleared, you didn't have a
DTV/ATV test on production line.
* After downloading, have to adjust TOOL OPTION again.

1) Push "IN-START" key in service remote control.
2) Select "Tool Option 1" and push "OK" key.
3) Punch in the number. (Each model has their number.)
Copyright ©
1. LM15U
X_TAL DDR3 1866 X 32
24MHz (512MB X 2EA)
CI Slot DDR3 1866 X 32
T2/C/S2 W/O AD (512MB X 2EA)
P_TS
Air/ P_TS B C
A
Cable TUNER DDR3 1866 X 32
R IF (+/-) T/C Demod (256MB X 2EA)
(T2/C/A)

E Analog Demod
A P_TS
DVB-S P_TS EEPROM(NVRA
R TUNER DEMOD I2C 1 M)
(S2) (S2) CVBS (256Kb)
LNB Chip Config

4b’1010
LG Electronics. Inc. All rights reserved.

B-CAS SMARTCARD_I/F eMMC
(JAPAN) B-CAS (4GB)
USB1 (3.0) OCP Vx1 51P

USB Mstar I2C 6
USB2 (2.0) LM15U
USB3 (2.0) OCP
- 23 -
I2S Out MAIN Audio AMP
HDMI3 I2C 4 (NTP7514)
HDMI
HDMI2(ARC)
HDMI1 USB_WIFI WIFI/BT Combo
BLOCK DIAGRAM
SUB
H/P ASSY
AV/COMP CVBS/YPbPr IR / KEY
LOGO LIGHT(Ready
SCART
CVBS/RGB
(IN/OUT)
SPDIF OUT Sub Micom

OPTIC
(RENESAS
I2C 3 R5F100GEAFB)
LAN ETHERNET (HW Port)
X_TAL
32.768KHz
LGE Internal Use Only

Copyright ©
X_TAL DDR3 1866 X 32
24MHz (512MB X 2EA)
CI Slot DDR3 1866 X 32
T2/C/S2 W/O AD (512MB X 2EA)
P_TS
Air/ P_TS B C
A
Cable TUNER DDR3 1866 X 32

R IF (+/-) T/C Demod (256MB X 2EA)
1-1. LM15U(+ URSA9)
E (T2/C/A)
Analog Demod
A P_TS
DVB-S P_TS EEPROM(NVRA
R TUNER DEMOD I2C 1 M)
(S2) (S2) CVBS (256Kb)
LNB Chip Config

4b’1010
B-CAS SMARTCARD_I/F eMMC
(JAPAN) B-CAS (4GB)
USB1 (3.0) OCP Vx1

USB Mstar URSA
USB2 (2.0) 51P/41P
- 24 -
LM15U 9
USB3 (2.0) OCP
DDR3 1866 X 32
HDMI3 (1Gb X 4EA)
HDMI
HDMI2 (ARC)
HDMI1 I2S Out MAIN Audio AMP
I2C 4 (NTP7515)
RS232C
H/P USB_WIFI WIFI/BT Combo
SUB
AV/COMP CVBS/YPbPr ASSY
SCART IR / KEY
CVBS/RGB
(IN/OUT) LOGO LIGHT(Ready)
OPTIC SPDIF OUT

Sub Micom
I2C 3 X_TAL
LAN ETHERNET (RENESAS
(HW Port) 32.768KH
R5F100GEAFB)
z

2. Internal
Copyright ©
+3. 3V_NORMAL
MSTAR
1.8KΩ LM15U
I2C_SDA4
IC5600 100Ω +3.3V_TU
I2C_SCL4

NTP7515(Main AMP)
33Ω IC6900
3. LM15U (+ URSA9) I2C
+3.3V_NORMAL 1.8KΩ LNB
I2C_SDA2(HW) TU6704
1.8KΩ 33Ω
TUNER

I2C_SCL2(HW)
IC3000 I2C_SCL3 (HW) +3.3V_NORMAL
RENESAS 33Ω
I2C_SDA3 (HW)
MICOM
1.8KΩ
+3.3V_NORMAL
- 26 -
I2C_SDA1(HW) IC102
33Ω
1.8KΩ I2C_SCL1(HW) NVRAM
+3.3V_LNA_TU
P7201 I2C_SDA6
0Ω
LCD Panel
I2C_SCL6
1.8KΩ
+3.3V_NORMAL
I2C_SDA5(HW) TU6704
+URSA model Only 33Ω
1.8KΩ I2C_SCL5(HW) TUNER
I2C_SDA7 (HW)
IC2500
URSA9 33Ω I2C_SCL7 (HW)

Copyright ©
4. URSA9
Power +12V
I2C_SCL6
I2C_SDA6
I2C_SCL7 V x1 V x1
URSA9 PQ
HTPDn_IN
LOCKn_IN
PANEL_VCC
(+12V)
URSA I2C_SDA7 8 lane 8 lane
DC- DC Converter +1.5V_U_DDR UART2_RX DEBUG
Data_Format_0
Data_Format_1
UART I2CS_SCL
(BD9D320EFJ _3A) Switch
(URSA DDR) UART2_TX
I2CS_SDA 51P 41P

URSA9 SYS
DC- DC Converter +1.15V
IRE SCL2_+3.3V_DB
(TPS53513RVER _8A) I2C_S Port
(URSA) UART
SDA2_+3.3V_DB 4 Pin
UART1_TX
Jig Download
X-Tal
(24Mhz)

XO_URSA
XIN_URSA
LOCKn
HTPDn
Data_Format_1
Vx1 VIDEO 8Lane
- 27 -
Data_Format_2
3D_EN
Vx1 OSD 4Lane L_DIM_EN
SPI_DI SPI FLASH
LM15U LOCKAn_OSD / LOCKAN_Video URSA9 SPI_DO/CK/CS (4MB)
IRE
UART1_TX
UART2_RX
UART2_TX
URSA9_CONNECT I2CS_SCL
I2CS_SDA
A_DDR3_DQ[31:0]
B_DDR3_DQ[31:0]
A_DDR3_A[15:0]/
BA[2:0]/CLK/CKE
B_DDR3_A[15:0]/
BA[2:0]/CLK/CKE
T-CON POWER
5 Pin DDR3 SDRAM DDR3 SDRAM
PANEL_VCC DDR3 SDRAM DDR3 SDRAM

- 1Gbit (x16) - 1Gbit (x16)
- 1866 - 1866

Copyright ©
DCDC LDO
MICOM
LM15U
3.5V IR Ass’y
3.3V

IC201 LM15U URSA9
AVDD
1.5V
3.3V NORMAL / 5A IC402 DDR_VTT
IC2302 DDR_VTT
5. LM15U (+ URSA9) Power
LM15U 1.5V
1.5V DDR / 3A IC407 DDR_VTT
IC2303 DDR3*6EA DDR_VTT

1.1V Core / 10A 1.8V eMMC
IC2501
LM15U
1A eMMC
12V IC2301
1.1V CPU Core / 6A
IC2300
LM15U
D.Demod_
Core 2A
- 28 -
1.15V URSA Core / 10A Tuner
URSA9 IC6500
IC13408
1.5V
URSA9 IC13100 URSA
1.5V_U_DDR / 3A URSA DDR_VTT DDR_VTT
IC13403 DDR3*4EA
H/P AMP
LNB LNB option NTP7515
CI SLOT WIFI
PANEL VCC Combo
NVRAM
5V NORMAL / 6A
IC2305 USB1
24V
USB2/3
NTP7514

Copyright ©
TDJM-G305D +3.3V_NORMAL
+2.5V_NORMAL
6. TUNER/CI
[+3.3V_LNA_TU] 1
[+3.3V_TUNER] 11
[3.3V_Demod_TU] 26
[+2.5V_DEMOD] 38 +3.3V_NORMAL
+1.1V_Demod_Core
[1,1V_D_Demod_Core] 28 1.8KΩ CI Slot
LNB_TX

10 [TONECTRL]
[LNB_TX] 29 LNB PCM_5V_CTL CI 5V +5V_CI_ON
LNB_OUT 2 [LNB] VCC
[LNB_OUT] 31 IC6900 Power detect
7 [SCL]
[I2C_SCL2_TU] 27 I2C_SCL2 A8303SESTR-TB
33Ω 8 [SDA]
[I2C_SDA2_TU] 30 I2C_SDA2
+5V_CI_ON
F5[SCK2]
LM15U
33 Ω
F6 [SDA2] AE3[GPIO_PM4] CAM_CD1_N 10K Ω
/CI_CD1 CI_CD1
[I2C_SCL5_TU] 4 I2C_SCL5 OR

33 Ω F10[SCK5] AR17[PCMCD] /CI_CD2
[I2C_SDA5_TU] 5 I2C_SDA5 G10[SDA5] GATE CI_CD2
AP13[TS2CLK] CI_MISTRT
FE_DEMOD1_TS_ERROR AP12[TS2VALID] CI_MIVA_ERR
[FE_DEMOD1_TS_ERROR_TU] 12 AM13[TS2SYNC] /PCM_CE1 CI_MCLKI
FE_DEMOD1_TS_CLK AM13[PCMCEN]
[FE_DEMOD1_1_TS_CLK] 14 PCM_CE1
FE_DEMOD1_TS_SYNC AN11[TS0CLK]
[FE_DEMOD1_TS_SYNC] 15 AP9(TS0SYNC]
FE_DEMOD1_TS_VAL
[FE_DEMOD1_TS_VAL] 16 AN9[TS0VALID] EB_BE_NO
AT15[PCMIOWR] CI_IOWR
AR15PCMIORD]
EB_BE_N1
CI_IORD
- 29 -
FE_DEMOD1_TS_DATA[0] 17
FE_DEMOD1_TS_DATA[2] 19 EB_ADDR[0-14] CI_ADDR[0-14]
FE_DEMOD1_TS_DATA[3] 20 AU10-AR19 CI_ADDR[0-14]
FE_DEMOD1_TS_DATA [0- AP10~AM9
FE_DEMOD1_TS_DATA[4] 21 [TS0DATA[0-7] EB_DATA[0-7] CI_DATA[0-7]
7] EB_DATA[0-7]
FE_DEMOD1_TS_DATA[5] 22 AT13-AT18
FE_DEMOD1_TS_DATA[7] 24 AU11[PCMRST]
PCM_RESET
PCM_RESET
AT10[PCMWAIT] CAM_WAIT_N CAM_WAIT_N
CAM_REG_N
REG
AR14[PCMREG]
CAM_IREQ_N CAM_IREQ_N
AU20[PCMIRQA]
/EB_OE_N
AT21[PCMOEN] CI_OE
RF_SWITCH_CTL /EB_WE_N
A15 [GPIO159] AR11[[PCMWEN] CI_WE
[RF_SWITCH_CTL] 2 /TU_RESET1
A12 [GPIO62] TPI_CLK CI_TS_CLK
[/TU_RESET1_TU] 25 AN17[TS1CLK] TS_OUT_CLK
TPI_VAL CI_TS_VAL
AM17[TS1VALID] TS_OUT_VAL
IF_P ADC_I_INP TPI_SOP CI_TS_SYNC
AP1 [VIFP] AN16[TS1SYNC] TS_OUT_SYNC
[IF_P] 6 IF_N FILTER
ADC_I_INN
AP2 [VIFM] TPI_DATA[0-7]
[IF_N] 7 AN16~AP19 TPI_DATA[0-7]
TUNER_SIF 33Ω TS_OUT[0-7]
AN2[SIFP] [TPI_DATA[0-7]]
[TU_SIF_TU] 8
TU_CVBS AM14~AM15 FE_DEMOD1_TS_DATA [0_7]
- CI_MDI[0-7]
[TU_CVBS_TU] 9 AE5[CVBS0] 33Ω TS_IN[0-7]
IF_AGC [TPO_DATA[0-7]]
[IF_AGC_TU] 3 AP3[IF_AGC]

Copyright ©
Jack Side SoC
Side
JK3802
COMP1_Y COMP1_Y
[GIN1P]
COMP1_Pb COMP1_Pb
[BIN1P]
COMP1_Pr COMP1_Pr
7. VIDEO / AUDIO IN

[RIN1P]
AV1_CVBS_IN AV1_CVBS_IN
[CVBS1]
COMP1/AV1/DVI_L_IN COMP1/AV1/DVI_L_IN
[LINE_IN_0L]
COMP1/AV1/DVI_R_IN COMP1/AV1/DVI_R_IN
[LINE_IN_0R]

SCART
SC_CVBS_IN SC_CVBS_IN LM15U
[CVBS2]
- 30 -
SC_FB/ID SC_FB/ID
[VSYNC0,HSYNC0]
SC_R/G/B SC_R/G/B
[RIN0P,GIN0P,BIN0P]
SC_L/R_IN SC_L/R_IN
[LINE_IN_1L,LINE_IN_1R]
DTV/MNT_V_OUT1 DTV/MNT_V_OUT
[CVBSOUT1]
DTV/MNT_L/R_OUT DTV/MNT_L/R_OUT
[LINE_IN_0L,LINE_IN_0R]
JK4600 DVB EU only
Tuner TU_CVBS_TU TU_CVBS

[CVBS0]
TUNER_SIF, IF_P/N_TU TUNER_SIF, IF_P/N

[SIFP,VIFP/VIFM]
FE_DEMOD1/2_TS_ERROR,CLK,SYNC,VAL FE_DEMOD1/2_TS_ERROR,CLK,SYNC,VAL
[TS0CLK,TS0SYNC,TS0VALID]

Copyright ©
COMP1/AV1/DVI_L_IN SCART
8. AUDIO OUT
COMP1/AV1/DVI_R_IN
[LINE_OUT_2L] SCART_L/Rout IC6000 DTV/MNT_L/R_OUT

JK3802 [LINE_OUT_2R] AZ4580MTR LPF
[LINE_IN_0L] OP AMP

[LINE_IN_0R]
SCART Mute CTRL
(TR)
JK4600
DVB EU only
SC_L_IN / SC_R_IN
SCART_MUTE

[LINE_IN_1L] AUD_LRCK
[I2S_OUT_WS]
JK4600 DVB EU only [LINE_IN_1R]
[I2S_OUT_SD]
AUD_LRCH
AUD_SCK
4P WAFER
[I2S_OUT_BCK]
IC1200
LPF SPEAKER_L
I2C_SDA4
Audio AMP
[DDCDC_DA/GPIO47]
NTP7515 LPF SPEAKER_R
[DDCDC_CK/GPIO46] I2C_SCL4
- 31 -
[GPIO160] AMP_RESET_N
LM15U AMP_MUTE
Tuner
TUNER_SIF [SIFP]
TR BUF
IC3000
MICOM
SIDE_HP_MUTE
SPDIF_OUT
HEAD PHONE
[SPDIF_OUT]
[EARPHONE_OUT_L] HP_LOUT / HP_ROUT
[ EARPHONE_OUT_R] LPF
JK3401 JK3403

Copyright ©
9. HDMI
DDC_SCL_1
DDC_SDA_1
TMDS Link 8bits
HDMI1

DDC_SCL_2
DDC_SDA_2

LM15U TMDS Link 8bits
HDMI_ARC
HDMI& ARC
- 32 -
CEC_REMOTE
DDC_SCL_3
DDC_SDA_3
TMDS Link 8bits
MHL_DET_LM15
HDMI3
X- Tal(X3000) RENESAS
32.768kHz MICOM(IC3000) Q3001
* TMDS Link 8bits = TMDS DATA 6bits(DATA0,1,2)+ TMDS CLK 2bits HDMI_CEC_MICOM

Copyright ©
USB_DM1 USB3
[USB_DM] +5V_USB_1
[USB_DP] USB_DP1
[GPIO162] /USB_OCD1
[GPIO163]
USB_CTL1
6A
USB_DM2 USB2

+5V_USB_2 DCDC USB2.0
[USB2_DM]
[USB2_DP] USB_DP2
IC2305
[GPIO50]
/USB_OCD2
[GPIO51] USB_CTL2

USB_DM3
[USB0_DM] USB1
USB_DP3
10. USB/ WIFI/ M-REMOTE/ UART
[USB0_DP] +5V_USB_3
LM15U
SSUSB_RXP/SSUSB_RXN
[USB_SSRX]
[USB_SSTX] SSUSB_TXP/SSUSB_TXN OCP
USB3.0
IC4500
- 33 -
/USB_OCD3
[GPIO14]
[GPIO18] USB_CTL3
WIFI_DM
[USB1_DM]
[USB1_DP]
WIFI_DP
WIFI Combo
M_RFModule_RESET
[GPIO57]
SOC_TX
[TX1]
SOC_RX
[RX1] RS232C_Debug(4P wafer)
RENESAS MICOM(IC3000)

EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
710
401
400
811
570
500
120
521
522
LV2
540
900
LV1
811
531
810
530
121
AG1
200
Stand screw
A10
A22
820
IC102-*1
BR24G256FJ-3
+3.3V_NORMAL
NVRAM +3.3V_NORMAL A0
1 8
VCC
CHIP CONFIG
A1 WP
2 7
A2 SCL
3 6
Atmel_NVRAM
4.7K
4.7K
4.7K
4.7K
GND SDA
IC102 4 5
AT24C256C-SSHL-T C103
OPT
Rohm_NVRAM
OPT
EAN61133501 0.1uF
Write Protection
R157
R161
IC100
R163
R165
IC100
A0
1 8
VCC
- Low : Normal Operation
- High : Write Protection LGE5331(LM15U) V-BY-ONE LGE5331(LM15U)
A1 WP LED1
2 7 EB_DATA[0-7]
AR100 SPI_DI_SOC
33 A16 AB36 TXVBY1_0N TPO_DATA[0-7]
LED0 PWM_DIM EB_DATA[0] AT13 AL6 TPO_DATA[0]
A2
3 A0’h 6
SCL
I2C_SCL1 C15
PWM0/GPIO157 LVSYNC/VBY0M
AB35 PCMDATA[0]/GPIO152 TS1DATA_[0]/GPIO187
PWM_DIM2 TXVBY1_0P EB_DATA[1] AT9 AM6 TPO_DATA[1]
PWM_PM PWM1/GPIO158 LHSYNC/VBY0P
4.7K
4.7K
4.7K
A15 AC36 PCMDATA[1]/GPIO153 TS1DATA_[1]/GPIO186
4.7K
I2C_SDA1 On_RF_Done TXVBY1_1N EB_DATA[2] AR13 AP8 TPO_DATA[2]
GND SDA PWM2/GPIO159 LDE/VBY1M
4 5 B15 AC37 TXVBY1_1P PCMDATA[2]/GPIO154 TS1DATA_[2]/GPIO185
AMP_RESET_N EB_DATA[3] AT17 AN7 TPO_DATA[3]
OPT
OPT
PWM3/GPIO160 LCK/VBY1P
C14 PCMDATA[3]/GPIO124 TS1DATA_[3]/GPIO184
M_RFModule_RESET PWM4/GPIO161 EB_DATA[4] AR16 AM5 TPO_DATA[4]
R158
E4 AD37 PCMDATA[4]/GPIO125 TS1DATA_[4]/GPIO183
R162
R164
R166
PWM_PM TXVBY1_2N EB_DATA[5] AT16 AM7 TPO_DATA[5]
PWM_PM/GPIO10 B0M/VBY2M
AD36 TXVBY1_2P PCMDATA[5]/GPIO126 TS1DATA_[5]/GPIO182
B0P/VBY2P EB_DATA[6] AR21 AN5 TPO_DATA[6]
H6 AD35 TXVBY1_3N PCMDATA[6]/GPIO127 TS1DATA_[6]/GPIO181
/USB_OCD2 SAR0/GPIO50 B1M/VBY3M EB_DATA[7] AT18 AN6 TPO_DATA[7]
J6 AE36 EB_ADDR[0-14] PCMDATA[7]/GPIO128 TS1DATA_[7]/GPIO180
SPI_CK_SOC TXVBY1_3P
LOCKAn_OSD
LM15U+URSA9 USB_CTL2 SAR1/GPIO51 B1P/VBY3P
TS1CLK/GPIO177
AL7
TPO_CLK
SPI_DI_SOC G5 AF36 TXVBY1_4N EB_ADDR[0]
SAR2/GPIO52 B2M/VBY4M AU10 AP5
URSA9_CONNECT J5 AF37 PCMADR[0]/GPIO151 TS1VALID/GPIO179 TPO_VAL
SPI_DO_SOC TXVBY1_4P EB_ADDR[1] AT14 AP6
SAR3/GPIO53 B2P/VBY4P
/SPI_CS L/D_VSYNC_SOC OLED_FW_Update D1 AF35 TXVBY1_5N EB_ADDR[2] PCMADR[1]/GPIO150 TS1SYNC/GPIO178 TPO_SOP
CHIP_CONFIG[3:0] SAR5 BCKM/VBY5M AR10
L/D_CLK_SOC AG37 PCMADR[2]/GPIO148 FE_DEMOD1_TS_DATA[0-7]
FRC_FLASH_SEL {LED1, SPI_DI,LED0, PWM_PM} TXVBY1_5P EB_ADDR[3] AT19 AP10 FE_DEMOD1_TS_DATA[0]
L/D_DI_SOC BCKP/VBY5P
D2 AG35 TXVBY1_6N EB_ADDR[4] PCMADR[3]/GPIO147 TS0DATA_[0]/GPIO166
FRC_FLASH_WP Value Mode Description SPI_CK_SOC SPI_CK/GPIO1 B3M/VBY6M AR18 AN10 FE_DEMOD1_TS_DATA[1]
URSA_RESET_SoC D3 AH36 PCMADR[4]/GPIO146 TS0DATA_[1]/GPIO167
4’b1000 SB51_ExtSPI 51 boot from SPI SPI_DI_SOC TXVBY1_6P EB_ADDR[5] AU19 AM8 FE_DEMOD1_TS_DATA[2]
TXOSD_3P SPI_DI/GPIO2 B3P/VBY6P
4’b1001 HEMCU_ExtSPI ARM boot from SPI E2 AH35 TXVBY1_7N EB_ADDR[6] PCMADR[5]/GPIO144 TS0DATA_[2]/GPIO168
TXOSD_3N 4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC SPI_DO_SOC SPI_DO/GPIO3 B4M/VBY7M AT11 AM10 FE_DEMOD1_TS_DATA[3]
R168 F1 AJ36 TXVBY1_7P EB_ADDR[7] PCMADR[6]/GPIO143 TS0DATA_[3]/GPIO169
TXOSD_2P 4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND SPI_CZ0/GPIO0 B4M/VBY7P AT12 AM11 FE_DEMOD1_TS_DATA[4]
0 E3 EB_ADDR[8] PCMADR[7]/GPIO142 TS0DATA_[4]/GPIO170
TXOSD_2N 4’b1100 DBUS for test only /SPI_CS AT20 AM12 FE_DEMOD1_TS_DATA[5]
SPI_CZ1/GPIO_PM6/GPIO19
4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication F2 AJ35 TXOSD_0N EB_ADDR[9] PCMADR[8]/GPIO136 TS0DATA_[5]/GPIO171
TXOSD_1P 4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication OPT SPI_CZ2/GPIO_PM10/GPIO23 A0M/VBY_OSD_0M AU14 AN8 FE_DEMOD1_TS_DATA[6]
AK37 TXOSD_0P EB_ADDR[10] PCMADR[9]/GPIO134 TS0DATA_[6]/GPIO172
TXOSD_1N 4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication; A0P/VBY_OSD_0P AU16 AM9 FE_DEMOD1_TS_DATA[7]
AK36 TXOSD_1N C EB_ADDR[11] PCMADR[10]/GPIO130 TS0DATA_[7]/GPIO173
TXOSD_0P A1M/VBY_OSD_1M NXP_VBY1_LOCK_LED_TR AR20 AN11
N5 AK35 TXOSD_1P B Q100-*1 EB_ADDR[12] PCMADR[11]/GPIO132 TS0CLK/GPIO176 FE_DEMOD1_TS_CLK
TXOSD_0N DDCA_CK DDCA_CK/UART0_RX/GPIO11 A1P/VBY_OSD_1P AR12 AN9
P5 AL35 MMBT3906(NXP) EB_ADDR[13] PCMADR[12]/GPIO141 TS0VALID/GPIO174 FE_DEMOD1_TS_VAL
+3.3V_NORMAL DDCA_DA TXOSD_2N AU13 AP9
DDCA_DA/UART0_TX/GPIO12 A2M/VBY_OSD_2M
COMPENSATION_DONE OLED LM15U_ONLY AM36 TXOSD_2P EB_ADDR[14] PCMADR[13]/GPIO137 TS0SYNC/GPIO175 FE_DEMOD1_TS_SYNC
DATA_FORMAT_1_SOC OPT A2P/VBY_OSD_2P E AR19
R155 C9 AM37 TXOSD_3N PCMADR[14]/GPIO138
On_RF_Done DATA_FORMAT_0_SOC FRC_FLASH_SEL SOC_TX GPIO67/TX1 ACKM/VBY_OSD_3M AM14
4.7K A10 AM35 TS2DATA_[0]/GPIO200 FE_DEMOD3_TS_DATA
OLED_FW_Update R167 SOC_RX TXOSD_3P AU20 AP15
0 GPIO68/RX1 ACKP/VBY_OSD_3P
E9 AJ33 CAM_IREQ_N PCMIRQA/GPIO140 TS2DATA_[1]/GPIO204
FRC_FLASH_SEL GPIO69/TX2 A3M/LOCKN LOCKAn_Video AT21 AN12
F9 AJ34 EB_OE_N PCMOEN/GPIO131 TS2DATA_[2]/GPIO205
/TU_RESET2 GPIO70/RX2 A3P/HTPDN HTPDAn_Video AR15 AN15
F10 AJ32 EB_BE_N1 PCMIORD/GPIO133 TS2DATA_[3]/GPIO206
GPIO71/TX3 A4M/OSD_LOCKN LOCKAn_OSD AU17 AN14
G10 AJ31 /PCM_CE1 PCMCEN/GPIO129 TS2DATA_[4]/GPIO207
LM15U HW Option +3.3V_NORMAL
GPIO72/RX3 A4P/OSD_HTPDN HTPDAn_OSD
EB_WE_N
AR11
PCMWEN/GPIO139 TS2DATA_[5]/GPIO208
AM16
HTPDAn_Video_Pull_down
D9
HTPDAn_OSD_Pull_down
R172 R173 AR17 AN13
I2C_SCL6 GPIO76/TX4
R126 M7 10K 10K CAM_CD1_N PCMCD/GPIO156 TS2DATA_[6]/GPIO209
AU11 AM15
19-21/R6C-FR1S1L/3T
I2C_SDA6 GPIO77/RX4
+3.3V_NORMAL 10K P6 +3.3V_NORMAL PCM_RESET PCMRST/GPIO155 TS2DATA_[7]/VSENSE/GPIO210
DDTS_TX AR14 AP13
VBY1_LOCK_LED
OPT GPIO94/TX5 FE_DEMOD3_TS_CLK
FRC_FLASH_WP N6 CAM_REG_N PCMREG/GPIO149 TS2CLK/GPIO203
DDTS_RX GPIO95/RX5 AT15 AP12
R179 EB_BE_N0 PCMIOWR/GPIO135 TS2VALID/GPIO201 FE_DEMOD3_TS_VAL
AT10 AM13
LD100
10K CAM_WAIT_N FE_DEMOD3_TS_SYNC
A12 PCMWAIT/GPIO145 TS2SYNC/GPIO202
VBY1_LOCK_LED
U_SPI_WP_f_SoC /TU_RESET1 GPIO62
NON_HDMI_EXT_EDID
A13 TPI_DATA[0-7]
URSA_RESET_SoC GPIO63 D7 AM18
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
NAND_ALE/GPIO194 TPI_DATA[0-7]
BIT2_1
C12 TS3DATA_[0]/GPIO211
BIT0_1
BIT1_1
BIT3_1
BIT4_1
BIT6_1
BIT7_1
BIT8_1
COMPENSATION_DONE GPIO64 F7 AP16 TPI_DATA[0]
3.3K
OPT
OPT
OPT
NAND_WPZ/GPIO193 TS3DATA_[1]/GPIO212
R195
G7 AM19 TPI_DATA[1]
B12 EMMC_CMD NAND_CEZ/EMMC_CMD/GPIO188 TS3DATA_[2]/GPIO213
R108
R110
R112
R116
R118
R120
R122
R124
E6
R181
R185
R183
AN18
R104
R156
R188
BIT0 GPIO65 TPI_DATA[2]

C11 NAND_CLE/GPIO190 TS3DATA_[3]/GPIO214
BIT1 GPIO66 F8 AP19 TPI_DATA[3]
B10 E Q100 EMMC_CLK NAND_REZ/EMMC_CLK/GPIO191 TS3DATA_[4]/GPIO215
HTPDAn_Video E7 AN20
BIT0 BIT2 GPIO73 2N3906S-RTK TPI_DATA[4]
C10 NAND_WEZ/GPIO192 TS3DATA_[5]/GPIO216
BIT3 GPIO74 HTPDAn_OSD E8 AP18 TPI_DATA[5]
BIT1 B11 B EMMC_RST NAND_RBZ/EMMC_RSTN/GPIO195 TS3DATA_[6]/GPIO217
BIT4 KEC_VBY1_LOCK_LED_TR D6 AN19 TPI_DATA[6]
GPIO75
F6 AD5 OPT C NAND_CEZ1/GPIO189 TS3DATA_[7]/GPIO218 TPI_DATA[7]
BIT2 BIT12 GPIO81/TX2 GPIO_PM0/GPIO13 COMP1_DET D8 AN17
F5 AD6 0 R180 EMMC_STRB NAND_DQS/GPIO196 TS3CLK/GPIO221 TPI_CLK
BIT13 GPIO82/RX2 GPIO_PM2/GPIO15 3D_EN AM17
BIT3 AE2 EMMC_DATA[0-7] TS3VALID/GPIO219 TPI_VAL
GPIO_PM3/GPIO16 AV2_CVBS_DET AN16
BIT4 AE3 EMMC_DATA[6] TS3SYNC/GPIO220 TPI_SOP
GPIO_PM4/GPIO17 PCM_5V_CTL R175 A6
AF4 22 EMMC_DATA[7] NAND_AD0/EMMC_D6/GPIO226
GPIO_PM7/GPIO20 TCON_I2C_EN C6
BIT5 K6 AG5 EMMC_DATA[2] NAND_AD1/EMMC_D7/GPIO225
I2C_SCL3 GPIO88/SCK0 GPIO_PM8/GPIO21 5V_DET_HDMI_1 A7
R176
L7 AG6 EMMC_DATA[1] NAND_AD2/EMMC_D2/GPIO224
I2C_SDA3 GPIO89/SDA0 GPIO_PM9/GPIO22 5V_DET_HDMI_2 B7 AP1
1K
BIT6 C16 AH6 NAND_AD3/EMMC_D1/GPIO223 VIFP
EMMC_DATA[0] C7 AP2
I2C_SCL1 DDCR_CK/GPIO59 GPIO_PM13/GPIO26 5V_DET_HDMI_3
B16 AJ5 NAND_AD4/EMMC_D0/GPIO199 VIFM
BIT7 I2C_SDA1 DDCR_DA/GPIO58 GPIO_PM17/GPIO30 BIT7 EMMC_DATA[3] B8
AJ4 NAND_AD5/EMMC_D3/GPIO198
GPIO_PM18/GPIO31 BIT8 EMMC_DATA[4] C8 AN2 Close to MSTAR DTV_IF
BIT8 +3.3V_NORMAL NAND_AD6/EMMC_D4/GPIO197 SIFP
EMMC_DATA[5] B9 AN1
AVDD_3P3 K5 NAND_AD7/EMMC_D5/GPIO227 SIFM
GPIO_PM1/GPIO14 /USB_OCD3 R140 100 C118 0.1uF OPT IF_P
BIT9 D5 L6 R177 C122
CPU_VID0 VID0/GPIO55 GPIO_PM5/GPIO18 USB_CTL3 10K AP3 100pF
D4 M5 OPT R174 0 IF_AGC
BIT10 CORE_VID0 VID1/GPIO56 GPIO_PM11/GPIO24 DATA_FORMAT_0_SOC AM4
H4 M6 URSA9_CONNECT PCM2_CD/GPIO123
WOL_WAKE_UP LED0 LED0/GPIO32 GPIO_PM12/GPIO25 DATA_FORMAT_1_SOC R178 AP4 AR2
R131 H5 RF_SWITCH_CTL PCM2_CE/GPIO119 TGPIO0/GPIO162 /USB_OCD1 R141 100 C119 0.1uF OPT
BIT11 10K 10K AL5 AM2 IF_N
LED1 LED1/GPIO33 C123
0 R187 L5 L4 OPT PCM2_IRQA/GPIO120 TGPIO1/GPIO163 USB_CTL1 33pF OPT
WOL_WAKE_UP WOL/GPIO57 AV_LNK/GPIO9 AN4 AK5 C126
BIT12 WOL_WAKE_UP J15 PCM2_WAIT/GPIO121 TGPIO2/GPIO164 I2C_SCL7 33pF
TEST AL4 AK6
PCM2_RESET/GPIO122 TGPIO3/GPIO165 I2C_SDA7
BIT13
OPT
HDMI_EXT_EDID
0 R191
10K
10K
10K
10K
10K
10K
10K
L_DIM_EN
10K
10K
10K
10K
10K
10K
10K
A18 C120 0.1uF R144 47

TU_SIF
BIT2_0
BIT5
BIT0_0
BIT1_0
GPIO112/SPI1_DI
BIT8_0
BIT7_0
BIT6_0
BIT3_0
BIT4_0
B18 C121 0.1uF R145 47

OPT
BIT6 R146
OPT
GPIO111/SPI1_CK BIT9 C124

C17 1000pF 300
GPIO114/SPI2_DI L/D_DI_SOC
R111
OPT
R103
R115
R117
R119
R123
R121
ANALOG SIF OPT

R159
R182
R184
R107
R109
R186
R189
B17 BIT10
GPIO113/SPI2_CK L/D_CLK_SOC
C18
L/D_VSYNC_SOC
Close to MSTAR
GPIO110/VSYNC_LIKE
D18
GPIO115/DIM0 BIT11
E18
GPIO116/DIM1 AV1_CVBS_DET +3.3V_NORMAL
F18
GPIO117/DIM2 HP_DET
E17 L100
GPIO118/DIM3 SC_DET
PZ1608U121-2R0TF
20140701 version
BIT(0/1) DVB ATSC JP R142 C125

0.1uF
10K
00 TW/COL US
R143
Low High 0
01 CN/HK KR JP IF_AGC
Support
10 EU BR/PH C127
BIT9 EXTERNAL EDID EXTERNAL NON_EXTERNAL
BIT(2/3) EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP 0.047uF
11 AJJA Sri Lanka FOR HDMI2.0 25V
BIT(7/8) B/E(FRC)
00 T2/C/S2 PIP T2/C PIP T2/C PIP Default ATSC NIM+T2 Default ISDB PIP Default
BIT10 Division NON_Division 4_Division
Low High 00 NONE
01 T2/C/S2 T2/C/S2 T2/C ATSC+T2 ISDB EXT
BIT11 CI+ Old CI Path New CI Path
BIT4 Display LCD OLED 01 URSA9
10 T/C T T/C ATSC ISDB INT BIT12 VID VID Enable VID Disable
BIT5 Resolution FHD UHD 10 URSA11 4K@60Hz
BIT6 URSA11 4K@120Hz 11 T2 ATSC PIP BIT13 Reserved
Model LM15U only LM15U+URSA 11
Mstart Debug RS232C_Debug +3.3V_TU

+3.3V_LNA_TU
+3.3V_NORMAL I2C PULL UP DDTS_Debug
GPIO PULL UP
+3.3V_NORMAL
MSTAR_DEBUG_OLD +3.3V_NORMAL
DDTS_Debug
R147
1.8K
R148
1.8K
R128
1.8K
R130
1.8K
R133
1.8K
R134
1.8K
R106
1.8K
R125
1.8K
R132
1.8K
R139
1.8K
R127
1.8K
R129
1.8K
R135
1.8K
R136
1.8K
P103 UART_4PIN_WAFER +3.5V_ST

MSTAR_DEBUG_NEW P100
12505WS-04A00 P102
P101 12507WS-04L
12507WS-04L
10K
10K
10K
10K
12507WS-04L
10K
10K
10K
10K
10K
10K
10K
I2C_SDA7
OPT
I2C for URSA9 (URSA9 Only)

10K
OPT
1 I2C_SCL7
OPT
1
OPT
R171
1 I2C_SDA6
R149
R153
R151
R152
R150
R169
R160
R154
R170
1 I2C for LCD Module
R102
I2C_SCL6
R100
2
I2C_SDA1 2 DDTS_RX
2 SOC_RX I2C for NAVRAM
10K
2 I2C_SCL1
10K
/TU_RESET1
DDCA_CK 3 I2C_SDA3
OPT
I2C for Micom RF_SWITCH_CTL 3
OPT
3 I2C_SCL3
3
R105
AMP_RESET_N
R101
4 I2C_SDA4
DDCA_DA I2C for Main Amp / Woofer AMP TCON_I2C_EN 4
I2C_SCL4 DDTS_TX
4 SOC_TX
4 /USB_OCD1
5 I2C_SDA5
I2C for tuner USB_CTL1 5
5 I2C_SCL5
5 /USB_OCD2
I2C_SDA2 USB_CTL2
I2C for tuner&LNB
I2C_SCL2 M_RFModule_RESET
AR101 PCM_5V_CTL
33
I2C_SDA_MICOM I2C_SDA3
I2C_SCL_MICOM I2C_SCL3
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS LM15U 2015-02-26
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_SYSTEM 1
Copyright © 2015 LG Electronics. Inc. All rights reserved. LGE Internal Use Only
+1.1V_Bypass Cap(CLOSE TO CHIP SIDE) 4th layer
WOL POWER ENABLE CONTROL +1.1V_VDDC DVDD_DDR11 AVDDL_HDMI11

IC100
LGE5331(LM15U) AVDD_3P3
L226 L205
+1.1V_VDDC PZ1608U121-2R0TF PZ1608U121-2R0TF
+3.5V_ST
0.47uF
L10 V7 +3.5V_WOL
0.1uF
0.1uF
0.1uF
VDDC_1 IC200
0.1uF
0.1uF
AVDD_NODIE
L11
L12
VDDC_2 AVDDL_HDMI11 AP2151WG-7 C228
2A 2A
C271
VDDC_3 10uF
PZ1608U121-2R0TF 10uF
OPT
L13 T13
10V
C324
C210
VDDC_4
C232
C235
AVDDL_MHL3_1 AVDD33 L204 10V
C306
C310
L14 T14 IN OUT
VDDC_5 AVDDL_MHL3_2 5 1
M10 L8
VDDC_6 AVDD3P3_MHL3_1
M11 M8 C239 +3.3V_NORMAL
VDDC_7 AVDD3P3_MHL3_2 R203
M12 0.1uF GND 10K
VDDC_8 AVDD33 2
M13 OPT
VDDC_9 R201
M14 W7 1K
VDDC_10 AVDD3P3_ETH WOL_CTL 0 R202 OPT EN FLG
N10 AD7 4 3
VDDC_11 AVDD3P3_DADC_1
N11 AD8 Close to chip side
VDDC_12 AVDD3P3_DADC_2
N12 Y7
VDDC_13 AVDD3P3_ADC_1
N13 Y8
VDDC_14 AVDD3P3_ADC_2
V12 AL10
VDDC_15 AVDD3P3_USB_1 +1.1V_VDDC AVDDL_MOD11
V13 AL11
VDDC_16 AVDD3P3_USB_2 4th layer
V14 AH14
VDDC_17 AVDD3P3_USB3_1 L202
W12 AH15 AVDD_AU33
VDDC_18 AVDD3P3_USB3_2 PZ1608U121-2R0TF
W13 AH7
VDDC_19 AVDD_AU33
W14 AG7
VDDC_20 AVDD_EAR33
0.1uF
0.1uF
0.1uF
AVDD_3P3
0.1uF
0.1uF
Y12 AL12
Y13
VDDC_21 AVDD3P3_DMPLL
AK15 C261
2A C264
VDDC_22 VDDP_1
Y14 AL15 1st layer 4th layer 10uF 10uF
VDDC_23 VDDP_2 10V 10V
OPT
C320
C285
C265
AF18
C275
C277
AVDD_PLL33
VDDC_24
AF19
VDDC_25
AF20 W26
VDDC_26
0.1uF
AVDD_MOD_1
AG18 Y27
0.1uF
VDDC_27 AVDD_MOD_2
AG19 Y28
VDDC_28 AVDD_LPLL_1
AG20 Y29
VDDC_29 AVDD_LPLL_2
AG21
C250
C249
VDDC_30
AG22
VDDC_31
AH18 U18 Close to chip side
VDDC_32 AVDD_PLL_A
AH19 U19
VDDC_33 AVDD_PLL_B VDDP_NAND
AH20 AL18
VDDC_34 AVDD_PLL_C
AH21 +1.1V_VDDC_CPU
VDDC_35
AH22 L17
VDDC_36 VDDP_3318_A_CAP 1st layer 4th layer
AVDDL_MOD11 L15
VDDP_3318_C_CAP
4.7uF
0.1uF
4.7uF
0.1uF
W23 G8
AVDDL_PREDRV_1 VDDP_3318_A
Y23 H7 Close to chip side
AVDDL_PREDRV_2 VDDP_3318_C
W24
0.1uF
0.1uF
VDDC15_M0 AVDDL_MOD_1 VDDC15_M0
Y24
C216
C219
C220
C221
AVDDL_MOD_2 C263 C322 C323

Y25 M20
AVDD15_MOD_1 AVDD_DDR_A_CMD_1 10uF 10uF 10uF
Y26 M21 10V 10V 10V
C276
C278
DVDD_DDR11 AVDD15_MOD_2 AVDD_DDR_A_CMD_2
N21
AVDD_DDR_A_MCK
AF14 M22
AVDDL_USB3_1 AVDD_DDR_A_DAT_1
AF15 N22
AVDDL_USB3_2 AVDD_DDR_A_DAT_2
+1.1V_VDDC_CPU N23
AVDD_DDR_A_DAT_3 +3.5V_WOL
AA21 N24
VDDC_CPU_1 AVDD_DDR_A_DAT_4 IC201
AA27 N25
VDDC_CPU_2 AVDD_DDR_B_CMD_1 AP2121N-3.3TRE1 AVDD_3P3
AA28 N26
VDDC_CPU_3 AVDD_DDR_B_CMD_2
AA29 P25
VDDC_CPU_4 AVDD_DDR_B_MCK VIN VOUT Close to chip side
AB21 R25 3 2 Close to chip side
VDDC_CPU_5 AVDD_DDR_B_DAT_1
AB22 T25
VDDC_CPU_6 AVDD_DDR_B_DAT_3 1
AB23 U25
VDDC_CPU_7 AVDD_DDR_B_DAT_4 VDDC15_M1 GND
AB24 R26
VDDC_CPU_8 AVDD_DDR_B_DAT_2 C206
AB25 AE25 C205
VDDC_CPU_9 AVDD_DDR_C_CMD_1 1uF
AB26 AE26 0.1uF
VDDC_CPU_10 AVDD_DDR_C_CMD_2 10V
AB27 AF26 16V
VDDC_CPU_11 AVDD_DDR_C_MCK
AB28 AE22
VDDC_CPU_12 AVDD_DDR_C_DAT_1
AB29 AE23
AC21 AE24
AC22 AF22 VDDC15_M0
AC23 VDDC15_M1
VDDC_CPU_16
AC24 N20
VDDC_CPU_17 AVDD_DDR_LDO_A
AC25 P24
VDDC_CPU_18 AVDD_DDR_LDO_B
AC26 AD25
VDDC_CPU_19 AVDD_DDR_LDO_C
AC27
VDDC_CPU_20 AVDD5V_MHL
AC28
VDDC_CPU_21
AC29 U7
VDDC_CPU_22 AVDD_HDMI_5V_PA
AC30 P7
VDDC_CPU_23 AVDD_HDMI_5V_PC
AD27
VDDC_CPU_24
AD28
VDDC_CPU_25
AD29 P8
VDDC_CPU_26 GND_EFUSE
DVDD_NODIE
AD30
VDDC_CPU_27 VDDC15_M0 +3.3V_Bypass Cap
L20
AVDD_DDR_VBP_A_1
N14 L21
DVDD_NODIE AVDD_DDR_VBP_A_2
DVDD_DDR11 0.47uF C227
R22 M24
C200 DVDD_DDR_1 AVDD_DDR_VBN_A_1
R24 M25 +3.3V_NORMAL AVDD_PLL33
1uF DVDD_DDR_2 AVDD_DDR_VBN_A_2
AF24 0.47uF C229
25V DVDD_DDR_C
P22 U27
DVDD_DDR_RX_A AVDD_DDR_VBP_B_1 1st layer 4th layer
T24 V27
DVDD_DDR_RX_B AVDD_DDR_VBP_B_2 L215
AF25 0.47uF C230
DVDD_DDR_RX_C PZ1608U121-2R0TF
U26
AVDD_DDR_VBN_B_1
0.1uF
0.1uF
0.47uF
0.47uF
V26
AVDD_DDR_VBN_B_2
0.47uF C231 VDDC15_M1
AD21 5V_HDMI_3 AVDD5V_MHL
2A C256
AVDD_DDR_VBP_C_1 C222 10uF
AD22 10uF
C274
C286
AVDD_DDR_VBP_C_2 10V
C311
C241
0.47uF C234 10V
AD23
AVDD_DDR_VBN_C_1 R200
AD24 10
AVDD_DDR_VBN_C_2
0.47uF C240
Close to chip side Close to chip side

+1.5V_Bypass Cap
+3.3V_NORMAL VDDP_NAND
+1.5V_DDR VDDC15_M0 AVDD33
4th layer
OPT L203
L227 PZ1608U121-2R0TF
PZ1608U121-2R0TF L222
PZ1608U121-2R0TF
0.1uF
0.1uF
1st layer 4th layer
0.47uF
0.1uF
L200
+1.8V 2A C304 2A C217
PZ1608U121-2R0TF C302 0.1uF
10uF
C238
C244
0.1uF
0.1uF
0.1uF
0.1uF
10uF
C251
C211
OPT L223 10V
10V
2A C207
10uF
C201
10uF
OPT
C314
C316
10uF
C223
10uF
PZ1608U121-2R0TF
10V 10V 0.47uF 10V 10V

C209
C224
C225
C226
2A
Close to chip side
Close to chip side Close to chip side AVDD_AU33

VDDC15_M1
4th layer
L212
1st layer 4th layer GND JIG POINT PZ1608U121-2R0TF
L201
0.1uF
0.1uF
0.1uF
PZ1608U121-2R0TF LM15U_DDR_EMI LM15U_DDR_EMI 2A
0.1uF
0.1uF
0.1uF
0.1uF
LM15U_DDR_EMI C236
JP202
JP204
JP203
JP205
OPT 10uF
OPT
C208 C202 C317 C212 C213 C214
2A
C243
C252
C253
10uF 10uF C315 10uF 20pF 20pF 20pF 10V
10V 10V 0.47uF 10V 50V 50V 50V
C218
C203
C204
C287
Close to chip side

Close to chip side Close to chip side

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM15U POWER 02
11/05/31
M0_DDR_VREFDQ Hynix_DDR3_4Gb_29n
Hynix_DDR3_4Gb_29n M0_1_DDR_VREFDQ Hynix_DDR3_4Gb_29n M1_DDR_VREFDQ
IC400 IC401 IC403
H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC DDR_VTT DDR_VTT
EAN63053201 EAN63053201 EAN63053201

IC100 AR400 AR407
M0_DDR_A0
N3 DDR3 M8
M0_DDR_A0
N3 DDR3 M8 N3 DDR3 M8 56 56
LGE5331(LM15U) P7
A0 VREFCA
P7
A0 VREFCA M1_DDR_A0 A0 VREFCA 1/16W 1/16W
M0_DDR_A1 A1 4Gbit M0_DDR_A1 A1
4Gbit P7
4Gbit C424 0.1uF C453 0.1uF
P3 P3 M1_DDR_A1 A1 M0_DDR_A14 M1_DDR_A14
M0_DDR_A2 A2 (x16) M0_DDR_A2 A2 (x16) M1_DDR_A2
P3
A2 (x16)
N2 H1 N2 H1 N2 H1 M0_DDR_A8 M1_DDR_A8
M0_DDR_A3 A3 VREFDQ M0_DDR_A3 A3 VREFDQ M1_DDR_A3
F21 G33 P8 P8 A3 VREFDQ M0_DDR_A11 M1_DDR_A11
M0_DDR_A0 A_A0 B_A0 M1_DDR_A0 M0_DDR_A4 A4 M0_DDR_A4 A4 P8 C425 0.1uF C454 0.1uF
C21 J36 P2 P2 M1_DDR_A4 A4 M0_DDR_A6 M1_DDR_A6
M0_DDR_A1 A_A1 B_A1 M1_DDR_A1 M0_DDR_A5 A5 M0_DDR_A5 A5 P2
E21 H34 R8 L8 R400 R8 L8 M1_DDR_A5 A5
240 R403 240 R8 L8 R404 AR401 AR408
M0_DDR_A2 A_A2 B_A2 M1_DDR_A2 M0_DDR_A6 A6 ZQ M0_DDR_A6 A6 ZQ M1_DDR_A6 240
F22 J32 R2 R2 A6 ZQ 56 56
M0_DDR_A3 M1_DDR_A3 M0_DDR_A7 VDDC15_M0 M0_DDR_A7 R2 VDDC15_M0 1/16W 1/16W
A_A3 B_A3 A7 A7 VDDC15_M0 M1_DDR_A7 A7
B22 J35 T8 T8 T8 C426 0.1uF C455 0.1uF
M0_DDR_A4 A_A4 B_A4 M1_DDR_A4 M0_DDR_A8 A8 M0_DDR_A8 A8 M1_DDR_A8 M0_DDR_A1 M1_DDR_A1
E22 H33 R3 B2 R3 B2 A8
M0_DDR_A5 A_A5 B_A5 M1_DDR_A5 M0_DDR_A9 A9 VDD_1 M0_DDR_A9 A9 R3 B2
VDD_1 M1_DDR_A9 A9 VDD_1 M0_DDR_A4 M1_DDR_A4
A21 J37 L7 D9 L7 D9 L7 D9
M0_DDR_A6 A_A6 B_A6 M1_DDR_A6 M0_DDR_A10 A10/AP VDD_2 M0_DDR_A10 A10/AP VDD_2 M1_DDR_A10 M0_DDR_A12 M1_DDR_A12
D21 G36 R7 G7 R7 G7 A10/AP VDD_2
DDR3 1.5V bypass Cap - Place these caps near Memory

R7 G7 C427 0.1uF C456 0.1uF

M0_DDR_A7 A_A7 B_A7 M1_DDR_A7 M0_DDR_A11 A11 VDD_3 M0_DDR_A11 A11 VDD_3 M1_DDR_A11 M0_DDR_BA1 M1_DDR_BA1
C20 H37 N7 K2 N7 K2 A11 VDD_3
M0_DDR_A8 A_A8 B_A8 M1_DDR_A8 M0_DDR_A12 A12/BC VDD_4 M0_DDR_A12 N7 K2
A12/BC VDD_4 M1_DDR_A12 A12/BC VDD_4
E20 F35 T3 K8 T3 K8 T3 K8 AR402 AR409
M0_DDR_A9 A_A9 B_A9 M1_DDR_A9 M0_DDR_A13 A13 VDD_5 M0_DDR_A13 A13 VDD_5 M1_DDR_A13 56 56
B23 K35 T7 N1 T7 N1 A13 VDD_5
M0_DDR_A10 M1_DDR_A10 M0_DDR_A14 M0_DDR_A14 T7 N1 1/16W 1/16W
A_A10 B_A10 A14 VDD_6 A14 VDD_6 M1_DDR_A14 A14 VDD_6
B21 H35 M7 N9 M7 N9 M7 N9 C428 0.1uF C457 0.1uF
M0_DDR_A11 A_A11 B_A11 M1_DDR_A11 M0_DDR_A15 NC_5 VDD_7 M0_DDR_A15 NC_5 VDD_7 M1_DDR_A15
D24 K34 R1 R1 NC_5 VDD_7
M0_DDR_A12 A_A12 B_A12 M1_DDR_A12 VDD_8 R1 M0_DDR_A13 M1_DDR_A13
VDD_8 VDD_8
F20 F36 M2 R9 M2 R9 M2 R9
M0_DDR_A13 A_A13 B_A13 M1_DDR_A13 M0_DDR_BA0 BA0 VDD_9 M0_DDR_BA0 BA0 VDD_9 M1_DDR_BA0 M0_DDR_A9 M1_DDR_A9
B20 H36 N8 N8 BA0 VDD_9 C429 0.1uF C458 0.1uF
M0_DDR_A14 A_A14 B_A14 M1_DDR_A14 M0_DDR_BA1 BA1 M0_DDR_BA1 BA1 N8
M1_DDR_BA1 BA1 M0_DDR_A7 M1_DDR_A7
E24 L33 M3 M3 M3
M0_DDR_A15 A_A15 B_A15 M1_DDR_A15 M0_DDR_BA2 BA2 M0_DDR_BA2 BA2
E23 K33 A1 A1 M1_DDR_BA2 BA2 AR403 AR410
M0_DDR_BA0 A_BA0 B_BA0 M1_DDR_BA0 VDDQ_1 A1 56 56
VDDQ_1 VDDQ_1
C22 K36 J7 A8 J7 A8 J7 A8 1/16W 1/16W
M0_DDR_BA1 A_BA1 B_BA1 M1_DDR_BA1 M0_D_CLK CK VDDQ_2 M0_D_CLK CK VDDQ_2 M1_D_CLK C430 0.1uF C459 0.1uF
F23 J33 K7 C1 K7 C1 CK VDDQ_2
M0_DDR_BA2 A_BA2 B_BA2 M1_DDR_BA2 M0_D_CLKN CK VDDQ_3 M0_D_CLKN K7 C1 M0_DDR_A2 M1_DDR_A2
CK VDDQ_3 M1_D_CLKN CK VDDQ_3
G26 M33 K9 C9 K9 C9 K9 C9
M0_DDR_RASN A_RASZ B_RASZ M1_DDR_RASN M0_DDR_CKE CKE VDDQ_4 M0_DDR_CKE CKE VDDQ_4 M0_DDR_A5 M1_DDR_A5
F25 M32 D2 D2 M1_DDR_CKE CKE VDDQ_4
M0_DDR_CASN M1_DDR_CASN D2 M0_DDR_A3 M1_DDR_A3
A_CASZ B_CASZ VDDQ_5 VDDQ_5 VDDQ_5 C431 0.1uF C460 0.1uF
E25 K32 L2 E9 L2 E9 L2 E9 M0_DDR_A0 M1_DDR_A0
M0_DDR_WEN A_WEZ B_WEZ M1_DDR_WEN M0_DDR_CS1 CS VDDQ_6 M0_DDR_CS2 CS VDDQ_6 M1_DDR_CS1
F24 L32 K1 F1 K1 F1 CS VDDQ_6
M0_DDR_ODT A_ODT B_ODT M1_DDR_ODT M0_DDR_ODT ODT VDDQ_7 M0_DDR_ODT ODT K1 F1 AR404 AR411
VDDQ_7 M1_DDR_ODT ODT VDDQ_7
C23 L36 J3 H2 C410 0.1uF J3 H2 C440 0.1uF J3 H2 56 56
M0_DDR_CKE A_CKE B_CKE M1_DDR_CKE M0_DDR_RASN RAS VDDQ_8 M0_DDR_RASN RAS VDDQ_8 C468 0.1uF 1/16W 1/16W
F19 F37 K3 H9 K3 H9 M1_DDR_RASN RAS VDDQ_8
C411 0.1uF C441 0.1uF K3 H9 C469 0.1uF
M0_DDR_RESET_N_1 A_RST B_RST M1_DDR_RESET_N_1 M0_DDR_CASN CAS VDDQ_9 M0_DDR_CASN CAS VDDQ_9 M1_DDR_CASN C432 0.1uF C461 0.1uF
A24 M37 L3 L3 CAS VDDQ_9 M0_DDR_BA0 M1_DDR_BA0
M0_D_CLK A_MCLK B_MCLK M1_D_CLK M0_DDR_WEN WE M0_DDR_WEN L3
WE M1_DDR_WEN WE
B24 L35 J1 J1 J1 M0_DDR_BA2 M1_DDR_BA2
M0_D_CLKN A_MCLKZ B_MCLKZ M1_D_CLKN NC_1 NC_1
E19 F34 T2 J9 T2 J9 NC_1 M0_DDR_A15 M1_DDR_A15
M0_DDR_CS1 A_CSB1 B_CSB1 M1_DDR_CS1 M0_DDR_RESET_N RESET NC_2 M0_DDR_RESET_N T2 J9 C433 0.1uF C462 0.1uF
RESET NC_2 M1_DDR_RESET_N RESET NC_2
D19 E37 L1 L1 L1 M0_DDR_A10 M1_DDR_A10
M0_DDR_CS2 A_CSB2 B_CSB2 M1_DDR_CS2 NC_3 NC_3
L9 L9 NC_3
L9 AR405 AR412
NC_4 NC_4 NC_4 56 56
C27 R36 F3 F3 F3
M0_DDR_DQ0 A_DQ[0] B_DQ[0] M1_DDR_DQ0 M0_DDR_DQS0 DQSL M0_DDR_DQS2 DQSL SS_DDR3_4Gb_25n 1/16W 1/16W
B26 N35 G3
SS_DDR3_4Gb_25n
IC400-*1
Hynix_DDR3_4Gb_25n
IC400-*2 G3
IC401-*1
K4B4G1646D-BCMA
Hynix_DDR3_4Gb_25n
IC401-*2
M1_DDR_DQS0 DQSL SS_DDR3_4Gb_25n
IC403-*1
Hynix_DDR3_4Gb_25n
IC403-*2
M0_DDR_DQ1 M1_DDR_DQ1 M0_DDR_DQS_N0 K4B4G1646D-BCMA H5TQ4G63CFR_RDC
M0_DDR_DQS_N2 H5TQ4G63CFR_RDC G3 K4B4G1646D-BCMA H5TQ4G63CFR_RDC C434 0.1uF C463 0.1uF
A_DQ[1] B_DQ[1] DQSL DQSL M1_DDR_DQS_N0 DQSL M0_DDR_WEN M1_DDR_WEN
B28 R35 N3 M8 N3 M8
N3
A0 VREFCA
M8
N3 M8 N3 M8 N3 M8
M0_DDR_DQ2 A_DQ[2] B_DQ[2] M1_DDR_DQ2 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
P7
P3
A1
A2
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
M0_DDR_CASN M1_DDR_CASN
C25 N36 C7 A9 P3
N2
A2
H1
P3
N2
A2
H1 C7 A9 N2
P8
A3 VREFDQ
H1 P3
N2
A2
H1
C7 A9
P3
N2
A2
H1
P3
N2
A2
H1
M0_DDR_DQ3 A_DQ[3] B_DQ[3] M1_DDR_DQ3 M0_DDR_DQS1 DQSU VSS_1 P8

A3 VREFDQ
P8
A3 VREFDQ
M0_DDR_DQS3 DQSU VSS_1 P2
A4 P8
A3 VREFDQ
P8
A3 VREFDQ
P8
A3 VREFDQ
B29 T35 B7 B3
P2
R8
A4
A5
L8
P2
R8
A4
A5
L8 B7 B3
R8
A5
A6 ZQ
L8 P2
R8
A4
A5
L8
M1_DDR_DQS1 DQSU VSS_1 P2
R8
A4
A5
L8
P2
R8
A4
A5
L8 M0_DDR_ODT M1_DDR_ODT
M0_DDR_DQ4 M1_DDR_DQ4 M0_DDR_DQS_N1 R2
A6 ZQ
R2
A6 ZQ
M0_DDR_DQS_N3
R2
A7 R2
A6 ZQ
B7 B3 R2
A6 ZQ
R2
A6 ZQ
C435 0.1uF C464 0.1uF
A_DQ[4] B_DQ[4] DQSU VSS_2 T8
A7
T8
A7
DQSU VSS_2 T8
R3
A8
B2 T8
A7
M1_DDR_DQS_N1 DQSU VSS_2 T8
A7
T8
A7
M0_DDR_RASN M1_DDR_RASN
C24 M36 E1 R3
L7
A8
A9 VDD_1
B2
D9
R3
L7
A8
A9 VDD_1
B2
D9
E1 L7
A9
A10/AP
VDD_1
VDD_2
D9 R3
L7
A8
A9 VDD_1
B2
D9
E1
R3
L7
A8
A9 VDD_1
B2
D9
R3
L7
A8
A9 VDD_1
B2
D9
M0_DDR_DQ5 A_DQ[5] B_DQ[5] M1_DDR_DQ5 VSS_3 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7
VSS_3
R7
N7
A11 VDD_3
G7
K2 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7 R7
A10/AP VDD_2
G7
C28 T36 E7 G8 N7
A11
A12/BC
VDD_3
VDD_4
K2 N7
A11
A12/BC
VDD_3
VDD_4
K2
E7 G8 T3
A12/BC
A13
VDD_4
VDD_5
K8 N7
A11
A12/BC
VDD_3
VDD_4
K2
VSS_3 N7
A11
A12/BC
VDD_3
VDD_4
K2 N7
A11
A12/BC
VDD_3
VDD_4
K2
AR406 AR413
M0_DDR_DQ6 A_DQ[6] B_DQ[6] M1_DDR_DQ6 M0_DDR_DM0 DML VSS_4
T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
M0_DDR_DM2 DML
VDD_6
N1 T3
A13 VDD_5
K8
E7 G8 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9 VSS_4 M7
NC_5 VDD_7
N9
R1
T7
M7
A14 VDD_6
N1
N9
M1_DDR_DM0 DML VSS_4 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9 56 56
B25 M35 D3 J2 NC_5 VDD_7
VDD_8
R1
NC_5 VDD_7
VDD_8
R1 D3 J2 M2
VDD_8
R9
NC_5 VDD_7
VDD_8
R1
D3 J2
NC_5 VDD_7
VDD_8
R1
NC_5 VDD_7
VDD_8
R1
1/16W 1/16W
M0_DDR_DQ7 A_DQ[7] B_DQ[7] M1_DDR_DQ7 M0_DDR_DM1 DMU VSS_5
M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9
M0_DDR_DM3 DMU VSS_5 N8
BA0
BA1
VDD_9 M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9
C26 P36 J8
N8
M3
BA1
N8
M3
BA1
J8
M3
BA2
A1
N8
M3
BA1 M1_DDR_DM1 DMU VSS_5 N8
M3
BA1
N8
M3
BA1
C436 0.1uF C465 0.1uF
M0_DDR_DM0 A_DQM[0] B_DQM[0] M1_DDR_DM0 VSS_6 J7
BA2
VDDQ_1
A1
A8 J7
BA2
VDDQ_1
A1
A8
VSS_6
J7
K7
CK
VDDQ_1
VDDQ_2
A8
C1 J7
BA2
VDDQ_1
A1
A8
J8 J7
BA2
VDDQ_1
A1
A8 J7
BA2
VDDQ_1
A1
A8 M0_DDR_CKE M1_DDR_CKE
A27 R37 E3 M1 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1
E3 M1 K9
CK
CKE
VDDQ_3
VDDQ_4
C9 K7
CK
CK
VDDQ_2
VDDQ_3
C1
VSS_6 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1
M0_DDR_DQS0 A_DQS[0] B_DQS[0] M1_DDR_DQS0 M0_DDR_DQ0 DQL0 VSS_7

K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
M0_DDR_DQ16 VDDQ_5
D2 K9
CKE VDDQ_4
C9
E3 M1 K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
L2
VDDQ_5
D2
E9 L2
VDDQ_5
D2
E9 DQL0 VSS_7 L2
K1
CS VDDQ_6
E9
F1 L2
VDDQ_5
D2
E9
M1_DDR_DQ0 DQL0 VSS_7 L2
VDDQ_5
D2
E9 L2
VDDQ_5
D2
E9
B27 P35 F7 M9 K1
CS
ODT
VDDQ_6
VDDQ_7
F1 K1
CS
ODT
VDDQ_6
VDDQ_7
F1 F7 M9 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2 K1
CS
ODT
VDDQ_6
VDDQ_7
F1
F7 M9
K1
CS
ODT
VDDQ_6
VDDQ_7
F1 K1
CS
ODT
VDDQ_6
VDDQ_7
F1
M0_DDR_DQS_N0 A_DQSB[0] B_DQSB[0] M1_DDR_DQS_N0 M0_DDR_DQ1 DQL1 VSS_8

J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9 M0_DDR_DQ17 DQL1 VSS_8 K3
CAS VDDQ_9
H9 J3
K3
RAS VDDQ_8
H2
H9
M1_DDR_DQ1
J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9 M0_D_CLKN M1_D_CLKN
F2 P1 L3
CAS VDDQ_9
L3
CAS VDDQ_9
F2 P1
L3
WE
J1 L3
CAS VDDQ_9
DQL1 VSS_8 L3
CAS VDDQ_9
L3
CAS VDDQ_9
C437 0.1uF C466 0.1uF
M0_DDR_DQ2 DQL2 VSS_9
WE
NC_1
J1
WE
NC_1
J1
M0_DDR_DQ18 DQL2
T2
NC_1
J9
WE
J1
F2 P1 WE
J1
WE
J1
M0_D_CLK M1_D_CLK
T2
RESET NC_2
J9 T2
RESET NC_2
J9
VSS_9 RESET NC_2
NC_3
L1 T2
RESET
NC_1
NC_2
J9
T2
RESET
NC_1
NC_2
J9 T2
RESET
NC_1
NC_2
J9
D27 N32 F8 P9 NC_3

L1
L9
NC_3
L1
L9 F8 P9 F3
NC_4
L9
T7
NC_3
L1
L9
F8 P9
NC_3
L1
L9
NC_3
L1
L9
M0_DDR_DQ8 A_DQ[8]/DQU0 B_DQ[8]/DQU0 M1_DDR_DQ8 M0_DDR_DQ3 DQL3 VSS_10 F3

NC_4
T7 F3
NC_4
M0_DDR_DQ19 DQL3 VSS_10 G3
DQSL NC_6 F3
NC_4
F3
NC_4
T7 F3
NC_4
D30 T34 H3 T1
G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL
H3 T1
DQSL G3
DQSL
DQSL M1_DDR_DQ3 DQL3 VSS_10 G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL
M0_DDR_DQ9 A_DQ[9]/DQU1 B_DQ[9]/DQU1 M1_DDR_DQ9 M0_DDR_DQ4 DQL4 VSS_11

C7 A9 C7 A9
M0_DDR_DQ20 DQL4
C7
B7
DQSU VSS_1
A9
B3 C7 A9 H3 T1 C7 A9 C7 A9
B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3 VSS_11 DQSU VSS_2
E1 B7
DQSU VSS_1
B3
M1_DDR_DQ4 DQL4 VSS_11 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3
E26 N33 H8 T9 E7
DQSU VSS_2
VSS_3
E1
G8 E7
DQSU VSS_2
VSS_3
E1
G8
H8 T9 E7
DML
VSS_3
VSS_4
G8
E7
DQSU VSS_2
VSS_3
E1
G8
H8 T9 E7
DQSU VSS_2
VSS_3
E1
G8 E7
DQSU VSS_2
VSS_3
E1
G8
M0_DDR_DQ10 A_DQ[10]/DQU2 B_DQ[10]/DQU2 M1_DDR_DQ10 M0_DDR_DQ5 DQL5 VSS_12 D3
DML VSS_4
J2 D3
DML VSS_4
J2 M0_DDR_DQ21 DQL5 VSS_12
D3
DMU VSS_5
J2
D3
DML VSS_4
J2 D3
DML VSS_4
J2 D3
DML VSS_4
J2
D31 T32 G2
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
G2 E3
DQL0
VSS_6
VSS_7
J8
M1
DMU VSS_5
VSS_6
J8 M1_DDR_DQ5 DQL5 VSS_12 DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
M0_DDR_DQ11 A_DQ[11]/DQU3 B_DQ[11]/DQU3 M1_DDR_DQ11 M0_DDR_DQ6 DQL6

E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
M0_DDR_DQ22 DQL6
F7
F2
DQL1 VSS_8
M9
P1
E3
F7
DQL0 VSS_7
M1
M9 G2 E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
F27 P33 H7
F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9 H7
F8
DQL2
DQL3
VSS_9
VSS_10
P9 F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
M1_DDR_DQ6 DQL6 F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
M0_DDR_DQ12 A_DQ[12]/DQU4 B_DQ[12]/DQU4 M1_DDR_DQ12 M0_DDR_DQ7 DQL7

H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1
M0_DDR_DQ23 DQL7
H3
H8
DQL4 VSS_11
T1
T9 H3
DQL3 VSS_10
T1 H7 H3
DQL3 VSS_10
T1 H3
DQL3 VSS_10
T1
VDDC15_M0
E30 U33 B1
H8
DQL4
DQL5
VSS_11
VSS_12
T9 H8
DQL4
DQL5
VSS_11
VSS_12
T9 G2
DQL5 VSS_12 H8
DQL4
DQL5
VSS_11
VSS_12
T9
M1_DDR_DQ7 DQL7 H8
DQL4
DQL5
VSS_11
VSS_12
T9 H8
DQL4
DQL5
VSS_11
VSS_12
T9
M0_DDR_CKE
G2
H7
DQL6
G2
H7
DQL6 B1 H7
DQL6
DQL7
G2
H7
DQL6
B1
G2
H7
DQL6
G2
H7
DQL6
M0_DDR_DQ13 A_DQ[13]/DQU5 B_DQ[13]/DQU5 M1_DDR_DQ13 VSSQ_1 DQL7

B1
DQL7
B1
VSSQ_1 D7
VSSQ_1
B1
B9
DQL7
B1
DQL7
B1
DQL7
B1
DDR_VTT_1
D26 N34 D7 B9 D7
DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9
D7 B9 C3
DQU0
DQU1
VSSQ_2
VSSQ_3
D1 D7
DQU0
VSSQ_1
VSSQ_2
B9
VSSQ_1 D7
DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9
M0_DDR_DQ14 A_DQ[14]/DQU6 B_DQ[14]/DQU6 M1_DDR_DQ14 M0_DDR_DQ8 DQU0 VSSQ_2

C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
M0_DDR_DQ24 DQU0
C8
DQU2 VSSQ_4
D8 C3
DQU1 VSSQ_3
D1
D7 B9 C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
C8 D8 C8 D8
VSSQ_2 C2 E2 C8 D8 C8 D8 C8 D8
1K
R418
E29 T33 C3 D1
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8 C3 D1
A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
M1_DDR_DQ8 DQU0 VSSQ_2 C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C3 D1
1K
R405
A2 F9
DQU4 VSSQ_6 DQU4 VSSQ_6 DQU4 VSSQ_6 DQU4 VSSQ_6 DQU4 VSSQ_6
M0_DDR_DQ15 A_DQ[15]/DQU7 B_DQ[15]/DQU7 M1_DDR_DQ15 M0_DDR_DQ9 DQU1 VSSQ_3
A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9
M0_DDR_DQ25 DQU1 VSSQ_3 B8
DQU5
DQU6
VSSQ_7
VSSQ_8
G1 A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9
E28 R33 C8 D8
B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
C8 D8
A3
DQU7 VSSQ_9
G9 B8
A3
DQU6 VSSQ_8
G1
G9 M1_DDR_DQ9 DQU1 VSSQ_3 B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
M0_DDR_DM1 M1_DDR_DM1 M0_DDR_DQ10

DQU7 VSSQ_9 DQU7 VSSQ_9
M0_DDR_DQ26
DQU7 VSSQ_9
C8 D8 DQU7 VSSQ_9 DQU7 VSSQ_9
AR414
A_DQM[1] B_DQM[1] DQU2 VSSQ_4 DQU2 VSSQ_4 M1_DDR_DQ10 DQU2 VSSQ_4 56
D28 R32 C2 E2 C2 E2 C2 E2
M0_DDR_DQS1 A_DQS[1] B_DQS[1] M1_DDR_DQS1 M0_DDR_DQ11 DQU3 VSSQ_5 M0_DDR_DQ27 DQU3 VSSQ_5 M1_DDR_DQ11 1/16W
E27 P32 A7 E8 A7 E8 DQU3 VSSQ_5 M0_DDR_RESET_N
M0_DDR_DQS_N1 M1_DDR_DQS_N1 M0_DDR_DQ12 M0_DDR_DQ28 A7 E8 C520 0.1uF
A_DQSB[1] B_DQSB[1] DQU4 VSSQ_6 DQU4 VSSQ_6 M1_DDR_DQ12 DQU4 VSSQ_6 M2_DDR_A14
A2 F9 A2 F9 A2 F9
M0_DDR_DQ13 DQU5 VSSQ_7 M0_DDR_DQ29 DQU5 VSSQ_7 M1_DDR_DQ13 M2_DDR_A8
C32 Y36 B8 G1 B8 G1 DQU5 VSSQ_7
M0_DDR_DQ16 A_DQ[16]/DQL0 B_DQ[16]/DQL0 M1_DDR_DQ16 M0_DDR_DQ14 DQU6 VSSQ_8 M0_DDR_DQ30 B8 G1
DQU6 VSSQ_8 M1_DDR_DQ14 DQU6 VSSQ_8 M2_DDR_A11
C30 V36 A3 G9 A3 G9 A3 G9 C521 0.1uF
M0_DDR_DQ17 A_DQ[17]/DQL1 B_DQ[17]/DQL1 M1_DDR_DQ17 M0_DDR_DQ15 DQU7 VSSQ_9 M0_DDR_DQ31 DQU7 VSSQ_9 M2_DDR_A6
B33 Y35 M1_DDR_DQ15 DQU7 VSSQ_9
M0_DDR_DQ18 A_DQ[18]/DQL2 B_DQ[18]/DQL2 M1_DDR_DQ18
A30 V37 AR415 M0_D_CLK
M0_DDR_DQ19 A_DQ[19]/DQL3 B_DQ[19]/DQL3 M1_DDR_DQ19 56 R412
C33 AA36 1/16W 56 C477
M0_DDR_DQ20 A_DQ[20]/DQL4 B_DQ[20]/DQL4 M1_DDR_DQ20
C29 U36 C522 0.1uF 1% 0.01uF
M0_DDR_DQ21 A_DQ[21]/DQL5 B_DQ[21]/DQL5 M1_DDR_DQ21 M2_DDR_A1 50V
A33 AA37
M0_DDR_DQ22 A_DQ[22]/DQL6 B_DQ[22]/DQL6 M1_DDR_DQ22 M2_DDR_A4
B30 U35 R413
M0_DDR_DQ23 A_DQ[23]/DQL7 B_DQ[23]/DQL7 M1_DDR_DQ23 M2_DDR_A12 56
B31 V35 C523 0.1uF 1%
M0_DDR_DM2 A_DQM[2] B_DQM[2] M1_DDR_DM2 M2_DDR_BA1
B32 W35
M0_DDR_DQS2 A_DQS[2] B_DQS[2] M1_DDR_DQS2 AR416
C31 W36 M0_D_CLKN
M0_DDR_DQS_N2 A_DQSB[2] B_DQSB[2] M1_DDR_DQS_N2 56
+1.5V_Bypass Cap +1.5V_Bypass Cap +1.5V_Bypass Cap 1/16W
C524 0.1uF
E33 W33
M0_DDR_DQ24
M0_DDR_DQ25
C35
A_DQ[24]/DQU0 B_DQ[24]/DQU0
AA32
M1_DDR_DQ24
M1_DDR_DQ25
Close to DDR Power Pin Close to DDR Power Pin Close to DDR Power Pin M2_DDR_A13 VDDC15_M0 M1_DDR_CKE
E31 U32
M0_DDR_DQ26 A_DQ[26]/DQU2 B_DQ[26]/DQU2 M1_DDR_DQ26 M2_DDR_A9
D35 AA34 C525 0.1uF
M0_DDR_DQ27 M1_DDR_DQ27 M2_DDR_A7
1K
R433
D33 V33
M0_DDR_DQ28 M1_DDR_DQ28 AR417
1K
R422
D34 AA33 56
M0_DDR_DQ29 A_DQ[29]/DQU5 B_DQ[29]/DQU5 M1_DDR_DQ29 VDDC15_M0 VDDC15_M0 1/16W
E32 V32 VDDC15_M0
M0_DDR_DQ30 A_DQ[30]/DQU6 B_DQ[30]/DQU6 M1_DDR_DQ30 C526 0.1uF
C34 Y32 M2_DDR_A2
M0_DDR_DQ31 A_DQ[31]/DQU7 B_DQ[31]/DQU7 M1_DDR_DQ31 M1_DDR_RESET_N
B35 W32 M2_DDR_A5
M0_DDR_DM3 A_DQM[3] B_DQM[3] M1_DDR_DM3
A35 Y33 M2_DDR_A3
M0_DDR_DQS3 A_DQS[3] B_DQS[3] M1_DDR_DQS3 C527 0.1uF
B34 W34 M2_DDR_A0
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
M0_DDR_DQS_N3 A_DQSB[3] B_DQSB[3] M1_DDR_DQS_N3

AR418
0.1uF
0.1uF
0.1uF
56 M1_D_CLK
1/16W R427
AM34 C528 0.1uF C497
C_A0 M2_DDR_A0 M2_DDR_BA0 56 0.01uF
C400
C401
C402
C412
C413
C415
AR35
C444
C445
C446
C_A1 M2_DDR_A1 1% 50V
AP34 M2_DDR_BA2
C_A2 M2_DDR_A2 M2_DDR_A15 R428
AM33 C529 0.1uF
C_A3 M2_DDR_A3 M2_DDR_A10 56
AT34 1%
C_A4 M2_DDR_A4
AN33 AR419
C_A5 M2_DDR_A5 56
AU35 1/16W M1_D_CLKN
C_A6 M2_DDR_A6
AR36 C530 0.1uF
C_A7 M2_DDR_A7 M2_DDR_WEN
AU36 M2_DDR_VREFDQ Hynix_DDR3_4Gb_29n
C_A8 M2_DDR_A8 Hynix_DDR3_4Gb_29n M2_1_DDR_VREFDQ Hynix_DDR3_4Gb_29n M1_1_DDR_VREFDQ M2_DDR_CASN VDDC15_M1 M2_DDR_CKE
AR37
C_A9 M2_DDR_A9 IC405 IC406 IC404 M2_DDR_ODT
AT33 C531 0.1uF
C_A10 M2_DDR_A10 H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC H5TQ4G63AFR-RDC M2_DDR_RASN
1K
R424
AT35
C_A11 M2_DDR_A11 AR420
1K
R420
AP31 EAN63053201 EAN63053201 EAN63053201
C_A12 M2_DDR_A12 56
AP35 1/16W
C_A13
AT37
M2_DDR_A13
M2_DDR_A0
N3
A0 DDR3 VREFCA
M8
M2_DDR_A0
N3
A0
DDR3 VREFCA
M8 N3 DDR3 M8 C532 0.1uF
M2_DDR_A14 P7 P7 M1_DDR_A0 A0 VREFCA M2_DDR_CKE
C_A14
AN31 M2_DDR_A1 A1 4Gbit M2_DDR_A1 A1
4Gbit P7 4Gbit M2_DDR_RESET_N
M2_DDR_A15 P3 P3 M1_DDR_A1 A1
C_A15 (x16)
AN32 M2_DDR_A2 A2 (x16) M2_DDR_A2 A2 M1_DDR_A2
P3
A2 (x16) M2_D_CLKN
C_BA0 M2_DDR_BA0 N2 H1 N2 H1 N2 H1 C533 0.1uF
AR34 M2_DDR_A3 A3 VREFDQ M2_DDR_A3 A3 VREFDQ M1_DDR_A3 M2_D_CLK
C_BA1 M2_DDR_BA1 P8 P8 A3 VREFDQ
AM32 M2_DDR_A4 A4 M2_DDR_A4 A4 P8
M2_DDR_BA2 P2 P2 M1_DDR_A4 A4
C_BA2 P2
AM29 M2_DDR_A5 A5 M2_DDR_A5 A5 M1_DDR_A5
C_RASZ M2_DDR_RASN R8 L8 R406 R8 L8 R407 A5 M2_D_CLK
AM30 M2_DDR_A6 240 M2_DDR_A6 240 R8 L8 R419 240
A6 ZQ A6 ZQ M1_DDR_A6 A6 ZQ R421 C534
C_CASZ M2_DDR_CASN R2 VDDC15_M1 R2 R2
AN30 M2_DDR_A7 A7 M2_DDR_A7 A7 56 0.01uF
VDDC15_M1 M1_DDR_A7 A7

C_WEZ M2_DDR_WEN T8 T8 T8 VDDC15_M0 1% 50V
AM31 M2_DDR_A8 A8 M2_DDR_A8 A8 M1_DDR_A8
C_ODT M2_DDR_ODT R3 B2 R3 B2 A8
AR33 M2_DDR_A9 A9 VDD_1 M2_DDR_A9 A9 VDD_1 R3 B2 R423
M2_DDR_CKE L7 D9 L7 D9 M1_DDR_A9 A9 VDD_1
C_CKE L7 D9 56
AP37 M2_DDR_A10 A10/AP VDD_2 M2_DDR_A10 A10/AP VDD_2 M1_DDR_A10
C_RST M2_DDR_RESET_N_1 R7 G7 R7 G7 A10/AP VDD_2 1%
M2_DDR_A11 DDR3 1.5V bypass Cap - Place these caps near Memory R7 G7
AU32 A11 VDD_3 M2_DDR_A11 A11 VDD_3 M1_DDR_A11
C_MCLK M2_D_CLK N7 K2 N7 K2 A11 VDD_3
AT32 M2_DDR_A12 A12/BC VDD_4 M2_DDR_A12 A12/BC VDD_4 N7 K2
M2_D_CLKN T3 K8 T3 K8 M1_DDR_A12 A12/BC VDD_4 M2_D_CLKN
C_MCLKZ T3 K8
AN34 M2_DDR_A13 A13 VDD_5 M2_DDR_A13 A13 VDD_5 M1_DDR_A13
C_CSB1 M2_DDR_CS1 T7 N1 T7 N1 A13 VDD_5
AP36 M2_DDR_A14 A14 VDD_6 M2_DDR_A14 A14 VDD_6 T7 N1 VDDC15_M0
M2_DDR_CS2 M7 N9 M7 N9 M1_DDR_A14 A14 VDD_6 VDDC15_M0
C_CSB2 M7 N9
M2_DDR_A15 NC_5 VDD_7 M2_DDR_A15 NC_5 VDD_7 M1_DDR_A15
R1 R1 NC_5 VDD_7
AR29 VDD_8 R1 M0_1_DDR_VREFDQ
VDD_8 VDD_8
C_DQ[0] M2_DDR_DQ0 M2 R9 M2 R9 M2 R9 M0_DDR_VREFDQ
AT30 M2_DDR_BA0 BA0 VDD_9 M2_DDR_BA0 BA0 VDD_9 M1_DDR_BA0
C_DQ[1] M2_DDR_DQ1 N8 N8 BA0 VDD_9
N8
R416
1K 1%
AT28 M2_DDR_BA1 BA1 M2_DDR_BA1 BA1
R410
1K 1%
M2_DDR_DQ2 M3 M3 M1_DDR_BA1 BA1
C_DQ[2] M3
AR31 M2_DDR_BA2 BA2 M2_DDR_BA2 BA2 M1_DDR_BA2
C_DQ[3] M2_DDR_DQ3 A1 A1 BA2
AT27 VDDQ_1 VDDQ_1 A1
C_DQ[4] M2_DDR_DQ4 J7 A8 J7 A8 VDDQ_1
AR32 M2_D_CLK CK VDDQ_2 M2_D_CLK CK VDDQ_2 J7 A8
M2_DDR_DQ5 K7 C1 K7 C1 M1_D_CLK CK VDDQ_2 C479
C_DQ[5] K7 C1 C472
1%
AR28 M2_D_CLKN CK VDDQ_3 M2_D_CLKN CK VDDQ_3 M1_D_CLKN 0.1uF
1%
C_DQ[6] M2_DDR_DQ6 K9 C9 K9 C9 CK VDDQ_3 0.1uF C483
K9 C9
R417
AT31 M2_DDR_CKE CKE VDDQ_4 M2_DDR_CKE CKE VDDQ_4 C474
R411
M2_DDR_DQ7 D2 D2 M1_DDR_CKE CKE VDDQ_4 1000pF
C_DQ[7] D2 1000pF
AR30 VDDQ_5 VDDQ_5 50V
1K
C_DQM[0] M2_DDR_DM0 L2 E9 L2 E9 VDDQ_5 50V
1K
AU29 M2_DDR_CS1 CS VDDQ_6 M2_DDR_CS2 CS VDDQ_6 L2 E9
M2_DDR_DQS0 K1 F1 K1 F1 M1_DDR_CS2 CS VDDQ_6
C_DQS[0] K1 F1
AT29 M2_DDR_ODT ODT VDDQ_7 M2_DDR_ODT ODT VDDQ_7 M1_DDR_ODT
C_DQSB[0] M2_DDR_DQS_N0 J3 H2 C502 J3 H2 C514 ODT VDDQ_7
M2_DDR_RASN 0.1uF M2_DDR_RASN 0.1uF J3 H2 C490 0.1uF
RAS VDDQ_8 RAS VDDQ_8 M1_DDR_RASN RAS VDDQ_8
K3 H9 C503 0.1uF K3 H9 C515 0.1uF K3 H9
AN27 M2_DDR_CASN CAS VDDQ_9 M2_DDR_CASN CAS VDDQ_9 M1_DDR_CASN C491 0.1uF
C_DQ[8]/DQU0 M2_DDR_DQ8 L3 L3 CAS VDDQ_9
AP25 M2_DDR_WEN WE M2_DDR_WEN WE L3
M2_DDR_DQ9 J1 J1 M1_DDR_WEN WE
C_DQ[9]/DQU1 J1
AN29 NC_1 NC_1 NC_1
C_DQ[10]/DQU2 M2_DDR_DQ10 T2 J9 T2 J9 T2 J9
AN24 M2_DDR_RESET_N RESET NC_2 M2_DDR_RESET_N RESET NC_2 M1_DDR_RESET_N
C_DQ[11]/DQU3 M2_DDR_DQ11 L1 L1 RESET NC_2
AN28 NC_3 NC_3 L1
C_DQ[12]/DQU4 M2_DDR_DQ12 L9 L9 NC_3
AN25 NC_4 NC_4 L9 SS_DDR3_4Gb_25n
IC404-*1
Hynix_DDR3_4Gb_25n
IC404-*2
C_DQ[13]/DQU5 M2_DDR_DQ13 F3 F3 NC_4 K4B4G1646D-BCMA H5TQ4G63CFR_RDC
AP28 M2_DDR_DQS0 DQSL M2_DDR_DQS2 DQSL F3

M2_DDR_DQ14 G3 G3 M1_DDR_DQS2 DQSL N3 M8 N3 M8
VDDC15_M0 VDDC15_M0 VDDC15_M1 VDDC15_M1
C_DQ[14]/DQU6 G3 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
AN26 M2_DDR_DQS_N0 DQSL M2_DDR_DQS_N2 DQSL M1_DDR_DQS_N2

P3
A2
P3
A2
C_DQ[15]/DQU7 M2_DDR_DQ15 DQSL N2

P8
P2
A3
A4
VREFDQ
H1 N2
P8
P2
A3
A4
VREFDQ
H1
AM26 R8
A5
A6 ZQ
L8 R8
A5
A6 ZQ
L8 M1_1_DDR_VREFDQ M2_1_DDR_VREFDQ
C_DQM[1] M2_DDR_DM1 C7 A9 C7 A9 C7 A9
R2
T8
A7
R2
T8
A7
M1_DDR_VREFDQ M2_DDR_VREFDQ
AM27 M2_DDR_DQS1 DQSU VSS_1 M2_DDR_DQS3 DQSU VSS_1 M1_DDR_DQS3
R3
A8
A9 VDD_1
B2 R3
A8
A9 VDD_1
B2
C_DQS[1] M2_DDR_DQS1 B7 B3 B7 B3 DQSU VSS_1 L7

R7
A10/AP VDD_2
D9
G7
L7
R7
A10/AP VDD_2
D9
G7
M2_DDR_DQS_N1 SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n SS_DDR3_2Gb Hynix_DDR3_2Gb SS_DDR3_4Gb_25n Hynix_DDR3_4Gb_25n B7 B3 A11 VDD_3 A11 VDD_3
R431
M2_DDR_DQS_N3
1K 1%
R414
AM28 DQSU VSS_2
1K 1%
N7 K2 N7 K2
DQSU VSS_2
R425
1K 1%
R408
1K 1%
IC405-*1 IC405-*2 IC405-*3 IC405-*4 IC406-*1 IC406-*2 A12/BC VDD_4 A12/BC VDD_4
M2_DDR_DQS_N1 E1 K4B4G1646D-BCMA H5TQ4G63CFR_RDC K4B2G1646Q-BCMA H5TQ2G63FFR-RDC

E1 K4B4G1646D-BCMA H5TQ4G63CFR_RDC M1_DDR_DQS_N3 DQSU VSS_2 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
C_DQSB[1] E1 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9
VSS_3 N3 M8 N3 M8 N3 M8 N3 M8 VSS_3 N3 M8 N3 M8
VSS_3
NC_5 VDD_7
VDD_8
R1
NC_5 VDD_7
VDD_8
R1
E7 G8 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
E7 G8 P7
A0
A1
VREFCA
P7
A0
A1
VREFCA
E7 G8
M2
N8
BA0 VDD_9
R9 M2
N8
BA0 VDD_9
R9
AR24 M2_DDR_DM0 DML VSS_4 P3

A2
P3
A2
P3
A2
P3
A2 M2_DDR_DM2 DML VSS_4 P3
A2
P3
A2
M1_DDR_DM2
M3
BA1
BA2
M3
BA1
BA2
C_DQ[16]/DQL0 M2_DDR_DQ16 D3 J2
N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1
D3 J2
N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1
DML VSS_4 J7
VDDQ_1
A1
A8 J7
VDDQ_1
A1
A8
AR26 M2_DDR_DM1 DMU VSS_5

P2
R8
A4
A5
L8
P2
R8
A4
A5
L8
P2
R8
A4
A5
L8
P2
R8
A4
A5
L8 M2_DDR_DM3 DMU VSS_5
P2
R8
A4
A5
L8
P2
R8
A4
A5
L8
D3 J2 K7
CK
CK
VDDQ_2
VDDQ_3
C1 K7
CK
CK
VDDQ_2
VDDQ_3
C1
M2_DDR_DQ17 J8 R2
A6 ZQ
R2
A6 ZQ
R2
A6 ZQ
R2
A6 ZQ
J8 R2
A6 ZQ
R2
A6 ZQ
M1_DDR_DM3 DMU VSS_5 K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
C_DQ[17]/DQL1 T8
A7
A8
T8
A7
A8
T8
A7
A8
T8
A7
A8
T8
A7
A8
T8
A7
A8 J8 L2
VDDQ_5
D2
E9 L2
VDDQ_5
D2
E9
C516 C518 C470 C473
AT23 VSS_6 VSS_6 CS VDDQ_6 CS VDDQ_6
1%
R3 B2 R3 B2 R3 B2 R3 B2 R3 B2 R3 B2
1%
1%
K1 F1 K1 F1
1%
A9 VDD_1 A9 VDD_1 A9 VDD_1 A9 VDD_1 A9 VDD_1 A9 VDD_1
C_DQ[18]/DQL2 M2_DDR_DQ18 E3 M1 L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9
E3 M1
L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9
VSS_6 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2 J3
ODT
RAS
VDDQ_7
VDDQ_8
H2
0.1uF 0.1uF 0.1uF 0.1uF
M2_DDR_DQ0
R7
A11 VDD_3
G7 R7
A11 VDD_3
G7 R7
A11 VDD_3
G7 R7
A11 VDD_3
G7 R7
A11 VDD_3
G7 R7
A11 VDD_3
G7
E3 M1 K3 H9 K3 H9
C519 C478
R432
M2_DDR_DQ16 CAS VDDQ_9 CAS VDDQ_9
C471
R415
AU26 DQL0 VSS_7 N7 K2 N7 K2 N7 K2 N7 K2
DQL0 VSS_7 N7 K2 N7 K2
C517
R426
R409
A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 A12/BC VDD_4 L3 L3
M2_DDR_DQ19 F7 M9
T3
A13 VDD_5
K8 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
F7 M9
T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
M1_DDR_DQ16 DQL0 VSS_7 WE
J1
WE
J1
1000pF 1000pF
C_DQ[19]/DQL3 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9 M7
VDD_6
N1
N9
T7
M7
A14 VDD_6
N1
N9
F7 M9 T2
RESET
NC_1
NC_2
J9 T2
RESET
NC_1
NC_2
J9
1000pF 1000pF
AR23 M2_DDR_DQ1 DQL1 VSS_8 NC_5 VDD_7
R1
NC_5 VDD_7
R1
NC_5 VDD_7
R1
NC_5 VDD_7
R1 M2_DDR_DQ17 DQL1 VSS_8 NC_5 VDD_7
R1
NC_5 VDD_7
R1
M1_DDR_DQ17
NC_3
L1
NC_3
L1
50V 50V
M2_DDR_DQ20 F2 P1
VDD_8 VDD_8 VDD_8 VDD_8
F2 P1
VDD_8 VDD_8
DQL1 VSS_8 L9 L9
50V
1K
NC_4 NC_4
R9 R9 R9
50V
1K
M2 M2 R9 M2 M2 R9 M2 M2 R9
C_DQ[20]/DQL4
1K
F3 T7 F3
1K
BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9 BA0 VDD_9
AR27 M2_DDR_DQ2 DQL2 VSS_9

N8
M3
BA1
N8
M3
BA1
N8
M3
BA1
N8
M3
BA1
N8
M3
BA1
N8
M3
BA1 F2 P1 G3
DQSL
DQSL
NC_6
G3
DQSL
DQSL
M2_DDR_DQ21 F8 P9
BA2
A1
BA2
A1
BA2
A1
BA2
A1
F8 P9
BA2
A1
BA2
A1
M1_DDR_DQ18 DQL2 VSS_9 C7 A9 C7 A9
C_DQ[21]/DQL5 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8 J7
CK
VDDQ_1
VDDQ_2
A8
F8 P9 B7
DQSU VSS_1
B3 B7
DQSU VSS_1
B3
AU23 M2_DDR_DQ3 DQL3 VSS_10 K7

CK VDDQ_3
C1 K7
CK VDDQ_3
C1 K7
CK VDDQ_3
C1 K7
CK VDDQ_3
C1
M2_DDR_DQ19 DQL3 VSS_10 K7
CK VDDQ_3
C1 K7
CK VDDQ_3
C1
M1_DDR_DQ19
DQSU VSS_2
VSS_3
E1
DQSU VSS_2
VSS_3
E1
C_DQ[22]/DQL6 M2_DDR_DQ22 H3 T1
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2
H3 T1
K9
CKE VDDQ_4
C9
D2
K9
CKE VDDQ_4
C9
D2 DQL3 VSS_10 E7
D3
DML VSS_4
G8
J2
E7
D3
DML VSS_4
G8
J2
AT26 M2_DDR_DQ4 DQL4 VSS_11

L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1 M2_DDR_DQ20 DQL4 VSS_11
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
L2
K1
CS
VDDQ_5
VDDQ_6
E9
F1
H3 T1 DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
M2_DDR_DQ23 H8 T9 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2
H8 T9 J3
ODT VDDQ_7
H2 J3
ODT VDDQ_7
H2 M1_DDR_DQ20 DQL4 VSS_11 E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1
C_DQ[23]/DQL7 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9 K3
RAS VDDQ_8
H9
H8 T9
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
AT25 M2_DDR_DQ5 DQL5 VSS_12 L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
M2_DDR_DQ21 DQL5 VSS_12 L3
CAS
WE
VDDQ_9
L3
CAS
WE
VDDQ_9
M1_DDR_DQ21 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9
C_DQM[2] M2_DDR_DM2 G2 T2
NC_1
J1
J9 T2
NC_1
J1
J9 T2
NC_1
J1
J9 T2
NC_1
J1
J9 G2 T2
NC_1
J1
J9 T2
NC_1
J1
J9
DQL5 VSS_12 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1
AT24 M2_DDR_DQ6 DQL6

RESET NC_2
NC_3
L1
RESET NC_2
NC_3
L1
RESET NC_2
NC_3
L1
RESET NC_2
NC_3
L1
M2_DDR_DQ22 DQL6
RESET NC_2
NC_3
L1
RESET NC_2
NC_3
L1 G2 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9
M2_DDR_DQS2 H7 NC_4
L9
NC_4
L9
NC_4
L9
NC_4
L9
H7 NC_4
L9
NC_4
L9
M1_DDR_DQ22 DQL6 H7
DQL6
H7
DQL6
C_DQS[2] F3
G3
DQSL NC_6
T7 F3
G3
DQSL
F3
G3
DQSL NC_6
T7 F3
G3
DQSL
F3
G3
DQSL NC_6
T7 F3
G3
DQSL
H7
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1
AR25 M2_DDR_DQ7 DQL7 DQSL DQSL DQSL DQSL

M2_DDR_DQ23 DQL7 DQSL DQSL
M1_DDR_DQ23
D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9
C_DQSB[2] M2_DDR_DQS_N2 B1 C7
DQSU VSS_1
A9 C7
DQSU VSS_1
A9 C7
DQSU VSS_1
A9 C7
DQSU VSS_1
A9
B1 C7
DQSU VSS_1
A9 C7
DQSU VSS_1
A9 DQL7 C3
C8
DQU1 VSSQ_3
D1
D8
C3
C8
DQU1 VSSQ_3
D1
D8
VSSQ_1
B7
DQSU VSS_2
VSS_3
B3
E1
B7
DQSU VSS_2
VSS_3
B3
E1
B7
DQSU VSS_2
VSS_3
B3
E1
B7
DQSU VSS_2
VSS_3
B3
E1
VSSQ_1
B7
DQSU VSS_2
VSS_3
B3
E1
B7
DQSU VSS_2
VSS_3
B3
E1 B1 C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8
D7 B9 E7
D3
DML VSS_4
G8
J2
E7
D3
DML VSS_4
G8
J2
E7
D3
DML VSS_4
G8
J2
E7
D3
DML VSS_4
G8
J2 D7 B9
E7
D3
DML VSS_4
G8
J2
E7
D3
DML VSS_4
G8
J2
VSSQ_1 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9 A2
DQU4
DQU5
VSSQ_6
VSSQ_7
F9
AN23 M2_DDR_DQ8 DQU0 VSSQ_2

DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
M2_DDR_DQ24 DQU0 VSSQ_2
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8 D7 B9 B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
M2_DDR_DQ24 C3 D1
E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1
C3 D1
E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1
M1_DDR_DQ24 DQU0 VSSQ_2 DQU7 VSSQ_9 DQU7 VSSQ_9
C_DQ[24]/DQU0 F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
C3 D1
AN21 M2_DDR_DQ9 DQU1 VSSQ_3 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 M2_DDR_DQ25 DQU1 VSSQ_3 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9
M1_DDR_DQ25
C_DQ[25]/DQU1 M2_DDR_DQ25 C8 D8 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1
C8 D8 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1 DQU1 VSSQ_3
AM25 M2_DDR_DQ10 DQU2 VSSQ_4
H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9

H8
G2
DQL5 VSS_12
T9 H8
G2
DQL5 VSS_12
T9
C8 D8
M2_DDR_DQ26 C2 E2 H7
DQL6
H7
DQL6
H7
DQL6
H7
DQL6
C2 E2
H7
DQL6
H7
DQL6
C_DQ[26]/DQU2 DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1
DQL7
VSSQ_1
B1
C2 E2
AM21 M2_DDR_DQ11 DQU3 VSSQ_5 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9
M2_DDR_DQ27 DQU3 VSSQ_5 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9
M1_DDR_DQ27
M2_DDR_DQ27 A7 E8
C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
A7 E8
C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
DQU3 VSSQ_5
C_DQ[27]/DQU3
AM23 M2_DDR_DQ12 DQU4 VSSQ_6
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8 M2_DDR_DQ28 DQU4 VSSQ_6
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8
C8
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
D8
E2
E8
A7 E8 * DDR_VTT
M2_DDR_DQ28 A2 F9 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9
A2 F9 A2
DQU4 VSSQ_6
F9 A2
DQU4 VSSQ_6
F9 M1_DDR_DQ28 DQU4 VSSQ_6
C_DQ[28]/DQU4 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1 B8
DQU5 VSSQ_7
G1
A2 F9
AM22 M2_DDR_DQ13 DQU5 VSSQ_7 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
M2_DDR_DQ29 DQU5 VSSQ_7 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
M1_DDR_DQ29
C_DQ[29]/DQU5 M2_DDR_DQ29 B8 G1 B8 G1 DQU5 VSSQ_7
AM24 M2_DDR_DQ14 DQU6 VSSQ_8 M2_DDR_DQ30 DQU6 VSSQ_8 B8 G1
M2_DDR_DQ30 A3 G9 A3 G9 M1_DDR_DQ30 DQU6 VSSQ_8
C_DQ[30]/DQU6 A3 G9
AT22 M2_DDR_DQ15 DQU7 VSSQ_9 M2_DDR_DQ31 DQU7 VSSQ_9 SS_DDR3_2Gb Hynix_DDR3_2Gb
M1_DDR_DQ31
C_DQ[31]/DQU7 M2_DDR_DQ31 IC406-*3
K4B2G1646Q-BCMA
IC406-*4
H5TQ2G63FFR-RDC
DQU7 VSSQ_9
AR22 VDDC15_M1 +3.3V_NORMAL
C_DQM[3] M2_DDR_DM3 N3
P7
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8
VDDC15_M0 +3.3V_NORMAL
AP21 P3
A1
A2
P3
A1
A2
C_DQS[3] M2_DDR_DQS3 N2
P8
A3 VREFDQ
H1 N2
P8
A3 VREFDQ
H1
IC407
AP22 P2
A4
P2
A4
C_DQSB[3] M2_DDR_DQS_N3 R8
R2
T8
A5
A6
A7
ZQ
L8 R8
R2
T8
A5
A6
A7
ZQ
L8
IC402 AP2303MPTR-G1 [EP]
A8 A8
AP2303MPTR-G1 [EP]
CIS21J121
R3 B2 R3 B2
A9 VDD_1 A9 VDD_1
L7 D9 L7 D9
A10/AP VDD_2 A10/AP VDD_2
R7 G7 R7 G7
A11 VDD_3 A11 VDD_3
N7 K2 N7 K2
C545
CIS21J121
A12/BC VDD_4 A12/BC VDD_4
L403
T3 K8 T3 K8
A13 VDD_5 A13 VDD_5
N1 T7 N1
M7
NC_5
VDD_6
VDD_7
N9 M7
A14
NC_5
VDD_6
VDD_7
N9
VIN NC_3 10uF
R1 R1
C544
L401
VDD_8 VDD_8
M2
N8
BA0 VDD_9
R9 M2
N8
BA0 VDD_9
R9
VIN NC_3 1 8 10V

M3
BA1
BA2
M3
BA1
BA2
1 8 10uF
THERMAL
A1 A1
J7
VDDQ_1
A8 J7
VDDQ_1
A8
10V C537
OPT K7
CK VDDQ_2
C1 K7
CK VDDQ_2
C1
C421
THERMAL
CK VDDQ_3 CK VDDQ_3
OPT K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
DDR_VTT_1 10uF GND NC_2
0 R440 D2 D2
9
VDDQ_5 VDDQ_5
10uF
+1.5V_Bypass Cap
L2 E9 L2 E9
M0_DDR_RESET_N 0 R441 K1
CS VDDQ_6
F1 K1
CS VDDQ_6
F1
GND NC_2 10V 2 7
+1.5V_Bypass Cap +1.5V_Bypass Cap
ODT VDDQ_7 ODT VDDQ_7
9
M1_DDR_RESET_N
J3
K3
RAS VDDQ_8
H2
H9
J3
K3
RAS VDDQ_8
H2
H9 10V 2 7
CIS21J121
CAS VDDQ_9 CAS VDDQ_9
L3 L3
WE WE
J1 J1
Close to DDR Power Pin Close to DDR Power Pin

T2
RESET
NC_1
NC_2
J9 T2
RESET
NC_1
NC_2
J9
Close to DDR Power Pin

DDR_VTT R446
VREFEN VCNTL
L402
L1 L1
NC_3
L9
NC_3
L9
R443 10K
F3
DQSL
NC_4
NC_6
T7 F3
DQSL
NC_4
VREFEN VCNTL 3 6
G3
DQSL
G3
DQSL 10K
C C7 A9 C7 A9 3 6 1/16W
CIS21J121
DQSU VSS_1 DQSU VSS_1

R434 NXP_DDR_RES0_TR C B7
DQSU VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1
1K B Q400 R436 NXP_DDR_RES1_TR E7

D3
DML
VSS_3
VSS_4
G8
J2
E7
D3
DML
VSS_3
VSS_4
G8
J2
1/16W 1% VOUT NC_1
L400
M0_DDR_RESET_N_1 1K B Q401
DMU VSS_5
VSS_6
J8
DMU VSS_5
VSS_6
J8
1% 4 5
MMBT3904(NXP) M1_DDR_RESET_N_1
E3
F7
DQL0 VSS_7
M1
M9
E3
F7
DQL0 VSS_7
M1
M9
VOUT NC_1
MMBT3904(NXP) F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
F2
F8
DQL1
DQL2
VSS_8
VSS_9
P1
P9
4 5
DQL3 VSS_10 DQL3 VSS_10
H3 T1 H3 T1
E VDDC15_M1 VDDC15_M1
H8
G2
DQL4
DQL5
VSS_11
VSS_12
T9 H8
G2
DQL4
DQL5
VSS_11
VSS_12
T9
VDDC15_M0
E H7
DQL6
H7
DQL6
R435
DQL7 DQL7
B1 B1
R437
VSSQ_1 VSSQ_1
10K
D7 B9 D7 B9
10K
C3 D1 C3 D1
C C C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
E2
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
E2
KEC_DDR_RES0_TR KEC_DDR_RES1_TR A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E8
F9
A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E8
F9
B Q400-*1 B Q401-*1 B8
A3
DQU6 VSSQ_8
G1
G9
B8
A3
DQU6 VSSQ_8
G1
G9
C536 C541 C542
2N3904S
C414 C417 C535 10uF 10uF 10uF C546
1%
1/16W
10K
R445
2N3904S 10uF 10uF 10uF 25V 25V 25V 0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
E 25V 25V 25V

0.1uF
0.1uF
0.1uF
E C543 16V
1%
1/16W
10K
R444
OPT 0.1uF
0 R442 16V
M2_DDR_RESET_N
C482
C492
C493
C504
C505
C506
C475
C476
C480
C
R438 NXP_DDR_RES2_TR
1K B Q402
M2_DDR_RESET_N_1 MMBT3904(NXP)
E
R439
10K
C
KEC_DDR_RES2_TR
B Q402-*1
2N3904S
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES E

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN3_DDR 4
COMPENSATION_DONE_1
DPC_CTRL
OLED
+3.3V_NORMAL
12V_ON Jtag I/F

C600 For Main Clock for MSD808KWD
R612 JTAG
R614 JTAG
R616 JTAG
0.1uF
JTAG
1K
1K
1K
SW600 MAIN Clock(24Mhz)
JS2235S
X-TAL_1
P600
12505WS-10A00 5pF
GND_1
JTAG
XIN_MAIN
1
C614
TRST_N0
TDI0 1 6 TDO0
R635
2
R602 R604 TDI0
24MHz
X600
1M
0 0
3
OPT OPT TDO0
TDI0_1 2 5 TDO0_1
4
TMS0
4
R603 JTAG R605
0 0
X-TAL_2
GND_2
OPT OPT 5
TCK0 5pF
3 4 XOUT_MAIN
6
SOC_RESET C615
7
JTAG
1K
R609
8 System Clock for Analog block(24Mhz)
9
10
11
IC100 IC100
LGE5331(LM15U) LGE5331(LM15U)
R636 0 T2 AG2
D0-_HDMI3 RXA0N LINE_IN_0L COMP1/AV1/DVI_L_IN R623 68 0.047uF C619 AB2 B1
R637 0 T3 AG1 2.2uF C601 RIN0M TN EPHY_TDN
D0+_HDMI3 RXA0P LINE_IN_0R COMP1/AV1/DVI_R_IN R624 33 0.047uF C620 AB1 C1
U2 AG3 2.2uF C602 SC_R
R625 68 C621 RIN0P TP EPHY_TDP
D1-_HDMI3 RXA1N LINE_IN_1L SC_L_IN 0.047uF AA3 A2
U3 AH1 2.2uF C603 33 C622 GIN0M RN EPHY_RDN
D1+_HDMI3 RXA1P LINE_IN_1R SC_R_IN R626 0.047uF AA1 B2
V2 AH2 2.2uF C604 SC_G GIN0P RP EPHY_RDP
D2-_HDMI3 RXA2N LINE_IN_2L R627 68 0.047uF C623 Y3
MHL Port V1 AH3 BIN0M
D2+_HDMI3 RXA2P LINE_IN_2R R628 33 0.047uF C624 Y2
R3 AJ2 SC_B BIN0P
CK-_HDMI3 RXACKN LINE_IN_3L C625 AA2
T1 AJ3 1000pF
SOGIN0 0 R642
CK+_HDMI3 RXACKP LINE_IN_3R W5 E5
W1 SC_ID HSYNC0 GPIO80/LED[1] I2C_SCL2
DDC_SCL_3 DDCDA_CK/GPIO42 W4 F4
W2 AK3 SC_FB VSYNC0 GPIO79/LED[0] I2C_SDA2
DDC_SDA_3 DDCDA_DA/GPIO43 LINE_OUT_0L 0 R643
V3 AL1
HDMI_HPD_3 HOTPLUGA/GPIO34 LINE_OUT_0R R629 68 0.047uF C626 AE1
R607 0 W3 AL2 RIN1M
I2C_SCL5 CEC/GPIO5 LINE_OUT_2L SCART_Lout R630 33 0.047uF C627 AD3
AL3 COMP1_Pr 68 0.047uF RIN1P
LINE_OUT_2R SCART_Rout R631 C628 AD1
N2 33 0.047uF GIN1M
D0-_HDMI2 RXB0N R632 C629 AD2
N3 AF2 COMP1_Y
HP_LOUT R633 68 0.047uF GIN1P
D0+_HDMI2 RXB0P EARPHONE_OUT_L C630 AC2
P2 AF3 BIN1M
D1-_HDMI2 RXB1N EARPHONE_OUT_R HP_ROUT R634 33 0.047uF C631 AB3
P3 COMP1_Pb BIN1P
D1+_HDMI2 RXB1P C605 1uF 1000pF C632 AC3
R2 Y6 SOGIN1
D2-_HDMI2 RXB2N ARC0 HDMI_ARC Y5
R1 HSYNC1
D2+_HDMI2 RXB2P Y4
M3 AK2 VSYNC1
CK-_HDMI2 RXBCKN AUVAG G4
N1 AK1 C606 L600 HWRESET SOC_RESET
CK+_HDMI2 RXBCKP AUVRM 1uF AC5
V5 10uF PZ1608U121-2R0TF
C609 RIN2M
DDC_SCL_2 DDCDB_CK/GPIO44 10V AB4 AU2
V6 C13 RIN2P XIN XIN_MAIN
DDC_SDA_2 DDCDB_DA/GPIO45 I2S_IN_BCK/GPIO99 TRST_N0 AB5 AT2
U4 B14 JTAG 0 R606 GIN2M XOUT XOUT_MAIN
47K
HDMI_HPD_2 +3.3V_NORMAL
JTAG
R615
HOTPLUGB/GPIO35 I2S_IN_SD/GPIO100 TCK0 AC6

R617 0 W6 B13 JTAG 1K R608 GIN2P
I2C_SDA5 CEC_1/GPIO6 I2S_IN_WS/GPIO98 AA6 K4
R610 BIN2M IRIN
AA5
G2 F16 22 BIN2P
RXC0N I2S_OUT_BCK/GPIO105 AUD_SCK AB6
G3 F15 R611 SOGIN2
RXC0P I2S_OUT_MCK/GPIO104 AC4 C5
H2 E16 22 HSYNC2 USB0_DM WIFI_DM
R618 AUD_LRCK B5
RXC1N I2S_OUT_WS/GPIO103 22
H3 D16 USB0_DP WIFI_DP
RXC1P I2S_OUT_SD/GPIO106 AUD_LRCH C4
J2 E15 R619 68 USB1_DM USB_DM2
RXC2N I2S_OUT_SD1/GPIO107 C613 0.047uF AE4 B4
J1 D15 C607 VCOM USB1_DP USB_DP2
RXC2P I2S_OUT_SD2/GPIO108 DPC_CTRL A4
F3 E14 22pF USB2_DM USB_DM1
RXCCKN I2S_OUT_SD3/GPIO109 12V_ON R620 33 C616 0.047uF AE5 B3
G1 TU_CVBS CVBS0 USB2_DP USB_DP1
RXCCKP C608 C611 R621 33 C617 0.047uF AF6 AR4
R5 AJ6 0 R644 AV1_CVBS_IN CVBS1 USB_SSTXP_1
MHL_DET_LM15 22pF 22pF R622 33 C618 0.047uF AE6 AT4
I2C_SCL4 DDCDC_CK/GPIO46 GPIO_PM14/GPIO27
R6 AH5 SC_CVBS_IN CVBS2 USB_SSTXN_1
I2C_SDA4 DDCDC_DA/GPIO47 GPIO_PM15/GPIO28 COMPENSATION_DONE_1 AU4
P4 AH4 USB_DM_PSS_1
CPU_VID1 HOTPLUGC/GPIO36 GPIO_PM16/GPIO29 /MHL_OCP AR5 AC-coupling CAP
T6 USB_DP_PSS_1
CORE_VID1 CEC_2/GPIO7 C612 AU5 Place near by MST
1000pF USB_SSRXP_1
50V AT5
K2 OPT USB_SSRXN_1
D0-_HDMI1 RXD0N JTAG AR7 C633 0.1uF
K3 USB_SSTXP_0 SSUSB_TXP
D0+_HDMI1 RXD0P R613 AT7 C634 0.1uF
L2 0 USB_SSTXN_0 SSUSB_TXN
D1-_HDMI1 RXD1N AU7
L3 TDO0_1 USB_DM_PSS_0 USB_DM3
D1+_HDMI1 RXD1P AF5 AR8
M2 DTV/MNT_V_OUT CVBSOUT1 USB_DP_PSS_0 USB_DP3
D2-_HDMI1 RXD2N AU8
M1 USB_SSRXP_0 SSUSB_RXP
D2+_HDMI1 RXD2P AT8
J3 USB_SSRXN_0 SSUSB_RXN
CK-_HDMI1 RXDCKN
K1
CK+_HDMI1 RXDCKP
T5
DDC_SCL_1 DDCDD_CK/GPIO48
T4
DDC_SDA_1 DDCDD_DA/GPIO49
U6
HDMI_HPD_1 HOTPLUGD/GPIO37
U5
JTAG CEC_3/GPIO8
R600
0 F14
TMS0 SPDIF_IN/GPIO101
G14
SPDIF_OUT SPDIF_OUT/GPIO102
JTAG
R601
0
TDI0_1
R639
100
HP_LOUT HP_LOUT_MAIN
R640
OPT C635
22K
0.01uF
OPT
R638
100
HP_ROUT HP_ROUT_MAIN
OPT
R641
C636
22K
0.01uF
OPT
Close to Main soc

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN4_EXT_IN/OUTPUT 04
AF33
AF34
AG10
AG11
AG12
AG13
AG16
AG17
AG23
AG24
AG25
AG26
AG27
AG28
AG29
AG30
AG31
AG32
AG33
AG34
AG36
AH10
AH11
AH12
AH13
AH16
AH17
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AH34
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ37
AK10
AK11
AK12
AK13
AK14
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AK34
AL13
AL14
AL16
AL17
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AL34
AL36
AM20
AN22
AN35
AN36
AN37
AP24
AP27
AP30
AP33
AT36
AU22
AU25
AU28
AU31
AU34
AG8
AG9
AH8
AH9
AJ7
AJ8
AJ9
AK7
AK8
AK9
AL8
AL9
AM3
AN3
AP7
AR1
AR3
AR6
AR9
AT1
AT3
AT6
GND_430
GND_431
GND_432
GND_433
GND_434
GND_435
GND_436
GND_437
GND_438
GND_439
GND_440
GND_441
GND_442
GND_443
GND_444
GND_445
GND_446
GND_447
GND_448
GND_449
GND_450
GND_451
GND_452
GND_453
GND_454
GND_455
GND_456
GND_457
GND_458
GND_459
GND_460
GND_461
GND_462
GND_463
GND_464
GND_465
GND_466
GND_467
GND_468
GND_469
GND_470
GND_471
GND_472
GND_473
GND_474
GND_475
GND_476
GND_477
GND_478
GND_479
GND_480
GND_481
GND_482
GND_483
GND_484
GND_485
GND_486
GND_487
GND_488
GND_489
GND_490
GND_491
GND_492
GND_493
GND_494
GND_495
GND_496
GND_497
GND_498
GND_499
GND_500
GND_501
GND_502
GND_503
GND_504
GND_505
GND_506
GND_507
GND_508
GND_509
GND_510
GND_511
GND_512
GND_513
GND_514
GND_515
GND_516
GND_517
GND_518
GND_519
GND_520
GND_521
GND_522
GND_523
GND_524
GND_525
GND_526
GND_527
GND_528
GND_529
GND_530
GND_531
GND_532
GND_533
GND_534
GND_535
GND_536
GND_537
GND_538
GND_539
GND_540
GND_541
GND_542
GND_543
GND_544
GND_545
GND_546
GND_547
GND_548
GND_549
GND_550
GND_551
GND_552
GND_553
GND_554
GND_555
GND_556
GND_557
GND_558
GND_559
GND_560
GND_561
GND_562
GND_563
GND_564
GND_565
GND_566
GND_567
GND_568
GND_569
GND_570
GND_571
GND_572
A3 W9
GND_1 GND_287
A9 W10
GND_2 GND_288
A19 W11
GND_3 GND_289
A22 W15
GND_4 GND_290
A25 W16
GND_5 GND_291
A28 W17
GND_6 GND_292
A31 W18
GND_7 GND_293
A34 W19
GND_8 GND_294
A36 W20
GND_9 GND_295
B6 W21
GND_10 GND_296
B19 W22
GND_11 GND_297
B36 W27
GND_12 GND_298
B37 W28
GND_13 GND_299
C2 W29
GND_14 GND_300
C3 W30
GND_15 GND_301
C19 W31
GND_16 GND_302
C36 Y9
GND_17 GND_303
C37 Y10
GND_18 GND_304
D10 Y11
GND_19 GND_305
D11 Y15
GND_20 GND_306
D12 Y16
GND_21 GND_307
D13 Y17
GND_22 GND_308
D14 Y18
GND_23 GND_309
D22 Y19
GND_24 GND_310
D25 Y20
GND_25 GND_311
D29 Y21
GND_26 GND_312
D32 Y22
GND_27 GND_313
D36 Y30
GND_28 GND_314
D37 Y31
GND_29 GND_315
E10 Y34
GND_30 GND_316
E11 Y37
GND_31 GND_317
E12 AA7
GND_32 GND_318
E13 AA8
GND_33 GND_319
E34 AA9
GND_34 GND_320
E35 AA10
GND_35 GND_321
E36 AA11
GND_36 GND_322
F11 AA12
GND_37 GND_323
F12 AA13
GND_38 GND_324
F13 AA14
GND_39 GND_325
F17 AA15
GND_40 GND_326
F26 AA16
GND_41 GND_327
F28 AA17
GND_42 GND_328
F29 AA18
GND_43 GND_329
F30 AA19
GND_44 GND_330
F31 AA20
GND_45 GND_331
F32 AA22
GND_46 GND_332
IC100
F33 AA23
GND_47 GND_333
G6 AA24
GND_48 GND_334
G9 AA25
GND_49 GND_335
G11 AA26
GND_50 GND_336
G12 AA30
GND_51 GND_337
G13 AA31
GND_52 GND_338
G15 AA35
GND_53 GND_339
G16 AB7
GND_54 GND_340
G17 AB8
GND_55 GND_341
G18 AB9
GND_56 GND_342
LGE5331(LM15U)
G19 AB10
GND_57 GND_343
G20 AB11
GND_58 GND_344
G21 AB12
GND_59 GND_345
G22 AB13
GND_60 GND_346
G23 AB14
GND_61 GND_347
G24 AB15
GND_62 GND_348
G25 AB16
GND_63 GND_349
G27 AB17
GND_64 GND_350
G28 AB18
GND_65 GND_351
G29 AB19
GND_66 GND_352
G30 AB20
GND_67 GND_353
G31 AB30
GND_68 GND_354
G32 AB31
GND_69 GND_355
G35 AB32
GND_70 GND_356
H8 AB33
GND_71 GND_357
H9 AB34
GND_72 GND_358
H10 AC7
GND_73 GND_359
H11 AC8
GND_74 GND_360
H12 AC9
GND_75 GND_361
H13 AC10
GND_76 GND_362
H14 AC11
GND_77 GND_363
H15 AC12
GND_78 GND_364
H16 AC13
GND_79 GND_365
H17 AC14
GND_80 GND_366
H18 AC15
GND_81 GND_367
H19 AC16
GND_82 GND_368
H20 AC17
GND_83 GND_369
H21 AC18
GND_84 GND_370
H22 AC19
GND_85 GND_371
H23 AC20
GND_86 GND_372
H24 AC31
GND_87 GND_373
H25 AC32
GND_88 GND_374
H26 AC33
GND_89 GND_375
H27 AC34
GND_90 GND_376
H28 AC35
GND_91 GND_377
H29 AD9
GND_92 GND_378
H30 AD10
GND_93 GND_379
H31 AD11
GND_94 GND_380
H32 AD12
GND_95 GND_381
J7 AD13
GND_96 GND_382
J8 AD14
GND_97 GND_383
J9 AD15
GND_98 GND_384
J10 AD16
GND_99 GND_385
J11 AD17
GND_100 GND_386
J12 AD18
GND_101 GND_387
J13 AD19
GND_102 GND_388
J14 AD20
GND_103 GND_389
J16 AD31
GND_104 GND_390
J17 AD32
GND_105 GND_391
J18 AD33
GND_106 GND_392
J19 AD34
GND_107 GND_393
J20 AE7
GND_108 GND_394
J21 AE8
GND_109 GND_395
J22 AE9
GND_110 GND_396
J23 AE10
GND_111 GND_397
J24 AE11
GND_112 GND_398
J25 AE12
GND_113 GND_399
J26 AE13
GND_114 GND_400
J27 AE14
GND_115 GND_401
J28 AE15
GND_116 GND_402
J29 AE16
GND_117 GND_403
J30 AE17
GND_118 GND_404
J31 AE18
GND_119 GND_405
K7 AE19
GND_120 GND_406
K8 AE20
GND_121 GND_407
K9 AE27
GND_122 GND_408
K10 AE28
GND_123 GND_409
K11 AE29
GND_124 GND_410
K12 AE30
GND_125 GND_411
K13 AE31
GND_126 GND_412
K14 AE32
GND_127 GND_413
K15 AE33
GND_128 GND_414
K16 AE34
GND_129 GND_415
K17 AE35
GND_130 GND_416
K18 AF7
GND_131 GND_417
K19 AF8
GND_132 GND_418
K20 AF9
GND_133 GND_419
K21 AF10
GND_134 GND_420
K22 AF11
GND_135 GND_421
K23 AF16
GND_136 GND_422
K24 AF17
GND_137 GND_423
K25 AF27
GND_138 GND_424
K26 AF28
GND_139 GND_425
K27 AF29
GND_140 GND_426
K28 AF30
GND_141 GND_427
K29 AF31
GND_142 GND_428
K30 AF32
GND_143 GND_429
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_238
GND_239
GND_240
GND_241
GND_242
GND_243
GND_244
GND_245
GND_246
GND_247
GND_248
GND_249
GND_250
GND_251
GND_252
GND_253
GND_254
GND_255
GND_256
GND_257
GND_258
GND_259
GND_260
GND_261
GND_262
GND_263
GND_264
GND_265
GND_266
GND_267
GND_268
GND_269
GND_270
GND_271
GND_272
GND_273
GND_274
GND_275
GND_276
GND_277
GND_278
GND_279
GND_280
GND_281
GND_282
GND_283
GND_284
GND_285
GND_286
K31
L9
L16
L18
L19
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L34
L37
M9
M15
M16
M17
M18
M19
M26
M27
M28
M29
M30
M31
N7
N8
N9
N15
N16
N17
N18
N19
N27
N28
N29
N30
N31
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P27
P28
P29
P30
P31
P34
P37
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R27
R28
R29
R30
R31
T7
T8
T9
T10
T11
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T27
T28
T29
T30
T31
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U20
U21
U22
U23
U24
U28
U29
U30
U31
U34
U37
V8
V9
V10
V11
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V28
V29
V30
V31
W8

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM15U_GND 05
CI Region * Option name of this page : CI_SLOT
(because of Hong Kong)
CI SLOT
+5V_CI_ON
CI_DATA[0-7]
CI TS INPUT
CI_SLOT
CI_DATA[0-7]
+5V_NORMAL CI_SLOT AR903 33 TPO_DATA[7]
C902 CI_MDI[7]
10uF TPO_DATA[6]
CI_SLOT 10V CI_MDI[6]
TPO_DATA[0-7]
R906 TPO_DATA[5]
CI_MDI[5]
10K TPO_DATA[4]
CI_MDI[4]
/CI_CD1 JK900
10125901-015LF CI_SLOT
CI_SLOT AR902 33
R912 35 1 CI_MDI[3]
100 CI_DATA[3] TPO_DATA[3]
CI_SLOT 36 2 CI_MDI[2]
AR901 CI_DATA[4] TPO_DATA[2]
33 37 3 CI_MDI[1]
CI_DATA[5] R916 TPO_DATA[1]
TPI_DATA[4] 38 4 10K CI_MDI[0]
CI_DATA[6]
TPI_DATA[5] 39 5 TPO_DATA[0]
CI_DATA[7] TPO_DATA[0-7]
TPI_DATA[6] 40 6
R918 33 CI_SLOT
TPI_DATA[7] 41 7 R914 47 CI_SLOT CI_MISTRT TPO_SOP
CI_ADDR[10] /PCM_CE1 R919 33 CI_SLOT
42 8 CI_MIVAL_ERR TPO_VAL
CI_SLOT R908 10K R920 100 CI_SLOT
43 9 CI_OE CI_MCLKI TPO_CLK
CI_ADDR[11]
CI_IORD 44 10 +5V_NORMAL
CI_ADDR[9]
CI_IOWR 45 11
CI_ADDR[8]
46 12 R917
CI_ADDR[13] 10K
CI_MDI[0] 47 13
CI_ADDR[14]
CI_MDI[1] 48 14 CI_SLOT
CI_MDI[2] 49 15 CI_WE
50 16 R915 100
CI_MDI[3] CI_SLOT
CAM_IREQ_N
51 17 CI_SLOT
CI_MDI[4]
GND
C901
0.1uF
52
53
18
19
C903
0.1uF
C904
0.1uF
CI HOST I/F
CI_SLOT GND CI_SLOT
CI_MDI[5] 54 20
+5V_NORMAL CI_ADDR[12]
CI_MDI[6] 55 21 CLOSE TO MSTAR
CI_ADDR[7]
R900 56 22 GND
CI_MDI[7] R909 10K CI_ADDR[6]
10K CI_SLOT CI_SLOT
57 23
CI_ADDR[5] AR906
CI_SLOT R901 47 CI_SLOT 58 24
PCM_RESET CI_ADDR[4] 33
R902 47 CI_SLOT 59 25
CAM_WAIT_N CI_ADDR[3] CI_ADDR[0] EB_ADDR[0]
CLOSE TO MSTAR 60 26
REG CI_ADDR[2] CI_ADDR[1] EB_ADDR[1]
R903 33 CI_SLOT 61 27
TPI_CLK CI_ADDR[1] CI_ADDR[2] EB_ADDR[2]
R904 33 CI_SLOT
TPI_VAL 62 28 EB_ADDR[3]
CI_ADDR[0] CI_ADDR[3]
R905 33 CI_SLOT 63 29
TPI_SOP
CI_DATA[0]
CI_SLOT 64 30
AR900 33 CI_DATA[1]
65 31 CI_ADDR[0-14]
TPI_DATA[0] CI_DATA[2]
66 32 CI_SLOT
TPI_DATA[1] 67 33 AR907
TPI_DATA[2] 68 34 33
TPI_DATA[3]
CI_ADDR[4] EB_ADDR[4]
G2 69 G1
R910 CI_ADDR[5] EB_ADDR[5]
100 CI_ADDR[6] EB_ADDR[6]
/CI_CD2
+5V_NORMAL CI_SLOT GND
CI_SLOT
CI_SLOT GND AR908 33
C900
2pF CI_ADDR[8] EB_ADDR[8]
R907
50V CI_ADDR[9] EB_ADDR[9]
10K GND
CLOSE TO MSTAR CI_SLOT
CI_SLOT
CI_MISTRT AR909 33
CI_MIVAL_ERR CI_ADDR[12] EB_ADDR[12]
CI_MCLKI CI_ADDR[14] EB_ADDR[14]
REG CAM_REG_N
CI_SLOT
AR913 33
CI_OE EB_OE_N
CI_WE EB_WE_N
CI_IORD EB_BE_N1
CI DETECT +3.3V_NORMAL
CI_IOWR EB_BE_N0
CI_SLOT
IC900
74LVC1G32GW +3.3V_NORMAL
B 1 5 VCC
/CI_CD2 CI_SLOT
A 2
/CI_CD1 AR904 33
GND 3 4 Y R911 CI_DATA[0] EB_DATA[0]
CI_SLOT
10K CI_DATA[1] EB_DATA[1]

CI_DATA[2] EB_DATA[2]
OR_GATE_CI_TI OR_GATE_CI_TOSHIBA CI_DATA[3] EB_DATA[3]
CI_DATA[0-7]
IC900-*1 IC900-*2
SN74LVC1G32DCKR TOSHIBA ELECTRONICS KOREA CORPORATION
EB_DATA[0-7]
A VCC IN_B VCC
CI_SLOT
1 5 1 5
CAM_CD1_N AR905 33
B IN_A R913 CI_DATA[4] EB_DATA[4]
2 2
47 CI_DATA[5] EB_DATA[5]
GND Y GND OUT_Y
CI_SLOT
3 4 3 4
CI_DATA[0-7]
CI POWER ENABLE CONTROL EB_DATA[0-7]
IC901
+5V_NORMAL
AP2151WG-7 +5V_CI_ON
IN OUT
5 1
C905 CI_SLOT
0.1uF C906
50V GND
2 1uF
CI_SLOT R923
25V
10K
R922 CI_SLOT
100 EN FLG CI_SLOT
PCM_5V_CTL 4 3
R921
10K
CI_SLOT

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UF71/7500 2014-07-24
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCI 9
PCMCI
[ED94 ONLY] PWR
MMBT3906(NXP)
+3.5V_ST
MMBT3906(NXP)
+3.5V_ST
10K
R2391
R2389
10K
R2347
Q2398
RL_ON 10K
1
R2390
Q2303
10K
DPC_CTRL +3.3V_NORMAL RESET_IC_DIODES RESET_IC_DIODES
3
2
IC2307-*1
P2399 IC2308-*1
SMAW200-H24S5 R2394
Power_DET APX803D29
3
APX803D29
1K
RESET 2 3 VCC RESET VCC
R2393 R2300 2 3
22 INV_CTL 100 1
PWR ON 1 2 INV CTL 1
+3.5V_ST L2395 GND GND
+3.5V_ST UBW2012-121F DPC 3 4 PDIM#2 PANEL_CTL
ZD2303 3.5V GND R2395
5 6 +12V +3.5V_ST +3.5V_ST
R2392 R2349
+3.5V_ST_ESD
0
+3.5V_ST_ESD
3.5V 3.5V
+3.5V_ST_ESD
C2395 7 8 0 100K
ZD2304
+3.5V_ST_ESD
ZD2305
PD_OLED_AC
ZD2307
ZD2306
5V
5V
5V
5V
5V
0.1uF GND 9 10 GND OLED_OLD_PSU

16V OLED_AC_DET OPT OPT RESET_IC_ROHM R2354
12V 11 12 12V R2335 R2343 IC2307 10K
12V 12V 2.7K 0
UBW2012-121F 13 14 OPT
1% 5% BD48K28G
12V 15 16 GND L2398 +24V R2399
+12V GND 12V_ON UBW2012-121F 0 POWER_DET
L2396 17 18 5% VDD VOUT
24V 24V OLED_AC_DET 3 2
19 20
UBW2012-121F 24V 24V L2399 C2399 C2350 1
C2394 21 22 OPT
GND GND UBW2012-121F 0.1uF 0.1uF GND
0.1uF 23 24 50V R2336
D2399 L2397 R2398 16V
50V 22K 1.2K
PTVS13VS1UR C2364
23.2V 1% 1%
25 0.1uF
R2360
1/16W
NEAR IC6801 P102/IC5800 P4100/P4101 16V
+12V
not to RESET
5%
0
at 8kV ESD
L/D_DI
PANEL_CTL C2396 C2397 C2398 +24V
12V_ON,PAENL_CTL IS FOR OLED QSM
10uF 10uF 10uF R2363
L/D_CLK 16V 16V 16V 100K
L/D_VSYNC
RESET_IC_ROHM
PWM_DIM R2361
IC2308
9.1K
1% BD48K28G
PWM_DIM2
VDD 3 2 VOUT
C2370 1 12V-->3.58V
0.1uF GND ST_3.5V-->3.5V
R2362 16V
1.6K
1%
+12V
+5.0V normal & USB
1%
150K 1%
DDR +1.5V R2
R2337 16K 1%
+3.3V - eMMC C2347
2200pF
OPT
C2349 C2352
R2339 16K
+1.5V_DDR
+12V 50V
1%
1/16W
100pF 0.047uF
6.8K
R2351
L2309 50V 25V
R2342
POWER_ON/OFF2_3 R2344
PZ1608U121-2R0TF 10K
+3.3V_NORMAL +1.8V +3.3V_NORMAL
3.3V_EMMC DVDD18_EMMC
TI_TPS54327_1.5V_DDR_DCDC
C2359 C2362 C2363
IC2303-*1
RSET2
RSET1
TPS54327DDAR [EP]GND 22uF 22uF 10uF
[EP]
AGND
RLIM
COMP
C2324 C2357 R1 10V 10V 10V
LD2300
C2322
FB
SS
ROHM_BD9D321_1.5V_DDR_DCDC L2314
LED
EN VIN
0.1uF 1 8
L2304 L2305 10uF 120-ohm 82pF
THERMAL
1%
1/16W
51K
PZ1608U121-2R0TF PZ1608U121-2R0TF 16V VFB VBST 50V
R2352
2 7
IC2303
28
27
26
25
24
23
22
R2326 VREG5 SW VIN_1 LX_3
BD9D321EFJ [EP] 3 6 1 21 L2313
R2315
10K 4.7uH
3.3K
SS GND THERMAL
C2308 C2307 4 5 VIN_2 2 20 LX_2
C2309 C2312 29
0.1uF 0.1uF
22uF 22uF EN VIN
16V 16V 1 8 C2340 C2341 C2344 VIN_3 3 19 LX_1 C2355
10V 10V
16V 10uF 10uF 0.1uF
IC2305
0.047uF +5V_NORMAL
THERMAL
0.1uF 50V PGND_1 BST 25V
C2336 35V 35V 4 18
R2320 R2321 FB BOOT SN1302001(TPS65286RHDR)
9
2 7 OPT
PGND_2 5 17 SW_IN2
R1 18K 4.7K L2312 C2360
R2350
1/16W
1% 1%
100K
100K
R2353
2.2uH PGND_3 SW_IN1
1/16W
VREG SW 6 16 1uF
5%
5%
1.0V_DCDC_TI
C2325
100pF
50V
3 6
PS064T-2R2MS V7V 7 6A 15 NFAULT1
10V
/USB_OCD2
SS GND
25V
1uF
C2343
10
11
12
13
14
4
3A 5 C2339
9
C2332-*1 C2338 ZD2302
3300pF 22uF 22uF 2.5V
R2322 10V
MODE/SYNC
EN
SW_OUT2
SW_OUT1
SW_EN2
SW_EN1
NFAULT2
50V 22K 10V
C2328 C2332 DCDC_DIODE
+1.8V - LM15U, eMMC 1% 1uF
10V
2200pF
50V
1.0V_DCDC_ROHM
& Vx1 pull-up Switching freq: 700K R2
Vout=0.6*(1+R1/R2)
/USB_OCD1
C2346
+5V_USB_1
+5V_USB_2
Vout=0.765*(1+R1/R2)=1.554V
USB_CTL1
USB_CTL2
R2338
10K
0.0068uF
POWER_ON/OFF1
50V
+1.8V 5.1V:R1-51K, R2-6.8K

+3.3V_NORMAL
IC2301
AZ1117EH-ADJTRG1
IN OUT
DCDC_DIODE
R2309
ADJ/GND
1
MAX 2.7A
D2302
1%
1/16W
75
2.5V
R2307
C2310 C2311
10uF 10uF
1%
1/16W
33
R2308
10V 10V
+1.1V or +1.15V _CPU CORE
+1.1V_VDDC_CPU LM15 Power SEQUENCE
+12V
IC2300 L2311
L2310 BD86106EFJ 2uH POWER_ON/OFF1(5V)
EAN62653301 [EP]
PZ1608U121-2R0TF
PGND SW_2
1 8
THERMAL
Placed on SMD-TOP VIN SW_1

OPT OPT OPT
9
2 7
C2329 C2353 C2333 C2334 C2354 C2356 R2334 POWER_ON/OFF2_1(3.3V)

MAX A AGND EN
0.0068uF R1
+3.3V_NORMAL 3 6
C2320 C2321 C2323 R2324 10uF 10uF 100uF 10uF 10uF 15K
50V
10uF 10uF 0.1uF 6.8K 10V 10V 10V 10V C2337 1%
16V 16V 16V
OPT
FB
4
6A 5
COMP
47pF
50V
DCDC_DIODE
+12V
TPS54527 => LM15U+URSA
ZD2301
POWER_ON/OFF2_3(1.5V, 2.5V)
5V
TPS54427 => LM15U +3.3V_NORMAL
R2325
POWER_ON/OFF2_4
L2300 C2326 10K R2-1.13V R2345

0.1uF 13K
PZ1608U121-2R0TF
16V R2-1.13V 1% POWER_ON/OFF2_4(1.1V)
R2332
20K
R2317 1% R2346
20K 43K R2
C2300 1% +3.3V_NORMAL 1%
KEC_CPU_CORE_VID_FET
10uF
25V DEV_TPS54527_3.3V_5A_DCDC +3.3V_NORMAL
KEC_CPU_CORE_VID_FET
R2333
IC2302 200K
Vout=0.8*(1+R1/R2)
DCDC_DIODE
TPS54527DDAR [EP]GND R2318 1%

ZD2300
200K R2327 D
5V
1%
R2-1.1V
2N7002KA
R2303 10K
10K EN VIN R2312 D R2330
2N7002KA
Q2302
1 8 R1:56K/R2:223K, V=1.000V Voltage drop 0.05V 10K G

CPU_VID1 D
16V
THERMAL
TPS54427_3.3V_4A_DCDC POWER_ON/OFF2_1 0.1uF R2316 0 5% S

Q2301
IC2302-*1 R1:56K/R2:149.10K, V=1.100V Voltage drop 0.05V G Q2302-*1

1% VFB VBST C2306 CPU_VID0 D G
2N7002K
9
TPS54427DDA [EP]GND
2 7 0 5% S
PS064T-2R2MS G Q2301-*1
EN VIN R2302 L2306 2N7002K S
1 8
R1 2.2uH
THERMAL
VFB VBST 51K VREG5 SW DIODEDS_CPU_CORE_VID_FET

9
2 7 3 6 S
VREG5 SW
C2301 DIODEDS_CPU_CORE_VID_FET
3 6 100pF
50V
SS GND
SS
4
4A
5
GND
OPT R2305
4
5A 5 C2313
22uF
10V
C2314
22uF
10V
15K C2303 C2305
1uF 0.015uF
10V 50V
1%
Switching freq: 700K R2
Vout=0.765*(1+R1/R2)
+1.1V or +1.15V _CORE MAX 7A
R2510
100
1/16W
1%
R2512 C2506
220K
POWER_ON/OFF2_4
1/10W
1%
1/16W
430K
330pF
IC2501
R2511
5% 50V
MP8762HGLE-Z
LPBN8050T-1R0N +1.1V_VDDC
R2507 L2500
1K EN SW_2 1.0uH
1 16
DCDC_DIODE
OPT
ZD2500
FREQ SW_1
R1
2.5V
C2500 2 15 C2507 C2509
1%
1/16W
13K
R2504
C2508
0.1uF 22uF 22uF
22uF
16V 10V 10V
R2 FB IN_2 10V
3 14
R2505
1/16W1/16W
R2-1
12K
1%
SS PGND_4
4 13
C2502
R2506
12K
0.033uF
1%
R2-3 R2-2 50V AGND

5 12
PGND_3
10A
R2502
1/16W
R2508
R2518
1/16W
120K
100K PG PGND_2
120K
6 11 +12V
1%
1%
C2501 1/16W
1uF 1%
+3.3V_NORMAL +3.3V_NORMAL VCC PGND_1
7 10
KEC_CORE_DCDC_FET
KEC_CORE_DCDC_FET
1%
1/16W
30K
R2503
1%
1/16W
30K
R2519
10V
L2501
BST IN_1
8 9
D R2500 D
R2516
2N7002KA
10K
2N7002KA
10K
R2517 R2501
Q2500
G
Q2501
G CORE_VID0 C2504 C2505

CORE_VID1
S 0 5% S R2509 10uF 10uF
0 5% C2503
33 25V 25V
1/16W 0.1uF
5% 16V
D
D
G Q2500-*1
G Q2501-*1 2N7002K
2N7002K
DIODES_CORE_DCDC_FET S
DIODES_CORE_DCDC_FET Vout=0.611*(1+R1/R2)
S
R1:13K/R2:22K, V=0.95V(CORE_VID0=L,CORE_VID1=L) Voltage drop 0.02V

R1:13K/R2:22K//150K, V=1.00V(CORE_VID0=H,CORE_VID1=L) Voltage drop 0.02V
R1:13K/R2:22K//150K, V=1.00V(CORE_VID0=L,CORE_VID1=H) Voltage drop 0.02V
R1:13K/R2:22K//150K//150K, V=1.05V(CORE_VID0=H,CORE_VID1=H) Voltage drop 0.02V
+2.5V
TU_JP
TU_JP/EU_UF77_ESD +2.5V_Normal
IC2502
R2513
TJ4220GDP-ADJ [EP]GND
POWER_ON/OFF2_3
R2514
TU_JP
22K
10K
C2512 1 8 R2
0.1uF
THERMAL
+3.3V_NORMAL NC_1 GND

TU_JP
TU_JP/EU_UF77_ESD
R2515
9
2 7 R1
47K
EN2 ADJ/SENSE
3 6
TU_JP VOUT
VIN3
C2510
0.1uF
16V
4 2A 5
NC4 NC_2 TU_JP
ZD2501
EAN62206201 C2513
OPT
5V
10uF
10V
Vout=0.6*(1+R1/R2)

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LM15U_PWR_2_ALL 25
Renesas MICOM
For Debug
+3.5V_ST
X3000-*1
32.768KHz
EPSON_MICOM_CRYSTAL
MICOM_DEBUG
R3016 1K
R3014 10K
MICOM_DEBUG Don’t remove R3016,

P3000
12507WS-04L
not making float P40 50V 50V
12pF 12pF
C3002 C3003 LOGO_LIGHT
MICOM_DEBUG
1
LOGO_LIGHT
MICOM_RESET
2 DAISHINKU_MICOM_CRYSTAL
MICOM_DEBUG
X3000
WIFI_EN
3
4
MICOM_RESET 32.768KHz +3.5V_ST
5
HDMI_WAUP:HDMI_INIT R3028
4.7M
MHL_DET_LM15 OPT
0 R3037
MHL_DET_LM15
10K
POWER_DET_1
R3032
10K
R3030
MICOM_RESET_SW
GND SW3000
JTP-1127WEM
2 1
33
R3031
1%
1/16W
270K
OPT
C3004
P124/XT2/EXCLKS
0.47uF
0.1uF
+3.5V_ST 4 3
16V
R3029
P122/X2/EXCLK
P41/TI07/TO07
C3001
P137/INTP0
P120/ANI19
P40/TOOL0
P123/XT1
C3000
P121/X1
0.1uF
RESET
+3.5V_ST
REGC
VDD
VSS
R3021-*1
LCD
OLED
R3021
LM15 Power SEQUENCE
1K
10K 5%
1/16W
48
47
46
45
44
43
42
41
40
39
38
37
POWER_ON/OFF1(5V) P60/SCLA0 1 36 P140/PCLBUZ0/INTP6 RL_ON
SCART_MUTE
I2C_SCL_MICOM
P61/SDAA0 2 35 P00/TI00/TXD1 POWER_ON/OFF2_4
I2C_SDA_MICOM SCART_MUTE
P62 3 34 P01/TO00/RXD1
3D&L_DIM_EN POWER_ON/OFF2_4
POWER_ON/OFF2_1(3.3V)
P63 4 33 P130
PANEL_CTL
P31/TI03/TO03/INTP4 IC3000 P20/ANI0/AVREFP
POWER_ON/OFF2_1
WOL/WIFI_POWER_ON 5 32 KEY2
POWER_ON/OFF2_3(1.5V)
IR
P75/KR5/INTP9/SCK01/SCL01 6 R5F100GEAFB#30 31 P21/ANI1/AVREFM
KEY1
R3038
100 P74/KR4/INTP8/SI01/SDA01 7 30 P22/ANI2
HDMI_CEC_MICOM
POWER_ON/OFF2_4(1.1V) P73/KR3/SO01 8 29 P23/ANI3

MODEL1_OPT_3
POWER_ON/OFF2_3
P72/KR2/SO21 9 28 P24/ANI4
MODEL1_OPT_0
P71/KR1/SI21/SDA21 10 27 P25/ANI5
SOC_RESET EYE_SDA SIDE_HP_MUTE
P70/KR0/SCK21/SCL21 11 26 P26/ANI6
EYE_SCL MHL_EN MHL_EN
P30/INTP3/RTC1HZ/SCK11/SCL11 12 25 P27/ANI7
MODEL1_OPT_1
13
14
15
16
17
18
19
20
21
22
23
24
AR3000
3.3K
EYE_Q
+3.5V_ST
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
P17/TI02/TO02
P16/TI01/TO01/INTP5
P15/PCLBUZ1/SCK20/SCL20
P14/RXD2/SI20/SDA20
P13/TXD2/SO20
P12/SO00/TXD0/TOOLTXD
P11/SI00/RXD0/TOOLRXD/SDA00
P10/SCK00/SCL00
P146
P147/ANI18
MICOM MODEL OPTION
+3.5V_ST
MICOM MODEL OPTION

10K
10K
10K
MICOM_OLED
MICOM_LOGO
OPT
R3006
R3008
R3013
0 1
MODEL_OPT_0 NON LOGO LOGO
MODEL1_OPT_0 MODEL_OPT_1 LCD OLED

MODEL1_OPT_1
MODEL1_OPT_3
MODEL_OPT_3 LM15U H15
POWER_DET
SOC_RX
AMP_MUTE
EDID_WP
URSA_RESET_MICOM
URSA_RESET_MICOM
WOL_WAKE_UP
INV_CTL
POWER_ON/OFF1
WOL_CTL
SOC_TX
LED_R
MICOM_NON_LOGO
10K
10K
10K
MICOM_LCD
R3009
R3004
R3012
For CEC
R3015
10K +3.5V_ST
MICOM_LM15U
LED_R
SOC_RESET
R3033 R3034
27K 120K
LM15U : Active high reset
G
D3000
BAT54_SUZHO
CEC_REMOTE HDMI_CEC_MICOM
S
Q3001
G
RUE003N02
Q3001-*1 ROHM_CEC_FET
SI1012CR-T1-GE3
D
VISHAY_CEC_FET
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MICOM 30
5V_HDMI_1
5V_DET_HDMI_1
R3309
1.8K
ESD_HDMI
R3312
R3302
VA3300
3.3K
1K R3337 R3305 CNPLUS_HDMI_JACK CNPLUS_HDMI_JACK CNPLUS_HDMI_JACK
JK3300-*1
33 JK3301-*1 JK3302-*1
4.7K 5501-56219 5501-56219 5501-56219
C OPT NON_HDMI_EXT_EDID
Q3300 TMDS_DATA2+
B 1K 1 TMDS_DATA2+ TMDS_DATA2+
1 1
2N3904S HDMI_HPD_1 TMDS_DATA2_SHIELD
2 TMDS_DATA2_SHIELD
2 TMDS_DATA2_SHIELD
BODY_SHIELD R3300 R3303 TMDS_DATA2- TMDS_DATA2-
2
3 3 TMDS_DATA2-
3
100K R3339 TMDS_DATA1+
4 TMDS_DATA1+ TMDS_DATA1+
E 4.7K
4 4
20 TMDS_DATA1_SHIELD
5 TMDS_DATA1_SHIELD TMDS_DATA1_SHIELD
KEC_HDMI_HPD_3_TR HDMI_EXT_EDID TMDS_DATA1-
5 5
ESD_HDMI
6 TMDS_DATA1- TMDS_DATA1-
VA3302
6
C TMDS_DATA0+
7 TMDS_DATA0+ TMDS_DATA0+
6
7
19 TMDS_DATA0_SHIELD TMDS_DATA0_SHIELD
7
HOT_PLUG_DETECT Q3300-*1 B 8 8 TMDS_DATA0_SHIELD

33 R3329 TMDS_DATA0- TMDS_DATA0-
8
18 MMBT3904(NXP) DDC_SDA_1 9 9 TMDS_DATA0-

9 5V_HDMI_3 5V_DET_HDMI_3
TMDS_CLK+
VDD[+5V] NXP_HDMI_HPD_3_TR 33 R3330 10 TMDS_CLK+
10 TMDS_CLK+
10
TMDS_CLK_SHIELD
E DDC_SCL_1 11 TMDS_CLK_SHIELD
11 TMDS_CLK_SHIELD
R3324
17 TMDS_CLK- TMDS_CLK-
11
DDC/CEC_GND 12 12 TMDS_CLK-
12
CEC CEC OPT 1.8K
ESD_HDMI
13 13 CEC
16 13
R3335
R3316
VA3308
SDA VA3304 VA3306 RESERVED
14 RESERVED RESERVED OPT
3.3K
14 14
1K R3336 R3319
ESD_HDMI ESD_HDMI SCL
15 SCL
15 SCL 33
15 SDA SDA
15
4.7K
SCL 16 16 SDA
16
DDC/CEC_GND DDC/CEC_GND
17 17 DDC/CEC_GND
14 VDD[+5V] VDD[+5V]
17
RESERVED 18 18 VDD[+5V]
18
OPT C OPT
HOT_PLUG_DETECT
CEC_REMOTE 19 HOT_PLUG_DETECT
19 HOT_PLUG_DETECT BODY_SHIELD Q3305 R3318
13 19
R3315
CEC 20 100K 2N3904S B 1K
20 20 HDMI_HPD_3
12 BODY_SHIELD BODY_SHIELD BODY_SHIELD
20
TMDS_CLK- OPT
ESD_HDMI
VA3312
D3302 E
11 RCLAMP7534P
TMDS_CLK_SHIELD 19
OPT HOT_PLUG_DETECT
10 1
CK-_HDMI1
TMDS_CLK+ 18
5
VDD[+5V]
9 CK+_HDMI1
TMDS_DATA0- 17
2 DDC/CEC_GND 33 R3333
8 DDC_SDA_3
TMDS_DATA0_SHIELD 4
16 33 R3334
D0-_HDMI1 SDA DDC_SCL_3
7
TMDS_DATA0+ 3 D0+_HDMI1 15
SCL VA3311
6 ESD_HDMI
TMDS_DATA1- 14
RESERVED VA3309
5 CEC_REMOTE ESD_HDMI
D3306
RCLAMP7534P
TMDS_DATA1_SHIELD 13
CEC
4 OPT
TMDS_DATA1+ D3303
RCLAMP7534P
12 1
CK-_HDMI3
TMDS_CLK-
3 5
TMDS_DATA2- OPT 11 CK+_HDMI3
1
D1-_HDMI1 TMDS_CLK_SHIELD
2 2
TMDS_DATA2_SHIELD 5 D1+_HDMI1 10
TMDS_CLK+ 4
1 D0-_HDMI3
TMDS_DATA2+ 2 9
TMDS_DATA0- 3 D0+_HDMI3
4
D2-_HDMI1 8
TMDS_DATA0_SHIELD
3
DAADR019A D2+_HDMI1
7
JK3301 TMDS_DATA0+
FOOSUNG_HDMI_JACK HDMI3 6
TMDS_DATA1-
D3307
RCLAMP7534P
+3.5V_ST C
5
TMDS_DATA1_SHIELD OPT
1
B Q3304-*1
D1-_HDMI3 MMBT3906(NXP)
R3326
4 NXP_MHL_TR
TMDS_DATA1+ 5 D1+_HDMI3
MHL
10K
E
5V_HDMI_2 3 2
TMDS_DATA2- MHL
5V_DET_HDMI_2 R3327 E 2N3906S-RTK
R3308 2 4
D2-_HDMI3 10K Q3304
TMDS_DATA2_SHIELD KEC_MHL_TR
1.8K 3
D2+_HDMI3
ESD_HDMI
1 B
R3304 OPT
R3310
VA3301
TMDS_DATA2+
3.3K
1K R3338 MHL C
R3307 C
33 MHL R3325
4.7K R3317 0
C B
NON_MHL
R3306 MHL_DET_LM15
Q3301 DAADR019A
R3328
1K
B 1K Q3303
R3314
NON_MHL
2N3904S HDMI_HPD_2 JK3302 MHL
10K
BODY_SHIELD VA3310 C3303 E
R3301 R3320 2N3904S
FOOSUNG_HDMI_JACK 5.6V 0.1uF
100K 300K KEC_MHL_TR
0
20 E MHL 16V
KEC_HDMI_HPD_2_TR OPT MHL Spec C
ESD_HDMI
C
VA3303
19 33 R3331
HOT_PLUG_DETECT Q3301-*1 B DDC_SDA_2 B Q3303-*1
MMBT3904(NXP) 33 R3332 MMBT3904(NXP)
18 NXP_MHL_TR
VDD[+5V] NXP_HDMI_HPD_2_TR DDC_SCL_2
E E
17
DDC/CEC_GND VA3305 VA3307
ESD_HDMI
HDMI1 with MHL
16 ESD_HDMI
SDA
15
SCL
HDMI_ARC
14
RESERVED
CEC_REMOTE
13
CEC
12
TMDS_CLK-
11
TMDS_CLK_SHIELD
D3301
RCLAMP7534P
EDID external EEPROM +5V_NORMAL
10 E
TMDS_CLK+ OPT 5V_HDMI_1
1
CK-_HDMI2
9 MMBT3904(NXP)
TMDS_DATA0- 5
CK+_HDMI2 Q3302-*1 B
A1
A2
8 2 C
TMDS_DATA0_SHIELD MMBD6100
NXP_HDMI_EXT_EDID_TR D3309
7 4
D0-_HDMI2
TMDS_DATA0+
C
6
3 D0+_HDMI2
TMDS_DATA1- E
KEC_HDMI_EXT_EDID_TR
ATMEL_HDMI_EXT_EDID
5 2N3904S
TMDS_DATA1_SHIELD ROHM_HDMI_EXT_EDID EDID_WP
4
IC3301 Q3302 B IC3301-*1
TMDS_DATA1+ BR24G02FJ-3GTE2 C AT24C02C-SSHM-T
D3300
3 RCLAMP7534P
TMDS_DATA2-
2 OPT
1 A0 VCC HDMI_EXT_EDID A0 VCC
TMDS_DATA2_SHIELD D1-_HDMI2 1 8 1 8
1 5 D1+_HDMI2
TMDS_DATA2+ R3323
A1 WP AR3305 A1 WP
2
2 7 4.7K 1/16W 2 7
4
47K
D2-_HDMI2
DAADR019A
3 A2 SCL A2 SCL
JK3300 D2+_HDMI2 3 6 3 6
FOOSUNG_HDMI_JACK
HDMI2 with ARC GND SDA GND SDA
4 5 4 5
R3321
22
DDC_SCL_1
HDMI_EXT_EDID
R3322
22
DDC_SDA_1
HDMI_EXT_EDID
MHL
Current Limit 5V_HDMI_3
MHL
L3301
IC3300 BLM31PG500SN1
5V_MHL TPS2553DBV 50-ohm DDC pull-up
IN OUT D3304
ESD_5V_HDMI_3
1 6
5V_HDMI_2 5V_HDMI_3
C3301 ZD3300 MHL 30V MHL +5V_NORMAL +3.5V_ST
MHL
VA3313
0.1uF 5V OPT C3302

GND ILIM MHL 1% R3313 +5V_NORMAL
16V OPT 2 5
+5V_NORMAL 10uF
5V_MHL 100K 10V
A1
A2
20K
A1
A2
A1
A2
R3311 MHL
MHL
EN FAULT MMBD6100
MHL_DET_LM15 3 4 MMBD6100 MMBD6100
L3300 D3305 D3310
/MHL_OCP D3308
C
PZ1608U121-2R0TF
C
MHL MHL
C3300
AR3302
0.1uF
AR3304
1/16W
/MHL_OCP
1/16W
16V
47K
47K
DDC_SDA_2
DDC_SDA_3
DDC_SCL_2
DDC_SCL_3

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HDMI 10
COMPONENT 1 PHONE JACK CVBS 1 PHONE JACK
C3822 R3814
VA3808 0.01uF
25V 470K
5.6V
1608 sizs For EMI

R3822
R3819 10K
1608 sizs For EMI
COMP1/AV1/DVI_L_IN
0 R3805
COMP1_Y 0
R3809
C3816 C3819
R3808
C3802 0 R3825
C3805 C3808
1/4W
560pF 100pF 12K
VA3803 150pF 27pF 100pF C3811 +3.3V_NORMAL 50V 50V
75
1%
5.5V OPT 50V 50V 47pF
50V OPT OPT
OPT OPT
+3.3V_NORMAL
JK3801
PEJ038-4G6
R3815
5 M5_GND 47K E
JK3803 Q3801
R3801
10K PEJ038-4Y6
4 M4 5 M5_GND B
R3802 C
3 M3_DETECT 1K AV1_CVBS_DET
4 M4
COMP1_DET
OPT R3816
1 M1 VA3804 C3824 10K
3 M3_DETECT
5.6V 0.1uF
50V
6 M6 1 M1
VA3807
EAG61030012 5.6V
1608 sizs For EMI 6 M6
0 R3804
COMP1_Pb_1 COMP1_Pb 1608 sizs For EMI
EAG61030011 R3824
R3820 10K
C3804 C3806
VA3801 R3806 C3810 COMP1/AV1/DVI_R_IN
27pF 27pF 0
5.5V 50V 50V 75 10pF
OPT OPT 1% 50V VA3809 C3823 R3817 C3817 C3820
5.6V 0.01uF R3826
25V 470K 560pF 100pF 12K
VA3802 50V 50V
5.5V OPT OPT
1608 sizs For EMI

0 R3803 COMP1_Pr
1uH
C3803 L3803 R3823
C3807 R3807 C3809 CM2012F1R0KT
27pF 0
27pF 75 10pF
50V 50V 50V AV1_CVBS_IN
OPT 1%
OPT
R3821
C3814 C3815 C3818
1/4W
VA3806 150pF 150pF 150pF C3821
75
1%
5.5V OPT 50V 50V 47pF
50V
FOR S2A
Solteam
JK3802-*1
JSTIB15
VIN A
Fiber Optic
VCC B
GND C
4
SHIELD
foxconn
JK3802
+3.3V_NORMAL 2F11TC1-EM52-4F
VIN
SPDIF OUT A
Fiber Optic
VCC B
R3800
33 GND C
SPDIF_OUT
VA3800 C3801 4
C3800 5.5V 0.1uF
18pF 16V
SHIELD
50V OPT
ADUC 5S 02 0R5L
HP OUT
RS232C
R3810-*1
1uF
10V
HP_BYPASS
RIN1 HP_OUT
HP_OUT
L3802 R3810
R 1 BLM18PG121SN1D 150
JP3814
DOUT1
JP3813
HP_LOUT_AMP HP_OUT 1/10W

DETECT 3 C3813 +3.3V_NORMAL
5%
0.22uF
10V R 1
L 4
DOUT1 R3813
10K DETECT 3
GND 5 HP_OUT
RIN1 R3812 HP_OUT
PEJ038-3B6 100
JP3815
L 4
JK3804 HP_DET
1/16W
HP_OUT HP_OUT 5% GND 5
L3801 R3811
BLM18PG121SN1D 150 PEJ038-3B6
JK3805
HP_ROUT_AMP HP_OUT 1/10W
C3812 5% R3811-*1
0.22uF 1uF VA3805
10V 10V 5.6V
HP_BYPASS HP_OUT

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK_COMMON_V 38 01
JACK_COMMON_V
[ED94 ONLY] IR/COMBO
WIFI POWER ENABLE CONTROL
P4101
12507WR-08L
+3.5V_WIFI
+3.5V_ST IC4100
1 AP2191WG-7
R4101 0.1uF
100 C4101 IN OUT
2 M_RFModule_RESET
5 1
C4112
3 0.1uF GND
2
4 WIFI_EN R4115 33 EN FLG

WOL/WIFI_POWER_ON 4 3
100
R4100 C4100 R4114
5 0.1uF
10K
R4103 OPT
JP4111 0
WIFI_DM
6
RCLAMP0502BA
R4104
0
7 WIFI_DP
Place Near Wafer
D4100
C4104 C4105
5pF 5pF
8 50V 50V
WIFI_DMDP_ESD
9
+3.5V_WIFI
50V 10V
3300pF 0.1uF 22uF L4100
C4102 C4103 C4107 BLM18PG121SN1D
P4100
12507WR-10L
+3.5V_ST
1 R4110 R4111
10K 10K
1% 1% R4112
100
2
KEY1
R4113
100
3
KEY2
+3.5V_ST C4110 C4111
0.1uF 0.1uF
4 OPT
OPT
C4106
1000pF
5 50V
JP4112 +3.5V_ST
JP4113 WIFI_EMI
6
10K
LOGO_LIGHT R4106
OPT
C LOGO_LIGHT
7
B
LOGO_LIGHT
LOGO_LIGHT
R4107
Q4100 1K C4109
8
10K
E MMBT3904(NXP) R4102 0.1uF

LOGO_LIGHT 16V
10
IR
C4108 5%
11 100pF
50V 10K
R4105
+3.5V_ST
EYE_SCL
100
R4109
EYE_SDA
100
R4108

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
[OLED]MULTI JACK
+5V_USB FOR USB3->USB1
+5V_USB_1
USB3
OCP USB1 USB_DM/DP_2.2ohm MAX 1.0A
R4300-*1
2.2
USB_DM/DP_2.2ohm
R4301-*1
2.2
JK4302
3AU04S-305-ZC-(LG)
+5V_USB_3 USB_DM/DP_0ohm
USB DOWN STREAM

+3.3V_NORMAL R4300
+5V_NORMAL 0
2
USB_DM1
IC4300 USB_DM/DP_0ohm
BD2242G R4301
0
3
USB_DP1
R4305 VIN VOUT
4.7K 1 6 C4322 C4323
D4301
RCLAMP0502BA
D4302
4
22uF
5V
10uF
C4300 GND ILIM 10V
10V
5
0.1uF 2 5
16V
14K
R4306
1%
EN OC
/USB_OCD3 3 4
USB_CTL3
R4304
10K
+5V_USB_2
USB2
USB_DM/DP_2.2ohm
R4302-*1
2.2
MAX 1.0A
USB_DM/DP_2.2ohm
R4303-*1
2.2
JK4300
3AU04S-305-ZC-(LG)
USB_DM/DP_0ohm
USB DOWN STREAM

R4302
0
2
USB_DM2
USB_DM/DP_0ohm
R4303
RCLAMP0502BA
0
3
USB_DP2
D4300
C4310
4
C4311
D4303
5V
10uF 22uF
5
10V 10V
+5V_USB_3
USB1 (3.0)
MAX 1.2A
ZD4302 JAE_USB3.0_JACK
C4312 C4313 5V CNPLUS_USB3.0_JACK
22uF 10uF JK4301 JK4301-*1
10V 10V SJ113262 5205-56209
USB3.0_TVS
VBUS
D4304 1
VBUS
1
RCLAMP0544T.TCT D- D-
2
USB_DM3 6.5VTO11.0V 2
1 8 D+ D+
USB_DP3 3 3
2 7
GND GND
4
3 6 4
STDA_SSRX-
SSUSB_RXP 4 5 5
STDA_SSRX-
5
STDA_SSRX+ STDA_SSRX+
6
SSUSB_RXN 9 6
GND_DRAIN GND_DRAIN
7 7
USB3.0_TVS STDA_SSTX-
8
STDA_SSTX-
8
D4305 STDA_SSTX+ STDA_SSTX+
RCLAMP0544T.TCT 9 9
6.5VTO11.0V 10 10
1 8
SHIELD SHIELD
2 7
3 6
SSUSB_TXP
4 5
SSUSB_TXN

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB3_HUB 43
Full Scart(18 Pin Gender)
+3.3V_NORMAL
EU
R4601 CLOSE TO JUNCTION
10K
EU
R4602
100
SC_DET
EU
C4604
VA4601 0.1uF
5.6V
FOR S2A
EU
EU
L4602
1uH
SC_CVBS_IN
R4606 C4605 C4606

EU 150pF 150pF
VA4607 75 50V 50V
SHIELD 5.5V EU EU
EU
EU
19
R4614
AV_DET 0
18
COM_GND
VA4608 EU DTV/MNT_V_OUT
5.5V R4600 EU 68pF 68pF OPT
17
SYNC_IN EU 75 C4612 C4613
16
SYNC_OUT
15
SYNC_GND EU
R4608
14 22
RGB_IO
13 SC_FB
R_OUT VA4602
12 5.6V EU
R_GND EU R4603
11 75
G_OUT
10
G_GND
9 SC_R
ID
8 VA4603
B_OUT EU
5.5V R4604
7
AUDIO_L_IN EU 75
6
B_GND
5 JP4613
SC_G
AUDIO_GND
4 VA4604
AUDIO_L_OUT
5.5V EU
3
AUDIO_R_IN EU R4605
75
2
AUDIO_R_OUT
1
SC_B
VA4605
5.5V EU
DA1R018H91E R4607
EU
JK4600 75
EU
EU R4615
15K
SC_ID
VA4600 R4616
20V 3.9K
EU
EU
R4619
10K
SC_L_IN
Applied as default
VA4609 EU EU
R4620 R4618 to protect Auto AV
5.6V
EU 470K 12K incase don’t using scart
EU
R4622
10K
SC_R_IN
EU EU
VA4606 R4623 R4621
5.6V 470K 12K
EU
BLM18PG121SN1D
L4600
DTV/MNT_L_OUT
VA4610 EU EU EU
5.6V C4600 C4602
EU 1000pF 4700pF
50V
BLM18PG121SN1D
L4601
DTV/MNT_R_OUT
EU EU
VA4611 EU C4603
5.6V C4601 4700pF
EU 1000pF
50V
AV2_CVBS_DET

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART_JACK_V 46 01
SCART_JACK_V
Ethernet Block
LAN_JACK_POWER
C5000 C5001 C5002 C5003

0.1uF 0.01uF 0.1uF 0.01uF
16V 50V 16V 50V
JK5000
BS-RSD0303
P1[CT]
R1
P2[TD+]
R2
EPHY_TDP
P3[TD-]
R3
EPHY_TDN
P4[RD+]
R4
EPHY_RDP
P5[RD-]
R5
EPHY_RDN
P6[CT] VA5000 VA5001 VA5002 VA5003

R6
5.5V 5.5V 5.5V 5.5V
P7
R7
P8
R8
9
R9 EMI
R5000
P10[GND] 0
R10
P11
R11
YL_C
P1
YL_A
P2
GN_C
P3
GN_A
P4
16
SHIELD

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LAN_V 50 01
LAN_V
AUDIO AMP(NTP7515) SM-6045-100
GET_AMP_COIL
L5802-*1
10.0uH
+3.3V_NORMAL
R5805
AMP_RESET_N 100
TAIYO_AMP_COIL
NRS6045T100MMGK
1/16W
+24V +24V_AMP L5802
L5801 R5806 C5806
1000pF 10.0uH
PZ1608U121-2R0TF 4.7K
L5800 50V SPK_L+
UBW2012-121F
50V
AUD_SCK
+24V_AMP
22000pF
R5807
1/10W
C5807
3.3
R5811
5%
C5821
C5805 0.1uF 4.7K
50V
[EP]GND
0.1uF C5813
C5809 390pF
VDD_IO
GND_IO
PGND1A
PVDD1A
PVDD1B
16V 10uF 50V
CLK_I
RESET
BST1A
OUT1A
35V
C5819
0.47uF
50V
AD
C5814
390pF
50V C5822 R5812
R5808
1/10W
TAIYO_AMP_COIL
0.1uF SPEAKER_L
3.3
50V 4.7K
5%
NRS6045T100MMGK
40
39
38
37
36
35
34
33
32
31
L5805
NC_1 1 30 OUT1B 10.0uH
SPK_L-
VDD_PLL 2 29 PGND1B C5811

THERMAL 22000pF SM-6045-100
NC_2 3 41 28 BST1B 50V GET_AMP_COIL
C5800
1uF L5805-*1
10V GND 4 27 VDR1 10.0uH
NC_3 5 IC5800 26 NC_5

C5801
1uF
10V
DVDD 6 NTP7515 25 AGND
AUD_LRCH
SDATA 7 24 VDR2
WCK 0x54 BST2A
C5817
1uF
C5818
1uF SM-6045-100
AUD_LRCK 8 23 10V 10V GET_AMP_COIL
NC_4 9 22 PGND2A C5812 L5803-*1

10.0uH
22000pF
AR5800
100 SDA 10 21 OUT2A 50V
I2C_SDA4
11
12
13
14
15
16
17
18
19
20
I2C_SCL4
TAIYO_AMP_COIL
NRS6045T100MMGK
C5802 C5804
33pF 33pF L5803
50V 50V 10.0uH
SCL
FAULT
MONITOR_0
MONITOR_1
MONITOR_2
BST2B
PGND2B
OUT2B
PVDD2B
PVDD2A
SPK_R+
+3.3V_NORMAL
R5809
1/10W
+24V_AMP
3.3
5%
C5823 R5813
R5801 0.1uF 4.7K
10K C5815 C5820 50V
390pF 0.47uF
R5804 C5810 50V
C5816
50V
SPEAKER_R
C 100 10uF 390pF
35V 50V
R5800 C5803 TAIYO_AMP_COIL C5824 R5814
R5810
1/10W
B Q5800 C5808 NRS6045T100MMGK
AMP_MUTE 1000pF 0.1uF 4.7K
3.3
2N3904S 50V
5%
10K 22000pF L5804 50V
E KEC_AMP_MUTE_TR
WOOFER_MUTE
50V 10.0uH
I2S_AMP
SPK_R-
SM-6045-100
GET_AMP_COIL
L5804-*1
C 10.0uH 4P Box type
B WAFER-ANGLE
Q5800-*1
MMBT3904(NXP)
NXP_AMP_MUTE_TR
E
TP5801 WOOFER_MUTE SPK_L+
4
TP5802 I2S_AMP
SPK_L-
3
SPK_R+
2
SPK_R-
1
P5800

STM_AMP 58
+12V
EU
L6000
IC6000
AUD_OUT >> EU/CHINA_HOTEL_OPT AZ4580MTR-E1 EU
C6004
EU 0.1uF
EU
C6000 50V
DTV/MNT_L_OUT
R6000 OUT1
1 8 VCC
EU
[SCART AUDIO MUTE]
10uF 2.2K EU
OPT OPT EU R6011 C6008
C6002 R6002 R6004 33K IN1- 7 OUT2 SIGN600013 2.2K
2 DTV/MNT_R_OUT DTV/MNT_L_OUT
6800pF 470K
C6003 33pF 10uF
EU IN1+ EU 6 IN2- R6008

EU
33K
OPT
R6010
OPT
3 C6007
470K EU
C6005 33pF 6800pF C
R6013
VEE 5 IN2+
EU Q6000 B 1K
4
MMBT3904(NXP) EU_SCART_MUTE_ISAHAYA
SCART_AMP_L_FB
E EU Q6002
RT1P141C-T112
R6007
1/16W
E
100K
EU SCART_AMP_R_FB SCART_MUTE
OPT
5%
EU
R6012
1/16W
R6006 R6020
100K
5.6K 0
OPT
B
SCART_Lout
5%
EU
1/16W EU
R6009
1/16W
R6021 R6016
100K
330pF 220K 5% DTV/MNT_R_OUT PDTA114ET

OPT
C6009 R6005 0 5.6K

5%
Q6002-*1
EU EU SCART_Rout
E
EU
R6015
1/16W
1/16W
100K
5% EU EU C
OPT
R6017 C6012 R6014

5%
220K 330pF Q6001 B 1K
B
MMBT3904(NXP)
EU_SCART_MUTE_NXP
CLOSE TO MSTAR E EU
CLOSE TO MSTAR
Near Place Scart AMP

EU
R6019
0 EU
SCART_AMP_R_FB
1/16W 10K
5% R6003
EU
R6018
0 EU
SCART_AMP_L_FB
1/16W 10K
5% R6001

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART AMP 17
EARPHONE AMP
C6100-*1
C6101-*1
CN_DRA
CN_DRA
2.2uF
2.2uF
IC6100
10V
TPA6138A2
10V
+INR +INL
C6104 1 14 C6109
C6100 18pF 18pF C6101
1uF R6100 R6106 R6104 R6101 1uF
10V 10K 43K -INR -INL 43K 10K 10V
2 13
HP_ROUT_MAIN HP_LOUT_MAIN
R6103
R6102
NON_CN_DRA
R6108
NON_CN_DRA
R6107
1% C6108 C6106 1%
43K
43K
OPT
10pF
OPT
1%
1%
OUTR OUTL 10pF
50V 3 12
0
50V
0
HP_LOUT_AMP
HP_ROUT_AMP
+3.3V_NORMAL GND_1 UVP
4 11
MUTE GND_2 +3.3V_NORMAL

4.7K 5 10
R6105
SIDE_HP_MUTE VSS VDD

6 9
C6105 C6107
C6102 CN CP 1uF 0.1uF
1uF 7 8
10V 16V
10V
C6103
1uF
10V

HP_AMP 61
B-CAS (SMART CARD) INTERFACE
+3.3V_NORMAL INT CMDVCC : STATUS

+3.3V_NORMAL ---------------------------------
HIGH HIGH CARD PRESENT
LOW HIGH CARD not PRESENT
SIGN630005
IC6300
TDA8024TT
2.7K
2.7K
R6301
R6303
R6305
JAPAN
JAPAN
CLKDIV1 CLKDIV2 : F_CRD_CLK

OPT
-----------------------------
1 0 CLKIN CLKDIV1 AUX2UC
1 28
JAPAN
JAPAN
JAPAN
R6317
R6318
R6315
R6319
R6316
OPT
OPT
1.2K
1.2K
1.2K
1.2K
1.2K
CLKDIV2 AUX1UC
2 27
R6300 33 5V/3V I/OUC

SMARTCARD_PWR_SEL TPO_DATA[1] 3 26
2.7K
JAPAN
R6302
R6304
R6306
JAPAN
OPT
OPT
PGND XTAL2
+5V_NORMAL 4 25
R6307 33 JAPAN
S2 XTAL1 TPO_DATA[6] SMARTCARD_DATA
JAPAN 5 24 R6308 33 JAPAN
TPO_DATA[5] SMARTCARD_CLK
L6300 R6309 33 JAPAN
TPO_DATA[3] SMARTCARD_DET
BLM18PG121SN1D VDDP OFF R6310 33 JAPAN
JAPAN 6 23 TPO_DATA[4] SMARTCARD_RST
JAPAN
C6301 C6303
10uF 0.1uF S1 GND JAPAN
10V 16V 7 22 R6311 33 TPO_DATA[2] SMARTCARD_VCC
L6301 JAPAN
+3.3V_NORMAL
JAPAN
VUP VDD BLM18PG121SN1D
8 21
JAPAN
JAPAN JAPAN
C6302 PRES RSTIN C6305 C6306
0.1uF 9 20 0.1uF 0.1uF
16V 16V 16V
B-CAS SLOT
PRES CMDVCC
10 19
P6300
I/O PORADJ 10057542-1311FLF(B CAS Slot)
11 18
AUX2 VCC JAPAN VCC

12 17 C1
C6307
0.33uF
AUX1 RST 16V RST
13 16 C2
CGND CLK Place CLK C3 far from C2,C7,C4 and C8 CLK

14 15 C3
JAPAN
C6304 RESERVED_1
0.1uF C4
16V
GND
C5
VPP JAPAN
C6
JAPAN
R6313
75 I/O
C7
75 ohm in I/O is for short circuit Protection
RESERVED
C8
SW1
S1
+3.3V_NORMAL
JAPAN
JAPAN
10K
R6312
R6314
1K SW2
S2
ZD6300 ZD6301
JAPAN
JAPAN
5V 5V

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS JAPAN B-CAS 2011.04.17
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 63
FE_DEMOD1_TS_ERROR
FE_DEMOD2_TS_ERROR
FE_DEMOD3_TS_CLK
1. should be guarded by ground FE_DEMOD3_TS_SYNC
2. No via on both of them FE_DEMOD3_TS_VAL
3. Signal Width >= 12mils FE_DEMOD3_TS_ERROR
close to Tuner Signal to Signal Width = 12mils FE_DEMOD3_TS_DATA
+3.3V_TUNER Ground Width >= 24mils
L6500
PZ1608U121-2R0TF close to TUNER
1 +3.3V_LNA_TU C6501
0.1uF TU_K/M/W_TW/BR/CO R6507 1K
TU_K/M/W_TW/BR/CO TU_K/M/W_TW/BR/CO
2 RF_SWITCH_CTL_TU RF_SWITCH_CTL
C6504 R6503
0.1uF 10K
TU_ALL_IntDemod
R6506 1K
3 IF_AGC_TU IF_AGC
C6502 close to Tuner TU_ALL_IntDemod
0.1uF
16V TU_W_BR/TW
TU_ALL AR6500-*1
AR6500
33 200
1/16W +3.3V_NORMAL
PZ1608U121-2R0TF
4 I2C_SCL5_TU I2C_SCL5
C6505
I2C_SDA5 +3.3V_TUNER
47pF
L6504
5 50V
I2C_SDA5_TU +3.3V_TUNER 1608 perallel
C6503 OPT
because of derating
47pF
50V
OPT TU_ALL_2178B TU_SIF
TU_ALL_2178B TU_ALL_2178B
R6513 0 R6516 R6517
R6504 200 200
10
6 IF_P_TU
TU_ALL_IntDemod C6519 IF_P C6517 C6508
33pF L6502 TU_CVBS 22uF 0.1uF
should be guarded by ground,Match GND VIA R6505 OPT 10V 16V
10 TU_H/M_EU/BR/TW/CO/KR/US E
7 IF_N_TU C6520 IF_N
TU_ALL_IntDemod 33pF KEC_TU_ALL_2178B_TR
TU_H/M_EU/BR/TW/CO/KR/US B Q6502
2N3906S-RTK
8 TU_SIF_TU C
E
TU_M_KR/EU // W_ALL
9 TU_CVBS_TU NXP_TU_ALL_2178B_TR
L6501 +3.3V_TUNER B Q6502-*1
Global F/E Option Name PZ1608U121-2R0TF MMBT3906(NXP)
1. TU C
10
2. Tuner Name = TDJ’H’,TDj’M’... C6510
3. Country Name = KR,US,BR,EU ... 0.1uF
11 +3.3V_TU
TU_M_KR/EU // W_ALL
T2 : Max 1.7A
Example of Option name else : Max 0.7A
12 close to Tuner

TU_ALL_IntDemod = All Tuner type for Internal demod FE_DEMOD1_TS_ERROR
TU_M/W = apply TDSM&TDSW Type Tuner FE_DEMOD1_TS_ERROR
TU_M/W_1.2V
14 FE_DEMOD1_TS_CLK FE_DEMOD1_TS_CLK TU_M/W Demod_Core
R6519-*1 R6521-*1
IC6500
TU_M/W_1.1V TU_M/W_1.1V
14’ Tuner Type for Global
15 AP2132MP-2.5TRG1
[EP]
TDJ’H’-G101D : Half NIM for EU,AJJA FE_DEMOD1_TS_SYNC FE_DEMOD1_TS_SYNC
18K
10K
R6521
TDJ’H’-H101F : Half NIM for US, KR
TDJ’K’-T101F : Half NIM for TW FE_DEMOD1_TS_VAL FE_DEMOD1_TS_VAL TU_M/W PG GND R2
16 1 8
TDJ’M’-C301D,F : FULL NIM for China
THERMAL
+3.3V_NORMAL C6516
10.5K
R6519
TU_M/W_1.2V
TDJ’M’-B101F : Brazil NIM with Isolater Type 0.1uF
16K
EN ADJ
9
17 FE_DEMOD1_TS_DATA[0] 2 7
TDJ’M’-K101F : colombia NIM R1
R6500
TU_M/W
10K
TDJ’M’-G101D,G105D,G151D : EU Combo&Full NIM VIN VOUT
18 FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[0-7]
TDJ’M’-H101F,H151F : Korea PIP tuner 3 6
TDJ’W’-A151D : AJJA T2 PIP FE_DEMOD1_TS_DATA[0]
19 FE_DEMOD1_TS_DATA[2] FE_DEMOD1_TS_DATA[1] +5V_NORMAL
VCTRL
4 2A 5
NC
FE_DEMOD1_TS_DATA[2] TU_M/W TU_M/W

FE_DEMOD1_TS_DATA[3]
20 FE_DEMOD1_TS_DATA[3] C6500 C6518
0.1uF 10uF
FE_DEMOD1_TS_DATA[4] 16V 10V
FE_DEMOD1_TS_DATA[4] TU_M/W
21 FE_DEMOD1_TS_DATA[5]
C6515
FE_DEMOD1_TS_DATA[6] 1uF
FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[7] 25V
22
Vout=0.6*(1+R1/R2)
TU_M/W
R6501
TU_M/W 100 /TU_RESET1 +3.3V_TUNER
25 /TU_RESET1_TU
C6507
TU_M/W
L6503
16V PZ1608U121-2R0TF
0.1uF
26 +3.3V_DEMOD_TU
C6511 TU_M/W
0.1uF
27 I2C_SCL2_TU TU_M/W TU_K/M/W_NON_JP 0 R6502
L6505 AR6501 FE_DEMOD1_TS_CLK_1 FE_DEMOD1_TS_CLK
33 TU_M/W TU_K/M/W_NON_JP 0 R6511
PZ1608U121-2R0TF OPT FE_DEMOD1_TS_SYNC_1 FE_DEMOD1_TS_SYNC
Demod_Core TU_K/M/W_NON_JP 0 R6512
28 D_Demod_Core
C6513 I2C_SCL2 FE_DEMOD1_TS_VAL_1 FE_DEMOD1_TS_VAL
TU_M/W 18pF I2C_SDA2 TU_K/M/W_NON_JP 0 R6514
C6506 50V FE_DEMOD1_TS_DATA0_1 FE_DEMOD1_TS_DATA[0]
0.1uF OPT
29 LNB_TX LNB_TX
C6512
18pF
50V
30 I2C_SDA2_TU
31 LNB_OUT LNB_OUT TU_JP 0 R6515

FE_DEMOD2_TS_CLK TU_JP 0 R6518
FE_DEMOD2_TS_SYNC TU_JP 0 R6520
34 FE_DEMOD2_TS_ERROR FE_DEMOD2_TS_ERROR FE_DEMOD2_TS_VAL
TU_JP 0 R6522
FE_DEMOD2_TS_DATA
36 FE_DEMOD2_TS_SYNC FE_DEMOD2_TS_SYNC
37 FE_DEMOD2_TS_CLK FE_DEMOD2_TS_CLK
L6506 +2.5V_Normal
BLM18PG121SN1D Close to Tuner
38 +2.5V_DEMOD
C6509 TU_JP
0.1uF
39 FE_DEMOD2_TS_VAL FE_DEMOD2_TS_VAL
TU_JP
40 FE_DEMOD2_TS_DATA FE_DEMOD2_TS_DATA
R6527
100 /TU_RESET2
45 /TU_RESET2_TU
C6514 TU_JP
16V
0.1uF
TU_JP

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_CIRCUIT 65
TU_K_BR TU_M_EU TU_W_JP
TU_H_US TU_M_T2_KR
TU6706 TU6705 TU6704 TU6702 TU6703
TDJK-T351F TDJH-H351F TDJM-H451F TDJM-G351D TDJW-J252F
B[3.3V] +3.3V +3.3V B1[+3.3V] B1[+3.3V]

1 1 1 1 1 +3.3V_LNA_TU 1
NC NC_1 NC_1 NC_1
2 2 2 2 RF_SWITCH_CTL_TU 2
IF_AGC DIF_AGC DIFAGC AIF_AGC NC_2
3 3 3 3 3 IF_AGC_TU 3
SCL SCL_RF SCL_RF SCL_RF SCL_RF
4 4 4 4 4 I2C_SCL5_TU 4
SDA SDA_RF SDA_RF SDA_RF SDA_RF
5 5 5 5 5 I2C_SDA5_TU 5
IF[P] DIF[P] DIF[P] AIF[P] NC_3
6 6 6 6 6 IF_P_TU 6
IF[N] DIF[N] DIF[N] AIF[N] NC_4
7 7 7 7 7 IF_N_TU 7
SIF SIF SIF SIF NC_5
8 8 8 8 8 TU_SIF_TU 8
CVBS CVBS CVBS CVBS NC_6
9 9 9 9 9 TU_CVBS_TU 9
NC_2 NC_2 NC_7
10 10 10 10
A1 B1 A1 B1 +3.3V_RF B2[+3.3V] B2[+3.3V]
A1 B1 A1 B1 11 11 11 +3.3V_TU 11
TU_GND_B
TU_GND_A
TU_GND_B
47 ERROR ERROR NC_8

TU_GND_A
47
12 12 12 FE_DEMOD1_TS_ERROR 12
GND GROUND GND_1
SHIELD SHIELD 13 13 13 13
MCLK MCKL
14 14 FE_DEMOD1_TS_CLK_1 14
SYNC SYNC
15 15 FE_DEMOD1_TS_SYNC_1
VALID VALID
16 16 FE_DEMOD1_TS_VAL_1 16
DATA DATA0
17 17 FE_DEMOD1_TS_DATA0_1 17
NC_3 DATA1
18 18 FE_DEMOD1_TS_DATA[1] 18
NC_4 DATA2
NC_5 DATA3
NC_6 DATA4
NC_7 DATA5
NC_8 DATA6
EMS Improvement NC_9 DATA7
TU_GND_A
C6704 C6705 RESET_DEMOD RESET_DEMOD M_RESET_DEMOD
3300pF 3300pF 25 25 25 /TU_RESET1_TU 25
630V 630V
TU_GND_B +3.3V_DEMOD B3[+3.3V] B3[+3.3V]
26 26 26 +3.3V_DEMOD_TU 26
SCL_DEMOD. SCL_DEMOD SCL_DEMOD
27 27 27 I2C_SCL2_TU 27
+1.2V_DEMOD B4[+1.2V] B4[+1.2V]
28 28 28
TUNER EMS GND SEPERATION 29
NC_10
29
F22_OUTPUT
29
NC_9
D_Demod_Core
LNB_TX
SDA_DEMOD SDA_DEMOD SDA_DEMOD
30 30 30 I2C_SDA2_TU 30
TU_GND_A
TU_GND_B
DVB ESD LNB LNB

31 31 LNB_OUT 31
Improvement
A1 B1 GND GND_2
A1 B1 32 32 32
TU_AJ/EU/JP_ESD
TU_AJ/EU/JP_ESD
TU_AJ/EU/JP_ESD
C6700
47 NC_10
C6703 C6707
TU_GND_A
33 33
0 R6705
0 R6706
0 R6707
TU_GND_B
1000pF 1000pF 1000pF

630V 630V A1 B1 M_ERROR
C6706 R6700 630V C6708
TU_GND_A3_1nF TU_GND_B1_1nF TU_GND_B3_1nF SHIELD A1 B1 34 34
0.022uF 0 1000pF FE_DEMOD2_TS_ERROR
R6708
630V R6703 R6704 630V
TU_GND_A2_0ohm
22 22 0 TU_GND_B4_1nF 47 GND_3
TU_GND_A 35 35
TU_GND_A1_22nF TU_GND_B5_0ohm
TU_GND_B
TU_GND_A4_22ohm TU_GND_B2_22ohm
M_SYNC
C6703-*1 C6707-*1 C6708-*1 SHIELD 36
0.022uF 0.022uF 0.022uF FE_DEMOD2_TS_SYNC 36
C6706-*1 R6700-*1 630V 630V 630V M_MCLK
1000pF C6700-*1 TU_GND_B1_22nF TU_GND_B4_22nF
0.022uF
0.022uF
TU_GND_B3_22nF 37 FE_DEMOD2_TS_CLK
630V 630V
630V 1st layer R6704-*1 R6704-*2 R6708-*1
TU_GND_A1_1nF TU_GND_A2_22nF 0 10 22 B5[+2.5V]
TU_GND_A3_22nF
38 +2.5V_DEMOD
4th Layer TU_GND_B2_0ohm TU_GND_B2_10ohm TU_GND_B5_22ohm
M_VALID
39 FE_DEMOD2_TS_VAL
GND_A GND_B M_DATA
40 FE_DEMOD2_TS_DATA 40
S_ERROR
41 FE_DEMOD3_TS_ERROR 41
S_SYNC
42 FE_DEMOD3_TS_SYNC 42
TU_GND_A EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP TU_M_TW/PA
S_MCLK
TU_W_JP_RDA5817
TU_M_CO TU_M_AJ/JA TU_M_CN 43 FE_DEMOD3_TS_CLK 43
TU6704-*1
TU6703-*1 TU6704-*4 TU6704-*3 TU6704-*2
TDJM-C451D
TDJW-J351F
TDJM-K352F TDJM-K351F TDJM-G355D S_VALID
GND A_1 X X 22 nF X 22 nF 1 nF 1
+3.3V_LNA B1[+3.3V] 44 FE_DEMOD3_TS_VAL 44
B1[+3.3V] B1[+3.3V] B1[+3.3V] 1
NC_1 1 1 1
2 NC_1
3
NC_2 2
NC_1 2
NC_2 S_RESET_DEMOD
GND A_2 X 22 nF 0 ohm
4
SCL_RF
3
NC_1
3
NC_1 3
AIF_AGC 3
45 /TU_RESET2_TU 45
0 ohm 0 ohm 0 ohm 5
6
SDA_RF
NC_3 4
SCL_RF
4
SCL_RF 4
SCL_RF 4
SCL_RF
SDA_RF
7
NC_4 5
SDA_RF
5
SDA_RF 5
SDA_RF 5
NC_3 S_DATA
22 nF 8
NC_5
6
NC_2
6
NC_2 6
AIF[P] 6
NC_4 46 FE_DEMOD3_TS_DATA 46
GND A_3 1 nF 1 nF X 22 nF 1 nF 9
NC_6
NC_7
7
NC_3
7
NC_3 7
AIF[N] 7
SIF
10 SIF SIF SIF 8
8 8 8
+3.3V_RF CVBS
11 CVBS 9
12
NC_8
GND_1
9
CVBS
NC_4
9
CVBS
NC_4
9
NC_2 10
NC_5 47
13 10 10 10
NC_6
GND A_4 22 ohm 22 ohm X 22 ohm 22 ohm NC_5 NC_5 11

B2[+3.3V] 11
A1 B1
22 ohm 11
12
ERROR
11
12
ERROR 12
ERROR 12
ERROR
A1 B1 48
GROUND
GND GND GND 13
13 13 13
MCLK
14
MCLK
14
MCLK 14
MCLK 14
SYNC 47
15
SYNC
15
SYNC 15
SYNC 15
VALID
49
TU_GND_B EU/CIS AJJA TW/COL CN/HK KR North.AM BR JP VALID VALID VALID 16
TU_GND_A
16 16 16
DATA0
TU_GND_B
DATA0 DATA0 DATA0 17
17 17 17
DATA1
18
DATA1
18
DATA1 18
DATA1
DATA2
18
19
DATA2 SHIELD
DATA2 DATA2 19
GND B_1 19 19 DATA3
1 nF 1 nF 22 nF X 22 nF X 25
26
RESET_M_DEMOD
+3.3V_DEMOD 20
DATA3
20
DATA3 20
DATA3
DATA4
20
21
DATA4
SCL_DEMOD
DATA4 DATA4 21
27 21 21 DATA5
+1.2V_DEMOD DATA5 DATA5 DATA5 22
28 22 22 22
DATA6
NC_9
DATA6 DATA6 DATA6 23
GND B_2 10 ohm 10 ohm 22 ohm X 22 ohm X
29
30
SDA_DEMOD
23
24
DATA7
23
24
DATA7
23
24
DATA7 24
DATA7
LNB RESET_DEMOD
31 RESET_DEMOD 25
GND_2
RESET_DEMOD RESET_DEMOD 25
32 25 25 B2[+3.3V]
NC_10 B2[+3.3V] B2[+3.3V] B3[+3.3V] 26
33 26 26 26
SCL_DEMOD
GND B_3 1 nF 1 nF X 1 nF 22 nF 1 nF
34
35
M_ERROR
GND_3
27
SCL_DEMOD
B3[+1.2V]
27
SCL_DEMOD
B3[+1.2V]
27
SCL_DEMOD
B4[+1.2V]
27
28
B3[+1.2V]
28 28 28
M_SYNC NC_7
36 NC_3 29
M_MCLK
NC_6 NC_6 29
37 29 29 SDA_DEMOD
+2.5V_DEMOD SDA_DEMOD SDA_DEMOD SDA_DEMOD 30
38 30 30 30
GND B_4 1 nF 22 nF
1 nF 1 nF 22 nF 1 nF 39
40
M_VALID
M_DATA
A1 B1 A1 B1 A1 B1
A1
A1 B1
B1
A1 B1 A1 B1 A1 B1
S_ERROR 47
41 47
S_SYNC
47 47
42
S_MCLK SHIELD
43 SHIELD SHIELD SHIELD
S_VALID
GND B_5 0 ohm X 0 ohm 44
45
S_RESET_DEMOD
S_DATA
46
A1 B1
A1 B1
47
SHIELD

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2014-08-11
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TU_SYMBOL_V_DVB 67_01
DVB-S2 LNB Part Allegro
(Option:LNB) Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A

3A
+12V
2A
D6904-*1
Max 1.3A
LNB
40V
LPH6050T-150M-R
LNB_TSC LNB_SX34 L6900
D6902-*1 D6902
3.5A
SS23L LNB_ONSEMI D6904
30V 40V 15uH

30V
LNB_SMAB34
C6909
10uF
C6903 C6905 C6906 C6907 25V
0.01uF 10uF 10uF 10uF LNB
50V 25V 25V 25V
LNB LNB LNB LNB
C6908 0.1uF
close to Boost pin(#1)

LNB_ALLEGRO
A_GND A_GND
30V
[EP]GND
close to VIN pin(#15) Caution!! need isolated GND

BOOST
GNDLX
NC_3 R6904
NC_2
SS23L C6910 0
A_GND
LX
D6901-*1 0.1uF
LNB_TSC 50V
20
19
18
17
16
LNB
D6901 VCP 1 15 VIN
MBR230LSFT1G THERMAL A_GND
LNB 2 14 GND
LNB_OUT 21
30V LNB
D6903 NC_1 3 13 VREG
LNB_ONSEMI C6904
0.1uF LNB_SMAB34 IC6900 R6903
C6900 C6901 R6900 TDI ISET 39K
2.2K LNB 50V 40V A8303SESTR-T
4 12
0.1uF 33pF
D6900 1W LNB_ALLEGRO 1/16W
LNB LNB C6902 TDO 5 11 TCAP C6912
LNB LNB 0.22uF 1%
LNB 25V D6903-*1
10
LNB
LNB_SX34
6
0.1uF
40V
IRQ
SCL
SDA
ADD
TONECTRL
0.22uF
BOOST
Close to Tuner
[EP]
NC_4
NC_3
PGND
A_GND A_GND +3.3V_NORMAL

LX
Surge protectioin
20
19
18
17
16
NC_1 1 15 VIN
LNB
THERMAL
LNB 2 14 GND
21
R6907
3.3K
C6911
NC_2 3 13 VREG
OPT
IC6900-*1
TDI 4 DT1803 12 ISET
TDO LNB_DMBT TCAP

5 11
10
6
9
IRQ
SCL
SDA
ADD
TONECTRL
LNB
R6906
0
R6901 33
R6902 33
LNB
LNB_NON_Tx
LNB_Tx
LNB
R6905
R6908
0
0
I2C_SDA2
LNB_TX
I2C_SCL2

ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR 20
LNB
[51P Vx1
output wafer]
51pin_Wafer
P7100
FI-RE51S-HF-J-R1500
+3.3V_NORMAL
2 TXDAP7_L
LOCKAn_HTPDAn_3.3VPullup
3 TXDAN7_L LOCKAn_HTPDAn_3.3VPullup R7121
4 +1.8V R7115 10K
10K LOCKAn
5 TXDAP6_L LOCKAn_HTPDAn_3.3VPullup
R7118 C
6 10K
TXDAN6_L LOCKAn_HTPDAn_3.3VPullup B Q7105
R7109 MMBT3904(NXP)
7
10K LOCKAn_HTPDAn_3.3VPullup
E
C
9 R7111
TXDAN5_L 100 B Q7101
10 MMBT3904(NXP)
LOCKAn_IN
11 E LOCKAn_HTPDAn_3.3VPullup
TXDAP4_L
12 TXDAN4_L
13
14 TXDAP3_L
+3.3V_NORMAL
15 TXDAN3_L
16
17 TXDAP2_L
LOCKAn_HTPDAn_3.3VPullup
18 TXDAN2_L LOCKAn_HTPDAn_3.3VPullup R7120
19 +1.8V R7114 10K
10K HTPDAn
R7117 C
21 10K
TXDAN1_L LOCKAn_HTPDAn_3.3VPullup B Q7104
22 R7108 MMBT3904(NXP)
10K LOCKAn_HTPDAn_3.3VPullup
E
C
24 TXDAN0_L R7110
+3.3V_NORMAL 100 B Q7100
25 MMBT3904(NXP)
HTPDAn_IN
26 E LOCKAn_HTPDAn_3.3VPullup
LOCKAn_IN
R7125
10K
27 HTPDAn_IN
28
D
29 R7103 G Q7102-*1
0 +3.3V_NORMAL 2N7002K
30 POWER_DET_1
EL_VDD_DETECT_22V TCON_I2C_EN S
31 JP7101 R7106 DIODE_FET
G
4.7K KEC_FET
32 EL_VDD_DETECT_22V OPT
R7112 0 R7122 0
I2C_SCL6
33
S
Q7102
34 2N7002KA
R7116
35
33 OPT D
36 +3.3V_NORMAL
G Q7103-*1
2N7002K
37 TCON_I2C_EN
R7107 KEC_FET S
G
4.7K DIODE_FET
38
OPT R7123 0
R7113 0
39 I2C_SDA6
R7101
S
JP7102 0
40 T_CON_SYS_POWER_OFF Q7103
2N7002KA
0 R7104
41 INV_CTL R7119
0 R7105
42 COMPENSATION_DONE 33 OPT
R7100
R7124
43 0
10K
JP7103
COMPENSATION_DONE_1
44 OPT
45 CONPENSATION_DONE -> TEMP USE(HDMI ARC PROBLEM)

R7102 CONPENSATION_DONE1 -> FINAL USE
46 0
LED_R
47 T_CON_SYS_POWER_OFF
48
49
50
51
52
Data_Format_0
Data_Format_1
L_DIM_EN
3D&L_DIM_EN
3D_EN

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Vx1 51P 21
[41P Vx1
output wafer]
41pin_Wafer
P7200
FI-RE41S-HF-J-R1500
10
11
12
13
14
15
16
17
18 TXDBP7_L
19 TXDBN7_L
20
21 TXDBP6_L
22 TXDBN6_L
23
24 TXDBP5_L
25 TXDBN5_L
26
27 TXDBP4_L
28 TXDBN4_L
29
30 TXDBP3_L
31 TXDBN3_L
32
33 TXDBP2_L
34 TXDBN2_L
35
36 TXDBP1_L
37 TXDBN1_L
38
39 TXDBP0_L
40 TXDBN0_L
41
42

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS UF71/7500 14/07/19
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Vx1 41P 22
eMMC I/F
DVDD18_EMMC 3.3v power delete, 131120
R8117
R8116
1/16W
10K
AR8104
1/16W
10K
AR8103
10K
10K
IC8100 IC8100-*1 IC8100-*2 IC8100-*3

THGBMBG5D1KBAIL THGBMBG6D1KBAIL H26M41103HPR KLM4G1FEPD-B031
EMMC_DATA[0-7] AR8100
EMMC_DATA[0] 0
1/16W
EMMC_DATA[1] A3 C8 A3 C8 A3 C7 A3 C7
DAT0 NC_23 DAT6 DAT0 NC_23 DAT0 NC_22 DAT0 NC_22
EMMC_DATA[2] A4 C9 A4 C9 A4 C8 A4 C8
DAT1 NC_24 DAT1 NC_24 DAT1 NC_23 DAT1 NC_23
A5 C10 A5 C10 A5 C9 A5 C9
EMMC_DATA[3] DAT2 DAT2 DAT2 DAT2 NC_24
NC_25 NC_25 NC_24 B2 C10
EMMC_DATA[4] B2 C11 B2 C11 B2 C10 DAT3
DAT3 NC_26 DAT3 NC_26 DAT3 NC_25 NC_25
B3 C12 B3 C12 B3 C11 B3 C11
EMMC_DATA[5] DAT4 NC_26
DAT4 NC_27 DAT4 NC_27 DAT4 NC_26 B4 C12
EMMC_DATA[6] B4 C13 B4 C13 B4 C12 DAT5
DAT5 NC_28 DAT5 NC_28 DAT5 NC_27 NC_27
B5 C14 B5 C14 B5 C13 B5 C13
DAT6 NC_29 DAT6 NC_29 DAT6 NC_28 DAT6 NC_28
EMMC_DATA[7] B6 D1 B6 D1 B6 C14 B6 C14
DAT7 NC_30 DAT5 DAT7 NC_30 DAT7 NC_29 DAT7 NC_29
D2 D2 D1 D1
NC_31 NC_31 NC_30 NC_30
0 R8104 D3 D3 D2 D2
NC_32 NC_32 NC_31 NC_31
0 R8105 M6 D4 M6 D4 M6 D3 M6 D3
CLK NC_33 CLK NC_33 CLK NC_32 CLK NC_32
0 R8106 M5 D12 M5 D12 M5 D4 M5 D4
CMD NC_34 CMD NC_34 CMD NC_33 CMD NC_33
0 R8107 D13 D13 D12 D12
NC_34
eMMC V5.0 GND NC_35
D14
NC_35
D14
NC_34
D13 D13
NC_36 NC_36 NC_35 NC_35
A6 E1 A6 E1 A7 D14 A7 D14
VSS_1 NC_37 VSS_1 NC_37 RFU_1 NC_36 RFU_1 NC_36
A7 E2 A7 E2 E5 E1 E5 E1
RFU_2 NC_38 RFU_2 NC_38 RFU_2 NC_37 RFU_2 NC_37
C5 E3 C5 E3 G3 E2 G3 E2
NC_21 NC_39 NC_21 NC_39 RFU_3 NC_38 RFU_3 NC_38
E5 E12 E5 E12 K6 E3 K6 E3
AR8102 RFU_4 NC_40 RFU_4 NC_40 RFU_4 NC_39 RFU_4 NC_39
E8 E13 E8 E13 K7 E12 K7 E12
0 1/16W RFU_5 NC_41 RFU_5 NC_41 RFU_5 NC_40 RFU_5 NC_40
E9 E14 E9 E14 E8 E13 E8 E13
EMMC_CLK VSF_1 NC_42 VSF_1 NC_42 VSF_1 NC_41 RFU_6 NC_41
E10 F1 E10 F1 E9 E14 E9 E14
RFU_7 NC_42
DAT7
EMMC_CMD VSF_2 NC_43 VSF_2 NC_43 VSF_2 NC_42 E10 F1

F10 F2 F10 F2 E10 F1 RFU_8
EMMC_RST VSF_3 NC_44 VSF_3 NC_44 VSF_3 NC_43 NC_43
G3 F3 G3 F3 F10 F2 F10 F2
RFU_9 NC_45 RFU_9 NC_45 VSF_4 NC_44 RFU_9 NC_44
G10 F12 G10 F12 G10 F3 G10 F3
RFU_10 NC_46 RFU_10 NC_46 VSF_5 NC_45 RFU_10 NC_45
H5 F13 H5 F13 K10 F12 K10 F12
DS NC_47 DS NC_47 VSF_6 NC_46 RFU_11 NC_46
J5 F14 J5 F14 P10 F13 P10 F13
C8107 VSS_5 NC_48 VSS_5 NC_48 VSF_7 NC_47 RFU_13 NC_47
K6 G1 K6 G1 H5 F14 H5 F14
OPT 10pF DS NC_48
RFU_13 NC_49 RFU_13 NC_49 DS NC_48 G1
50V K7 G2 K7 G2 G1
RFU_14 NC_50 RFU_14 NC_50 NC_49 NC_49
EMMC_STRB K10 G12 K10 G12 G2 G2
RFU_15 NC_51 RFU_15 NC_51 NC_50 NC_50
P7 G13 P7 G13 G12 G12
R8103
RFU_16 NC_52 RFU_16 NC_52 NC_51 NC_51

P10 G14 P10 G14 G13 G13
10K
RFU_17 NC_53 RFU_17 NC_53 NC_52 NC_52

H1 H1 G14 G14
NC_54 NC_54 NC_53 NC_53
EMMC_STRB H1
H2 H2 H1 NC_54
NC_55 NC_55 NC_54 K5 H2
K5 H3 K5 H3 K5 H2 RSTN
RSTN NC_56 RSTN NC_56 RSTN NC_55 NC_55
H12 H12 H3 H3
C8100 DVDD18_EMMC NC_56
EMMC5.0_4G_TOSHIBA
NC_57 NC_57 NC_56 H12

H13 H13 H12
EMMC5.0_8G_TOSHIBA
OPT 0.1uF NC_57
NC_58 NC_58 NC_57 C6 H13
16V C6 H14 C6 H14 C6 H13
VCCQ_1 NC_59 VCCQ_1 NC_59 VCCQ_1 NC_58 VDD_1 NC_58
M4 J1 M4 J1 M4 H14 M4 H14
3.3V_EMMC VDD_2 NC_59
VCCQ_2 NC_60 VCCQ_2 NC_60 VCCQ_2 NC_59 N4 J1
N4 J2 N4 J2 N4 J1 VDD_3 NC_60
EMMC5.0_8G_HYNIX
VCCQ_3 NC_61 VCCQ_3 NC_61 VCCQ_3 NC_60 P3 J2
P3 J3 P3 J3 P3 J2
EMMC5.0_4G_SS
Bottom P5 J12 P5 J12 P5 J3 P5 J3
J12
DAT3
DAT4
DAT5
DAT6
EMMC_CLK_BALL
EMMC_CMD_BALL
EMMC_RESET_BALL
OPT OPT J13 J13 J12 NC_63

C8108 C8109 C8105 C8106 NC_64 NC_64 NC_63 J13
0.1uF 2.2uF 0.1uF 2.2uF J14 EMMC_RESET_BALL J14 J13 NC_64
NC_65 NC_65 NC_64 E6 J14
16V 10V 16V 10V E6 K1 E6 K1 E6 J14
VCC_1 NC_66 VCC_1 NC_66 VCC_1 NC_65 VDDF_1 NC_65
F5 K2 F5 K2 F5 K1 F5 K1
J10 K3 J10 K3 J10 K2 J10 K2
K9 K12 K9 K12 K9 K3 K9 K3
K13 K13 K12 K12
NC_70 NC_70 NC_69 NC_69
K14 K14 K13 K13
EMMC_VDDI NC_70
Bottom pattern 0.2mm NC_71 NC_71 NC_70 C2 K14
C2 L1 C2 L1 C2 K14 VDDI
VDDI NC_72 VDDI NC_72 VDDI NC_71 NC_71
OPT L2 L2 L1 L1
C8101 C8104 NC_73 NC_73 NC_72 NC_72
L3 L3 L2 L2
1uF 2.2uF NC_73
NC_74 NC_74 NC_73 C4 L3
10V 10V E7 L12 E7 L12 C4 L3
VSS_2 NC_75 VSS_2 NC_75 VSSQ_1 NC_74 VSS_1 NC_74
G5 L13 G5 L13 N2 L12 N2 L12
H10 L14 H10 L14 N5 L13 N5 L13
K8 M1 K8 M1 P4 L14 P4 L14
OPT VSS_4 NC_77
VSS_6 NC_78 VSS_6 NC_78 VSSQ_4 NC_77 P6 M1
C8102 C8103 C8111 C4 M2 C4 M2 P6 M1
VSSQ_1 NC_79 VSSQ_1 NC_79 VSSQ_5 NC_78 VSS_5 NC_78
0.1uF 2.2uF 4.7uF N2 M3 N2 M3 A6 M2 A6 M2
16V 10V 10V EMMC_CLK_BALL VSS_6 NC_79
VSSQ_2 NC_80 VSSQ_2 NC_80 VSS_1 NC_79 E7 M3
N5 M7 N5 M7 E7 M3 VSS_7
VSSQ_3 NC_81 VSSQ_3 NC_81 VSS_2 NC_80 NC_80
P4 M8 P4 M8 G5 M7 G5 M7
VSSQ_4 NC_82 VSSQ_4 NC_82 VSS_3 NC_81 VSS_8 NC_81
P6 M9 P6 M9 H10 M8 H10 M8
VSSQ_5 NC_83 VSSQ_5 NC_83 VSS_4 NC_82 VSS_9 NC_82
M10 M10 J5 M9 J5 M9
NC_84 NC_84 VSS_5 NC_83 VSS_10 NC_83
M11 M11 K8 M10 K8 M10
NC_85 NC_85 VSS_6 NC_84 VSS_11 NC_84
M12 M12 M11 M11
NC_86 NC_86 NC_85 NC_85
A1 M13 A1 M13 M12 M12
DAT3 NC_1 NC_87 NC_1 NC_87 NC_86 NC_86
A2 M14 A2 M14 A1 M13 A1 M13
DAT4 NC_2 NC_88 NC_2 NC_88 NC_1 NC_87 NC_1 NC_87
A8 N1 A8 N1 A2 M14 A2 M14
A9 N3 A9 N3 A8 N1 A8 N1
EMMC_CMD_BALL NC_3 NC_89
NC_4 NC_90 NC_4 NC_90 NC_3 NC_89 A9 N3
A10 N6 A10 N6 A9 N3 NC_4
NC_5 NC_91 NC_5 NC_91 NC_4 NC_90 NC_90
A11 N7 A11 N7 A10 N6 A10 N6
NC_6 NC_92 NC_6 NC_92 NC_5 NC_91 NC_5 NC_91
A12 N8 A12 N8 A11 N7 A11 N7
A13 N9 A13 N9 A12 N8 A12 N8
A14 N10 A14 N10 A13 N9 A13 N9
B1 N11 B1 N11 A14 N10 A14 N10
B7 N12 B7 N12 B1 N11 B1 N11
B8 N13 B8 N13 B7 N12 B7 N12
B9 N14 B9 N14 B8 N13 B8 N13
B10 P1 B10 P1 B9 N14 B9 N14
B11 P2 B11 P2 B10 P1 B10 P1
B12 P8 B12 P8 B11 P2 B11 P2
NC_15 NC_101
Don’t Connect Power At VDDI EMMC_VDDI DVDD18_EMMC B13
B14
NC_16
NC_17
NC_102
NC_103
P9
P11
B13
B14
NC_16
NC_17
NC_102
NC_103
P9
P11
B12
B13
NC_15
NC_16
NC_101
NC_102
P7
P8
B12
B13
NC_16 RFU_12
P7
P8
C1 P12 C1 P12 B14 P9 B14 P9
NC_18 NC_103
(Just Interal LDO Capacitor) DAT5
C3
NC_19
NC_20
NC_105
NC_106
P13 C3
NC_19
NC_20
NC_105
NC_106
P13 C1
NC_18
NC_19
NC_104
NC_105
P11 C1
NC_19 NC_104
P11
C7 P14 C7 P14 C3 P12 C3 P12
C5 P13 C5 P13
NC_21 NC_107 NC_21 NC_106
P14 P14
NC_108 NC_107

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. eMMC 81
RS-232C Control INTERFACE
RS232C
R6820
100
+3.5V_ST DOUT1
RS232C
R6821
100
RIN1
OPT OPT
ZD6802 ZD6803
ADUC 20S 02 010L ADUC 20S 02 010L
RS232C 20V 20V
RS232C C6813
0.1uF
IC6801
MAX3232CDR
C1+ VCC
RS232C 1 16
C6808
0.1uF V+ GND
RS232C 2 15
C6809
0.1uF C1- DOUT1
3 14
C2+ RIN1
RS232C 4 13
C6810
0.1uF C2- ROUT1
5 12
SOC_RX
V- DIN1
RS232C 6 11
SOC_TX
C6811
0.1uF DOUT2 DIN2
7 10
RIN2 ROUT2
8 9
EAN41348201

RS232C 22
URSA9 VIDEO/OSD LOCKn
+3.3V_NORMAL
VDDP
4st Layer
L2190
BLM18PG121SN1D
LOCKAn_Video LOCKAn_Video C2190 C2145 C13314 C13315
R12902 10K
+3.3V_NORMAL 10uF 0.1uF 0.1uF 10uF
10V 16V 16V 10V
Close to Chip side

AVDD_PLL 4st Layer
L2101
BLM18PG121SN1D
LOCKAn_OSD LOCKAn_OSD
R12903 10K
+3.3V_NORMAL
C2105 C2192 C13302 C2151
R12904
VBY1_LOCK_LED
10uF 0.1uF 0.1uF 10uF
22
VBY1_LOCK_LED
10V 16V 16V 10V
SML-512UW
IC2500
LD12900
VBY1_LOCK_LED
LGE7411(URSA9)
R12905
3.3K
AG2
AG1
RB0N E Q12900
IC2500 Close to Chip side
AH3
RB0P MMBT3906(NXP) LGE7411(URSA9) AVDD_MOD
AH1
RB1N
B VBY1_LOCK_LED 4th Layer
RB1P L2102
AH2 C BLM18PG121SN1D
RB2N
AJ3
RB2P
AJ2
RBCKN
AK2
RBCKP C2193 C2142 C13306
AK1 AM17
RB3N VX1_0- 10uF 0.1uF 0.1uF
AL1 AK17
AM2
RB3P VX1_0+
AL18
10V 16V 16V
RB4N VX1_1-
AL2 AK18
RB4P VX1_1+
AM19
VX1_2-
AL19
D1
VX1_2+ HDMI_RXCP_0
AK3
RC0N VX1_3-
AL20 D3
HDMI_RXCN_0
AL3
AK4
RC0P
RC1N
VX1_3+
VX1_4-
AM20
AK22 0.1uF C13008 TXDBN7_L
E3
HDMI_RX0P_0
Close to Chip side
AL4
RC1P VX1_4+
AL21 0.1uF C13009 TXDBP7_L D2
AM4 AK23 0.1uF C13010 TXDBN6_L HDMI_RX0N_0
AK5
RC2N VX1_5-
AM22
F3
0.1uF C13011 TXDBP6_L HDMI_RX1P_0
RC2P VX1_5+ +1.1V_U_VDDC +1.1V_U_VDDC 4th Layer
AM5
RCCKN VX1_6-
AK24 0.1uF C13012 TXDBN5_L E2
AL5 AL23 0.1uF C13013 TXDBP5_L HDMI_RX1N_0
AK6
RCCKP VX1_6+
AL25
F1
0.1uF C13014 TXDBN4_L HDMI_RX2P_0
RC3N VX1_7-
AL6
RC3P VX1_7+
AK25 0.1uF C13015 TXDBP4_L F2
AK7 AM26 0.1uF C13016 TXDBN3_L HDMI_RX2N_0
RC4N VX1_8-
AL7 AK26 0.1uF C13017 TXDBP3_L
RC4P VX1_8+ C2191 C2198 C2194 C2122 C2132 C2137 C2144 C2146 C2147 C2148 C2149 C13307 C2150 C2196
AL27 0.1uF C13018 TXDBN2_L
VX1_9-
AK27 10uF 10uF 10uF 10uF 10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF
0.1uF C13019 TXDBP2_L
AM7
VX1_9+
AM28 10V 10V 10V 10V 10V 10V 16V 16V 16V 16V 16V 16V 10V 10V
0.1uF C13020 TXDBN1_L
RD0N VX1_10-
AK8 AL28 0.1uF C13021 TXDBP1_L
RD0P VX1_10+
AM8 AL29 0.1uF C13022 TXDBN0_L
RD1N VX1_11-
AL8 AM29 0.1uF C13023 TXDBP0_L
RD1P VX1_11+
AK9 AM31 0.1uF C13024 TXDAN7_L AVDDL_MOD
RD2N VX1_12-
AL9 AL30 0.1uF C13025 TXDAP7_L
AK10
AL10
RD2P
RDCKN
VX1_12+
VX1_13-
AL32
AL31
0.1uF C13026 TXDAN6_L
L2104
4th Layer
Close to Chip side
0.1uF C13027 TXDAP6_L BLM18PG121SN1D
RDCKP VX1_13+
AM10 AK31 0.1uF C13028 TXDAN5_L
AK11
RD3N VX1_14-
AK32
G1
0.1uF C13029 TXDAP5_L HDMI_RXCP_1
RD3P VX1_14+
AM11
RD4N VX1_15-
AJ30 0.1uF C13030 TXDAN4_L G3 C2115 C13311 C13305 C2154
AL11 AJ31 0.1uF C13031 TXDAP4_L HDMI_RXCN_1 0.1uF 10uF 10uF
RD4P VX1_15+ H3 0.1uF
AH30 0.1uF C13064 TXDAN3_L
VX1_16- HDMI_RX0P_1 16V 10V 16V 10V
VX1_16+
AH32 0.1uF C13065 TXDAP3_L G2
AK12 AG30 0.1uF C13066 TXDAN2_L HDMI_RX0N_1
AL12
RE0N VX1_17-
AG31
J3
0.1uF C13067 TXDAP2_L HDMI_RX1P_1
RE0P VX1_17+
AK13 AE31 0.1uF C13068 TXDAN1_L H2
AL13
AM13
RE1N
RE1P
VX1_18-
VX1_18+
AF30
AD32
0.1uF
0.1uF
C13069
C13070
TXDAP1_L
TXDAN0_L
J1
HDMI_RX1N_1
AVDDL_DRV
Close to Chip side
RE2N VX1_19- HDMI_RX2P_1
AK14
RE2P VX1_19+
AE30 0.1uF C13071 TXDAP0_L J2 4th Layer
AM14 HDMI_RX2N_1
RECKN L2105
AL14 BLM18PG121SN1D
RECKP
AK15 AH29
RE3N VX1_HTDPN HTPDAn
AL15 AG29
RE3P VX1_LOCKN
AK16 C2116 C13310 C13304 C2153
RE4N R1938
AL16
RE4P
10K 0.1uF 10uF 0.1uF 10uF
URSA_TX_HTPD_pulldown 16V 10V 16V 10V
0.1uF C12900 AE2

TXOSD_3N VBY1_RXM[0]
TXOSD_3P 0.1uF C12901 AE1
VBY1_RXP[0] DVDD_DDR Close to Chip side
OSD
0.1uF C12902 AD2

TXOSD_2N VBY1_RXM[1] LOCKAn
0.1uF C12903 AE3 4th Layer
TXOSD_2P VBY1_RXP[1]
0.1uF C12904 AC2 L2106
TXOSD_1N VBY1_RXM[2]
0.1uF C12905 AD3 BLM18PG121SN1D
TXOSD_1P
AC3
VBY1_RXP[2] N4
TXOSD_0N 0.1uF C12906 HDMITX_SCL
VBY1_RXM[3] +3.3V_NORMAL
0.1uF C12907 AC1 M4 C2152
TXOSD_0P VBY1_RXP[3]
HDMITX_SDA C2117 C13312 C13303 C13313
Wafer_side_VBY1_LOCK_LED
AB2
N1 0.1uF 4.7uF 10uF 0.1uF 4.7uF
TXVBY1_7N 0.1uF C12908 HDMI_TXCP
AB1
VBY1_RXM[4]
P1 16V 10V 10V 16V 10V
TXVBY1_7P 0.1uF C12909
VBY1_RXP[4]
0.1uF C12910 AA2 HDMI_TXCN
TXVBY1_6N N3
VBY1_RXM[5]
0.1uF C12911 AB3
HDMI_TX0P
R1952
TXVBY1_6P VBY1_RXP[5]
0.1uF C12912 Y2 N2
22
TXVBY1_5N
VIDEO
VBY1_RXM[6]
0.1uF C12913 AA3 HDMI_TX0N
TXVBY1_5P
Y3
VBY1_RXP[6] M3
TXVBY1_4N
TXVBY1_4P
0.1uF
0.1uF
C12914
C12915 Y1
VBY1_RXM[7]
M2
HDMI_TX1P Close to Chip side
SML-512UW
VBY1_RXP[7] AVDDL_HDMI_TX_RX
HDMI_TX1N
LD1900
W2
L1
0.1uF C12916
TXVBY1_3N VBY1_RXM[8] HDMI_TX2P

TXVBY1_3P 0.1uF C12917 W1
VBY1_RXP[8]
R1939 L2 L2107
V2 10K HDMI_TX2N BLM18PG121SN1D
TXVBY1_2N 0.1uF C12918
VBY1_RXM[9]
0.1uF C12919 W3
R1943
TXVBY1_2P VBY1_RXP[9]
3.3K
0.1uF C12920 U2
TXVBY1_1N
V3
VBY1_RXM[10] C2118 C2126 C2131 C13309
TXVBY1_1P 0.1uF C12921
U3
VBY1_RXP[10] 0.1uF 0.1uF 0.1uF 10uF
TXVBY1_0N 0.1uF C12922
VBY1_RXM[11] 16V 16V
0.1uF C12923 U1 16V 10V
TXVBY1_0P VBY1_RXP[11] E Q1901
MMBT3906(NXP)
B
Wafer_side_VBY1_LOCK_LED C
AVDDL_LVDSRX
L13300
BLM18PG121SN1D
C13300 C13301 C13308

0.1uF 0.1uF 10uF
16V 16V 10V
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES BSD-14Y-UD-128-02-HD

FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 2013.12.17
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. U_LVDS INPUT
IC2500
LGE7411(URSA9)
F14 H27 B_DDR3_A[0]

B_DDR3_A[0-15] DDR PHY VREF
A_DDR3_A[0] A_DDR3_A0 B_DDR3_A0
B13 G31 B_DDR3_A[1] +1.5V_U_DDR +1.5V_U_DDR
A_DDR3_A[1] A_DDR3_A1 B_DDR3_A1 U_MVREFCA_A0 U_MVREFCA_A1
E13 G28 B_DDR3_A[2]
A_DDR3_A[2] A_DDR3_A2 B_DDR3_A2
D13 G29 B_DDR3_A[3]
A_DDR3_A[3] A_DDR3_A3 B_DDR3_A3 URSA_DDR_Hynix DDR_VTT_URSA_1
C14 H30 B_DDR3_A[4]
A_DDR3_A[4] A_DDR3_A4 B_DDR3_A4 R13110 R13120 URSA_DDR_Hynix
F13 G27 B_DDR3_A[5] 1K
A_DDR3_A[5] A_DDR3_A5 B_DDR3_A5 1%
1K IC2600
C13 G30 B_DDR3_A[6] 1%
H5TQ1G63EFR-RDC IC2700
A_DDR3_A[6] A_DDR3_A6 B_DDR3_A6 AR13100 AR13102 AR13104 AR13106 AR13108 AR13110 AR13112
A_DDR3_A[7]
B10 D31 B_DDR3_A[7] U_MVREFCA_A0 100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
A_DDR3_A7 B_DDR3_A7 U_MVREFCA_A1
A12 F32 B_DDR3_A[8]
A_DDR3_A[8] A_DDR3_A8 B_DDR3_A8 R13111 C13131 C13136 R13121 C13143 C13147
C10 D30 B_DDR3_A[9]
1K
A_DDR3_A[9] A_DDR3_A9 B_DDR3_A9 0.1uF 1000pF 1K 0.1uF 1000pF N3 M8
A14 H32 B_DDR3_A[10] 1% 1% A_DDR3_A[0] A0 VREFCA N3 M8
A_DDR3_A[10] A_DDR3_A10 B_DDR3_A10 P7 A_DDR3_A[0] A0 VREFCA
B12 F31 B_DDR3_A[11] A_DDR3_A[1] A1 P7
A_DDR3_A[11] A_DDR3_A11 B_DDR3_A11 P3 A_DDR3_A[1] A1
F15 J27 B_DDR3_A[12] A_DDR3_A[2] A2 P3
A_DDR3_A[12] A_DDR3_A12 B_DDR3_A12 N2 H1 A_DDR3_A[2] A2
C11 E30 B_DDR3_A[13] A_DDR3_A[3] A3 VREFDQ N2 H1
A_DDR3_A[13] A_DDR3_A13 B_DDR3_A13 P8 A_DDR3_A[3] A3 VREFDQ
C12 F30 B_DDR3_A[14] A_DDR3_A[4] A4 P8
A_DDR3_A[14] A_DDR3_A14 B_DDR3_A14 P2 A_DDR3_A[4] A4
D17 L29 B_DDR3_A[15] A_DDR3_A[5] A5 P2
A_DDR3_A[15] A_DDR3_A15 B_DDR3_A15 R8 L8 R13126 240
A_DDR3_A[5] A5
E14 H28 A_DDR3_A[6] A6 ZQ R8 L8 R13134 240
A_DDR3_BA[0] A_DDR3_BA0 B_DDR3_BA0 B_DDR3_BA[0] R2 1%
A_DDR3_A[6] A6 ZQ
B14 H31 A_DDR3_A[7] A7 R2 1% +1.5V_U_DDR
T8 +1.5V_U_DDR A_DDR3_A[7]
A_DDR3_BA[1] A_DDR3_BA1 B_DDR3_BA1 B_DDR3_BA[1] A_DDR3_A[8] A7
E15 J28 A8 T8
A_DDR3_BA[2] A_DDR3_BA2 B_DDR3_BA2 B_DDR3_BA[2] R3 B2 A_DDR3_A[8] A8
A_DDR3_A[9] A9 VDD_1 R3 B2
L7 D9 A_DDR3_A[9] A9 VDD_1
E17 L28 A_DDR3_A[10] A10/AP VDD_2 L7 D9
A_DDR3_RASZ A_DDR3_RASZ B_DDR3_RASZ B_DDR3_RASZ R7 G7 A_DDR3_A[10] A10/AP VDD_2
C17 L30 A_DDR3_A[11] A11 VDD_3 R7 G7
A_DDR3_CASZ A_DDR3_CASZ B_DDR3_CASZ B_DDR3_CASZ N7 K2 A_DDR3_A[11] A11 VDD_3
C16 K30 A_DDR3_A[12] A12/BC VDD_4 N7 K2
A_DDR3_WEZ A_DDR3_WEZ B_DDR3_WEZ B_DDR3_WEZ T3 K8 A_DDR3_A[12] A12/BC VDD_4
F17 L27 A_DDR3_A[13] NC_7 VDD_5 T3 K8
A_DDR3_ODT A_DDR3_ODT B_DDR3_ODT B_DDR3_ODT N1 A_DDR3_A[13] NC_7 VDD_5
C15 J30 VDD_6 N1
A_DDR3_CKE A_DDR3_CKE B_DDR3_CKE B_DDR3_CKE M7 N9 A_DDR3_A[14] VDD_6
B11 E31 A_DDR3_A[15] NC_5 VDD_7 M7 N9
A_DDR3_RESET A_DDR3_RESETB B_DDR3_RESETB B_DDR3_RESET R1 A_DDR3_A[15] NC_5 VDD_7
B16 K31 VDD_8 R1
A_DDR3_MCLK A_DDR3_MCLK B_DDR3_MCLK B_DDR3_MCLK +1.5V_U_DDR M2 R9 VDD_8
A16 K32 A_DDR3_BA[0] BA0 VDD_9 M2 R9
A_DDR3_MCLKZ B_DDR3_MCLKZ +1.5V_U_DDR N8 URSA_DDR_Samsung
A_DDR3_MCLKZ B_DDR3_MCLKZ U_MVREFCA_B0 U_MVREFCA_B1 A_DDR3_BA[0] BA0 VDD_9 IC2700-*2

C9 C30 A_DDR3_BA[1] BA1 +1.5V_U_DDR N8 K4B1G1646G-BCMA
M3 +1.5V_U_DDR
R13123R13122
A_DDR3_CSB1 A_DDR3_CSB1 B_DDR3_CSB1 B_DDR3_CSB1 A_DDR3_MCLK A_DDR3_BA[1] BA1
A9 C32 A_DDR3_BA[2] BA2 M3
56
A_DDR3_CSB2 A_DDR3_CSB2 B_DDR3_CSB2 B_DDR3_CSB2 C13233 A1 A_DDR3_BA[2] BA2
N3
P7
A0 VREFCA
M8
VDDQ_1 A1 P3
A1
A_DDR3_DQ[0-15] B_DDR3_DQ[0-15] R13108 0.01uF J7 A8 VDDQ_1 N2

A2
H1
R13118
56
A_DDR3_DQ[0] D23 U29 B_DDR3_DQ[0] CK VDDQ_2 J7 A8 P8
A3 VREFDQ
1K 1K K7 C1 P2
A4
A_DDR3_DQ0 B_DDR3_DQ0 A_DDR3_MCLK CK VDDQ_2 R8
A5
L8
A_DDR3_DQ[1] A19 N32 B_DDR3_DQ[1] 1% 1% A_DDR3_MCLKZ CK VDDQ_3 K7 C1 R2
A6 ZQ
A_DDR3_DQ1 B_DDR3_DQ1 K9 C9 A_DDR3_MCLKZ CK VDDQ_3 T8

A7
A_DDR3_DQ[2] E22 T28 B_DDR3_DQ[2] A_DDR3_CKE CKE VDDQ_4 K9 C9 R3

A8
A9 VDD_1
B2
A_DDR3_DQ2 B_DDR3_DQ2 D2 A_DDR3_CKE CKE VDDQ_4

L7
R7
A10/AP VDD_2
D9
G7
A_DDR3_DQ[3] B18 M31 B_DDR3_DQ[3] VDDQ_5 D2 N7
A11 VDD_3
K2
A_DDR3_DQ3 B_DDR3_DQ3 L2 E9 VDDQ_5 T3

A12/BC VDD_4
K8
A_DDR3_DQ[4] C23 U30 B_DDR3_DQ[4] R13109 C13138 C13134 R13119 C13142 C13145 A_DDR3_CSB1 CS VDDQ_6 L2 E9
A13 VDD_5
VDD_6
N1
A_DDR3_DQ4 B_DDR3_DQ4 1K 0.1uF 1000pF 1K K1 F1 A_DDR3_CSB2 CS VDDQ_6

M7
NC_5 VDD_7
N9
A_DDR3_DQ[5] C18 M30 B_DDR3_DQ[5] 0.1uF 1000pF A_DDR3_ODT ODT VDDQ_7 K1 F1

R1
1% 1% J3 H2 M2
BA0
VDD_8
VDD_9
R9
A_DDR3_DQ5 B_DDR3_DQ5 A_DDR3_ODT ODT VDDQ_7 N8

A_DDR3_DQ[6] B22 T31 B_DDR3_DQ[6] A_DDR3_RASZ RAS VDDQ_8 J3 H2 M3
BA1
BA2
A_DDR3_DQ6 B_DDR3_DQ6 K3 H9 A_DDR3_RASZ RAS VDDQ_8 J7
VDDQ_1
A1
A8
A_DDR3_DQ[7] A18 M32 B_DDR3_DQ[7] A_DDR3_CASZ CAS VDDQ_9 K3 H9 K7
CK VDDQ_2
C1
A_DDR3_DQ7 B_DDR3_DQ7 L3 A_DDR3_CASZ CAS VDDQ_9 K9

CK VDDQ_3
C9
A_DDR3_DQ[8] E19 N28 B_DDR3_DQ[8] A_DDR3_WEZ WE L3
CKE VDDQ_4
VDDQ_5
D2
A_DDR3_DQ8 B_DDR3_DQ8 J1 A_DDR3_WEZ WE

L2
K1
CS VDDQ_6
E9
F1
A_DDR3_DQ[9] B21 R31 B_DDR3_DQ[9] NC_1 J1 J3
ODT VDDQ_7
H2
A_DDR3_DQ9 B_DDR3_DQ9 T2 J9 NC_1 K3

RAS VDDQ_8
H9
A_DDR3_DQ[10] F18 M27 B_DDR3_DQ[10] A_DDR3_RESET RESET NC_2 T2 J9 L3
CAS
WE
VDDQ_9
A_DDR3_DQ10 B_DDR3_DQ10 L1 A_DDR3_RESET RESET NC_2 T2

NC_1
J1
J9
A_DDR3_DQ[11] C22 T30 B_DDR3_DQ[11] NC_3 L1 RESET NC_2
L1
A_DDR3_DQ11 B_DDR3_DQ11 L9 NC_3 NC_3

L9
A_DDR3_DQ[12] D20 P29 B_DDR3_DQ[12] NC_4 L9 F3
DQSL
NC_4
NC_6
T7
A_DDR3_DQ12 B_DDR3_DQ12 F3 T7 NC_4

G3
DQSL
A_DDR3_DQ[13] F22 T27 B_DDR3_DQ[13] A_DDR3_DQS0 DQSL NC_6 A_DDR3_A[14] F3 T7 C7 A9
A_DDR3_DQ13 B_DDR3_DQ13 G3 A_DDR3_DQS2 DQSL NC_6 A_DDR3_A[14] B7

DQSU VSS_1
B3
A_DDR3_DQ[14] E18 M28 B_DDR3_DQ[14] A_DDR3_DQS0B DQSL G3 E7
DQSU VSS_2
VSS_3
E1
G8
A_DDR3_DQ14 B_DDR3_DQ14 A_DDR3_DQS2B DQSL D3
DML VSS_4
J2
A_DDR3_DQ[15] D22 T29 B_DDR3_DQ[15] DMU VSS_5
J8
A_DDR3_DQ15 B_DDR3_DQ15 C7 A9 E3
VSS_6
M1
B19 N31 A_DDR3_DQS1 DQSU VSS_1 C7 A9 F7

DQL0
DQL1
VSS_7
VSS_8
M9
A_DDR3_DM0 A_DDR3_DM0 B_DDR3_DM0 B_DDR3_DM0 B7 B3 A_DDR3_DQS3 DQSU VSS_1

F2
F8
DQL2 VSS_9
P1
P9
E21 R28 A_DDR3_DQS1B DQSU VSS_2 B7 B3 H3
DQL3 VSS_10
T1
A_DDR3_DM1 A_DDR3_DM1 B_DDR3_DM1 B_DDR3_DM1 E1 A_DDR3_DQS3B DQSU VSS_2 H8

DQL4 VSS_11
T9
VSS_3 E1 G2
DQL5
DQL6
VSS_12
E7 G8 VSS_3
H7
DQL7
B1
A21 R32 A_DDR3_DM0 DML VSS_4 E7 G8 D7
VSSQ_1
B9
A_DDR3_DQS0 A_DDR3_DQS0 B_DDR3_DQS0 B_DDR3_DQS0 D3 J2 A_DDR3_DM2 DML VSS_4 C3

DQU0 VSSQ_2
D1
B20 P31 A_DDR3_DM1 DMU VSS_5 D3 J2 C8

DQU1
DQU2
VSSQ_3
VSSQ_4
D8
A_DDR3_DQS0B A_DDR3_DQS0B B_DDR3_DQS0B B_DDR3_DQS0B J8 A_DDR3_DM3 DMU VSS_5

C2
A7
DQU3 VSSQ_5
E2
E8
C20 P30 A_DDR3_DQ[0-15] VSS_6 J8 A2
DQU4 VSSQ_6
F9
A_DDR3_DQS1 A_DDR3_DQS1 B_DDR3_DQS1 B_DDR3_DQS1

A_DDR3_DQ[0] E3 M1 A_DDR3_DQ[16-31] VSS_6 B8
DQU5 VSSQ_7
G1
C19 N30 DQL0 VSS_7 A_DDR3_DQ[16] E3 M1 A3

DQU6
DQU7
VSSQ_8
VSSQ_9
G9
A_DDR3_DQS1B A_DDR3_DQS1B B_DDR3_DQS1B B_DDR3_DQS1B

A_DDR3_DQ[1] F7 M9 DQL0 VSS_7
DQL1 VSS_8 A_DDR3_DQ[17] F7 M9
A_DDR3_DQ[16-31] B_DDR3_DQ[16-31]
A_DDR3_DQ[2] F2 P1 DQL1 VSS_8
A_DDR3_DQ[16] B27 AA31 B_DDR3_DQ[16] DQL2 VSS_9 A_DDR3_DQ[18] F2 P1
A_DDR3_DQ16 B_DDR3_DQ16
A_DDR3_DQ[3] F8 P9 DQL2 VSS_9
A_DDR3_DQ[17] A24 V32 B_DDR3_DQ[17] DQL3 VSS_10 URSA_DDR_Samsung A_DDR3_DQ[19] F8 P9 URSA_DDR_Nanya
A_DDR3_DQ[4] H3 T1 URSA_DDR_Nanya
IC2600-*2 DQL3 VSS_10
DQL4 VSS_11 IC2600-*1 IC2700-*1
A_DDR3_DQ[18] C27 AA30 B_DDR3_DQ[18] NT5CB64M16FP-EK K4B1G1646G-BCMA A_DDR3_DQ[20] H3 T1 NT5CB64M16FP-EK
A_DDR3_DQ[5] H8 T9 DQL4 VSS_11
A_DDR3_DQ[19] C24 V30 B_DDR3_DQ[19] DQL5 VSS_12 A_DDR3_DQ[21] H8 T9
A_DDR3_DQ[6] G2 N3
A0 VREFCA
M8 N3
P7
A0 VREFCA
M8
DQL5 VSS_12 N3
A0 VREFCA
M8
A_DDR3_DQ[20] A28 AB32 B_DDR3_DQ[20] DQL6 P7

A1 P3
A1 A_DDR3_DQ[22] G2 P7
A1
A_DDR3_DQ[7] H7 P3
N2
A2
H1 N2
A2
H1
DQL6
P3
N2
A2
H1
A_DDR3_DQ[21] E24 V28 B_DDR3_DQ[21] DQL7 P8
A3 VREFDQ P8
A3
A4
VREFDQ
A_DDR3_DQ[23] H7 P8
A3 VREFDQ
A_DDR3_DQ21 B_DDR3_DQ21 +1.5V_U_DDR A_DDR3_CKE B1 P2

A4
A5
P2
R8
A5
L8 DQL7 P2
A4
A5
A_DDR3_DQ[22] B28 AB31 B_DDR3_DQ[22] VSSQ_1 R8
A6 ZQ
L8
R2
A6 ZQ
B1 R8
A6 ZQ
L8
A_DDR3_DQ[8] D7 B9 R2
T8
A7 T8
A7
VSSQ_1
R2
T8
A7
A_DDR3_DQ[23] B23 U31 B_DDR3_DQ[23] R13112 DQU0 VSSQ_2 R3

A8
B2 R3
A8
A9 VDD_1
B2 A_DDR3_DQ[24] D7 B9 R3
A8
B2
R13102
1K
A_DDR3_DQ[9] C3 D1 L7
A9
A10/AP
VDD_1
VDD_2
D9 L7
R7
A10/AP VDD_2
D9
G7 DQU0 VSSQ_2 L7
A9
A10/AP
VDD_1
VDD_2
D9
1K DQU1 VSSQ_3 R7 G7 R7 G7
A_DDR3_DQ[24] D25 W29 B_DDR3_DQ[24] A11 VDD_3 N7
A11 VDD_3
K2 A_DDR3_DQ[25] C3 D1 A11 VDD_3
A_DDR3_DQ[10] C8 D8 N7
T3
A12/BC VDD_4
K2
K8 T3
A12/BC VDD_4
K8
DQU1 VSSQ_3
N7
T3
A12/BC VDD_4
K2
K8
A_DDR3_DQ[25] E27 AA28 B_DDR3_DQ[25] A_DDR3_RESET DQU2 VSSQ_4 NC_6 VDD_5
N1
A13 VDD_5
VDD_6
N1 A_DDR3_DQ[26] C8 D8 NC_6 VDD_5
N1
A_DDR3_DQ[11] C2 E2 M7
NC_5
VDD_6
VDD_7
N9 M7
NC_5 VDD_7
N9
R1 DQU2 VSSQ_4 M7
NC_5
VDD_6
VDD_7
N9
A_DDR3_DQ[26] C25 W30 B_DDR3_DQ[26] DQU3 VSSQ_5 VDD_8

R1
M2
VDD_8
R9 A_DDR3_DQ[27] C2 E2 VDD_8
R1
A_DDR3_DQ[12] A7 E8 M2
N8
BA0 VDD_9
R9
N8
BA0 VDD_9
DQU3 VSSQ_5
M2
N8
BA0 VDD_9
R9
A_DDR3_DQ[27] D28 AB29 B_DDR3_DQ[27] DQU4 VSSQ_6 M3

BA1 M3
BA1
BA2
A_DDR3_DQ[28] A7 E8 M3
BA1
A_DDR3_DQ[13] A2 F9 BA2
VDDQ_1
A1
J7
VDDQ_1
A1
A8 DQU4 VSSQ_6
BA2
VDDQ_1
A1
A_DDR3_DQ[28] E26 Y28 B_DDR3_DQ[28] DQU5 VSSQ_7 J7

CK VDDQ_2
A8
K7
CK VDDQ_2
C1 A_DDR3_DQ[29] A2 F9 J7
CK VDDQ_2
A8
A_DDR3_DQ[14] B8 G1 K7
K9
CK VDDQ_3
C1
C9 K9
CK VDDQ_3
C9
DQU5 VSSQ_7
K7
K9
CK VDDQ_3
C1
C9
A_DDR3_DQ[29] E28 AB28 B_DDR3_DQ[29] DQU6 VSSQ_8 CKE VDDQ_4
D2
CKE VDDQ_4
VDDQ_5
D2 A_DDR3_DQ[30] B8 G1 CKE VDDQ_4
D2
A_DDR3_DQ[15] A3 G9 L2
CS
VDDQ_5
VDDQ_6
E9 L2
K1
CS VDDQ_6
E9
F1 DQU6 VSSQ_8 L2
CS
VDDQ_5
VDDQ_6
E9
A_DDR3_DQ[30] E25 W28 B_DDR3_DQ[30] DQU7 VSSQ_9 K1

J3
ODT VDDQ_7
F1
H2 J3
ODT VDDQ_7
H2 A_DDR3_DQ[31] A3 G9 K1
J3
ODT VDDQ_7
F1
H2
RAS VDDQ_8
A_DDR3_DQ30 B_DDR3_DQ30 K3
RAS
CAS
VDDQ_8
VDDQ_9
H9 K3
CAS VDDQ_9
H9
DQU7 VSSQ_9 K3
RAS
CAS
VDDQ_8
VDDQ_9
H9
A_DDR3_DQ[31] C28 AB30 B_DDR3_DQ[31] L3
WE
J1
L3
WE
J1
L3
WE
J1
A_DDR3_DQ31 B_DDR3_DQ31 +1.5V_U_DDR B_DDR3_CKE T2
NC_1
J9 T2
NC_1
J9 T2
NC_1
J9
B24 V31 RESET NC_2
L1
RESET NC_2
NC_3
L1 RESET NC_2
L1
A_DDR3_DM2 A_DDR3_DM2 B_DDR3_DM2 B_DDR3_DM2 NC_3
NC_4
L9
NC_4
L9 NC_3
NC_4
L9
B26 Y31 F3
DQSL NC_7
T7 F3
G3
DQSL NC_6
T7 F3
DQSL NC_7
T7
A_DDR3_DM3 A_DDR3_DM3 B_DDR3_DM3 B_DDR3_DM3 R13113 G3

DQSL DQSL
G3
DQSL
R13103 1K C7 A9 C7
DQSU VSS_1
A9 C7 A9
DQSU VSS_1 B7 B3 DQSU VSS_1
1K B7
DQSU VSS_2
B3
DQSU VSS_2
B7
DQSU VSS_2
B3
B25 W31 E7
VSS_3
E1
G8 E7
VSS_3
E1
G8 E7
VSS_3
E1
G8
A_DDR3_DQS2 A_DDR3_DQS2 B_DDR3_DQS2 B_DDR3_DQS2 D3
DML VSS_4
J2 D3
DML VSS_4
J2 D3
DML VSS_4
J2
A25 W32 B_DDR3_RESET DMU VSS_5
J8
DMU VSS_5
VSS_6
J8 DMU VSS_5
J8
A_DDR3_DQS2B A_DDR3_DQS2B B_DDR3_DQS2B B_DDR3_DQS2B E3
DQL0
VSS_6
VSS_7
M1 E3
DQL0 VSS_7
M1 E3
DQL0
VSS_6
VSS_7
M1
D26 Y29 F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
A_DDR3_DQS3 A_DDR3_DQS3 B_DDR3_DQS3 B_DDR3_DQS3 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9 F8
DQL2 VSS_9
P9
C26 Y30 H3
DQL3 VSS_10
T1 H3
DQL3
DQL4
VSS_10
VSS_11
T1 H3
DQL3 VSS_10
T1
A_DDR3_DQS3B A_DDR3_DQS3B B_DDR3_DQS3B B_DDR3_DQS3B H8
DQL4
DQL5
VSS_11
VSS_12
T9 H8
G2
DQL5 VSS_12
T9 H8
DQL4
DQL5
VSS_11
VSS_12
T9
G2 G2
DQL6 DQL6 DQL6
H7 H7 H7
DQL7 DQL7 DQL7
B1 B1 B1
VSSQ_1 VSSQ_1 VSSQ_1
D7 B9 D7 B9 D7 B9
DQU0 VSSQ_2 DQU0 VSSQ_2 DQU0 VSSQ_2
C3 D1 C3 D1 C3 D1
C8 D8 C8 D8 C8 D8
C2 E2 C2 E2 C2 E2
A7 E8 A7 E8 A7 E8
A2 F9 A2 F9 A2 F9
B8 G1 B8 G1 B8 G1
A3 G9 A3 G9 A3 G9
* DDR_VTT
DDR_VTT_URSA_0
URSA_DDR_Hynix
+1.5V_U_DDR +3.3V_NORMAL
IC13100 URSA_DDR_Hynix AR13101 AR13103 AR13105 AR13107 AR13109 AR13111 AR13113

IC2900
AP2303MPTR-G1 [EP]
C13119
100 100 100 100 100 100 100 H5TQ1G63EFR-RDC
L13101 IC2800 U_MVREFCA_B1
10uF
VIN NC_3 CIS21J121 10V
C13114
1 8 H5TQ1G63EFR-RDC
THERMAL
10uF
U_MVREFCA_B0
DDR_VTT_URSA GND NC_2 N3 M8
9
10V 2 7 B_DDR3_A[0] A0 VREFCA

P7
VREFEN VCNTL B_DDR3_A[1] A1
L13100 3 6 N3 M8 P3
CIS21J121 B_DDR3_A[0] A0 VREFCA B_DDR3_A[2] A2
1% 10K
R13100
P7 N2 H1
VOUT NC_1 B_DDR3_A[1] A1 B_DDR3_A[3] A3 VREFDQ
4 5 P3 P8
B_DDR3_A[2] A2
R13101
B_DDR3_A[4] A4
1% 10K
C13110 C13111 C13113

C13118
N2 H1 P2
0.1uF
10uF 10uF 10uF

B_DDR3_A[3] A3 VREFDQ B_DDR3_A[5] A5
P8 R8 L8 R13135 240
B_DDR3_A[4] A4 B_DDR3_A[6] A6 ZQ
P2 R2 1%
B_DDR3_A[5] A5 B_DDR3_A[7] A7 +1.5V_U_DDR
R8 L8 R13127 240
T8
B_DDR3_A[6] A6 ZQ B_DDR3_A[8] A8
R2 1%
R3 B2
B_DDR3_A[7] A7 +1.5V_U_DDR B_DDR3_A[9] A9 VDD_1
T8 L7 D9
B_DDR3_A[8] A8 B_DDR3_A[10] A10/AP VDD_2
R3 B2 R7 G7
B_DDR3_A[9] A9 VDD_1 B_DDR3_A[11] A11 VDD_3
L7 D9 N7 K2
B_DDR3_A[10] A10/AP VDD_2 B_DDR3_A[12] A12/BC VDD_4
R7 G7 T3 K8
B_DDR3_A[11] A11 VDD_3 B_DDR3_A[13] NC_7 VDD_5
N7 K2 N1
B_DDR3_A[12] A12/BC VDD_4 B_DDR3_A[14] VDD_6
T3 K8 M7 N9
B_DDR3_A[13] NC_7 VDD_5 B_DDR3_A[15] NC_5 VDD_7
DDR_VTT_URSA N1
DDR_VTT_URSA_0 R1
L13102 VDD_6 VDD_8
BLM18PG121SN1D M7 N9 M2 R9
B_DDR3_A[15] NC_5 VDD_7 B_DDR3_BA[0] BA0 VDD_9
R1 N8 +1.5V_U_DDR URSA_DDR_Samsung
C13181 C13179 C13189 C13151

VDD_8 B_DDR3_BA[1] BA1 IC2900-*2
C13105 M2 R9 M3 K4B1G1646G-BCMA
1uF 0.1uF 0.1uF 0.1uF
25V 16V 16V 16V
0.1uF
16V
C13123 C13125 B_DDR3_BA[0]
N8
BA0 VDD_9 B_DDR3_BA[2] BA2
A1 N3 M8
10uF 0.1uF B_DDR3_MCLK
R13125R13124
B_DDR3_BA[1]
M3
BA1
+1.5V_U_DDR VDDQ_1 P7
A0
A1
VREFCA
J7 A8 P3
A2
10V 16V B_DDR3_BA[2] BA2 B_DDR3_MCLK CK VDDQ_2 N2 H1
56
A3 VREFDQ
C13234 A1 K7 C1
P8
P2
A4
VDDQ_1 B_DDR3_MCLKZ CK VDDQ_3 R8
A5
L8
0.01uF J7 A8 K9 C9 R2
A6 ZQ
56
A7
DDR_VTT_URSA DDR_VTT_URSA_1 CK VDDQ_2 B_DDR3_CKE CKE VDDQ_4 T8
A8
L13103
K7 C1 D2
R3

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North/Latin America http://aic.lgservice.com

MODEL : 65EG960T 65EG960T-TA

P/NO : MFL69302301 (1505-REV00) Printed in Korea

SAFETY PRECAUTIONS ......................................................................... 3

EXPLODED VIEW ................................................................................... 34

SCHEMATIC CIRCUIT DIAGRAM ............................................ APPENDIX

TROUBLE SHOOTING GUIDE.................................................. APPENDIX

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed

Leakage Current Cold Check(Antenna Cold Check)

Fuse and Conventional Resistor

1. Application range 3. Test method

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

4. Model General Specification

(2) Component (Y, CB/PB, CR/PR)

(2) HDMI input

(4) Component Input ( 3D) (3D supported mode manually)

2) DLNA - Photo (3D) (3D supported mode manually)

3) DLNA (3D) (3D supported mode automatically)

(6) Miracast, Widi (3D supported mode manually)

■ Remark: 3D Input mode

In case of keeping module is in the circumstance of below

3.6. WIFI MAC ADDRESS CHECK

(2) Check the menu on in-start

# HDMI 1(C/S : E6 F4) - HDMI UHD Deep Off Case

EDID Block 1, Bytes 128-255 [80H-FFH]

EDID Block 1, Bytes 128-255 [80H-FFH]

EDID Block 1, Bytes 128-255 [80H-FFH]

EDID Block 1, Bytes 128-255 [80H-FFH

* Checksum (HDMI 1/2/3)

▪ Standard color coordinate and temperature using CA-210(CH 14)

▪ AUO, INX, Sharp, CSOT, BOE (Cool :13000 K)

(3) Don't wear a 3D Glasses, Check the picture like below.

3) Check the Sound from the Speaker or using AV & Optic

4.8. Ship-out mode check (In-stop)

(4) Updating is starting.

* After downloading, have to adjust TOOL OPTION again.

Only for training and service purposes

LNB Chip Config

LG Electronics. Inc. All rights reserved.

USB1 (3.0) OCP Vx1 51P

SPDIF OUT Sub Micom

LGE Internal Use Only

Only for training and service purposes

LNB Chip Config

LG Electronics. Inc. All rights reserved.

USB1 (3.0) OCP Vx1

OPTIC SPDIF OUT

LGE Internal Use Only

Only for training and service purposes

+3.3V_NORMAL 1.8KΩ LNB

LG Electronics. Inc. All rights reserved.

LGE Internal Use Only

Only for training and service purposes

3) Check the Sound from the Speaker or using AV & Optic