LOGIC GATES LOGIC GA’ ‘+ Logic gates are the fundamental building blocks of digital systems, ‘+ There are 3 basic types of gates AND, OR and NOT. + Logic gates are electronic circuits because they are made up of a number of electronic devices and ‘components, ‘+ Inputs and outputs of logic gates can occur only in 2 levels. These two levels are termed HIGH and LOW, or TRUE and FALSE, or ON and OFF or simply 1 and 0. ‘+ The table which lists all the possible combinations of input variables and the corresponding outputs is called a truth table. LEVEL LoGic: A logic in which the voltage levels represents logic 1 and logic 0. Level logic may be positive or negative logic. Positive Logi ‘A positive logic system is the one in which the higher of the two voltage levels represents the logic 1 and the lower of the two voltages level represents the logic 0. Negative Logi ‘A negative logic system is the one in which the lower of the two voltage levels represents the logic 1 and the higher of the two voltages level represents the logic 0. DIFFERENT TYPES OF LOGIC GATE! + ANOT gate, also called and inverter, has only one input and one output * itis a device whose output is always the complement of its input. ‘+The output of a NOT gate is the logic 1 state when its input is in logic 0 state and the logic 0 state when its inputs is in logic 1 state. IC No. :- 7404 ‘Timing Diagram 1 0 0 4 AAND GATE: ‘+ ANAND gate has two or more inputs but only one output ‘+ The output is logic 1 state only when each one of its inputs is at logic 1 state. ‘+ The output is logic 0 state even if one of its inputs is at logic 0 state, IC No.:- 7408 Ieuth Table ‘OUTPUT a |B QA.B o | 0 0 o [4 0 o 0 1 1 7 o A 1 1 1 o 4 o 4 B o ° o 4 a OR GATE:- + An OR gate may have two or more inputs but only one output + The output is logic 1 state, even if one of its input is in logic 1 state. + The output is logic 0 state, only when each one of its inputs is in logic state IC No.:- 7432 Logic Symbol Truth Table A INPUT ‘OUTPUT B 7 >- Q A B Q=A+B o [0 0 o [4 1 1 | 0 1 1 [1 1 o 0 14 A o 4 o 4 B o 4 1 4 aNAND GATE: ‘+ NAND gate is a combination of an AND gate and a NOT gate. ‘= The output is logic 0 when each of the input is logic 1 and for any other combination of inputs, the output is logic 1 IC No.:- 7400 two input NAND gate 7410 three input NAND gate 7420 four input NAND gate 7430 eight input NAND gate Logic Symbol Truth Table INPUT ‘OUTPUT s-[ >> A |B a A.B 5 o oO 1 0 1 4 1 0 4 Timing Dit 8 1 1 0 o o 4 4 A o 4 +o 4 B ee) Q NOR GATE; ‘+ NOR gate is a combination of an OR gate and a NOT gate. ‘+The output is logic 1, only when each one of its input is logic 0 and for any other combination of inputs, the output is a logic 0 level IC No.:- 7402 two input NOR gate 7427 three input NOR gate 7425 four input NOR gate Logic Symbol Truth Table A INPUT OUTPUT 8B Q 8 Q= AFB oO 1 clo|> ° cloleA o 41 o 4 B 1 0 0 0 Q USIVE IR) GAT! © ANX-OR gate is a two input, one output logic circuit ‘+ The output is logic 1 when one and only one of its two inputs is logic 1. When both the inputs is logic 0 or when both the inputs is logic 1, the output is logic 0. IC No.:- 7486, Logic Symbol Truth Table >) >- INPUT | OUTPUT A | B |Q=a0B o | 0 0 INPUTS are A and B 0 1 1 OUTPUT isQ=A QB 1 0 1 =AB+AB 1 1 0 vam A o 4 o 4 B o 4 1 ~=«0 Q ‘+ AnX-NOR gate is the combination of an X-OR gate and a NOT gate. ‘*ANX-NOR gate is a two input, one output logic circuit. ‘+ The output is logic 1 only when both the inputs are logic 0 or when both the inputs is 4 The output is logic 0 when one of the inputs is logic 0 and other is 1IC No.:- 74266 Logic Symbol A INPUT OUTPUT OUT=AXNOR B out a8 B oO oO 1 0 1 O a 4 0 0 OUT=A B+AB 1 1 1 =AXNORB ‘Timing Diagram o oO 1 1 A oO 1 0 1 B 1 oO o 1 OUT /ERSAL G There are 3 basic gates AND, OR and NOT, there are two universal gates NAND and NOR, each of which can realize logic circuits single handedly. The NAND and NOR gates are called universal building blocks. Both NAND and NOR gates can perform all logic functions i.e. AND, OR, NOT, EXOR and EXNOR NAND GATE: Ls op d) NOR gate from NAND gate Inputs are A and B Output Q = A+B B ©) EX-OR gate from NAND gate Inputs are A and B_ Output Q=AB+AB 8 f) EX-NOR gate From NAND gate Inputs are A and B Output Q= AB+AB 8 NOR GATE; a) Inverter from NOR gate Input A Output Q= A b) AND gate from NOR gate Input s are A and B Output Q= A.Bc) OR gate from NOR gate inputs are A and B Output = A+B . I >o> d) NAND gate from NOR gate Inputs are A and B Output Q= AB A ©) EX-OR gate from NOR gate Inputs are A and B_ Output Q= AB + AB f) EX-NOR gate From NOR gate Inputs are A and B__ Output Q=AB+AB J e— a xvor THRESHOLD LOGIC RODUCTION:- ‘+ The threshold element, also called the threshold gate (T-gate) is a much more powerful device than any of the conventional logic gates such as NAND, NOR and others, ‘+ Complex, large Boolean functions can be realized using much fewer threshold gates, ‘+ Frequently a single threshold gate can realize a very complex function which otherwise might require a large number of conventional gates, ‘+ T-gate offers incomparably economical realization; it has not found extensive use with the digital system designers mainly because of the following limitations. 1. Itis very sensitive to parameter variations. 2. tis difficult to fabricate it in IC form.3. The speed of switching of threshold elements in much lower than that of conventional gates. THE THRESHOLD ELEMENTS:- ‘* A threshold element or gate has ‘n’ binary inputs x, X2, ..... X; and a single binary output F. But in addition to those, it has two more parameters. ‘+ Its parameters are a threshold T and weights w, We, ...)W,- The weights w;, Wp, .... Wp are associated with the input variables x:, x2, .... X. ‘©The value of the threshold (T) and weights may be real, positive or negative number. ‘+The symbol of the threshold element is shown in fig.(a). «It is represented by a circle partitioned into two parts, one part represents the weights and other represents T + Itis defined as n F 1, Koy ones Md) = 1 Hf and only if wx 2T fs otherwise Ft Kay oss Me) =O n ‘© The sum and product operation are normal arithmetic operations and the sum. w.x 27 i=t is called the weighted sum of the element or gate. Example: Obtain the minimal Boolean expression from the threshold gate shown in figure. % Xe 2 F x Solution:- The threshold gate with three inputs x;, Xo, Xs with weights -2(w:) , 4(w2) and 2( ws) respectively. The value of threshold is 2(T). The table shown is the weighted sums and outputs for all input combinations. For this threshold gate, the weighted sum is We Wax + Wake + WX = -2)x; + (4x + (2)x 52K, + Axe + 2x5The output F is logic 1 for w22 and it is logic 0 for we2 Input Variables _| Weighted Sum Output xe [xs | we-2x + 4+ Oe | F 0 oo [0 0 0 o [4 [2 1 0 io [4 1 0 1 [1 [6 1 1 o {fo [2 oO 1 Ce oO 1 1 [o [2 1 1 14 7 From the input - output relation is given in the table, the Boolean expression for the output is FSX m(1, 2,3, 6,7) The K-map for F is XoX xX00 01 41 10 o t 3] 3 0 114 1 ay | _Ta 1 41 UNIVERSALITY OF A T-GATE: + Assingle T-gate can realize a large number of functions by merely changing either the weights or the threshold or both, which can be done by altering the value of the corresponding resistors, ‘+ Since a threshold gate can realize universal gates, ie., NAND gates and NOR gates, a threshold gate is also a universal gate. ‘+ Single threshold gate cannot realize by a single T-gate ‘+ Realization of logic gates using T-gates is shown in the below figureinput Weighted sum Output A F A We-A F 0 ° 1 1 A ° (@) NOT gato F = Tnpuis Weighted sum —_Ouiput AB w=A+B i F 0 0 0 ° o4 1 1 8 10 1 1 14 2 1 (b) OR gate F= A+B, 7 Tnputs Weighted sum —Outbut AB w=A+B F F 00 0 0 o1 1 0 e 10 1 0 14 2 4 (6) AND gate F = AB input Weighted sum Output A_B8 w--A-B e oo o 7 o4 a 4 10 a 4 44 2 o NAND gate (@)F=A+ 6228 73 i rile “Wouls Weighted sum Output : AB w=A-B F 00 ° O41 a 8 10 1 14 ° (QF =ABBOOLEAN ALGEBRA ITRODUCTIO! ‘+ Switching circuits are also called logic circuits, gates circuits and digital circuits ‘+ Switching algebra is also called Boolean algebra ‘* Boolean algebra is a system of mathematical logic. |t is an algebraic system consisting of the set of elements (0,1), two binary operators called OR and AND and unary operator called NOT. ‘* tis the basic mathematical tool in the analysis and synthesis of switching circuits. ‘itis a way to express logic functions algebraically. ‘+ Any complex logic can be expressed by a Boolean function. ‘The Boolean algebra is governed by certain well developed rules and laws AXIOMS AND LAWS OF BOOLEAN ALGEBRA:- ‘Axioms or postulates of Boolean algebra are set of logical expressions that are accepted without proof and upon which we can build a set of useful theorems. Actually, axioms are nothing more than the definitions of the three basic logic operations AND, OR and INVERTER. Each axiom can be interpreted as the outcome of an ‘operation performed by a logic gate. AND operation OR operation NOT operation Axiom 1:0 .0=0 Axiom 5:0+0=0 Axiom 9: T= 0 Axiom 2:0. 1=0 Axiom 6:0+1=4 Axiom 10:0 = 1 Axiom 3:1. 0= 0 Axiom 7:1+0=1 Axiom 2:1.1= 1 Axiom 8:1+1=1 1. Complementation Laws:- ‘The term complement simply means to invert, ie. to changes Os to 1s and 1s to Os. The five laws of are as follows: ‘A= 0 (double complementation law) 2. OR Laws:- ‘The four OR laws are as follows Law 1: A+0= (Null law) 3. AND Laws:- ‘The four AND laws are as follows : A. O= O(Null law) A(\dentity law) A.A=A Law4: AK4, Commutative Laws:- ‘Commutative laws allow change in position of AND or OR variables. There are two commutative laws. Law1:A+B=B+A Proof A [|B [A+B B [A [Bea o fo jo o jo fo o ft fa = o jt fa 1 jo [4 1 jo |1 1 |i fa 1 [4a |a Law2:A.B=B.A Proof a [sp |a.B B [A [BA o fo |o o jo fo o |1 jo = o |1 fo 1 |o [0 1 [o fo 1 jt oft 1 fa fa This law can be extended to any number of variables. For example AB.C=B.C.A=C.AB= ‘The associative laws allow grouping of variables. There are 2 associative laws, Law 1: (A+B) +C=A+(B +0) Proof A |B ASB | (AtB)+C A |B B+C | A+(B+C) o jo fo 0 0 o fo fo |[o 0 o |i fo 1 0 o jt fa fa 0 1 fo fa fa 0 1 fo [1 |a 0 ais fa fa * 0 a1 ofa fa fa 1 o jo |i |1 1 o jo jo |1 1 o ft ia ft 1 o jt fa fa 1 1 fo ja fa 1 1 fo [1 |1 1 1 fa fa fa 1 1 [1 [a [4Law 2: (A.B) C= A(B.C) Proof A |B AB | (AB)C A [B [¢ [BC [A(BC) o fo [o fo Jo 0 o fo fo |[o 0 o |1 |o Jo 0 o |1 fo [o 0 1 |o |o |o 0 1 [o |o |o 0 1 [1 |[o |o . 0 1 [1 [1 fo 1 o jo |o fo 1 o fo fo |[o 1 o |i jo fo 1 o |i jo fo 1 1 |o |1 fo 1 1 [o |[o fo 1 1 [1 ]1 [4 1 1 [1fa [a This law can be extended to any number of variables. For example 1C)D = (AB) (CD) The distributive laws allow factoring or multiplying out of expressions. There are two distributive laws. Law 4; A(B+C)=AB+AC Proof A [|B [c_ [B+c [A(B+c) A |B ‘AB [AC | A+(B+C) o {o [co |o fo o fo [o |o |o |[o 0 o |i ja fo o jo {1 |o jo fo 0 1 [o |a fo 0 1 |o |o |o jo 0 1 [1 [a fo = 0 1 [1 [o |[o fo 1 o |o |o fo 1 o jo jo jo fo 1 o ft ia ft 1 o |i jo fa fa 1 1 fo ja fa 1 1 fo {1 jo |i 1 1 [a fa fa 1 a [1 [a [a fa Proof RHS = (A+B) (A+C) AA+AC+BA+BC +AC +AB+BC =A(1+C +B) +BC 1+BC (140+B=14+B=1) +BC = LHS 7. Redundant Literal Rule (RLR):- Law 1:A+AB=A+BProof A+AB=(A+A) (A+B) =1.(A+B) FASB Law 2: A(A + B) Proof A(A+B) = AA+ AB =0+AB =AB 8, Idempotence Laws: Idempotence means same value. Law1:A.A=A Proof IfA=0, then A.A=0.0=0=A IfA=1,thenA.A=1.1=1=A This law states that AND of a variable with itself is equal to that variable only. Law2:A+A=A Proof IfA=0, then A+A=0+0=0=A IfA=1,thenA+A=14+1=1=A4 This law states that OR of a variable with itself is equal to that variable only. 9. Absorption Laws:~ There are two laws: Lawt:A+A-B=A ry aa aa Proof A+A:B=A(1+B)=A-1=A o fo |o fo o |i [o fo 1 |o |[o [1 1 |. [a fa Law 2:A(A+B)=A Proof A(A+B)=A-A+A-+B=A+AB=A(1+B)=A11=A A |B [A+B] A(A+B) o jo fa fo o |1 ja fo 1 fo fa fa10. Consensus Theorem (Included Factor Theorem):- Theorem 1:_ _ AB +AC + BC = AB +AC Proot LHS=AB+AC+BC = AB + AC + BC (AtA) AB +AC +BCA+BCA = AB (1 +0) +AC (1+ B) =AB (1) #AC (1) AB + AC = RHS Theorem 2: (A+ B)(A+C)(B+ C) =(A+B)(A+ C) Proof LHS = (A+B) (A+ 0) (B+C) (AA + AC + BA + BC) (B+ C) =(AC+BC+AB)(B+C) ABC + BC + AB + AC + BC+ABC = AC+BC +AB RHS= (A +B) (A+C) AA+ AC +BC +AB = AC +BC +AB LHS ition Theorem:- AB +AC = (A+ C)A+B) Proof RHS= (A+) (A+B) = AA+CA+AB+CB O+AC+AB+ BC _ ‘AC + AB + BC (A+A) AB + ABC + AC +ABC = AB+AC. = LHS 12. De Morgan’s Theorem:- De Morgan's theorem represents two laws in Boolean algebra Law1: A¥B=A-B Proof === A A+B /AtB a = |*5 o [oo 0 1 a 1|t o | 4 1 0 = {0 ojo 1 | 0 1 0 d 1] 0 1 |4 1 0 1 oj}?This law states that the complement of a sum of variables is equal to the product of their individual complements Law2: A Proof A | 8 |A.8 | 4-8 ale] a |B lass. ofofo|4 abet ; ° oj 7 of+[1]|o|1 tyeojolt +{o[ojf+]4 a 7{[1[ 0 [ol] o This law states that the complement of a product of variables is equal to the sum of their individual ‘complements, DUALITY:- The implication of the duality concept is that once a theorem or statement is proved, the dual also thus stand proved. This is called the principle of duality. TAB, Coo 0 1,4, e214, B,C, Relations between complement and dual £.(A, B,C, ....)=1(A, B,C, f(A, B,C, .....) =£(A,B,C....) = f(A, B,C, .....) The first relation states that the complement of a function f(A, B, C, ...) can be obtained by complementing all the variables in the dual function f, (A, B,C, .....). ‘The second relation states that the dual can be obtained by compiementing all the literals in TAB.C,...). DUALS:- Given expression Dual 1=0 1+ 141 o+ At At AtASA At A+B=BtA A+(B+C)=(A+B)+C A+BC= (A+B) (A+C) A+AB=A, At At +8 A+B= AB 45. (A+B) (AtC)(B+C) =(AtB)(A+C) AB+AC+BC= ABS AC 46. A¥BC=(A+B)(A+C) A(BtC)=AB+AC 47. (A4C\(A*B) = ABYAC AC#AB=(A+B) (A+C) 418. (A+B)(C+D) = AC + AD + BC + BD. (AB+CD) = (A+C)(A+D)(B+C)(B+D) 419. A+B=AB+AB+ AB AB =(A+B) (A+B) (A+B) 20. AB+A+AB=0 RYB-A-(A+B)=4SUM - OF - PRODUCTS FORM:- ‘+ This is also called disjunctive Canonical Form (DCF) or Expanded Sum of Products Form or Canonical ‘Sum of Products Form. ‘+ In this form, the function is the sum of a number of products terms where each product term contains all variables of the function either in complemented or uncompiemented form. ‘+ This can also be derived from the truth table by finding the sum of all the terms that corresponds to those combinations for which f” assumes the value 1 Forexample = _ (A.B,C)=AB+BC) AB(C+C)+BC(A+A) BC + ABC + ABC + ABC ‘© The product term which contains all the variables of the functions either in complemented or uncomplemented form is called a minterm ‘+The minterm is denoted as mo, m1, m2 ... ‘+ An‘n’ variable function can have 2n minterms. ‘+ Another way of representing the function in canonical SOP form is the showing the sum of minterms for which the function equals to 1 For example £(A,B, C)= mi + met my + ms or £(A,B, C)=¥ m(1, 2, 3,5) Where 5m represents the sum of all the minterms whose decimal codes are given the parenthesis. PRODUCT- OF - SUMS FORM:- ‘* This form is also called as Conjunctive Canonical Form ( CCF) or Expanded Product - of - Sums Form or Canonical Product Of Sums Form, ‘This is by considering the combinations for which f = 0 Each term is a sum of all the variables. _ The function f(A, B, C)= (A+B + CC) +(A+B+C-0) . (A+B4C)(A+B+C)(A+B+C)(A+B4+C) ‘+The sum term which contains each of the ‘n’ variables in either complemented or uncomplemented form is called a maxterm. ‘+ Maxterm is represented as Mo, M;, Mz, Thus CCF of f may be written as f(A, B, C= Mo ~ Ma * Me: Mz or f(A, B, C)=(0, 4,6, 7) Where represented the product of all maxterms. CONVERSION BETWEEN CANONICAL FORM:- ‘The complement of a function expressed as the sum of minterms equals the sum of minterms missing from the ‘original function. Example:- f(A, B, C) = 3m( 0,246.7) This has a complement that can be expressed as £ (A,B, C) =¥ m(1, 3, 5) =m, + ms + m5 if we complement f by De- Morgan's theorem we obtain fin a form. (MEF Mey = Ty. THs. Ts= My Ms Ms =P] M(1, 3,5) Example: oo Expand A (A+B) (A+B + C) to maxterms and minterms. Solution:- InPOS form _ A(A+B) (A+B+0) A=A+BB+CG =(A+B)(A+B)4+CC _ =(A+B+CC)(A+B+C6) =(A+B+C) (A+B +0)(A+B+0)(A+B+6) A+B=A+B+ CC =A+B+C)A+B+0) Therefore A(A+ B)(A+B+C) a - _ _ = (A+B +C) (A+B +6) (A+ B+ C) (A+B +C) (A¥B+C) (A¥B+C) (000) (001) (010) (011) (100) (101) My My» My My ~ Mg Ms =f1M(0, 1, 2, 3, 4,5) The maxterms Me and M; are missing in the POS form. ‘So, the SOP form will contain the minterms 6 and 7 KARNAUGH MAP OR K. ‘The K- map is a chart or a graph, composed of an arrangement of adjacent cells, each representing a Particular combination of variables in sum or product form. The K- map is systematic method of simplifying the Boolean expression. TWO VARIABLE K- MAP:- ‘A two variable expression can have 2” = 4 possible combinations of the input variables A and B. Mapping of SOP Expression:- * The 2 variable K-map has 2? = 4 squares. These squares are called cells. = A't'ls placed in any square indicates that corresponding minterm is included in the output expression, and a 0 or no entry in any square indicates that the corresponding minterm does not appear in the expression for output. B 04 o | AB] AB A = 1 | ap | aB Example:- 8 Map expression f= AB + AB Solution:- ‘The expression minterms is F= m+ m= m( 1,2)Minimization of SOP Expressi To minimize a Boolean expression given in the SOP form by using K- map, the adjacent squares having 1s, that is minterms adjacent to each other are combined to form larger squares to eliminate some variables. ‘The possible minterm grouping in a two variable K- map are shown below Ae o a | ae wo 4 ay 7 7 off 7a 0] [7] ] 0 of oo a3 ey z 1} o} o a} Ly] o fo] — -K 4-8 B a ° 1 feat ‘+ Two minterms, which are adjacent to each other, can be combined to form a bigger square called 2 — square or a pair. This eliminates one variable that is not common to both the minterms. ‘© Two 2-squares adjacent to each other can be combined to form a 4- square. A 4- square eliminates 2 variables. A 4-square is called a quad. ‘* Consider only those variables which remain constant throughout the square, and ignore the variables Which are varying. The non-complemented variable is the variable remaining constant as 1.The complemented variable is the variable remaining constant as 2 0 and the variables are written as a product term. Example:- se Reduce the expression f= AB + A B + AB using mapping, Solution:- Expressed in terms of minterms, the given expression is f=my+m,+m3= Fm (0, 1,3)Mapping of POS Expression:- Each sum term in the standard POS expression is called a Maxterm. A function in two variables (A,B) has 4 possible maxterms, A+ B, A+B, A+B and A+B. They are represented as Mo, M;, Mz and Ms respectively. B A 0 1 o a OJA+BjA+B ~ 2 2 1|A+B/A+B ‘The maxterm of a two variable K-map Example:- 8 Plot the expression f= (A + B)(A + BY(A+ B) Solution:- Expression interms of maxterms is f= TTM (0, 2, 3) B A 0 1 0 1 oO; oO 1 3 1 Oo oO Minimization of POS Expressions: In POS form the adjacent 0s are combined into large square as possible. If the squares having complemented variable then the value remain constant as a 1 and the non-complemented variable if its value remains constant as a 0 along the entire square and then their sum term is written. The possible maxterms grouping in a two variable K-map are shown below 8 Woo 1 Wo 1 No a Onn yt o] 4 o| [oy] + of 1] 4 aT orn) 3 1} 1} [o a} fof] 4 ilo} eA 4-8 8 =A B a\_o 4 7 o| fo fo z 1] lo | o)Example:- aoe Reduce the expression f = (A + B)(A + B)(A +B ) using mapping Solution:- ‘The given expression in terms of maxterms is f= TTM (0, 1, 3) wo 4 eta) ) if tte” sO THREE VARIABLE K- MAP:. ‘A function in three variables (A, B, C) can be expressed in SOP and POS form having eight possible ‘combination. A three variable K- map have 8 squares or cells and each square on the map represents a minterm or maxterm is shown in the figure below. BC BC AX_00___ on ci 10 a 00 on 1" 10 x8c'| asc'| xe0'| aac" cla+e+o é ¢ ° O|A+B+C/A+B+Ci/A+B+TlA+B+C| wo oo (my) | (m) Mo) |) | yy |) ca z = z a ABT | ABC | ABC | ABT A lA 1 1/A+B+ClA+B+CA+8+C)AsB+c (ing | md | omy | (ro) wy | Md | my | ay (@) Minterms (b) Maxtérms Example:- ee ‘Map the expression f = ABC+ABC + ABC + ABC +ABC Solution:- So in the SOP form the expression is f= 5 m (1, 5.2.6, 7) BC AX_00. 01 11:10 oO q1 3 2 oj o 1 0 1 4 5 7 6 1] 0 1 1 4 Example: _ Ree ce iat ee Map the expression f= (A+ B + C) (A+ B+G) (A+ 6+ 6) (A+ B+ G)(A+B+C) Solution:- So in the POS form the expression is f= TT M (0, 5, 7, 3, 6)M ation of SOP and POS Expressions:- For reducing the Boolean expressions in SOP (POS) form the following steps are given below + Draw the K-map and place 1s (0s) corresponding to the minterms (maxterms) of the SOP (POS) expression + Inthe map 1s (0s) which are not adjacent to any other 1(0) are the isolated minterms (maxterms). They are to be read as they are because they cannot be combined even into a 2-square + For those 1s (0s) which are adjacent to only one other 1(0) make them pairs (2 squares) + For quads (4- squares) and octet (8 squares) of adjacent 1s (0s) even if they contain some 1s (0s) which have already been combined. They must geometrically form a square or a rectangle. + For any 1s (0s) that have not been combined yet then combine them into bigger squares if possible. + Form the minimal expression by summing (multiplying) the product (sum) terms of all the groups. ‘Some of the possible combinations of minterms in SOP form 8c oo or 1110 0 77a — ; 1 sept tae WAALS PART POT aR 1-80 ty These possible combinations are also for POS but 1s are replaced by Os. FOUR VARIABLE K-MAP:- A four variable (A, B, C, D) expression can have 2* = 16 possible combinations of input variables. A four variable K-map has 2* = 16 squares or cells and each square on the map represents either a minterm or a maxterm as shown in the figure below. The binary number designations of the rows and columns are in the gray code. The binary numbers along the top of the map indicate the conditions of C and D along any column and binary numbers along left side indicate the conditions of A and B along any row. The numbers in the top right comers of the squares indicate the minterm or maxterm desginations.SOP FORM cp ae 00 o1 W 10 00 POS FORM ne? 00 ot n 10 3 + 5 7 A+B+C+0| A+B+C+0] A+B+C0+D] A+B+E4D 00} yy my (a) ™) 7 = 7 7 or | A*B+C+0 A+B+C+0| A+B+C+D/ A+B+C+D (My (™,) (™,) (™,) a = 7 7 1] AtB+c+0 K+B+0+0| A+B+0+0/A+B+C+d ™) M,.) (Mg) 40) 3} 7 7 to|At8+C+0| A+ BsC+D) Av B+O+0| A+Bs 040 (My) M) (™,,) (Myo) M ation of SOP and POS Expressions:~ For reducing the Boolean expressions in SOP (POS) form the following steps are given below * Draw the K-map and place 1s (0s) corresponding to the minterms (maxterms) of the SOP (POS) expression + Inthe map 1s (0s) are not adjacent to any other 1(0) are the isolated minterms (maxterms). They are to be read as they are because they cannot be combined even into a 2-square + For those 1s (0s) which are adjacent to only one other 1(0) make them pairs (2 squares) + For quads (4- squares) and octet (8 squares) of adjacent 1s (0s) even if they contain some 1s (0s) Which have already been combined. They must geometrically form a square or a rectangle. + For any 1s (Os) that have not been combined yet then combine them into bigger squares if possible, + Form the minimal expression by summing (multiplying) the product (sum) terms of all the groups. Example: Reduce using mapping the expression f = 5 m (0, 1, 2, 3, 5, 7, 8, 9, 10, 12, 13) Solution:- ‘The given expression in POS form is f= TT M (4, 6, 11, 14, 15) and in SOP form f= 5 m(0, 1, 2,3, 5,7, 8,9. 10, 12, 13)ABN” 00 ott 10 ABS. 0001 14110 3] 7s a ay oof TF 00 on 1 4 oro) r ape] a a] 33] —e] 98 ula pd 1" a] fa} 4] 38 ay 79 soft} 4 H 10 | fn = BD + AC + AD =A+B+DA+ C+ DA+B+C) (a) SOP K-map (&) POS K-map ‘The minimal SOP expression is frr= BO + AC + AD The minimal POS expression is fin=(A+B + D) (A+ C+D) (A+ B+C) DON’T CARE COMBINATIONS: ‘The combinations for which the values of the expression are not specified are called don't care combinations or optional combinations and such expression stand incompletely specified. The output is a don't care for these invalid combinations. The don't care terms are denoted by d or X. During the process of designing using SOP maps, each don't care is treated as 1 to reduce the map otherwise it is treated as 0 and left alone. During the process of designing using POS maps, each don't care is treated as 0 to reduce the map otherwise it is treated as 1 and left alone. A standard SOP expression with don't cares can be converted into standard POS form by keeping the don't cares as they are, and the missing minterms of the SOP form are written as the maxterms of the POS form. Similarly, to convert a standard POS expression with don't cares can be converted into standard SOP form by keeping the don't cares as they are, and the missing maxterms of the POS form are written as the minterms of the SOP form. Example:~ Reduce the expression f = J m(1, 5, 6, 12, 13, 14) + d(2, 4) using K- map. Solution:- ‘The given expression in SOP form is f= 5m (1, 5.6, 12, 13, 14) + d(2, 4) The given expression in POS form is f= TT M (0, 3, 7, 8, 9, 10, 11,15) + 4(2, 4) as? 00 014110 ap oo 01 11__ 410 00 ool 0 oF oi] x un n 10 tol Tey [-o— Inn = BC + BB + AED fon = (G+ D\A+ BYE + D) (@) SOP K-map (b) POS K-map ‘The minimal of SOP expression is fiji, = BC + BD +ACD ‘The minimal of POS expression is fain = (B + D(A + B) (C+ D)SEQUENTIAL LOGIC CIRCUIT SEQUENTIAL CIRCUIT: It is @ circuit whose output depends upon the present input, previous output and the sequence in which the inputs are applied, HOW THE SEQUENTIAL CIRCUIT |S DIFFERENT FROM COMBINATIONAL CIRCUIT? - In combinational circuit output depends upon present input at any instant of time and do not use memory. Hence previous input does not have any effect on the circuit. But sequential circuit has memory and depends upon present input and previous output ‘Sequential circuits are slower than combinational circuits and these sequential circuits are harder to design SEQUENTIAL LOGIC CIRCUIT Input Output MEMORY Clock | J L [Block diagram of Sequential Logic Circuit] The data stored by the memory element at any given instant of time is called the present state of sequential circuit. ‘TYPES:- ‘Sequential logic circuits (SLC) are classified as, @ ‘Synchronous SLC (i) Asynchronous SLC The SLC that are controlled by clock are called synchronous SLC and those which are not controlled by a clock are asynchronous SLC Clock:- A recurring pulse is called a clock FLIP-FLOP AND LATCH:~ A flip-flop or latch is a circuit that has two stable states and can be used to store information. A flip-flop is a binary storage device capable of storing one bit of information. in a stable state, the output of a flip-flop is either 0 or 1 Latch is a non-clocked flip-flop and it is the building block for the flip-flop. A storage element in digital circuit can maintain a binary state indefinitely until directed by an input signal to switch state, ‘Storage element that operate with signal level are called latches and those operate with clock transition are called as flip-flops.‘+ The circuit can be made to change state by signals applied to one or more control inputs and will have fone or two outputs. ‘+ Afiip-flop is called so because its output either flips or flops meaning to switch back and forth. + A flip-flop is also called a bi-stable multi-vibrator as it has two stable states. The input signals which ‘command the flip-flop to change state are called excitations ‘+ Flip-flops are storage devices and can store 1 or 0. ‘+ Flip-flops using the clock signal are called clocked flip-flops. Control signals are effective only if they are applied in synchronization with the clock signal. ‘+ Clock-signals may be positive-edge triggered or negative-edge triggered ‘+ Positive-edge triggered fip-flops are those in which state transitions take place only at positive- going edge of the clock pulse. ffl ‘+ Negative-edge triggered flip-flops are those in which state transition take place only at negative- going edge of the clock pulse ‘+ Some common type of flip-flops include a) SR (set-teset) F-F b) D (data or delay) F-F ©) T (toggle) F-F and 0) JKFF SRlatch ‘+ The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates. ‘+ Ithas two outputs labeled Q and Q’. Two inputs are there labeled S for set and R foe reset ‘+The latch has two useful states. When Q=0 and Q’=1 the condition is called reset state and when Q=1 and Q'=0 the condition is called set state. ‘+ Normally Q and Q’ are complement of each other. ‘+ The figure represents a SR latch with two cross-coupled NOR gates. The circuit has NOR gates and as we know if any one of the input for a NOR gate is HIGH then its output will be LOW and if both the inputs are LOW then only the output will be HIGH. 1 o (cet a @ JL 0 ‘* Under normal conditions, both inputs of the latch remain at 0 unless the state has to be changed. The application of a momentary 1 to the S input causes the latch to go to the set state. The S input must go back to 0 before any other changes take place, in order to avoid the occurrence of an undefined next state that results from the forbidden input condition, ‘+ The first condition (S = 1, R = 0) is the action that must be taken by input S to bring the circuit to the set state. Removing the active input from S leaves the circuit in the same state. After both inputs retum to 0, itis then possible to shift to the reset state by momentary applying a 1 to the R input. The 1 can then be removed from R, whereupon the circuit remains in the reset state. When both inputs S and R are equal to 0, the latch can be in either the set or the reset state, depending on which input was most recently a1‘+ Ifa.1 is applied to both the S and R inputs of the latch, both outputs go to 0. This action produces an undefined next state, because the state that results from the input transitions depends on the order in which they return to 0. it also violates the requirement that outputs be the complement of each other. In normal operation, this condition is avoided by making sure that 1’s are not applied to both inputs simultaneously ‘Truth table for SR latch designed with NOR gates is shown below. Input ‘Output ‘Comment s R a a Ghee 0 0 0 7 0 No change 0 0 7 0 7 0 7 0 7 0 Reset 0 7 7 0 0 7 0 0 7 7 Set 7 0 7 0 7 1 7 0 7 x Prohibited 7 7 7 7 x state s —r >— SR ‘Symbol for SR NOR Latch Racing Condition:- In case of a SR latch when S Racing condition. ‘SR latch using NAND gate:- = input is given both the output will try to become 0. This is called ‘+ The below figure represents a SR latch with two cross-coupled NAND gates. The circuit has NAND. gates and as we know if any one of the input for a NAND gate is LOW then its output will be HIGH and if both the inputs are HIGH then only the output will be LOW. ‘+ It operates with both inputs normally at 1, unless the state of the latch has to be changed. The application of 0 to the S input causes output Q to go to 1, putting the latch in the set state. When the S input goes back to 1, the circuit remains in the set state. After both inputs go back to 1, we are allowed to change the state of the latch by placing a 0 in the R input. This action causes the circuit to go to the reset state and stay there even after both inputs return to 1 1 0 ‘+The condition that is forbidden for the NAND latch is both inputs being equal to 0 at the same time, an input combination that should be avoided,In comparing the NAND with the NOR latch, note that the input signals for the NAND require the complement of those values used for the NOR latch. Because the NAND latch requires a 0 signal to change its state, itis sometimes referred to as an S'R’ latch. The primes (or, sometimes, bars over the letters) designate the fact that the inputs must be in their complement form to activate the circuit. The above represents the symbol for inverted SR latch or SR latch using NAND gate. = SR ‘Truth table for SR latch using NAND gate or Inverted SR latch S R Quo Yaaxt 0 0 Race Race 0 1 oO 1 (Reset) 1 0 1 0 (Set) 1 1 ‘Q (No change) Q’ (No change) DLATCH:- ‘+ One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs $ and R are never equal to 1 at the same time. D En » [> e Lp] ‘© This is done in the D latch. This latch has only two inputs: D (data) and En (enable), ‘+The D input goes directly to the S input, and its complement is applied to the R input. 5D ° (2) Loge dagen a (Symbol for D-Latch) ‘+ As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level and the circuit can't change state regardless of the value of D. ‘+ The below represents the truth table for the D-latch En D Next State of 0 a x No change. 1 0 (Q=0;Reset State 1 1 (Q=1:Set State‘+The D input is sampled when En = 1. If D = 1, the Q output goes to 1, placing the circuit in the set state. If D = 0, output Q goes to 0, placing the circuit in the reset state. This situation provides a path from input D to the output, and for this reason, the circuit is often called a TRANSPARENT latch. ‘TRIGGERING METHODS:- ‘+ The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger, and the transition it causes is said to trigger the fip-flop. Fiip-flop circuits are constructed in such a way as to make them operate properly when they are part of a sequential circuit that employs a common clock. The problem with the latch is that it responds to a change in the level of a clock pulse. For proper operation of a flip-flop it should be triggered only during a signal transition. This can be accomplished by eliminating the feedback path that is inherent in the operation of the sequential circuit using latches. A clock pulse goes through two transitions: from 0 to 1 and the return from 1 100. ‘Aways that a latch can be modified to form a flip-flop is to produce a flip-flop that triggers only during a signal transition (from 0 to 1 or from 1 to 0) of the synchronizing signal (clock) and is disabled during the rest of the clock pulse. (a) Resp pose ee (b) Positive ee rape (6) Nepiveedpe rapene JK FLIP-FLOP:- ‘+The JK flip-flop can be constructed by using basic SR latch and a clock. In this case the outputs Q and are returned back and connected to the inputs of NAND gates. This simple JK fiip Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit ‘The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the same “Set” and “Reset” inputs. The difference this time is that the "JK fiip flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at logic “1” (The below diagram shows the circuit diagram of a JK flip-flop) J—> -Q CcLK— K—j >» Q ‘+The JK fip flop is basically a gated SR Flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level ar ‘© Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1°, “logic 0”, “no change” and “toggle”.‘+The symbol for a JK fip flop is similar to that of an SR bistable latch except the clock input. (The above diagram shows the symbol of a JK flip-flop.) ‘+ Both the S and the R inputs of the SR bi-stable have now been replaced by two inputs called the J and K inputs, respectively after its inventor Jack and Kilby. Then this equates to: J = S and K = R ‘+ The two 2-input NAND gates of the gated SR bi-stable have now been replaced by two 3-input NAND. gates with the third input of each gate connected to the outputs at Q and Q’ ‘This cross coupling of the SR flip-flop allows the previously invalid condition of S to be used to produce a “toggle action” as the two inputs are now interlocked ‘ifthe circuit is now “SET” the J input is inhibited by the “0” status of Q’ through the lower NAND gate. If the circuit is "RESET" the K input is inhibited by the “0” status of Q through the upper NAND gate. As Q and Q are always different we can use them to control the input. = "1" and R= "1" state (Truth table for JK fip-fop) ‘Output ‘Comment Qrent No change Reset Set Toggle ‘© When both inputs J and K are equal to lagi “1", the JK flip flop toggles. TELIP-FLOP- ‘+ Toggle flip-flop or commonly known as T flip-flop. ‘+ This flip-flop has the similar operation as that of the JK flip-flop with both the inputs J and K are shorted i.e. both are given the common input iu ‘+ Hence its truth table is same as that of JK flip-flop when follows, 0 and So its truth table is as‘Comment No change Toggles CHARACTERISTIC TABLE: ‘= A characteristic table defines the logical properties of a flip-flop by describing its operation in tabular form. ‘+ The next state is defined as a function of the inputs and the present state. = Q(t) refers to the present state and Q (t + 1) is the next. ‘+ Thus, Q (t) denotes the state of the fi-flop immediately before the clock edge, and Q(t + 1) denotes the state that results from the clock transition. ‘+The characteristic table for the JK flip-flop shows that the next state is equal to the present state when inputs J and K are both equal to 0. This condition can be expressed as Q (t+ 1) = Q (t), indicating that the clock produces no change of state. Characteristic Table Of JK Flip-Flop J K ate) a 0 Qi) No change 0 7 0 Reset 7 0 7 Set 7 7 QW Complement + When K = 1 and J = 0, the clock resets the flip-flop and Q(t + 1) = 0. With J = 1 and K = 0, the flip-flop sets and Q(t + 1) = 1. When both J and K are equal to 1, the next state changes to the complement of the present state, a transition that can be expressed as Q(t + 1) = Q'(), ‘+ The characteristic equation for JK flip-flop is represented as Qqtet}= Ja+ KO Characteristic Table of D Flip-Flop D Q(t+1) 0 0 7 1 The next state of a D flip-flop is dependent only on the D input and is independent of the present state. This can be expressed as Q (t+ 1) = D. it means that the next-state value is equal to the value of D. Note that the D flip-flop does not have a “no-change” condition and its characteristic equation is written as Qit+1)=D Characteristic Table of T Flip-Flop te) ‘Q()_No change. ‘Q(t)_ Complement elaThe characteristic table of T flip-flop has only two conditions: When T = 0, the clack edge does not change the stale; when T = 1, the clock edge complements the state of the flip-flop and the characteristic equation is, Q(t#1)=T©Q=TQ+TQ MASTER-SLAVE JK FLIP-FLOP: FLIP-FLOP CONVERSIONS:. The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. ‘The outputs from Q and Q’ from the “Siave" flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” fp flop being connected to the two inputs of the “Siave" fip flop. This feedback configuration from the slave's output to the master's input gives the characteristic toggle of the JK fip flop as shown below. ‘The Master-Slave JK Flip Flop Master | Slave Flip-flop _|_Flip-flop The input signals J and K are connected to the gated “master” SR fip flop which “locks” the input condition while the clock (Cik) input is “HIGH” at logic level “1” As the clock input of the “slave” flip flop is the inverse (complement) of the “master’ clock input, the “slave” SR fi flop does not toggle The outputs from the “master” fip flop are only “seen” by the gated "slave" flip flop when the clock input goes “LOW to logic level “0” When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes to its inputs are ignored. The gated "slave" fip flop now responds to the state of its inputs passed over by the "master" section. Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed through to the gated inputs of the "slave" flip flop and on the “High-to-Low’ transition the same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse-triggered Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on the faling-edge of the clock signal in other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal ‘SR Flip Flop to JK Flip Flop For this J and K will be given as external inputs to S and R. As shown in the logic diagram below, S and R will be the outputs of the combinational circuit,The truth tables for the flip flop conversion are given below. The present state is represented by Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp, the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be obtained by the JK fip flop after the value of Qp. The table is then completed by writing the values of S and R required to get each Qp+1 from the corresponding Qp. That is, the values of S and R that are required to change the state of the fip flop from Qp to Qp+1 are written 'S-R Flip Flop to J-K Flip Flop Conversion Table TH inputs | Owpas | SR input a « | on} s 2 opie Diagram K-Map JK Flip Flop to SR Flip Flop ‘+ This will be the reverse process of the above explained conversion. S and R will be the external inputs to J and K. J and K will be the outputs of the combinational circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight combinations are made, For each combination, the corresponding Qp+1 outputs are found out ‘+ The outputs for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the outputs are considered invalid and the J and K values are taken as “don't cares”.2+ Flip Flop to S-R FlipFlop ‘Conversion Table o9ie Diegram 2x Inputs ‘SR Flip Flop to D Flip Flop 'S and R are the actual inputs of the flip flop and D is the external input of the fp flop. The four combinations, the logic diagram, conversion table, and the K-map for S and R in terms of D and Qp are shown below. S-R Flip Flop to D Flip Flop Conversion Table opie Bagram po s=0 D Flip Flop to SR Flip Flop Dis the actual input of the flip flop and S and R are the external inputs. Eight possible combinations are achieved from the external inputs S, R and Qp. But, since the combination of S=1 and R=1 are invalid, the values of Qp+1 and D are considered as “don't cares” The logic diagram showing the conversion from D to SR, and the K-map for D in terms of S, R and Qp are shown below.Flip Flop to S-R Flip Flop Camere Te map Loge Deg ee, ko oe wy x o} o o o r 1 2 lc »{ o-par 7 “ ’ & b= sion Tivol” [Donteare JK Flip Flop to T Flip Flop:- Jaand K are the actual inputs of the flip flop and T is taken as the external input for conversion Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. ‘©The conversion table, K-maps, and the logic diagram are given below. ings 344 Flip Flop to T Flip Flop 5 D Flip Flop to JK Fiip Flop: In this conversion, D is the actual input to the fip flop and J and K are the external inputs. J, K and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qy p. The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to JK are given in the figure below.D Flip Flop to 2-K Flip Flop remap Loge Otgram JK Flip Flop to D Flip Flop: © Dis the external input and J and K are the actual inputs of the flip flop. D and Qp make four combinations. J and K are expressed in terms of D and Qp. ‘© The four combination conversion table, the K-maps for J and K in terms of D and Qp, 3-K Flip Flop to 0 Flip FlopCOMBINATIONAL LOGIC CIRCUIT ‘+ Acombinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. ‘* A combinational circuit performs an operation that can be specified logically by a set of Boolean functions. ‘It consists of an interconnection of logic gates. Combinational logic gates react to the values of the signals at their inputs and produce the vaiue of the output signal, transforming binary information from the given input data to a required output data A block diagram of a combinational circuit is shown in the below figure. The n input binary variables come from an external source; the m output variables are produced by the internal combinational logic circuit and go to an external destination. ‘+ Each input and output variable exists physically as an analog signal whose values are interpreted to be a binary signal that represents logic 1and logic 0. Combinational [= output Circuit BINARY ADDER-SUBTRACTOR: ‘* Digital computers perform a variety of information-processing tasks. Among the functions encountered are the various arithmetic operations. ‘+The most basic arithmetic operation is the addition of two binary digits. This simple addition consists of four possible elementary operations: 0+ 0=0,0+1=1,1+0=1,and1+1= 10. ‘+ The first three operations produce a sum of one digit, but when both augend and addend bits are equal to 1; the binary sum consists of two digits. The higher significant bit of this result is called a carry. ‘+ When the augend and addend numbers contain more significant digits, the carry obtained from the addition of two bits is added to the next higher order pair of significant bits, A combinational circuit that performs the addition of two bits is called a half adder. One that performs the addition of three bits (two significant bits and a previous carry) is a full adder. The names of the circuits stem from the fact that two haif adders can be employed to implement a full adder HALF ADDER: This circuit needs two binary inputs and two binary outputs ‘+The input variables designate the augend and addend bits; the output variables produce the sum and carry. Symbols x and y are assigned to the two inputs and S (for sum) and C (for carry) to the outputs. ‘The truth table for the haif adder is listed in the below table. The C output is 1 only when both inputs are 1. The S output represents the least significant bit of the sum. ‘+ The simplified Boolean functions for the two outputs can be obtained directly from the truth table. x yo 28 o ofo 0 o afi 0 1 of i 0 a a1fo i ‘Truth Table ‘© The simplified sum-of-products expressions are S=xytxy Caxy ‘+ The logic diagram of the half adder implemented in sum of products is shown in the below figure. It can be also implemented with an exclusive-OR and an AND gate.Dy, TO ; —: << oe FULL ADDER: © A full adder is a combinational circuit that forms the arithmetic sum of three bits. ‘© It consists of three inputs and two outputs. Two of the input variables, denoted by x and y , represent the two significant bits to be added. The third input, z , represents the carry from the previous lower significant position. Truth Table ‘+ Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary representation of 2 or 3 needs two bits. The two outputs are designated by the symbols S for sum and C for carry Ao oo XV wot 0 4 1 o ‘ @s=x' rye! tay'2' taye (by) C=ay baz tye K-Map for full adder ‘+ The binary variable S gives the value of the least significant bit of the sum. The binary variable C gives the output carry formed by adding the input carry and the bits of the words ‘+ The eight rows under the input variables designate all possible combinations of the three variables. The output variables are determined from the arithmetic sum of the input bits. When all input bits are 0, the. output is 0. ‘+ The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output has a carry of 1 if two or three inputs are equal to 1 ‘+ The simplified expressions are S=xyz4 xyz + xyz tzCaxytetyz The logic diagram for the full adder implemented in sum-of-products form is shown in figure. [) =_. [ A y 4q)H Implementation of Full Adder in SOP form It can also be implemented with two half adders and one OR gate as shown in the figure. Half Adder oe : ell @eyzty Implementation of Full Adder using Two Half Adders and an OR gate ‘Aull adder is a combinational circuit that forms the arithmetic sum of three bits. BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n-1 full adders. in the former case, the input carry to the least significant position is fixed at 0. The interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple carry adder is shown in the figure. The augend bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bit. The carries are connected in a chain through the full adders. The input carry to the adder is CO, and it ripples through the full adders to the output carry C4. The S outputs generate the required sum bits. ‘An n-bit adder requires n full adders, with each output carry connected to the input carry of the next higher order full adder. Consider the two binary numbers A = 1011 and B = 0011. Their sum S = 1110 is formed with the four- bit adder as follows:Subscript i: x 2) f) ® Input carry o 41 0 Augend i © 1 Addend oo 1 1 Sum f (i) @) |e Output carry oo 1 1 ‘+ The bits are added with full adders, starting from the least significant position (subscript 0), to form the sum bit and carry bit. The input carry Co in the least significant position must be 0. ‘+ The value of C..; in a given significant position is the output carry of the full adder. This value is transferred into the input carry of the full adder that adds the bits one higher significant position to the left. ‘+ The sum bits are thus generated starting from the rightmost position and are available as soon as the corresponding previous carry bit is generated, All the carries must be generated for the correct sum bits to appear at the outputs. tt it ii ti ak & 4G 4 Four Bit Binary Adder HALF SUBTRACTOR:- ‘This circuit needs two binary inputs and two binary outputs. ‘+ Symbols x and y are assigned to the two inputs and D (for difference) and B (for borrow) to the outputs. ‘+The truth table for the haif subtractor is listed in the below table fea oi || a) ms) 2 || (ae i a se) 2) | ae Truth Table ‘+The B output is 1 only when the inputs are 0 and 1. The D output represents the least significant bit of the subtraction. ‘* The subtraction operation is done by using the following rules as with borrow 1; ‘+The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum-of products expressions are D= xy +xy and B=xyHy o=x@y oxy ‘+The logic diagram of the half adder implemented in sum of products is shown in the figure. It can be also implemented with an exclusive-OR and an AND gate with one inverted input. FULL SUBTRACTOR:- ‘* full subtractor is a combinational circuit that forms the arithmetic subtraction operation of three bits. ‘* It consists of three inputs and two outputs. Two of the input variables, denoted by x and y , represent the two significant bits to be subtracted. The third input, z , is subtracted from the result Of the first subtraction Truth Table ‘+ Two outputs are necessary because the arithmetic subtraction of three binary digits ranges in value from 0 to 3, and binary representation of 2 or 3 needs two bits. The two outputs are designated by the symbols D for difference and B for borrow. ‘+ The binary variable D gives the value of the least significant bit of the difference. The binary variable B gives the output borrow formed during the subtraction process. \_o o “no o on wo 0 1 1 0 a 1 xfi] 1 1 elt iL l \ I D= x'y'zex'yz'tay'2'txyz B=x'zex'ytyz K-Mep for full Subtractor ‘+ The eight rows under the input variables designate all possible combinations of the three variables. The output variables are determined from the arithmetic subtraction of the input bits. ‘© The difference D becomes 1 when any one of the input is tor all three inputs are equal to1 and the borrow B is 1 when the input combination is (0.0 1) or (0 1 0) or (0.1 1) or (1 1 1), ‘+ The simplified expressions are D=xyz + xyz! + xyz + yz Bexz+xy+yz ‘* The logic diagram for the full adder implemented in sum-of-produets form is shown in figure.Lit ; { )- Implementation of Full Subtractor in SOP form MAGNITUDE COMPARATOR ‘+ Amagnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The following description is about a 2-bit magnitude comparator circuit The outcome of the comparison is specified by three binary variables that indicate whether A < B, A = B,orA>B ‘* Consider two numbers, A and B, with two digits each. Now writing the coefficients of the numbers in descending order of significance: A=AiAy B=B; By ‘+The two numbers are equal if all pairs of significant digits are equal ie. if and only if Ai = B41, and AQ = BO. ‘+ When the numbers are binary, the digits are either 1 or 0, and the equality of each pair of bits can be expressed logically with an exclusive-NOR function as X1=A\B +A By ‘And x0=AyBy+Aq Bo! © The equality of the two numbers A and B Is displayed in a combinational circuit by an output binary variable that we designate by the symbol (A = B). This binary variable is equal to 1 if the input numbers, A and B , are equal, and is equal to 0 otherwise. For equaiity to exist, all xi variables must be equal to 1, a condition that dictates an AND operation of all variables: (A= B) = xix0 ‘The binary variable (A = 8) is equal to 1 only if all pairs of digits of the two numbers are equal. To determine whether A is greater or less than B, we inspect the relative magnitudes of pairs of significant digits, starting from the most significant position. if the two digits of a pair are equal, we ‘compare the next lower significant pair of digits. if the corresponding digit of A is 1 and that of Bis 0, we conclude that A > B. If the corresponding digit of A is 0 and that of B is 1, we have A < B. The sequential comparison can be expressed logically by the two Boolean functions, (A> B) = A:B:'#x;AcB'o (A Logic Diagram of 2-bit Magnitude ComparatorDECODER: 14D o 2 & Diy Ds Ds a+Do- i's i i 00 a i 0 0 01 0 D, r—De ot ‘+ Adecoder is a combinational circuit that converts binary information from n input lines to a maximum of 2" unique output lines. If the n -bit coded information has unused combinations, the decoder may have fewer than 2n outputs. ‘The decoders presented here are called n -to- m line decoders, where m ... 2n. ‘Their purpose is to generate the 2n (or fewer) minterms of n input variables. Each combination of inputs will assert a unique output. The name decoder is also used in conjunction with other code converters, such as a BCD-to-seven-segment decoder. ‘+ Consider the three-to-eight-line decoder circuit of three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables. ‘+ The three inverters provide the complement of the inputs, and each one of the eight AND gates generates one of the minterms. ‘+ The input variables represent a binary number, and the outputs represent the eight digits of a number in the octal number system. ‘+ However, a three-to-eight-ine decoder can be used for decoding any three-bit code to provide eight ‘outputs, one for each element of the code. ‘A two-to-four-line decoder with an enable input constructed with NAND gates is shown in Fig. The circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to 0 (ie., active-low enable). As indicated by the truth table, only one output can be equal to 0 at any given time; all other outputs are equal to 1 The output whose value is equal to 0 represents the minterm selected by inputs A and B. The circuit is disabled when E is equal to 1, regardless of the values of the other two inputs, When the circuit is disabled, none of the outputs are equal to 0 and none of the minterms are selected In general, a decoder may operate with complemented or un-complemented outputs, ‘The enable input may be activated with a 0 or with a 1 signal ‘Some decoders have two or more enable inputs that must satisfy a given logic condition in order to enable the circuit ‘+ Adecoder with enable input can function as a demultiplexer— a circuit that receives information from a single line and directs it to one of 2n possible output lines. The selection of a specific output is controlled by the bit combination of n selection lines. ‘The decoder of Fig. can function as a one-to-four-ine demultiplexer when E is taken as a data input line and A and B are taken as the selection inputs. ‘©The single input variable E has a path to all four outputs, but the input information is directed to only fone of the output lines, as specified by the binary combination of the two selection lines A and B ‘+ This feature can be verified from the truth table of the circuit ‘+ For example, if the selection lines AB = 10, output Dz will be the same as the input value E, while all other outputs are maintained at 1 ‘+ Since decoder and demultiplexer operations are obtained from the same circuit, a decoder with an enable input is referred to as a decoder — demuttiplexer. ‘+ Aapplication of this decoder is binary-to-octal conversionENCODER: ‘+ An encoder is a digital circuit that performs the inverse operation of a decoder. ‘+ Anencoder has 2n (or fewer) input lines and n output ines. ‘+ The output lines, as an aggregate, generate the binary code corresponding to the input value. Inputs Outputs DoD, Dz Ds Dy Ds De _—iDy ge iz i) Saha) |S ||| Ra) a o 0 0 @ i |e) Dip) a le) o 0 1 fi) |||) | || ay) eae) a wa |G a) 6 |) oi] a |lio| to me al | 0 (56s! (Nec) | ||iea || fews || 1 0 0 1 8 8) 2 @ | t i) o 1 dt a) me lem) io!) iy) a | a i @ 6 aij) (fae) ||) afl) ie: ‘+ The above Encoder has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. ‘+ Itis assumed that oniy one input has a value of 1 at any given time. ‘+ The encoder can be implemented with OR gates whose inputs are determined directly from the truth table Output z is equal fo 1 when the input octal digit is 1, 3, 5, or 7. Output y is 1 for octal digits 2, 3, 6, oF 7, and output x is 1 for digits 4, 5, 6, or 7. ‘+ These conditions can be expressed by the following Boolean output functions: 2 =D, +D,+Ds+Dy y =D, +D3+Ds+Dy Dy + Ds + De+ Dy ‘The encoder can be implemented with three OR gates. ‘The encoder defined above has the limitation that only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination ‘+ To resoive this ambiguity, encoder circuits must establish an input priority to ensure that only one input is encoded which is done in the Priority Encoder PRIORITY ENCODER: ‘© Apriority encoder is an encoder circuit that includes the priority function. ‘+The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. =, Ds xy V o x x o ° oo 1 o oid ° 1 0 1 1 114 ‘+ In addition to the two outputs x and y , the circuit has a third output designated by V ; this is a valid bit indicator that is set to 1 when one or more inputs are equal to 1Ifall inputs are 0, there is no valid input and V is equal to 0. The other two outputs are not inspected when V equals 0 and are specified as don'-care conditions. Here X's in output columns represent don'-care conditions, the X's in the input columns are useful for representing a truth table in condensed form. Inputs Outputs De Dy Ds Ds a # 0 0 0 0 x xb 1 0 0 oO oo 1 x 2 6 D fi, @ @ xe L 8 i op i x K x 4 aoa 4 Higher the subscript number, the higher the priority of the input. Input D3 has the highest priority, so, regardless of the values of the other inputs, when this input is 1, the output for xy is 11 (binary 3). If D2 = 1, provided that D3 = 0, regardless of the values of the other two lower priority inputs the output is 10. The output for D1 is generated only if higher priority inputs are 0, and so on down the priority levels. DD; ee DD. = DDN 0 _o1 it DPN 00 or __—*10 rm — a a of x | fr ]ir 00 | a affa on ao » Dd, u aia " Do} be Ht a 10| a ff 10| Ds x= Dit Ds ‘The maps for simplifying outputs x and y are shown in above Fig. ‘The minterms for the two functions are derived from its truth table. Although the table has only five rows, when each X in a row is replaced first by O and then by 1, we obtain all 16 possible input combinations. For example, the fourth row in the table, with inputs XX10, represents the four minterms 0010, 0110, 1010, and 1110. The simplified Boolean expressions for the priority encoder are obtained from the maps. The condition for output V is an OR function of all the input variables. ‘The priority encoder is implemented according to the following Boolean functions: Dy + Dy s+ D:D 0+ D, + D2 + D5Ds Ds MULTIPLEXE! ‘A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. ‘The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2" input lines and n selection lines whose bit combinations determine which input is selected A four-to-one-jine multiplexer is shown in the below figure. Each of the four inputs, |o through |, is applied to one input of an AND gate. Selection lines S; and So are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one-line output The function table lists the input that is passed to the output for each combination of the binary selection values. To demonstrate the operation of the circuit, consider the case when. SiS 10. The AND gate associated with input |, has two of its inputs equal to 1 and the third input connected to b The other three AND gates have at least one input equal to 0, which makes their outputs equal to 0. The output of the OR gate is now equal to the value of ls, providing a path from the selected input to the output, A multiplexer is also called a data selector, since it selects one of many inputs and steers the binary information to the output line. 4x1 MUX »—s, x—S, z 0 F (b) Multiplexer implementation4 Truth table % + Logic diagram DEMULTIPLEXER:- ‘+ The data distributor, known more commonly as @ Demuttipiexer or “Demux" for short, is the exact opposite of the Multiplexer. ‘+ The demultiplexer takes one single input data line and then switches it to any one of a number of individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a Parallel data at its output lines as shown below. ‘+ The Boolean expression for this 1-to-4 demuttiplexer above with outputs A to D and data select lines a, bis given as: F = (abyA + albB + abc + abD ‘* The function of the demultiplexer is to switch one common data input line to any one of the 4 output data lines A to D in our example above. As with the multiplexer the individual solid state switches are selected by the binary input address code on the output select pins “a” and "b" as shown. T}— a ar [Ones —,Logle Diagram Unlike multiplexers which convert data from a single data line to multiple lines and demultiplexers which convert multiple lines to a single data line, there are devices available which convert data to and from multiple lines and in the next tutorial about combinational logic devices. Standard demultiplexer \C packages available are the TTL 74LS138 1 to 8-output demultiplexer, the TTL 74L S139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-to-16 output demultiplexer. Output Select Data output Selected b a ° ° A ° 1 8 1 ° c 1 1 D “Truth TableLOGIC FAMILIES ‘* A cirouit configuration or approach used to produce a type of digital integrated circuit is called Logic Fa '* By using logic families we can generate different logic functions, when fabricated in the form of an IC with the same approach, or in other words belonging to the same logic family, will have identical electrical characteristics. ‘+ The set of digital ICs belonging to the same logic family are electrically compatible with each other. * Some common Characteristics of the Same Logic Family include Supply voltage range, speed of response, power dissipation, input and output logic levels, current sourcing and sinking capability, fan- out, noise margin, etc. '* Choosing digital (Cs from the same logic family guarantees that these ICs are compatible with respect to each other and that the system as a whole performs the intended logic function ‘TYPES OF LOGIC FAMILY: The entire range of digital ICs is fabricated using either bipolar devices or MOS devices or a combination of the two. © Bipolar families include:- Diode logic (DL) Resistor-Transistor logic (RTL) Diode-transistor logic (DTL) Transistor- Transistor logic (TTL) Emitter Coupled Logic (ECL), (also known as Current Mode Logic(CML)) Integrated Injection logic (/2L) * The Bi-MOS logic family uses both bipolar and MOS devices. wv wv wv ¥ L, mB = 3 A +Y-An 5 af — = Seacieee eh case esiaanragte: Diode-Transistor logic ree ogic (RTL) ou tore * Above are some example of DL, RTL and DTL. ‘+ MOS families include: ‘ThePMOS family (using P-channel MOSFETs) ‘The NMOS family (using N-channel MOSFETs) The CMOS family (using both N- and P-channel devices) SOME OPERATIONAL PROPERTIES OF LOGIC FAMILY The nominal value of the de supply voltage for TTL (transisitor-transistor logic) and CMOS (complementary metal-oxide semiconductor) devices is +5V_ Although ommitted from logic diagrams for simplicity, this voltage is connected to Vec or VDD pin of an IC package and ground is connected to the GND pin.TIL Logic Levels Vou ae 50 Vv Vision so Vv V. on tages Vin Logic 1 Vor oary 24 Vv Vescnny 20 Vv junpredictat ie} junpredictat le! \ 08 v You oie vif Yeo |g Vout Vertes |_togico | 84 Y “Meo Lb9 Jog y output input Vout ote) Logie] —— Vont Vannes [ Cosiet 159 ¥ Vit max 50 Vv Vw Logic 4 Ves cme 35 V fuera Uunpredictable| fw is ¥ Vo. uae Vie Logic 0 Voit vam [Logic 18:5 Y Vicor) oo v CMOS Logic Levels output input Noise Immunity:- ‘+ Noise is the unwanted voltage that is induced in electrical circuits and can present a threat to the poor operation of the circuit. In order not to be adversely effected by noise, a logic circuit must have a certain amount of ‘noise immunity’ ‘+ This is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing its output state is called Noise |mmunity. Noise Margin: ‘* Ameasure of a circuit's noise immunity is called ‘noise margin’ which is expressed in volts. ‘+ There are two values of noise margin specified for a given logic circuit: the HIGH (Vj) and LOW (Vw.) noise margins. ‘These are defined by following equations Vie = Vow: (Min) - Vai (Min) Via. = Va. (Max) - Vou (Max) Power Dissipation:- ‘* Allogic gate draws ICCH current from the supply when the gate is in the HIGH output state, draws ICCL. current from the supply in the LOW output state. ‘+ Average powers PD = VCC ICC where ICC = (ICCH + ICCL) /2 Propagation Delay time:- ‘+ When a signal passes ( propagates ) through a logic circuit, it always experiences a time delay as shown below. A change in the output level always occurs a short time, called ‘propagation delay time’ later than the change in the input level that caused it Fan Out of Gates:-‘+ When the output of a logic gate is connected to one or more inputs of other gates, a load on the driving gate is created. There is a limit to the number of load gates that a given gate can drive. This limit is called the 'Fan-Out of the gate. TRANSISTOR-TRANSISTOR LOGIC:- ‘+ In Transistor-Transistor logic or just TTL, logic gates are built only around transistors. ‘+ TTL.was developed in 1965. Through the years basic TTL has been improved to meet performance requirements, There are many versions or families of TTL. + For example + Standard TTL + High Speed TTL (twice as fast, twice as much power) + Low Power TTL (1/10 the speed, 1/10 the power of “standard” TTL) + Schhottky TTL etc. (for high-frequency uses ) + All TTL logic families have three configurations for outputs 1. Totem pole output 2. Open collector output 3. Tristate output ‘Totem pole output:- ‘© Addition of an active pull up circuit in the output of a gate is called totem pole. ‘+ To increase the switching speed of the gate which is limited due to the parasitic capacitance at the output totem pole is used ‘+ The circuit of a totem-pole NAND gate is shown below, which has got three stages 4, Input Stage 2. Phase Splitter Stage 3. Output Stage Input Input 8. o GND + Transistor Q1 is a two-emitter NPN transistor, which is equivalent two NPN transistors with their base and emitter terminals tied together. ‘+ The two emitters are the two inputs of the NAND gate in TTL technology multiple emitter transistors are used for the input devices Diodes D2 and D3 are protection diodes used to limit negative input voltages ‘+ When there is large negative voltage at input, the diode conducts and shorting it to the ground Q2 provides complementary voltages for the output transistors Q3 and Q4. ‘+ The combination of Q3 and Q4 forms the output circuit often referred to as a totem pole arrangement (Q4 is stacked on top of Q3). In such an arrangement, either Q3 or Q4 conducts at a time depending upon the logic status of the inputs Diode D1 ensures that Q4 will turn off when Q2 is on (HIGH input) The output Y is taken from the top of Q3Advantages of Totem Pole Output ‘+ The features of this arrangement are 1. Low power consumption 2. Fast switching 3. Low output impedance OPEN COLLECTOR OUTPUT:- ‘* Figure below shows the circuit of a typical TTL gate with open-collector output Observe here that the Circuit elements associated with Q3 in the totem-pole circuit are missing and the collector of Qa is left open- circuited, hence the name open-collector. 7 c Input a- Input 8: oupia Dy Y ‘* An open-collector output can present a logic LOW output. Since there is no intemal path from the output Y to the supply voltage Vee . the circuit cannot present a logic HIGH on its own, Advantages of Open Collector Outputs: ‘+ Open-collector outputs can be tied directly together which results in the logical ANDing of the outputs. Thus the equivalent of an AND gate can be formed by simply connecting the outputs. ‘+ Increased current levels - Standard TTL gates with totem-pole outputs can only provide a HIGH current output of 0.4 mA and a LOW current of 1.6 mA. Many open-collector gates have increased current ratings. ‘Different voltage levels - A wide variety of output HIGH voltages can be achieved using open-collector gates. This is useful in interfacing different logic families that have different voltage and current level Fequirements. Disadvantage of open-collector gates:- ‘* They have slow switching speed. This is because the vaiue of pull-up resistor is in KW, which results in a relatively long time Constants Comparison of Totem Pole and Open Collector Output:- ‘* The major advantage of using a totem-pole connection is that it offers jow-output impedance in both the HIGH and LOW output states. Totem Pole ‘Open Collector ‘Output stage consists of pull-up transistor _| Output stage consists of only pull-down (Q3), diode resistor and pull-down transistor transistor ( External pull-up resistor is notrequired | External pull-up resistor i required for proper operation of gate ‘Output oF two gates cannot be tied together | Output of two gates can be tied together using wired AND technique ‘Operating speed is high Operating speed is low. TRISTATE (THREE-STATE) LOGIC OUPUT: ‘+ Tristate output combines the advantages of the totem-pole and open collector circuits. ‘© Three output states are HIGH, LOW, and high impedance (Hi-Z)EN IN OUT f oO x HI-Z IN our 1 0 0 Tai 2 EN ‘© For the symbol and truth table, IN is the data input, and EN, the additional enable input for control. For EN = 0, regardless of the value on IN(denoted by X), the output value is Hi-Z. For EN = 1, the output value follows the input value ‘© Data input, IN, can be inverted. Control input, EN, can be inverted by addition of "bubbles" to signals IN OUT EN This requires two inputs: input and enable EN is to make output Hi-Z or follow input. STANDARD THLNAND GATE Voc Input A Input 8. GND (MOS TECHNOLOGY:- ‘MOS stands for Metal Oxide Semiconductor and + MOS can be classified into three sub-families: PMOS (P-channel) NMOS (N-channel) CMOS (Complementary MOS, most common) ‘+ The following simplified symbols are used to represent MOSFET transistors in most CMOS. The gate of a MOS transistor controls the flow of the current between the drain and the source. The MOS transistor can be viewed as a simple ON/OFF switch Advantages of MOS Digital |Cs:- ‘+ They are simple and inexpensive to fabricate. + Can be used for Higher integration and consume little power. i igital \Cs:- ‘© There is possibility for Static-electricity damage. © They are slower than TTL. technology uses FETs.Gate Termin 4 Source Terminal N-Channel MOSFET Symbol ‘ nMOs ot $ 4 oMos of ECL: EMITTER-COUPLED LOGIC:- Drain Terminal Gate -q| Terminal L Source Terminal P-Channel MOSFET Symbol g=1 { 4 oFF on DANII 4 4 i EN 4 orF t t ‘+ The key to reduce propagation delay in a bipolar logic family is to prevent a gate’s transistors from saturating. It is possible to prevent saturation by using a radically different circuit structure, called ‘current-mode logic (CML) or emitter-coupled logic (ECL) ‘+ Unlike the other logic families in this chapter, ECL does not produce a large voltage swing between the LOW and HIGH levels but it has a small voltage swing, less than a volt, and it internally switches current between two possible paths, depending on the output state. Basic ECL. Circuit The basic idea of current-mode logic is illustrated by the inverter/buffer circuit in the figure. This circuit has both an inverting output (OUT) and a non-inverting output (OUT2). ‘Two transistors are connected as a differential amplifier with a common emitter resistor. The supply voltages for this example are VCC = 5.0, VBB = 4.0, and VEE = 0 V, and the input LOW and HIGH levels are defined to be 3.6 and 4.4 V. This circuit actually produces output LOW and HIGH levels that are 0.6 V higher (4.2 and 5.0 V).nol Vours= 5.0 V (HIGH) INTERFACING OF TTL TO CMOS INTERFACING OF CMOS TO TTL Veo = Yoo ~|emos 2 fe) TTL has less propagation delay than CMOS i.e. TTL is good where high speed is needed, ‘And CMOS 4000 is good for Battery equipment and where speed is not so important. CMOS requires less power than TTL ie. power dissipation and hence power consumption is less for cMos.COUNTER ‘+ Accounter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred. In electronics, counters can be implemented quite easily using register-type circuits. ‘+ There are different types of counters, viz. Asynchronous (ripple) counter ‘Synchronous counter Decade counter Upidown counter Ring counter Johnson counter Cascaded counter Modulus counter © 0000000 Synchronous counter ‘+ Abit synchronous counter using Jk flip-flops is shown in the figure. ‘+ Insynchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel) ‘+ The circuit below is a 4-bit synchronous counter. ‘+ The J and K inputs of FFO are connected to HIGH. FF 1 has its J and K inputs connected to the output of FFO, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FFO and FF1. ‘+ Assimple way of implementing the logic for each bit of an ascending counter (which is what is depicted in the image to the right) is for each bit to toggle when all of the less significant bits are at logic high state ‘+ For example, bit 1 toggles when bit 0 is logic high: bit 2 toggles when both bit 1 and bit 0 are logic high; bit 3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.‘+ Synchronous counters can also be implemented with hardware finite state machines, which are more ‘complex but allow for smoother, more stable transitions. Asynchronous Counter ‘An asynchronous (ripple) counter is a single d-type fip-flop, with its J (data) input fed from its own inverted output. ‘+ This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0), {Count peer —— a] a TEI da, Lope ‘* This counter will increment once for every clock cycle and takes two clock cycles to overfiow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0. This creates a new clock with a 50% duty cycie at exactiy half the frequency of the input clock If this output is then used as the clock signal for a similarly arranged D flip-flop, remembering to invert the output to the input, one will get another 1 bit counter that counts half as fast. These together yield a two-bit counter. ‘+ Additional fip-flops can be added, by always inverting the output to its own input, and using the output from the previous fip-flop as the clock signal. The result is called a ripple counter, which can count to 2" = 1, where n is the number of bits (flip-flop stages) in the counter. ‘+ Ripple counters suffer from unstable outputs as the overflows "ripple" from stage to stage, but they find application as dividers for clock signals. Modulus Counter ‘+ A modulus counter is that which produces an output pulse after a certain number of input pulses is applied ‘+ Inmodulus counter the total count possible is based on the number of stages, ie... digit positions.As synchronous Decade ‘+ Modulus counters are used in digital computers, * A binary modulo-8 counter with three flip-flops, i.e.. three stages, will produce an output pulse, i.e.. display an output one-digit, after eight input puises have been counted, ie., entered or applied. This assumes that the counter started in the zero-condition. ‘+ Adecade counter can count from BCD “0” to BCD “9° ‘+ Adecade counter requires resetting to zero when the output count reaches the decimal value of 10, ie ‘when DCBA = 1010 and this condition is fed back to the reset input. ‘+ Acounter with a count sequence from binary "0000" (BCD = “0") through to “1001” (BCD = “S") is, generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common. ‘+ This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from 0000 until it reaches an output 1001 (decimal 9) ‘+ Both outputs Q, and Q, are now equal to logic “1” and the output from the NAND gate changes state from logic “1” to a logic “0” level and whose output is also connected to the CLEAR ( CLR)) inputs of all the J-K Flip-flops. ‘+ This signal causes all of the Q outputs to be reset back to binary 0000 on the count of 10. Once QA and QD are both equal to logic “0” the output of the NAND gate returns back to a logic level “1” and the counter restarts again from 0000. We now have a decade or Modulo-10 counter.Decade Counter Truth Table ‘© Ina synchronous up-down binary counter the flip-flop in the lowest-order position is complemented with every pulse ‘+ A flip-flop in any other position is complemented with a pulse, provided all the lower-order pulse equal to0. ‘+ Up/Down counter is used to control the direction of the counter through a certain sequence. Up [arpar] Down [oz] 7 44-44 ‘From the sequence table we can observe that For both the UP and DOWN sequences, Qo toggles on each clock pulse. For the UP sequence, Q; changes state on the next clock puise when Qe For the DOWN sequence, Q; changes state on the next clock pulse when For the UP sequence, Qz changes state on the next clock puise when Q For the DOWN sequence, Q, changes state on the next clock pulse when Q 00000‘+ These characteristics are implemented with the AND, OR & NOT logic connected as shown in the logic diagram above.REGISTERS INTRODUCTION: ‘+ The sequential circuits known as register are very important logical block in most of the digital systems. ‘+ Registers are used for storage and transfer of binary information in a digital system. ‘+ A register is mostly used for the purpose of storing and shifting binary data entered into it from an external source and has no characteristics internal sequence of states. ‘+ The storage capacity of a register is defined as the number of bits of digital data, it can store or retain ‘+ These registers are normally used for temporary storage of data. ER REGISTER: ‘+ These are the simplest registers and are used for simply storing a binary word. + These may be controlled by Controlled Butter Register. ‘© _D flip-flops are used for constructing a buffer register or other fip- flop can be used, ‘+ The figure shown below is a 4- bit buffer register. “Lema Lee “Leap FF, FF, FF, CLK . Logic diagram of a 4-bit buffer register. ‘+ The binary word to be stored is applied to the data terminals. ‘+ When the clock pulse is applied, the output word becomes the same as the word applied at the input terminals, i.e. the input word is loaded into the register by the application of clock pulse. ‘+ When the positive clock edge arrives, the stored word becomes: Q4 QS Q2 Q1= X4 X3X2.X1 or a= This circuit is too primitive to be of any use. CONTROLLED BUFFER REGISTER: ‘+ The figure shows a controlled buffer register. tow. 3 x % x BE fe, 9] fe. a] al oa es ( ad ¥ r z “i contaed bier register. + IFCLR goes LOW, all the flip-flops are RESET and the output becomes, Q = 0000. ‘+ When CLR is HIGH, the register is ready for actionCONTROLLED BUFFER REGISTER: LOAD is control input When LOAD is HIGH, the data bits X can reach the D inputs of FFs. At the positive going edge of the next clock pulse, the register is loaded, i. Q4 QS Q2 Q1= X4X3.X2X1 or Q=x When LOAD is LOW, the X bits cannot reach the FFs. At the same time the inverted signal LOAD is HIGH. This forces each flip-flop output to feedback to its data input ‘Therefore data is circulated or retained as each clock pulse arrives, In other words the content register remains unchanged in spite of the clock pulses. Longer buffer registers can built by adding more FFs. A number of FFs connected together such that data may be shifted into and shifted out of them is called a shift register. Data may be shifted into or out of the register either in serial form or in parallel form. ‘There are four basic types of shift registers 1. Serial in, serial out 2. Serial in, parallel out 3. Parallel in, serial out 4, Parallel in , parallel out SERIAL IN, SERIAL OUT SHIFT REGISTER:- This type of shift register accepts data serially, ie., one bit at a time and also outputs data serially. The logic diagram of a four bit serial in, serial out shift register is shown in below figure: In 4 stages i.e, with 4 FFs, the register can store upto 4 bits of data Serial data is applied at the D input of the first FF. The Q output of the first FF is connected to the D input of the second FF, the output of the second FF is connected to the D input of the third FF and the Q output of the third FF is connected to the D input of the fourth FF. The data is outputted from the Q terminal of the last FF. When a serial data is transferred to a register, each new bit is clocked into the first FF at the positive going edge of each clock pulse. The bit that is previously stored by the first FF is transferred to the second FF. The bit that is stored by the second FF is transferred to the third FF, and so on. ‘The bit that was stored by the last FF is shifted out ‘A shift register can also be constructed using J-K FFs or S-R FFs as shown in the figure below.