Unit 4 Notes
Unit 4 Notes
Memory Hierarchy
The memory hierarchy design in a computer system mainly includes different
storage devices. Most of the computers were inbuilt with extra storage to run more
powerfully beyond the main memory capacity. The following memory hierarchy
diagram is a hierarchical pyramid for computer memory. The designing of the
memory hierarchy is divided into two types such as primary (Internal) memory and
secondary (External) memory.
Primary Memory
The primary memory is also known as internal memory, and this is accessible by
the processor straightly. This memory includes main, cache, as well as CPU
registers.
Secondary Memory
The secondary memory is also known as external memory, and this is accessible
by the processor through an input/output module. This memory includes an optical
disk, magnetic disk, and magnetic tape.
Characteristics of Memory Hierarchy
Performance
Previously, the designing of a computer system was done without memory
hierarchy, and the speed gap among the main memory as well as the CPU registers
enhances because of the huge disparity in access time, which will cause the lower
performance of the system. So, the enhancement was mandatory. The enhancement
of this was designed in the memory hierarchy model due to the system’s
performance increase.
Ability
The ability of the memory hierarchy is the total amount of data the memory can
store. Because whenever we shift from top to bottom inside the memory hierarchy,
then the capacity will increase.
Access Time
The access time in the memory hierarchy is the interval of the time among the data
availability as well as request to read or write. Because whenever we shift from top
to bottom inside the memory hierarchy, then the access time will increase
Primary memories-
All programs, files, and data are stored in secondary storage that is larger and
hence has greater access time.
Secondary memory can not be accessed directly by a CPU or processor.
In order, to execute any process operating system loads the process in primary
memory which is smaller and can be accessed directly by the CPU.
Since only those processes are loaded in primary memory which is ready to be
executed, the CPU can access those processes efficiently and this optimizes the
performance of the system.
Read-Only Memory
Any data which need not be altered are stored in ROM. ROM includes those programs
which run on booting of the system (know as a bootstrap
program that initializes OS) along with data like algorithm required by OS. Anything
stored in ROM cannot be altered or changed.
Types of ROM:
ROM can be broadly classified into 4 types based on their behavior:
MROM: Masked ROM are hardwired and pre-programmed ROM. Any content that is once
written cannot be altered anyhow.
PROM: Programmable ROM can be modified once by the user. The user buys a blank
PROM and writes the desired content but once written content cannot be altered.
EPROM: Erasable and Programmable ROM Content can be changed by erasing the initial
content which can be done by exposing EPROM to UV radiation. This exposure to ultra-
violet light dissipates the charge on ROM and content can be rewritten on it.
EEPROM: Electrically Erasable and Programmable ROM Content can be changed by
erasing the initial content which could be easily erased electrically. However, one byte can
be erased at a time instead of deleting in one go. Hence, reprogramming of EEPROM is a
slow process.
Any process in the system which needs to be executed is loaded in RAM which is
processed by the CPU as per Instructions in the program. Like if we click on
applications like Browser, firstly browser code will be loaded by the Operating system
into the RAM after which the CPU will execute and open up the Browser.
Types of RAM:
RAM can be broadly classified into SRAM (Static RAM) and DRAM (Dynamic RAM)
based on their behavior:
DRAM: Dynamic RAM or DRAM needs to periodically refresh in few milliseconds to retain
data. DRAM is made up of capacitors and transistors and electric charge leaks from
capacitors and DRAM needs to be charged periodically. DRAM is widely used in home
PCs and servers as it is cheaper than SRAM.
SRAM: Static RAM or SRAM keeps the data as long as power is supplied to the system.
SRAM uses Sequential circuits like a flip-flop to store a bit and hence need not be
periodically refreshed. SRAM is expensive and hence only used where speed is the utmost
priority.
Secondary Memory
We have read so far, that primary memory is volatile and has limited capacity. So, it is
important to have another form of memory that has a larger storage capacity and from
which data and programs are not lost when the computer is turned off. Such a type of
memory is called secondary memory. In secondary memory, programs and data are
stored. It is also called auxiliary memory. It is different from primary memory as it is
not directly accessible through the CPU and is non-volatile. Secondary or external
storage devices have a much larger storage capacity and the cost of secondary
memory is less as compared to primary memory.
Use of Secondary memory
Secondary memory is used for different purposes but the main purposes of using
secondary memory are:
Permanent storage: As we know that primary memory stores data only when the power
supply is on, it loses data when the power is off. So we need a secondary memory to
stores data permanently even if the power supply is off.
Large Storage: Secondary memory provides large storage space so that we can store
large data like videos, images, audios, files, etc permanently.
Portable: Some secondary devices are removable. So, we can easily store or transfer
data from one computer or device to another.
2n = N
where n is the no. of address lines and N is the total memory in bytes.
There will be 2n words.
2D Memory organization –
In 2D organization, memory is divided in the form of rows and columns(Matrix). Each row
contains a word, now in this memory organization, there is a decoder. A decoder is a
combinational circuit that contains n input lines and 2n output lines. One of the output lines
selects the row by the address contained in the MAR and the word which is represented by that
row gets selected and is either read or written through the data lines.
2.5D Memory organization –
In 2.5D Organization the scenario is the same but we have two different decoders one is a
column decoder and another is a row decoder. Column decoder is used to select the column and a
row decoder is used to select the row. The address from the MAR goes as the decoders’ input.
Decoders will select the respective cell through the bit outline, then the data from that location
will be read or through the bit, inline data will be written at that memory location.
Read and Write Operations –
1. If the select line is in Reading mode then the Word/bit which is represented by the MAR will be
available to the data lines and will get read.
2. If the select line is in write mode then the data from the memory data register (MDR) will be sent to
the respective cell which is addressed by the memory address register (MAR).
3. With the help of the select line, we can select the desired data and we can perform read and write
operations on it.
Cache Memory
is a special very high-speed memory. It is used to speed up and synchronizing with
high-speed CPU. Cache memory is costlier than main memory or disk memory but
economical than CPU registers. Cache memory is an extremely fast memory type that
acts as a buffer between RAM and the CPU. It holds frequently requested data and
instructions so that they are immediately available to the CPU when needed.
Cache memory is used to reduce the average time to access data from the Main
memory. The cache is a smaller and faster memory which stores copies of the data
from frequently used main memory locations. There are various different independent
caches in a CPU, which store instructions and data.
Levels of memory:
Level 1 or Register –
It is a type of memory in which data is stored and accepted that are immediately
stored in CPU. Most commonly used register is accumulator, Program counter,
address register etc.
Level 2 or Cache memory –
It is the fastest memory which has faster access time where data is temporarily
stored for faster access.
Level 3 or Main Memory –
It is memory on which computer works currently. It is small in size and once power
is off data no longer stays in this memory.
Level 4 or Secondary Memory –
It is external memory which is not as fast as main memory but data stays
permanently in this memory.
Cache Performance:
When the processor needs to read or write a location in main memory, it first checks
for a corresponding entry in the cache.
If the processor finds that the memory location is in the cache, a cache hit has
occurred and data is read from cache
If the processor does not find the memory location in the cache, a cache miss has
occurred. For a cache miss, the cache allocates a new entry and copies in data
from main memory, then the request is fulfilled from the contents of the cache.
The performance of cache memory is frequently measured in terms of a quantity
called Hit ratio.
Hit ratio = hit / (hit + miss) = no. of hits/total accesses
We can improve Cache performance using higher cache block size, higher
associativity, reduce miss rate, reduce miss penalty, and reduce the time to hit in the
cache.
Cache Mapping:
There are three different types of mapping used for the purpose of cache memory
which are as follows: Direct mapping, Associative mapping, and Set-Associative
mapping. These are explained below.
1. Direct Mapping –
The simplest technique, known as direct mapping, maps each block of main
memory into only one possible cache line. or
In Direct mapping, assign each memory block to a specific line in the cache. If a
line is previously taken up by a memory block when a new block needs to be
loaded, the old block is trashed. An address space is split into two parts index field
and a tag field. The cache is used to store the tag field whereas the rest is stored in
the main memory. Direct mapping`s performance is directly proportional to the Hit
ratio.
2. i = j modulo m
3. where
4. i=cache line number
5. j= main memory block number
m=number of lines in the cache
Division of Physical Address-
Example-
Example-
Here,
k = 2 suggests that each set contains two cache lines.
Since cache contains 6 lines, so number of sets in the cache = 6 / 2 = 3 sets.
Block ‘j’ of main memory can map to set number (j mod 3) only of the cache.
Within that set, block ‘j’ can map to any cache line that is freely available at that moment.
If all the cache lines are occupied, then one of the existing blocks will have to be replaced.
Problem-01:
Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main memory
is 128 KB. Find-
1. Number of bits in tag
2. Tag directory size
Solution-
Given-
Cache memory size = 16 KB
Block size = Frame size = Line size = 256 bytes
Main memory size = 128 KB
We have,
Size of main memory
= 128 KB
= 217 bytes
Thus, Number of bits in physical address = 17 bits
We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits
Consider a direct mapped cache of size 512 KB with block size 1 KB. There are 7 bits in the tag.
Find-
1. Size of main memory
2. Tag directory size
Solution-
Given-
Cache memory size = 512 KB
Block size = Frame size = Line size = 1 KB
Number of bits in tag = 7 bits
We have,
Block size
= 1 KB
= 210 bytes
Thus, Number of bits in block offset = 10 bits
We have,
Number of bits in physical address = 26 bits
Thus, Size of main memory
= 226 bytes
= 64 MB
Problem-03:
Consider a direct mapped cache with block size 4 KB. The size of main memory is 16 GB and there
are 10 bits in the tag. Find-
1. Size of cache memory
2. Tag directory size
Solution-
Given-
Block size = Frame size = Line size = 4 KB
Size of main memory = 16 GB
Number of bits in tag = 10 bits
We have,
Size of main memory
= 16 GB
= 234 bytes
Thus, Number of bits in physical address = 34 bits
Number of Bits in Block Offset-
We have,
Block size
= 4 KB
= 212 bytes
Thus, Number of bits in block offset = 12 bits
Problem-01:
Consider a fully associative mapped cache of size 16 KB with block size 256 bytes. The size of main
memory is 128 KB. Find-
1. Number of bits in tag
2. Tag directory size
Solution-
Given-
Cache memory size = 16 KB
Block size = Frame size = Line size = 256 bytes
Main memory size = 128 KB
We have,
Size of main memory
= 128 KB
= 217 bytes
Thus, Number of bits in physical address = 17 bits
We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits
Number of Bits in Tag-
Problem-02:
Consider a fully associative mapped cache of size 512 KB with block size 1 KB. There are 17 bits in
the tag. Find-
1. Size of main memory
2. Tag directory size
Solution-
Given-
Cache memory size = 512 KB
Block size = Frame size = Line size = 1 KB
Number of bits in tag = 17 bits
We have,
Block size
= 1 KB
= 210 bytes
Thus, Number of bits in block offset = 10 bits
Number of Bits in Physical Address-
We have,
Number of bits in physical address = 27 bits
Thus, Size of main memory
= 227 bytes
= 128 MB
Problem-03:
Consider a fully associative mapped cache with block size 4 KB. The size of main memory is 16 GB.
Find the number of bits in tag.
Solution-
Given-
Block size = Frame size = Line size = 4 KB
Size of main memory = 16 GB
We have,
Size of main memory
= 16 GB
= 234 bytes
Thus, Number of bits in physical address = 34 bits
We have,
Block size
= 4 KB
= 212 bytes
Thus, Number of bits in block offset = 12 bits
Problem-01:
Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes. The size of
main memory is 128 KB. Find-
1. Number of bits in tag
2. Tag directory size
Solution-
Given-
Set size = 2
Cache memory size = 16 KB
Block size = Frame size = Line size = 256 bytes
Main memory size = 128 KB
We have,
Size of main memory
= 128 KB
= 217 bytes
Thus, Number of bits in physical address = 17 bits
Number of Bits in Block Offset-
We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits
Problem-02:
Consider a 8-way set associative mapped cache of size 512 KB with block size 1 KB. There are 7
bits in the tag. Find-
1. Size of main memory
2. Tag directory size
Solution-
Given-
Set size = 8
Cache memory size = 512 KB
Block size = Frame size = Line size = 1 KB
Number of bits in tag = 7 bits
We have,
Block size
= 1 KB
= 210 bytes
Thus, Number of bits in block offset = 10 bits
Number of Lines in Cache-
We have,
Number of bits in physical address = 23 bits
Thus, Size of main memory
= 223 bytes
= 8 MB
Problem-03:
Consider a 4-way set associative mapped cache with block size 4 KB. The size of main memory is
16 GB and there are 10 bits in the tag. Find-
1. Size of cache memory
2. Tag directory size
Solution-
Given-
Set size = 4
Block size = Frame size = Line size = 4 KB
Main memory size = 16 GB
Number of bits in tag = 10 bits
We have,
Size of main memory
= 16 GB
= 234 bytes
Thus, Number of bits in physical address = 34 bits
We have,
Block size
= 4 KB
= 212 bytes
Thus, Number of bits in block offset = 12 bits
Number of Bits in Set Number-
We have-
Number of bits in set number = 12 bits
Thus, Total number of sets in cache = 212 sets
We have-
Total number of sets in cache = 212 sets
Each set contains 4 lines
Thus,
Total number of lines in cache
= Total number of sets in cache x Number of lines in each set
= 212 x 4 lines
= 214 lines
Virtual Memory
Virtual memory is the separation of logical memory from physical memory.
This separation provides large virtual memory for programmers when only
small physical memory is available.
Virtual memory is used to give programmers the illusion that they have a
very large memory even though the computer has a small main memory. It
makes the task of programming easier because the programmer no longer
needs to worry about the amount of physical memory available.