Introduction to Embedded Systems- EC208

Syllabus

Fundamentals of embedded systems

Embedded systems, examples of embedded system (Washing machine and plant watering
system), components of typical embedded system: Memory, CPU architecture, input-output
devices.

Arduino board and ATMega328P architecture

Overall architecture, general purpose registers, memory, Introduction to embedded C

Input-output (I/O) interfacing

I/O port pins and their functions, alternate or dual functions of I/O ports, I/O port
programming, I/O devices and their interfacing: push button, key, LED, LCD, ADC, sensors,
DAC, motors, and relays.

Timer programming
Timer basics, modes of operations, programming of timers

Interrupt handling
Interrupt vs polling, interrupt service routine, steps in executing an interrupt, interrupts and
their vector locations, external interrupts, interrupt programming

Serial communication
Basics of serial communication, universal synchronous and asynchronous serial receiver and
transmitter (USART): modes of operations, registers, and programming, interrupt based serial
programming

Embedded system architecture

Instruction set architecture, instruction formats, instruction specifications, single-cycle
hardwired control, instruction decoder, sample instructions and program

Laboratory component
Laboratory experiments are conducted using Arduino boards: Interfacing keyboard, LEDs,
LCDs, sensors, ADCs, DACs, motors, and experiments using interrupts and serial
programming

Evaluation scheme
Mid Semester exam: 20%
End Semester Exam: 30%
Quiz (written): 10% (Average of two quizzes)
Assignments: 15% (Application Assignment)
Lab experiments: 25%
What is an embedded system?

 It is a combination of hardware and software designed to perform a specific task.

 It can be used as a part of a large system or it can be an independent system. (The
word ‘embedded’ used as the system is fixed into a larger system)

Every task has its own requirements and embedded system is designed to satisfy the
requirements of a specific task. The embedded system designed for one task cannot be used
for another task.

Is your personal computer an embedded system? No. It can perform many tasks and not
specialized for a specific task. It is called general purpose computing system.

A typical embedded system

An example of an embedded system.

Washing machine

Working of top load washing machine

Components

1. Inner tub: We need to put the cloths in this tub. It has holes for the water.

2. Outer tub: The inner tub is placed inside the outer tub. The outer tub contains the water and
avoids water leaking into other parts.

3. Agitator: It is at the center of the inner tub and it rotates back and forth to wash the cloths.
4. Motor (Not visible in the above diagram): It is used to rotate the inner drum along with the
agitator to wash the cloths.

5. Inlet valve and pipe: This is located near the water inlet and it automatically opens and
closes based on the phase of washing and amount of water required.

6. Water outlet valve and pipe: The dirty water after washing flows through the outlet pipe
and outlet valve is closes and opens based on the phase of washing.

7. Water pump (Not visible): It is used to drain the water from the outer tub.

8. Integrated control panel with user interface: It contains a microcontroller based board with
input-output interface and a control algorithm running in it. Input interfaces include the
keyboard which allows to select the wash type (wash, spin, rinse), cloth type (light, medium,
heavy duty), and washing time setting. The output interfacing consists of LED/LCD displays.

Other parts include different sensors including temperature sensor, water level sensor, used to
control the water inlet and agitator control

Operation of washing machine

3 phases namely wash, spin, rinse

You load the cloths into the inner tub and set the cloth type or timer setting. Also add the
detergent.

1. Wash phase

 The microcontroller opens the inlet valve and the fills the inner tub with the water.
 After the water reaches the desired level based on the settings, inlet valve is closed.
 Motor turns the agitator back and forth resulting in cloths moving up and down to
remove the dirt on the cloths.

2. Spin phase

 Drain the water by opening the outlet valve and close the valve after all the water is
drained.
 Motor rotates the inner drum in one direction at high speed and due to centrifugal
force removes any remaining water.

2. Rinse phase

 Open the inlet valve to add clean water and repeat the wash operation to remove any
remaining detergent.
 Repeat the spin operation to remove the remaining water and cloths are ready to be
taken out.

In wash option all the three phases are carried out. Spin and rinse operations can be done
independently as well. Setting the timer allows to complete the washing in the desired time.
Look at the problem as an embedded system.

Central processing unit Instructions and data

Memory: The instructions to be performed for operating the embedded system are stored in
memory. The data required for carrying out the instructions is also stored in the memory. Eg:
All the sequence of operations to be performed after pressing the ‘wash’ button on the display
panel of washing machine need to be stored in memory.

Input devices: These devices provide the information to the central processing unit to carry
out the instructions. Eg: Keys for the different operations on washing machine, water level
sensor provide the information about the level of water filled in the tub.

Output devices: The central processing unit (based on the information from the input
devices) controls the operations outside the embedded system through output devices. Output
devices are also used to display the information about the operations being carried out. Eg:
Motor used for moving the agitator, pump used for draining the water, Light emitting diodes
(LEDs), liquid crystal displays (LCDs) used to display the washing phase and time
remaining.

System core or central processing unit: It receives the instructions from the memory and
input devices and it controls the output devices to perform the desired operations.

Communication devices: The central processing unit uses the communication devices to
send information to other devices. Eg: A bluetooth communication device can be used to
send the information to user mobile that washing is completed and cloths can be taken from
the washing tub.

Other subsystems or integrated circuits: These systems are additional processing units
used to help the central processing units to perform specific operations in less time.

In this course we will discuss each of the above components in details.

 Memory
The SR latch can be used as a memory element to store one bit of information.

Figure 1: SR latch

The operation of the SR latch shown in Figure 1 can be summarized as

1. If S=1, R=0. The output ̅ of the NOR gate with S as input will be set to 0 irrespective of
the other input. R=0 and ̅ = 0 make as 1. Now if we set S=0, R=0, the output will still
hold the previous output of 1.

2. If S=0, R=1. The output of the NOR gate with R as input will be set to 0 irrespective of
the other input. S=0 and = 0 make ̅ as 1. Now if we set R=0, S=0, the output will still
hold the previous output of 0.

Thus, even after removing the input S or R which changed the output, the previous output is
retained. This holding on to previous value is the memory. To this element either we can
store 0 or 1 based on the value of S and R and hold it for as long as we do not want to change.
Thus, this SR latch can be used as a memory element or memory cell.

A select line is added to allow reading and writing only when a ‘select’ input is high. This
will be required to read a specific memory cell among several memory cells. Also we need to
add control signals to enable reading from a specific memory cell or writing to a specific
memory cell.

The Figure 2a shows how the ‘Select’ and ‘Read/write’ control is included in a memory cell.
In this the RS latch of the Figure 1 is represented a box with R and S as inputs, and Q as
output. The ‘NOT’ gate for the input is added to avoid the undefined state output for inputs
S=R=1. The ‘AND’ gates with ‘Select’ and ‘Read/write’ control enable the memory
operations if set to ‘1’ and disable the memory operations if set to ‘0’

The operation can be summarized in the following table

Select Read/write Memory operation

0 X No change or no operation
1 0 Write to selected memory cell
1 1 Read from selected memory cell
 (a) Logic diagram

(b) Block diagram of the binary (or one bit) memory cell

Figure 2: Memory ‘select’ and ‘read/write’ control logic

The entire memory cell with control signals can be simplified as one bit memory cell as
shown in Figure 2b.

The logical construction of a small RAM with 12 binary memory cells with 4 rows of 3
memory cells each is shown in Figure 3. The number of memory cells in one row constitute
one word of memory. For ease of understanding, the Figure 3 shows one word consisting of
3 memory cells. Generally one word can be one byte (8 memory cells) or two bytes (16
memory cells) or four bytes (32 memory cells). In embedded applications, we read one word
of memory or we write to one word of memory at a time. To enable this, each of the ‘Data
inputs’ is connected to all the cells in one column and all the outputs of one columns are input
to a ‘OR’ gate and one output is obtained for a column. Thus, the 2 x 4 decoder produces
select lines such that one word of the memory is selected for read or write operations. During
write operation the Read/write is at logic ‘0’ and one word of ‘Data inputs’ is written to one
word of memory selected. During read operation Read/write is at logic 1, and outputs of
memory cells in the selected word are read into ‘Data outputs’. During read operations, the
memory cells which are not selected will produce logic 0 output and thus using ‘OR’ gate
will result in the ‘Data outputs’ corresponding to the selected word only.

Figure 3: Logical diagram of 4x3 memory

The 2x4 decoder is called address decoder and produces logic ‘1’ to one of the four words
based on the ‘Address inputs’. The truth table for the decoder is shown in below table

Address inputs Outputs of the decoder

Word 0 Word 1 Word 2 Word 3 Word selected
00 1 0 0 0 Word 0
01 0 1 0 0 Word 1
10 0 0 1 0 Word 2
11 0 0 0 1 Word 3
We can also select one memory cell for read or write operation by using an additional address
decoder for selecting the particular column.

Operation sequence for reading or writing to a word

Word read operation

1. Select the word for reading by setting the ‘Address inputs’ appropriately. Eg: If word 0 to
be read then set ‘Address inputs’ = 0 0.

2. Set the Read/write =1. The ‘Data outputs’ provide the content of word 0.

Word write operation

1. Select the word for writing by setting the ‘Address inputs’ appropriately. Eg: If word 1 to
be written then set ‘Address inputs’ = 0 1.

2. Set the Read/write =0. The ‘Data inputs’ are written to word 1.

General block diagram of the memory unit is shown in Figure 4.

Figure 4: Block diagram of the memory unit

Here, the memory unit includes the address decoder and all the memory cells. The memory
address register is used to hold the address of the memory word to be selected until the
memory is read by the central processing unit. The memory buffer register is used to hold one
word of memory until it is read by the central processing unit. During write operation,
memory buffer register holds the one word of data from the central processing unit until it is
written to the corresponding memory word.

The above memory unit consisting of SR latches is called ‘Static Random access memory’
(SRAM). The word ‘Static’ is used as it holds the data as long as the power is being is
supplied. (Note that all the gates in the SR latch and other controls circuit of memory cell
require power to retain the information). The word ‘Random access’ is used as the memory of
any word can be obtained by providing its address. There are ‘Sequential memory’ in which
the memory words to need to be read in a sequence and to read one word of memory all the
words before that need to read as well.

Basics of register

Register is a collection of edge triggered flip-flops. We can control the writing to all the flip-
flops in a register by using a ‘Load’ control signal and a common clock pulse ‘CP’ as shown
in the Figure 6 for a 4-bit (4 flip-flops) register. The clear signal sets all the flip-flops output
to zero. ‘Load’ signal allows all the 4 inputs to be written to 4 corresponding outputs of the 4
flip-flops in the register.

Figure 6: 4-bit register with load control

Random Access Memory (RAM)

The RAM is used for writing and reading the temporary data (Eg: The variables declared in
the ‘C’ program are stored in the RAM). Thus, the RAM is also called Read/Write memory
or data memory.

There are three types of RAM

1. SRAM: Uses SR latches as the memory cells. Retains data as long as the power is being
supplied. It requires relatively a small amount of time around 10 ns to read one word of
memory. Generally the SRAM cell uses 6 CMOS transistors to store one bit of memory and
thus require relatively more silicon.

2. DRAM (dynamic RAM): It stores the data in the form of charge on capacitor. The
memory cell is shown in Figure 5.

Writing operation: ‘Select’ line makes the transistor a closed switch and connects bit line (is
the data input) to the capacitor. The voltage on the bit line either charges the capacitor for
logic ‘1’ or discharges the capacitor for logic ‘0’

Word line (select)

Figure 5: DRAM memory cell

Reading operation: Initially the bit line capacitor is pre-charged to half of the voltage for
logic 1 (Vcc/2). The select line makes the transistor a closed switch and connects the bit line
to the capacitor. If the data stored was logic ‘1’ then the bit line capacitor starts charging and
the bit line capacitor voltage increases and this increase in voltage is sensed by a sense
amplifier and thus a logic ‘1’ is read. Similarly if the data stored was logic ‘0’ then the bit
line capacitor starts discharging resulting in a decreased voltage at the bit line. This decrease
in voltage is sensed by the sense amplifier and thus a logic ‘0’ is read. As the charge stored
on capacitor changes due to reading and thus reading is a destructive process. To maintain the
data information, the voltage on the capacitor needs to be refreshed regularly.

The DRAM requires one MOSFET and a capacitor and thus requires less silicon. As the
memory need to be refreshed periodically, the read operation requires more time
approximately around 60 ns and thus DRAM reading is relatively slow. It is less expensive
then SRAM. Even though the DRAM does not consume power when the select line is
disabled (logic 0), the sense amplifier and refresh operations require more power. Thus,
DRAM in general consumes more power than SRAM.

3. NVRAM (Non-volatile RAM): Non-volatile RAM is a random access memory with a

battery for providing power to the memory after the external power supply is switched off. It
is used in applications where data needs to be retained even after the power is switched off.
Eg: The system clock information is retained using the NVRAM in desktop computers.

Read only memory (ROM)

This memory holds the memory content even after the power is switched off. This type of
memory is used for storing the instructions or code and thus is called code memory. Unlike
RAM the ROM data is always read. There are several types of ROM.

1. Masked ROM: It uses enhancement or depletion mode MOSFETs with threshold voltage
higher than operating voltage and thus the memory cannot be modified after it is
manufactured. It is programmed at the factory by using masking processing. It is the least
expensive ROM and is used in the final production of embedded systems (after the embedded
system is developed and tested).

2. Programmable ROM or One-time programmable ROM: It is also programmable only

once but this memory can be programmed by the user instead of manufacturer. The memory
consists of wires which can be viewed as fuses with logic 1 represented by fuses not burned
and logic 0 represented by fuses burned. This memory is also used for final production of
embedded system as it is a low cost memory.

3. Erasable Programmable Read Only Memory (EPROM): This ROM can be re-
programmed after erasing the original memory using UV radiation. Thus, this memory is
suitable during development of embedded system as it will allow the change of code.
However, for erasing the memory the EPROM chip needs to be taken out from the circuit
board and erasing using UV radiation takes nearly 20 to 30 minutes. Thus erasing is a time
consuming and tedious process.

4. Electrically Erasable Programmable Read Only Memory (EEPROM): This memory

can be erased using electrical signals in few milliseconds in the circuit board and thus is
suitable for embedded system development. This memory allows modifying specific byte of
the memory.

5. FLASH: It is a variation of EEPROM memory and it is organized as blocks of memory

cells. Thus, any modification requires at least one block of memory to be reprogrammed.
Unlike EEPROM this memory does not allow modifying individual bytes. Due to blockwise
modification, the read and write control signals need to be added only once for the entire
block and thus requires less hardware compared to EEPROM. Flash is the most commonly
used ROM for embedded system development. Flash memory is less expensive than
EEPROM.
 Central processing unit

Address bus

Memory

Central Processing Unit

Program counter

Arithmetic and Logic

Unit (ALU)
Instruction Register

Instruction Decoder Data bus

Register A
Register B
Register C Control and Timing
Generation

Control signal
wires

Figure 7: Central processing unit

Figure 7 shows the block diagram of the central processing unit interfaced with the memory.

The memory contains the instructions to be performed by the central processing unit.

Components of central processing unit

1. Program counter: It holds the address of the next instruction to be executed by the CPU. It
puts the address on the address bus to select a word (corresponding to an instruction) from the
memory. The program counter is automatically incremented to address of instruction after the
current instruction is executed. The program counter is also called as instruction pointer.

2. Register file: These are registers used to store the data temporarily. Registers cane be 8-bit,
16-bit, or 32-bit. Reading and writing to register is very fast compared to reading and writing
from SRAM memory.
3. Arithmetic logic unit: It consists of adders, subtracters, and logic gates to perform
arithmetic operations such as addition, subtraction, multiplication, and logical operations
such as AND, OR, and NOT.

4. Instruction register, instruction decode, and control and timing generation: Every
instruction in the memory has an operation code that decides the operation to be performed
and optionally a data on which the operation needs to be performed. The instruction register
holds the operation code of the instruction being executed. The instruction decoder uses the
operation code in the instruction register as the input and its output helps the control and
timing generation unit to generate appropriate control signals for the operation.

Example demonstrating the operations performed by the CPU.

Assume a CPU with 8-bit data bus, 16 bit address bus (can decode 216 = 16384 memory
words each of 8-bits), and register file with registers A, B, C, D each of 8 bit.

The example sequence of instructions is assumed as

1. Move 21H into register A

2. Add value 42H to register A contents

3. Add 12 H value to register A contents

Every instruction has an operation code (known as opcode) and an optional data byte. For this
example we have assumed the opcodes randomly but the opcodes are fixed by the person
who designs the processor.

Operation opcode data

Move 21H into register A B0H 21H
Add value 42H to register A contents 04H 42H
Add 12 H value to register A contents 04H 12H

Observe that Add operation uses the same opcode in the 2 nd and 3rd instructions.

Assuming the first instruction is available at address 1400H. We can obtain the contents of
the memory locations starting from 1400 H for the above set of instructions as below

Memory address Content Description

1400H B0H Opcode for moving value to register A
1401H 21H Value to be moved
1402H 04H Opcode for adding a value to register A
1403H 42H Value to be added
1404H 04H Opcode for adding a value to register A
1405H 12H Value to be added
1406H F4H Code for halting the execution

The sequence of operations can be described as below

1. CPU program counter set to 1400H and the contents of program counter are put on the 16
bit address bus to select the word at 1400H. CPU sends the read control signal and the opcode
‘B0H’ is put on data bus and brought into instruction register in the CPU. Program counter
automatically incremented to next memory location 1401H.

2. Instruction decoder decodes the opcode ‘B0H’ and comes to know that next byte in the
memory is the data to be copied to register A. The CPU enables the ‘Load’ control signal of
register A and disables all the ‘Load’ signal of all other registers. The next byte in the
memory ‘21H’ is loaded into the register A. Program counter automatically incremented to
next memory location 1402H.

3. CPU fetches the opcode of next instruction at 1402H i.e., 04H into the instruction register.
Now, after decoding the opcode 04H CPU comes to know that next byte of the memory to be
added to register A. Program counter automatically incremented to next memory location
1403H. Once the data in the next memory location 1403H i.e., 42H is available on the data
bus, CPU stores this 42H into a operand or temporary register of ALU. Other operand
register of the ALU is loaded from the register A and CPU sends the control signal to the
ALU to add the two operands. After addition is completed, the CPU copies the result to the
register A by enabling the ‘Load’ signal of the register A. Program counter automatically
incremented to next memory location 1404H.

4. The procedure in the step 3 is repeated to add the contents of register A and the data byte
12H in the memory location 1405H and the result is stored to register A. Program counter
automatically incremented to next memory location 1406H.

5. Once the contents of the 1406H are read and decoded, CPU comes to know that this is an
HALT instruction and it will stop the program counter from incrementing. If the HALT
instruction was not executed then CPU continues to increment program counter and execute
next instructions.

The timing diagram of the instruction to load the register A with value 21 H is shown in
Figure 8 for a microprocessor. Every instruction can be split into many operations called
machine cycles (Eg: Reading opcode of a instruction is one machine cycle, reading one word
of data memory is one machine cycle etc.). Each machine cycle requires several clock cycles
to complete. For the instruction there are two machine cycles, first operation is opcode fetch
and second operation is memory read.
 B0H Data 21H

1400 H 1401 H

Figure 8: Timing diagram for the instruction to load the register A with the immediate data.

The ‘t’ indicates the timing and is measured as the number of clock cycles. Generally clock
frequencies used are in MHz (Eg: 1 MHz frequency results in time period of 1 microsecond).
The sequence of operations is described below

1. t1: In this clock cycle, the program counter puts the address on the address bus. Program
counter is automatically incremented to next instruction.

2. t2 and t3: In this clock cycle, read control signal (it is active low signal means memory
reading happens if RD =0) is set to 0 and the memory read is enabled. It takes two clock
cycles t2 and t3 to read the operation code from memory for the instruction.

3. t4: In this clock cycle read control signal is disabled. The opcode (B0H) read from the
memory is decoded by the instruction decoder and CPU comes to know that next byte in the
memory needs to be read into the register A.

4. t5: In this clock cycle, next operation (memory read machine cycle) starts. To begin with
program counter puts the address on the address bus.

5. t6 and t7: In this clock cycle, read control signal is set to 0 and the memory read is enabled.
It takes two clock cycles t6 and t7 to read the data 21H from memory.

Observe that one instruction takes two operations (or machine cycles) and 7 clock cycles. If
we use 1 MHz clock frequency then we need 7 clock periods = 7 microseconds to execute
this one instruction. Thus, timing diagrams helps us to understand the time taken by the CPU
to execute the instruction.
Microprocessor vs Microcontroller

Address bus

Memory

Central Processing Unit

I/O Program counter

devices
Arithmetic and
Logic Unit (ALU)
Instruction Register
Timers
Instruction Decoder Data bus

Register A
Interrupt Register B
modules Register C Control and Timing
Generation

Control signal
wires

Communication
devices

Figure 9: Microprocessor vs microcontroller

Input devices such as sensors, keys etc. and output devices such as motors, pumps, and
display devices need to be interfaced with the CPU to develop an embedded system. To
interface the input/output devices (I/O devices) we need buffer registers to hold the input and
output values before it is read by the processor or it is used by the output devices. Thus these
registers and additional functionalities are required to interface I/O devices.

To measure time we can execute some instructions (without any specific purpose or
operation) repeatedly until the required numbers of clock cycles are elapsed. This execution
of instructions keep the CPU from executing any other useful instruction as CPU can execute
only one instruction at a time. To avoid this, special timer units can be used which measure
the time and inform the CPU after the set time duration is elapsed.
To prioritize the operations interrupt modules are required. The communication devices are
required to communicate with other devices.

The central processing unit consisting of ALU, general purpose registers, instruction decoder,
and control and timing generation module without any peripherals (such as memory, I/O
devices, timers, interrupt modules and communication devices) is called microprocessor.
Microprocessor requires peripheral devices for it to be used in any application.
Microprocessor are used for general purpose applications. If microprocessor along with all
the required peripherals integrated into one chip then it is called a microcontroller.
Microcontroller alone can be used in specific applications without any additional peripherals.

Harvard vs Von-Neuman architecture

If the data and code (instructions or program) are stored in the memory, the instruction needs
to be fetched first and data needs to be fetched after the instruction is fetched. This
architecture of common code (program) and data memory with common address and data bus
is known as Von_neuman architecture. In this architecture, the CPU will be idle as long as
the data is not fetched.

To utility of the CPU can be increased if the code and data are stored in memory. This
architecture with separate code and data memory is known as Harvard architecture. It allows
fetching the next instruction while the current instruction is executed and thus results in faster
execution. However, as there are two memories, two separate buses, separate control signals,
the amount of hardware required also increases.

Von-Neuman Architecture Harvard Architecture

Figure 10: Harvard vs Von-Neman Architecture

Difference between Harvard vs Von-Neuman architecture

Harvard architecture Von-Neuman architecture

Separate buses for separate code and data Single shared bus and memory
memory
High cost due to separate bus, memory, and Cheaper cost due to shared bus and memory
control signals
Pipelining possible and results in faster Slower execution (pipelining is possible but
execution slow due to data and code memory overlap)
As the code and data memory are separate, As the code and data memory share the
code memory will never be corrupted during memory, code memory can be corrupted
program execution during program execution if we write the
data to an address where code is written.
Introduction to ATmega328P microcontroller

In this course we will be using the ATmega328P microcontroller to learn about designing an
embedded system.

Features of ATmega328P

It uses RISC architecture with 131 instructions.

The features are summarized in the below table

The microcontroller has an inbuilt flash memory of 32 kb (kilo bytes). The name 32 in
ATmega328P is due to the 32 kb of flash memory. We will discuss each of these features
during the course. The microcontroller has 2 kb of SRAM as data memory and 1 kb of
EEPROM for storing data.

ATmega328P with 28 pin package is used in Arduino board. The pin diagram is shown in
Figure 11. It shows that there are 3 ports: Port B (8 pins: PB7 –PB0), Port C (7 pins: PC6-
PC0), PORT D (8 pins: PD7 –PD0). These port pins can be used to connect input or output
devices. Several of these pins have additional functionalities. The addition functionalities are
shown using ‘/’ in the pin diagram. We will discuss these additional features in the course.

Other than these 23 pins, there is one pin for providing the supply voltage (VCC) and two
points for ground point (GND). AVCC is the supply voltage pin for ADC (Analog to digital
converter) and AREF is the reference voltage for ADC converter.
 Figure 11: Pin diagram of the 28 pin ATmega328P

Crystal oscillator and the clock frequency for the microcontroller

The ATmega328P is an independent processing unit which can be used in many applications
without the need for any peripherals. The ATmega328P has an internal (inbuilt) RC oscillator
which provides a clock of approximately 8 MHz. A crystal oscillator can also be connected
external to the microcontroller to provide a clock frequency of maximum 16 MHz. The pins
XTAL1 (PB6, pin 9) is the input and XTAL2 (PB7, pin 10) is the output. The crystal
oscillator is connected as shown in Figure 12.

Figure 12 Crystal oscillator connections

The capacitor C1 and C2 values in the range 12 to 22 pF can be used. We can choose the
value of capacitor which provides clock with less noise by looking at the clock signal at
XTAL2. Note that we can use clock frequency lower than 16 MHz also.

A simplified block diagram of the microcontroller is shown in Figure 13. The microcontroller
uses Harvard architecture with separate code and data memory with separate buses. There are
32 general purpose registers and an ALU to perform arithmetic and logical operations. It has
a program counter, instruction register, and instruction decoder. It has several peripherals
which interact with the processing unit through data bus.
 Figure 13: Simplified block diagram of ATmega328P

Data memory map of the ATmega328P

2048 x 8

Figure 14: Data memory map of ATmega328P

The first 32 bytes of the data memory are 32 general purpose registers. These registers can be
accessed using their memory address of 0x0000 to 0x001F. The 64 I/O registers are the
registers used for configuring the special functions of the microcontroller (Eg: A DDR
register is used to configure a pin as input or output). These I/O registers can be accessed
using their memory address of 0x0020 to 0x005F. The 160 Ext I/O registers are not used in
the microcontroller ATmega328P and they are reserved for future extension/upgrading of the
microcontroller. The SRAM of 2 kb (2048 words each of 1 byte) has the address range from
0x0100 to 0x08FF.
Program memory map of ATmega328P

Figure 15: Flash/code memory map of ATmega328P

The ATmega328P contains 32 kb of flash memory 0x0000 to 0x3FFF) to store the code or
program. Since all the instructions in the microcontroller are either 16 bit or 32 bit, the flash
memory is organized as 16 k words with each word of 16 bits (32 k x 8 bits = 32x1024x8 bits
= 262144 bits => 16 k x 16 bits = 16x1024x16 = 262144 bits. Since, most of the instructions
are 16 bit wide, the flash memory word has 16 bits as it helps to fetch one instruction in one
clock cycle. If we choose 8 bits in the flash memory word then fetching one instruction from
memory requires two clock cycles and additional hardware to decode it. To access 16 k
memory space 14 bits of program counter is used (Address bus is 14 bits wide = 2 14=
24x1024 = 16 k words memory space). The microcontroller has a self-programmable feature
i.e., using the communication interface the microcontroller can itself write the user code into
flash memory. The flash memory is organized into two sections: Application section (used
for storing the user code) and boot loader section (code in this section is used for self-
programming the microcontroller). (Note: Self-programming details will be discussed at the
end of the course if time permits)

Instruction execution timing

The timing diagram of the parallel instruction execution is shown in Figure 16. The clk CPU is
the clock source of the microcontroller (obtained using internal or external oscillator). After
the power up or start of the microcontroller, first instruction is fetched in the first clock cycle.
In the second clock cycle, first instruction is executed and simultaneously the second
instruction is fetched as the ATmega328P uses Harvard architecture. Similarly, in the third
clock cycle, the second instruction is executed and simultaneously the third instruction is
fetched. Thus, we can see that after one cycle delay in executing the first instruction, every
instruction is executed in one clock cycle due to the parallel execution and fetching
mechanism. This pipelining of execution and fetching is possible due to Harvard architecture
and additional hardware. Thus, approximately in one second 16 million instructions are
executed (ignoring the first cycle delay) if clock frequency is 16 MHz. However, some
instructions of the ATmega328P require two clock cycle to execute.
The Figure 17 shows the execution of the instruction in one clock cycle. It can be seen that
fetching the operand for the ALU operation, ALU operation, and storing the results back to
register, are completed in one cycle sequentially. Thus, the time required for executing one

Figure 16: Parallel instruction fetches and instruction execution

instruction controls the minimum time period or the maximum clock frequency of the
microcontroller can support. If the clock period reduced below this period then instruction
execution cannot be completed in one clock cycle.

Figure 17: Instruction execution in one clock cycle

The reading and writing to the SRAM (2 kb from 0x100 to 0x08FF) requires two clock
cycles. The timing diagram is shown in Figure 18. In the first clock cycle (of the instruction),
the address of the SRAM is computed and in the second clock cycle the data is read or
written from the SRAM. Thus, any instruction which require reading from SRAM or writing
to SRAM will take 2 clock cycles to execute.
Figure 18: SRAM access timing diagram
I/O (Input/Output) Port Programming

I/O ports help to interface the input/output devices with the central processing unit. The
ATmega328P has 3 I/O ports PORT B (8 pins), PORT C (7 pins), and PORTD (8 pins).
These pins can be used to connect I/O devices. The pins can be configured to input or output.
Every port is associated with 3 I/O (or special function) registers: DDR (Data direction
register), PORT (data register or for holding the output), PIN (port input register). These
registers are 8-bit register corresponding to 8 pins and thus the flip-flop in these registers
corresponds to one pin. The flip-flop of these registers are represented as PORTxn, DDRxn,
and PINxn, where x represents the PORT (B, C, or D) and n represents the bit number. Eg:
PORTB3 represents the PORT flip-flop for bit 3 of the PORT B. The I/O port logical
diagram is shown in Figure 19.

Figure 19: I/O port diagram of ATmega328P

The DDR is used to configure the pin as input or output.

If the Q output of the DDRxn is set to logic 0, then the tristate buffer disconnects the
connection between the Q output of the PORTxn and the pin Pxn (Note: Except Pxn
everything else in the diagram is inside the ATmega328P). Thus, we cannot control the status
of the pin. However, the pin status can be read into the PINxn register through the latch and
an external input device can change the status of the pin. Thus, the pin is configured as an
input port when the DDRxn is set to zero. The additional latch is used to avoid the problem of
metastability of the PINxn register. (Metastatbility: If the input to an edge triggered flip-flop
is not maintained for appropriate set-up time before the edge and hold time after the edge,
then the output of the flipflop oscillates between logic 1 and 0. This problem is called
metastability). Since the latch is level triggered, the output of the latch and the input of the
PINxn is not changed during the negative clock cycle. Thus, the input of PINxn is
maintained constant for at least the 50% of the clock cycle and thus avoids the problem of
metastability.

Note: A tristate buffer connects the input to output if its enable signal (line at the middle of triangle
symbol) is 1. If the enable signal is 0, then the input is completely isolated from the output. This will
avoid any current from flowing backwards to the input. Tristate means 3 states: logic 1, logic 0, high
impedance (no connection between input and output).

If the Q output of the DDRxn is set to logic 1, then the tristate buffer connects the Q output of
the PORTxn and the pin Pxn. Thus, we can control the status of the pin by changing the
PORTXn bit and can control the output device connected to this pin configuring the pin as an
output port. Note that the pin status can still be read into the PINxn register through the latch.

Writing to the I/O registers DDRxn and PORTxn

The DDRxn register can be set to logic 1 or logic 0 using the ‘OUT DDRxn, Rr’ instruction.
The 8 bits of Rr registers are individually set to logic 1 or 0 as required by the programmer.
When this instruction is executed, the data in the Rr is put onto the data bus connected to the
input of the DDRxn register and the WDx is set to 1, and the data on the data bus is copied to
the output of the DDRxn register. Similarly, the PORTxn register is set to 1 or 0 by using the
OUT instruction (the instruction using PORTxn sets the WRx to 1).

Reading from I/O registers DDRxn, PORTxn, and PINxn register

The instruction ‘IN Rd, DDRxn’ reads the contents of the DDRxn register to the Rd register.
When this instruction is executed the output of the DDRxn register is copied to the data bus
by setting the RDx to 1. Similarly we can read the PORTxn (instruction sets the RRx to 1)
and PINxn (instruction sets the RPx to 1) register using IN instruction.

Need for pull-up resistor

Assume a switch connected to a pin of the ATmega328P microcontroller as shown in the

Figure 20 a). When the switch is closed the input pin is at logic low and can be read into
PINxn register. When the switch is open, the input pin is floating and is not at either logic 0
or logic 1. However, due to external noise this pin can oscillate between logic 1 and logic 0.
To avoid this we can connect the resistor (connected to the pin at one end and connected to
the VCC at other end) as shown in Figure 20b. This resistor is called pull-up resistor and
keeps the pin fixed to VCC if the switch is open.

ATmega328P ATmega328P

Figure 20: a) Floating input pin b) Pull-up resistor

The pull-up resistor can be connected external to the microcontroller as shown in Figure 20b
or many microcontrollers have internal pull-up resistors. The ATmega328P microcontroller
has an internal pull-up resistor (PMOS transistor acts as resistor if the input to it is logic 0
otherwise transistor acts as open circuit) and the pull-up resistor is enabled according to the
output of the 3 input AND gate shown in the Figure 19. The ‘NOT’ output is 0 if the AND
gate output is 1 and a 0 at the input of the PMOS transistor makes the transistor to behave as
a resistor. The pullup resistor is enabled if following conditions are satisfied.

1. PUD bit in the MCUCR (microcontroller control register) register is set to 0. If this PUD
bit is set to 0 then it enable PUD of all the pins in the microcontroller and setting it logic 1
disables pullup for all the pins in the microntroller. Thus, it helps to disable all the pullups of
all the ports in the microcontroller.

2. DDRxn register should be at logic 0 as the pullup is enabled only if the pin is configured as
input. Pullup is disabled if the pin is configured as output.

3. PORTxn register output should be at logic 1 to enable the pullup resistor. Thus, PORTxn
status can be changed if we want to disable or enable the pullup of the one pin. Thus, even
though the pullup can be enabled for all the pins using PUD, the enabling or disabling the
pullup resistor of a specific pin is controlled by the output of the PORTxn register.

Toggling the PORTxn register output

To toggle the PORTxn register output, we can read the current status using IN instruction and
then the register bit is set to opposite to the current status using OUT instruction. This
operation can also be done by writing logic 1 to the PINxn register using the OUT
instruction. The logic 1 at the data bus and the WPx set by the OUT instruction selects the
inverted logic of current output as the input to the PORTxn register and thus the status of the
PORTxn register is toggled (means set to a status opposite to the previous state).
Sleep mode functionality

If sleep mode signal is at logic 0, the pin status is read into the PINxn register. But, if the
sleep mode signal is at logic 1, then the NMOS transistor input is at logic 1 and it connects
the input of the latch to ground (logic 0). Thus, during the sleep mode, the PINxn register is
set to logic 0.

Timing diagram during the reading the pin

Figure 21: Timing diagram during reading the pin status to PINxn register

Figure 21 shows the timing diagram during reading the pin status to PINxn register. The latch
before the PINxn register introduces a delay between the change in pin status and the
corresponding change in the PINxn register (output Q). The ‘SYNC LATCH’ shows the
output of the latch. It can be seen that the output of the latch is changed at the beginning of
the positive level of the 2nd clock cycle. The external input connected to input of the latch
might have changed any time after the negative edge of the first clock cycle. The PINxn
register value is changed at the positive edge of the 3 rd clock cycle. The delay between the pin
status (input to the latch) and the change in the PINxn value can be varying based on when
the pin status was changed. The maximum delay is 1.5 clock cycle (when the pin status
changes just after the negative edge of the first clock cycle) and minimum delay is 0.5 clock
cycle (when the pin status changes just before the negative edge of the 2 nd clock cycle).

Alternate function of the PORT pins

Most of the port pins in ATmega328P have alternate functions such as PORTC pins are used
for Analog-to-Digital converter functionality, PORTD pins are used for serial
communication, for crystal oscillator connection, for interrupts. These alternate
functionalities are implemented using the Multiplexer at appropriate positions as shown in
Figure 22. A brief description for overriding the pull-up functionality is given below in table.
We can discuss details later in the course.
Figure 22: Implementation of alternate functionalities of the port pins
Let’s try a simple experiment to interface a switch to the Arduino board. To verify the
interface is working correctly turn ON the LED for some time duration (Eg: 2 secs) if the key
is pressed.

28 pins of ATmega 328 are connected to different pins of Arduino board . The pinout
mapping between Arduino and ATMega328p is shown in Figure 23.

Figure 23: Pin mapping between ATmega328 and Arduino board

Let’s connect switch to pin PD7 of PORTD register and use the LED connected to pin PB5 of
PORTB as output. We have to configure the pin D7 as input with pullup enabled. Note that
D7 (pin 13) of ATmega328 is connected to Pin 7 of Arduino and PB5 (pin 19) of
ATmega328 is connected to Pin 13 of Arduino.

The diagram Figure 24 is as below (note the LED is already connected to pin13 of Arduino
board).

You can see that bit 4 of this register is PUD (Pullup enable signal) which needs to set to 0 to
enable the pullup for the input. Setting this bit to 0 enables all the pins in the microcontroller
but there are two other inputs to enable the pullup of the port pin. Thus we need to set the
corresponding DDRx to 0 and PORTx to 1 to enable the pullup for that pin. Here in this
example we set the bit 7 of DDRD to 0 and bit 7 of PORTD to 1 to enable the pullup of the
pin7 of PORTD. To make the PB5 as output port we set the bit 5 DDRB to 1. Initially to
keep the LED off, the PORTB bit 5 PB5 is set to zero.

Gnd

Figure 24: Example of connecting a switch to the Arduino board

void setup() {

MCUCR = MCUCR & 0b11101111; Enable the pullup for all pins

DDRD = DDRD & 0b01111111; Make PD7 as input

PORTD = PORTD | 0b10000000; Enable the pullup for PD7 by setting D7 as 1

DDRB = DDRB | 0b00100000; Make the PB5 as output

PORTB = PORTB & 0b11011111; Initially keep the LED off

void loop() {

byte temp;

temp = PIND; Read the status of all the pins of PORTD

temp = temp & 0b10000000; Get the status of PD7

// if the PD7 is zero => temp == 0 => Switch is closed

 if(temp == 0)

PORTB = PORTB | 0b00100000; Turn ON the LED

delay(2000); wait for 2 secs

PORTB = PORTB & 0b11011111; Turn off the LED

Interfacing a 4x4 keyboard to the microcontroller

We can connect one switch to one pin of the microcontroller. Thus, if we want to connect a
keyboard with 16 keys (switches) to the microcontroller then we need 16 pins of the
microcontroller. However, using keyboards in the form of a matrix we can reduce the number
of pins required (Eg: we can interface 16 keys using 4x4 matrix keyboard using only 8 pins
of the microcontroller). The interfacing of the 4x4 matrix keyboard using 8 microcontroller
pins is shown in Figure 25. In this arrangement, 16 keys are arranged in the form of matrix
with 4 rows and 4 columns.

Procedure for detecting the single key press

1. Configure all the pins corresponding rows as output ports and the all the pins
corresponding to the columns as input ports.

2. Set all the rows pins to logic 0 (pin is grounded internally) and read all the status of the
column pins.

3. If none of the key is pressed, then the all the column pins status will be at logic 1 (VCC). If
any key is pressed, then the switch connects the corresponding row and column lines. Thus, if
a key is pressed then the status of the corresponding column changes to logic 0 (gnd) as the
row pin is at logic 0. However, the column pin status changes to logic 0 for any of the key
pressed in the corresponding column. Thus, we do not know the row of the key being
pressed.

4. To obtain the row of the key pressed, we set each of the row to logic 0 and remaining rows
to logic 1 sequentially (1 st setting: Rows = 0111, 2nd setting: Rows =1011, 3rd setting: Rows =
1101, 4th setting: Rows=1110). In this sequence, the column status changes to logic 0 only if
the corresponding row is set to 0. Thus, we can find the row of the key pressed.

Steps 2, 3, and 4 are carried out in an infinite loop to detect any key press conitnuosly.
Note that to avoid the short circuit of VCC and Ground, we connect a pull up resistor to the
column pins as shown in the Figure 25. In case of ATmega328P, we can configure the
column pins as input with pullup instead of connecting the resistors.

Figure 25: Matrix keyboard interfacing

Note: Do not use the matrix keyboard for detecting the two or more keys pressed
simultaneously as it may lead to short circuit between VCC and ground.

Key debouncing

Sometimes due to noise or other reasons the key seems to be pressed even though the key is
not pressed intentionally. To avoid this, once a key press is detected the status of the key is
checked again after a small amount of time (called as debounce time) and a valid key press is
detected only if the key status has not changed compared to the status before the debounce
time. Generally a duration of 20–50 ms is used for debounce time.

Light emitting diode (LED)

LED emits light when it is forward biased and current flows through it. The LED has an
anode and cathode, and to forward bias the LED anode should be connected to VCC and
cathode should be connected to ground.

Interfacing LED to the microcontroller

LED is an output device and it can be connected to any port of microcontroller that is
configured as output port. Every LED has a maximum current that can flow through it
without damaging it. Typically this is 20 mA. To limit the current through the LED, a current
limiting resistor is connected in series with the LED as shown in the Figure 26.
 ATmega328P

PB7

Figure 26: LED interfacing

In the above circuit, when the port pin PB7 is set to logic 1, the LED is forward biased and
current flows through the LED and LED glows. During forward bias, a voltage drop of
typically 2V occurs across the LED. The resistor R can be calculated to limit the current
through the LED as below

( )

Similar to the current limiting capacity of LED, there is a limit for current sourced by a
microcontroller pin (in other words there is a limit for current flowing from the port pin as the
current flows from VCC to Ground). The current limiting resistor should be selected by
considering both these conditions.

The LED can also be connected as in Figure 26 (b)

ATmega328P

PB7

Figure 26 (b): LED interfacing

In the above configuration, LED is forward biased if the PB7 is set to logic 0. In this case
current flows into the microcontroller pin and the resistor value should be chosen considering
the maximum current that can flow into the microcontroller and the maximum current than
can flow through the LED.

Seven segment display

It is an output device used to display numbers and some alphabets. It consists of 7 segments
(A, B, C, D, E, F, G) made using 7 LEDs and arranged as shown below. There is one
additional segment to display the decimal point (DP).

To interface the 7-segment display, LEDs of each segment need to be connected to one port
pin (configured as output) of the ATmega328P. Thus, to interface a 7-segment display we
require 8 pins of the ATmega328P. To display a specific character corresponding LEDs need
to be turned ON. For example, for displaying the number 4, the segments F, G, B and C need
to be turned ON. For displaying 3, the segments A, B, C, D, and G need to be turned ON.

The seven segment displays either have common cathode or common anode as show below.

The current through each segment can be limited by connecting a current limiting resistor to
the anode or cathode of each segment.

Note: We need to add the current limiting resistor for every pin of the seven-segments
connected to the ATMega328P.
LCD (Liquid Crystal Display)

The molecules in the liquid crystals are twisted by default. When electric current is passed
through these crystals, the molecules get untwisted. This property of liquid crystal is used to
block some part of the light (emitted by a backlight) on the display and a character can be
displayed by blocking the appropriate segments of the character. Unlike LEDs, liquid crystals
do not emit light of their own and thus a backlight (florescent tubes) is used as light source.

LCD device details

LCD devices come with a built-in microcontroller to help the process of interfacing to
microcontroller easy. The LCD available in Lab can display 2 lines of 16 characters each. For
each character 5 x 8 segments are used to control the display. The pin configuration and
default connections of the LCD device are given below.

The voltage at the pin V0 is used to control the contrast of the LCD display. (To control the
contrast connect 1st terminal of potentiometer to VDD (+5 v), 2nd or middle terminal to V0,
and 3rd terminal to ground. Rotating the potentiometer will help you to adjust the contrast)

DB0-DB7 pins

These pins are used to send the ASCII code of the character to be displayed. Same pins are
also used to send commands to the LCD (Eg: Clear the display, move the cursor to the home,
blink the cursor, etc.). The data and commands can be sent using all 8 pins of the LCD or
using only four pins. Using four pins helps to reduce the number of pins of the
microcontroller (ATmega328P) to be used for LCD display.
RS pin: Register select

There are two registers in the LCD device. RS pin is used to select the register.

RS =0 => Command register is selected. In this state, data sent on the data pins DB0-DB7 is
considered as a command by the LCD device.

RS=1=> Data register is selected. In this state, data sent on the data pins DB0-DB7 is
considered as the ASCII code of the character to be displayed by the LCD device.

R/W

R/W = 0 => Used to write/send data or command to the LCD device.

R/W = 1 => Used to read data from the LCD device.

E (Enable signal)

When a high-to-low pulse is applied to this pin, the data on the data pins is stored onto a latch
by the LCD device and used to display the character or controlling the display. Minimum
width of the Enable signal pulse is 450 ns. We choose 100 μs which is larger than 450 ns.

How to send the commands to the LCD device?

(Note: After power up of the LCD device, we need to wait for 15 ms before sending any
command. In your code for the experiment, please add this 15 ms delay at the beginning
before any initialization.)

1. Initialize the LCD: Send the commands to configure the LCD for 8 or 4 data pins.

2. Send the commands: Send the commands to control the display if any. RS=0, R/W=0, put
the command on data pins. We need to send the enable pulse for 100 μs. After sending each
command we need to wait for 5 ms. Otherwise we can check a busy-flag sent by the LCD
device to indicate whether the operation is completed or not. Most of the commands are
executed within 100 μs but some of them require 5 ms. Thus, we can choose a delay of 5 ms
to avoid changing the delay every time we send a command.

3. Send the data: Send the data to be displayed on the LCD. RS=1 (this is the main change
for sending the data), R/W=0, put the data on data pins. We need to send the enable pulse
for 100 μs. After sending each data character we need to wait for 100 μs.)
List of commands and their codes

Interfacing LCD to microcontroller

Connect I/O pins of the microcontroller to the E, RS, and R/W pins of the LCD. Connect
either 4 or 8 pins of the microcontroller to the data pins DB0-DB7.

Initialization for using 8-pin

Send the commands 0x38 (5x7 dot matrix, 8-bit), 0x0E (display on, cursor blinking), 0x01
(clear display). We need to send enable pulse after putting the data on data pins and setting
the RS and RW pins. After this initialization, send the 8-bit ASCII code on data pins to
display the character. Wait for 5 ms after every command is sent allowing the LCD device to
complete the execution of the command.
Initialization for using 4-pin

During 4-bit configuration, high nibble (4 bits) of 8-bit data is sent first followed by low
nibble. Send the commands 0x33, 0x32,0x28 (5x7 dot matrix, 4-bit), 0x0E, 0x01. These
commands to initialize the LCD to 4-bit mode require 5 ms delay. We need to send enable
pulse after putting the data on data pins and setting the RS and RW pins. After initialization,
send the 8-bit ASCII code on data pins with high nibble first followed by low nibble.