Verilog-XL

CS6710 Tool Suite

Synthesis and Place & Route
Behavioral
Synopsys
Verilog Design Compiler
Synopsys design compiler Structural
Cadence Verilog
Your SOC
Library Encounter
Cadence Encounter Digital
Circuit Verilog-XL
Implementation System (EDI) Layout CSI

Cadence LVS Cadence

CCAR
Virtuoso Composer
AutoRouter Layout-XL
Layout Schematic

Design Compiler Synthesis Process: Design Compiler

 Synthesis of behavioral to structural 1. Define synthesis environment

 Three ways to go: 2. Read in your behavioral RTL Verilog
– Type commands to the design compiler shell 3. Set synthesis constraints (speed, area, etc.)
Start with syn-dc and start typing
4. Compile (synthesize) the design
– Write a script
Use syn-script.tcl as a starting point 5. Evaluate results (timing, area, power, ...)
– Use the Design Vision GUI
Friendly menus and graphics...

Design Compiler – Basic Flow Design Compiler – Basic Flow

1. Define environment 4. Compile the design
– target libraries – your cell library – compile or compile_ultra
– synthetic libraries – DesignWare libraries – Does the actual synthesis
– link libraries – libraries to link against 5. Write out the results
2. Read in your behavioral RTL Verilog – Make sure to change_names
– Usually split into analyze and elaborate – Write out structural verilog, report, ddc, sdc
3. Set constraints files
– Timing – define clock, loads, etc.
 Beh2str – the simplest script addsub.v
> beh2str moudle addsub (a, b, addnsub, result);
parameter SIZE = 8; // default word size is 8
beh2str – Synthesizes a verilog RTL code to a
input [SIZE-1:0] a, b; // two SIZE-bit inputs
structural code based on the synopsys
input addnsub; // control bit: 1 = add, 0 = sub
technology library specified
output reg [SIZE:0] result; // SIZE+1 bit result
Usage: beh2str <input.v> <output.v> <libfile>
always @(a, b, addnsub) begin
if (addnsub) result = a + b;
beh2str addsub.v addsub_dc.v Lib5710_00.db
else result = a – b;
end
Results in addsub_dc.v, addsub_dc.v.rep endmodule

addsub_dc.v addsub_dc.v.rep

beh2str – the simplest script! .synopsys_dc.setup

#!/bin/tcsh set SynopsysInstall [getenv "SYNOPSYS"]
setenv SYNLOCAL /uusoc/facility/cad_common/local/class/6710/F13/synopsys
#set the path of dc shell script file
set search_path [list . \
setenv SCRIPTFILE ${SYNLOCAL}/beh2str.tcl
[format "%s%s" $SynopsysInstall /libraries/syn] \
# store the arguments
setenv INFILE $1
[format "%s%s" $SynopsysInstall /dw/sim_ver] \
setenv OUTFILE $2 ]
setenv LIBFILE $3 define_design_lib WORK -path ./WORK
# setup to run synopsys design compiler set synthetic_library [list dw_foundation.sldb]
source /uusoc/facility/cad_common/local/setups/F13/setup-synopsys set synlib_wait_for_design_license [list "DesignWare-Foundation"]
# run (very simple) design compiler synthesis set link_library [concat [concat "*" $target_library] $synthetic_library]
dc_shell-xg-t -f $SCRIPTFILE set symbol_library [list generic.sdb]
 beh2str – the actual script What beh2str leaves out...
# beh2str script
set target_library [list [getenv "LIBFILE"]]  Timing!
set link_library [concat [concat "*" $target_library]
$synthetic_library]
 No clock defined so no target speed
read_file -f verilog [getenv "INFILE"]  No wire load model so not as placement
#/* This command will fix the problem of having */ constrained
#/* assign statements left in your structural file. */  No input drive defined so assume infinite drive
set_fix_multiple_port_nets -all -buffer_constants
compile -ungroup_all  No output load define so assume something
check_design
#/* always do change_names before write... */
redirect change_names { change_names -rules verilog
-hierarchy -verbose }
write -f verilog -output [getenv "OUTFILE"]
quit

syn-script.tcl syn-script.tcl
#/* below are parameters that you will want to set for each design */
 /uusoc/facility/cad_common/local/class/6710/F13/synopsys #/* list of all HDL files in the design */
set myFiles [list !!all-your-structural-Verilog-files!! ]
#/* search path should include directories with memory .db files */ set fileFormat verilog ;# verilog or VHDL
#/* as well as the standard cells */ set basename !!basename!! ;# Name of top-level module
set myClk !!clk!! ;# The name of your clock
set search_path [list . \
set virtual 0 ;# 1 if virtual clock, 0 if real clock
[format "%s%s" SynopsysInstall /libraries/syn] \ #/* compiler switches... */
[format "%s%s" SynopsysInstall /dw/sim_ver] \ set useUltra 1 ;# 1 for compile_ultra, 0 for compile
!!your-library-path-goes-here!!] #mapEffort, useUngroup are for
#/* target library list should include all target .db files */ #non-ultra compile...
set mapEffort1 medium ;# First pass - low, medium, or high
set target_library [list !!your-library-name!!.db]
set mapEffort2 medium ;# second pass - low, medium, high
#/* synthetic_library is set in .synopsys_dc.setup to be */ set useUngroup 1 ;# 0 if no flatten, 1 if flatten
#/* the dw_foundation library. */
set link_library [concat [concat "*" $target_library] $synthetic_library]

syn-script.tcl syn-script.tcl
#/* Timing and loading information */ #/* the following control which output files you want. They */
set myPeriod_ns !!10!! ;# desired clock period (speed goal) #/* should be set to 1 if you want the file, 0 if not */
set myInDelay_ns !!0.25!! ;# delay from clock to inputs valid set write_v 1 ;# compiled structural Verilog file
set myOutDelay_ns !!0.25! ;# delay from clock to output valid set write_db 0 ;# compiled file in db format (obsolete)
set myInputBuf !!INVX4!! ;# name of cell driving the inputs
set write_ddc 0 ;# compiled file in ddc format (XG-mode)
set myLoadLibrary !!Lib!! ;# name of library the cell comes from
set write_sdf 0 ;# sdf file for back-annotated timing sim
set myLoadPin !!A!! ;# pin that outputs drive
set write_sdc 1 ;# sdc constraint file for place and route
set write_rep 1 ;# report file from compilation
#/* Control the writing of result files */
set write_pow 0 ;# report file for power estimate
set runname struct ;# Name appended to output files
 syn-script.tcl syn-script.tcl
# analyze and elaborate the files
analyze -format $fileFormat -lib WORK $myfiles # Set the driving cell for all inputs except the clock
elaborate $basename -lib WORK -update # The clock has infinite drive by default. This is usually
# what you want for synthesis because you will use other
current_design $basename
# tools (like SOC Encounter) to build the clock tree (or define it by hand).
# The link command makes sure that all the required design
set_driving_cell -library $myLoadLibrary -lib_cell $myInputBuf \
# parts are linked together. [remove_from_collection [all_inputs] $myClk]
# The uniquify command makes unique copies of replicated # set the input and output delay relative to myclk
modules. set_input_delay $myInDelay_ns -clock $myClk \
link [remove_from_collection [all_inputs] $myClk]
uniquify set_output_delay $myOutDelay_ns -clock $myClk [all_outputs]
# now you can create clocks for the design # set the load of the circuit outputs in terms of the load
if { $virtual == 0 } { # of the next cell that they will drive, also try to fix hold time issues
create_clock -period $myPeriod_ns $myClk set_load [load_of [format “%s%s%s%s%s” $myLoadLibrary \
} else { "/" $myInputBuf "/" $myLoadPin]] [all_outputs]
create_clock -period $myPeriod_ns -name $myClk set_fix_hold $myClk
}

syn-script.tcl syn-script.tcl
# Check things for errors
# now compile the design with given mapping effort
# and do a second compile with incremental mapping check_design
# or use the compile_ultra meta-command report_constraint -all_violators
if { $useUltra == 1 } { set filebase [format "%s%s%s" $basename "_"
compile_ultra $runname]
} else { # structural (synthesized) file as verilog
if { $useUngroup == 1 } {
if { $write_v == 1 } {
compile -ungoup_all -map_effort $mapEffort1
compile -incremental_mapping -map_effort $mapEffort2 set filename [format "%s%s" $filebase ".v"]
} else { redirect change_names { change_names -rules
compile -map_effort $mapEffort1 verilog \
compile -incremental_mapping -map_effort $mapEffort2 -hierarchy -verbose }
} write -format verilog -hierarchy -output $filename
} }
# write the rest of the desired files... then quit

Using Scripts Using Design Vision

 Modify syn-script.tcl or write your own  You can do all of these commands from the
 syn-dc –f scriptname.tcl design vision gui if you like
 Make sure to check output!!!!  syn-dv
 Follow the same steps as the script
 Set libraries in your own .synopsys_dc.setup
 analyze/elaborate
 define clock and set constraints
 compile
 write out results
 addsub_struct.v – 10ns target addsub_struct.v – 4ns target

addsub_struct.v – 3ns target

From the log file:

Using Design Vision Setup


You can do all of these commands from the
design vision gui if you like

syn-dv

Follow the same steps as the script
- Set libraries
- analyze/elaborate
- define clock and set constraints
- compile
- write out results
File ->Setup
 analyze/elaborate Look at results...
File -> Analyze

File ->Elaborate

Define clock Compile

attributes -> specify clock

Design -> Compile Ultra

Also look at other attributes...

Timing Reports Write Results

change_names

File -> Save As...

Timing -> Report Timing Path
 Or, use syn-dv after script... syn-dv with mips_struct.v
 syn-dc –f mips.tcl
 results in .v, .ddc, .sdc, .rep files File -> Read
 Read the .ddc file into syn-dv and use it to
explore timing...

Endpoint slack... Path Slack

Timing -> Path Slack

Timing -> Endpoint Slack

Encounter Digital Implementation System Encounter Digital Implementation (EDI)

 Need structural Verilog, .sdc, library.lib, 1. Import Design

library.lef Converts structural verilog
2. Floorplan into physical layout
 make a new directory for edi... (very chatty) 3. Power Plan
 Configuration file sets up names, etc.
4. Place cells
 use UofU_edi.globals as starting point.
5. Synthesize clock tree
 Usual warnings about scripting...
6. Route signal nets
top.tcl is the generic script Shorthand for this process:
 .../local/class/6710/F13/cadence/EDI
7. Verify results
Place and Route
 cad-edi 8. Write out results
 EDI Usage cad-edi Flow
Need structural Verilog, struct.sdc, library.lib, library.lef 1. Import Design
Make a new directory for EDI (very chatty) 
.v, .sdc, .lib, .lef – can put this in a
Make an mmmc.tcl file with timing/lib info <name>.globals and mmmc.tcl
<design>.globals has design-specific settings 
mmmc = multi-mode multi-corner
Use UofU_edi.globals as starting point 2. Floorplan
Usual warnings about scripting... 
Choose physical size, ratio, utilization, etc.
top.tcl and other *.tcl are in the class directory as starting points
/uusoc/facility/cad_common/local/class/6710/F13/cadence/EDI 3. Power plan
Call with cad-edi

Rings, stripes, row-routing (sroute)
4. Timing optimization – preCTS

cad-edi Flow cad-edi Flow

5. Placement 8. Add filler cells

Place cells in the rows 
Fill in the spots in the row with no cells

Timing optimization – preCTS 
Adds NWELL for continuity
6. Synthesize clock tree 9. Write out results

Use your buf or inv footprint cells 
<name>.def can be imported as layout

Timing optimization – postCTS 
<name>_edi.v is the placed and routed
7. Global routing structural verilog file

Nanoroute

.spef, .sdc, _edi.lib have timing information

Timing optimization - postRoute

cad-edi gui Design Import

 Using a .globals file UofU_edi.globals
 Put the load information into a .globals file #
# Set the name of your structural Verilog file
 Load it up without having to re-type # This comes from Synopsys synthesis
 Also need a mmmc.tcl file set init_verilog {!!your-file-name.v!!}
# Set the name of your top module
set init_design {!!your-top-module-name.v!!}
# Set the name of your .lef file
# This comes from ELC
set init_lef_file {!!your-file-name.lef!!}
...

UofU_edi.globals mmmc.tcl
######################################################
# set the name of your .lib file (e.g. lib5710-01.lib)
# below here you probably don't have to change anything
# You can create multiple library sets if you have multiple libraries
######################################################
# such as fast, slow, and typ
# Set the name of your “multi-mode-multi-corner data file
# You don't need to change this unless you're using a # If you have multiple .lib files, put them in a [list lib1 lib2] structure
# different mmmc.tcl file create_library_set -name typical_lib \
set init_mmmc_file {mmmc.tcl} -timing {!!your-lib-file!!.lib}
# Some helpful input mode settings # Specify the .sdc timing constraints file to use
set init_import_mode {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1} # This file comes from Synopsys synthesis (e.g. design_struct.sdc)
# Set the names of your ground and power nets create_constraint_mode -name typical_constraint \
set init_gnd_net {gnd!}
-sdc_files {!!your_sdc_file!!.sdc}
set int_pwr_net {vdd!}
…

Design
mmmc.tcl Import
#########################################################
# Below here you shouldn't have to change, unless you're doing
# something different than the basic EDI run...
######################################################### Some screen
shots are from
# Create an RC_corner that has specific capacitance info
an older version
create_rc_corner -name typical_rc \ of EDI, but not
… this one...
# Define delay corners and analysis views
create_delay_corner -name typical_corner \
-library_set {typical_lib}
-rc_corner {typical_rc}
create_analysis_view -name typical_view \
-constraint_mode {typical_constraint} \
- delay_corner {typical_corner}
Floorplan Floorplan

Specify -> Floorplan Specify -> Floorplan

Floorplan Power Rings

and Stripes

Specify ->
Floorplan

Power -> Power Planning

Place cells

Sroute
to
connect
things
up Place -> Place cells...

Route -> Sroute

pre-CTS timing optimization Clock Tree Synthesis
clock -> create clock tree spec
Timing -> Optimization

clock ->Synthesize clock tree

Display Clock Tree post-CTS optimization

NanoRoute Routed circuit

Route -> NanoRoute -> Route

 Routed circuit postRoute optimization
Timing -> Optimization

Add Filler Write Results...

Design -> Save -> Netlist

Design -> Save -> DEF

Place -> Filler -> Add...

Encounter Scripting top.tcl

 Usual warnings – know what’s going on!
# set the basename for the config and floorplan files. This
 Use opt.tcl as a starting point # will also be used for the .lib, .lef, .v, and .spef files...
 And the other .tcl files it calls... set basename “mips"
 EDI has a floorplanning stage that you may # The following variables are used in fplan.tcl
want to do by hand # Note that rowgap and coregap should be divisible by
# the basic grid unit of 0.3 that our process uses
 write another script to read in the floorplan and
set usepct 0.60 ; # percent utilization in placing cells
go from there...
set rowgap 15 ; # gap (microns) between pairs of rows
 Use encounter.cmd to see the text versions of set aspect 0.60 ; # aspect ratio ( 1 is square)
what you did in the GUI... set coregap 30.0 ; # gap (microns) between core and rails
 top.tcl top.tcl
#############################################################
# You may not have to change things below this line - but check! # Set the flag for SOC to automatically figure out
#
# You may want to do floorplanning by hand in which case you
# buf, inv, etc.
# have some modification to do! set dbgGPSAutoCellFunction 1
#############################################################
# import design and floorplan
# Set some of the power and stripe parameters - you can change
# if the config file is not named $basename.conf,
# these if you like - in particular check the stripe space (sspace)
# and stripe offset (soffset)!
# edit this file.
set pwidth 9.9; # power rail width loadConfig $basename.conf 0
set pspace 1.8; # power rail space commitConfig
set swidth 4.8; # power stripe width
set sspace 123; # power stripe spacing
set soffset 120; # power stripe offset to first stripe
set coregap 30.0; # gap between the core and the power rails

top.tcl fplan.tcl
puts “------------------ floorplanning -----------------”
# source the files that operate on the circuit
source fplan.tcl; # percent utilization in placing cells # Make a floorplan – this works for projecst that are all
source pplan.tcl; # create the power rings and stripes # standard cells and include no blocks that
source place.tcl; # place the cells and optimize (pre-CTS) # need hand placement
source cts.tcl; # create clock tree, and optimize (post-CTS) setDrawView fplan
source route.tcl; # route the design using nanoRoute setFPlanRowSpacingAndType $rowgap 2
source verify.tcl; # verify the design and produce output files floorPlan –site core –r $aspect $usepct \
exit $coregap $coregap $coregap $coregap
fit

# save design so far

saveDesign ${BASENAME}_fplan.enc
saveFPlan ${BASENAME}.fp
Puts “-------------- floorplanning done ----------------”

pplan.tcl pplan.tcl
puts “------------------ Power Planning -----------------” puts "------making power stripes-----------------”
# Make Power Stripes. This step is optional. If you keep it
Puts “------------------ Making Power Rings --------------”
# in remember to check the stripe spacing
# (set-to-set-distance = $sspace) and stripe offset
# Make power and ground rings - $pwidth microns wide # (xleft-offset = $soffset))
# with $pspace spacing between them addStripe -block_ring_top_layer_limit metal3 \
# and centered in the channel -max_same_layer_jog_length 3.0 \
addRing –spacing_bottom $pspace \ -snap_wire_center_to_grid Grid \
-width_left $pwidth \ -padcore_ring_bottom_layer_limit metal1 \
-width_bottom $pwidth \ …
-width_top $pwidth \ # Use the special-router to route the vdd! and gnd! nets
sroute -allowJogging 1
-spacing_top $pspace \
-layer_bottom metal1 \
# Save the design so far
-center 1 \ saveDesign ${BASENAME}_pplan.enc
-stacked_via_top_layer metal3 \ puts "-------------Power Planning done---------"
…
 top.tcl Report Files
Read the script...  <topname>_Conn_regular.rpt
place  <topname>_Conn_special.rpt
pre-CTS optimization
 <topname>_Geom.rpt
clock tree synthesis
post-CTS optimization
routing  Desire 0 violations
post-ROUTE optimization  If you have 1 or 2 in the geometry, you might be
add filler able to fix them easily in Virtuoso…
write out results

Read back to
Change abstract to layout cellviews
icfb
Edit -> Search
File -> Import -> DEF

DRC, Extract

Import Verilog Schematic view

File -> Import -> Verilog

LVS...
LVS Result Summary
 Behavioral -> structural -> layout
 Can be automated by scripting, but make
sure you know what you’re doing
 on-line tutorials for TCL
 Google “tcl tutorial”
Yay!  Synopsys documentation for design_compiler
 encounter.cmd (and documentation) for EDI
 End up with placed and routed core layout
 or BLOCK for later use...