FIFO Depth Calculation

Introduction FIFO Depth Calculation Cont... FIFO Depth Calculation Cont...

FIFO is a distinct kind of buffer. First in, first out, or FIFO, refers to the order in Sol: - It means that, after reading one data, module B is waiting for 3 clock cycles,
which data is written to and read from a buffer. A FIFO (First-In-First-Out) is a - It means that, after writing one data, module A is waiting for one clock cycle, to initiate the next read. So, it can be understood that for every four clock
memory queue, which controls the data flow between two modules. to initiate the next write. So, it can be understood that for every two clock cycles, one data is read.
cycles, one data is written. - Time required to write one data item = 2 * 1/ 50MHz = 40 nSec.
Why do we use FIFO in VLSI? - The no. of idle cycles between two successive reads is 3 clock cycles. It - Time required to write all the data in the burst = 120 * 40 nSec. = 4800
means that, after reading one data, module B is waiting for 3 clock cycles, to nSec.
FIFOs are used in designs to safely pass multi-bit data words from one clock domain initiate the next read. So, it can be understood that for every four clock - Time required to read one data item = 4 * 1/ 50MHz = 80 nSec.
to another, or to control the flow of data between source and destination sides cycles, one data is read. - So, for every 80 nSec, the module B is going to read one data item in the
sitting in the same clock domain. - Time required to write one data item = 2 * 1/ 80Mhz = 25 nSec. burst.
- Time required to write all the data in the burst = 120 * 25 nSec. = 3000 - So, in a period of 4800 nSec, 120 no. of data items can be written.
What are the different types of FIFO? nSec. - The no. of data items can be read in a period of 4800 nSec
- Time required to read one data item = 4 * 1/ 50MHz = 80 nSec. =4800nSec/80nSec =60
Three kinds of FIFO are Shift Register, Exclusive read/write FIFO, Concurrent - So, for every 80 nSec, the module B is going to read one data in the burst. - The remaining no. of bytes to be stored in the FIFO = 120 – 60 = 60.
read/write FIFO. - So, in a period of 3000 nSec, 120 no. of data items can be written. - So, the FIFO which has to be in this scenario must be capable of storing 60
- The no. of data items can be read in a period of 3000 nSec = data items.So, the minimum depth of the FIFO should be 60.
Shift register: A type of digital circuit using a cascade of flip-flops where the 3000nSec/80nSec =37.5 ≈37 Case – 9 : If the data rates are given as follows.
output of one flip-flop is connected to the input of the next. - The remaining no. of bytes to be stored in the FIFO = 120 – 37 = 83. - Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Exclusive Read/Write FIFOs: In exclusive read/write FIFOs, the writing of data - So, the FIFO which has to be in this scenario must be capable of storing 83 - Outgoing Data= 8 DATA/10 Clock.
is not independent of how the data are read. There are timing relationships data items. So, the minimum depth of the FIFO should be 83. - Burst size = 160
between the write clock and the read clock. For instance, overlapping of the Case – 4 : fA > fB with duty cycles given for wr_enb and rd_enb. Sol:
read and the write clocks could be prohibited. To permit use of such FIFOs Sol: - The given specifications indicate that the Writing Frequency is equal to
between two systems that work asynchronously to one another, an external - This scenario is no way different from the previous scenario (case - 3), reading frequency.
circuit is required for synchronization. But this synchronization circuit usually because, in this case also, one data item will be written in 2 clock cycles and - But, both reading and writing can happen at any random instants with the
considerably reduces the data rate. one data item will be read in 4 clock cycles. constraints that “writing of 80 data items will be completed in 100 cycles”
Concurrent Read/Write FIFOs: In concurrent read/write FIFOs, there is no Case – 5 : fA < fB with no idle cycles in both write and read (i.e., the delay and ”reading of 8 data items will be completed in 10 cycles”.
dependence between the writing and reading of data. Simultaneous writing between two consecutive writes and reads is one clock cycle). - The following are possibilities.
and reading are possible in overlapping fashion or successively. This means - Writing frequency = fA = 30MHz.
that two systems with different frequencies can be connected to the FIFO. The - Reading Frequency = fB = 50MHz.
designer need not worry about synchronizing the two systems because this is
taken care of in the FIFO. Concurrent read/write FIFOs, depending on the - Burst Length = No. of data items to be transferred = 120.
control signals for writing and reading, fall into two groups Synchronous FIFOs - There are no idle cycles in both reading and writing which means that, all the
and Asynchronous FIFOs. items in the burst will be written and read in consecutive clock cycles.
Synchronous FIFOs:In a Synchronous FIFO, the write and read to the FIFO happen on a Sol:In this case, a FIFO of depth ‘1’ will be sufficient because, there will not
single clock. This means in Synchronous FIFO, either write or read can happen at a single be any data loss since the reading is faster than writing.
time (on single clock).In Synchronous FIFO the read and write operations are performed at
the same rate.
Case – 6 : fA < fB with idle cycles in both write and read (duty cycles of
Asynchronous FIFO:In asynchronous FIFO, data read and write operations use different wr_enb and rd_enb can also be given in these type of questions).
clock frequencies. Since write and read clocks are not synchronized, it is referred to as - Writing frequency = fA = 30MHz. - The following are the observations from the above diagram.
asynchronous FIFO. Usually, these are used in systems where data need to pass from one - Reading Frequency = fB = 50MHz.
clock domain to another which is generally termed as ‘clock domain crossing’. Thus, - Burst Length = No. of data items to be transferred = 120.
asynchronous FIFO helps to synchronize data flow between two systems working on
different clocks.
- There are no idle cycles in both reading and writing which means that, all the
items in the burst will be written and read in consecutive clock cycles.
Sol: - To obtain safer FIFO size, we need to consider the worst case scenario for
FIFO Depth Calculation - The no. of idle cycles between two successive writes is 1 clock cycle. It the data transfer across the FIFO under consideration to avoid the data loss.
means that, after writing one data, module A is waiting for one clock cycle, to - For worst case scenario, the difference between the data rate between write
The following examples describe the different possible scenarios in which Asyn- initiate the next write. So, it can be understood that for every two clock and read should be maximum. Hence, for write operation, maximum data
chronous FIFO is required. In the following examples, considered that, the mod- cycles, one data is written. rate should be considered and for read operation, minimum data rate should
ule ‘A’ wants to send some data to the module ‘B’. - The no. of idle cycles between two successive reads is 3 clock cycles. It be considered.
means that, after reading one data, module B is waiting for 3 clock cycles, to - The maximum data rate for the write is in case – 4. (Write operation is
initiate the next read. So, it can be understood that for every four clock completed in minimum no. of cycles in this case). So, consider the case - 4
cycles, one data is read. for further calculations.
- Time required to write one data item = 2 * 1 /30MHz = 66.667 nSec. - So, in a period of 160 clock cycles, 160 no. of data items can be written.
Case – 1 : fA > fB with no idle cycles in both write and read. - Time required to write all the data in the burst = 120 * 66.667 nSec.= 8000 - The data rate for the read is 8 data / 10 clock cycles.
- frequency = fA = 80MHz. nSec. - The no. of data items can be read in a period of 160 clock cycles = (160 *
- Reading Frequency = fB = 50MHz. - Time required to read one data item = 4 * 1 /50MHz = 80 nSec. 8)/10=128
- Burst Length = No. of data items to be transferred = 120. - So, for every 80 nSec, the module B is going to read one data item in the - The remaining no. of bytes to be stored in the FIFO = 160 – 128 = 32.
- There are no idle cycles in both reading and writing which means that, all the burst. - So, the FIFO which has to be in this scenario must be capable of storing 32
items in the burst will be written and read in consecutive clock cycles. - So, in a period of 8000 nSec, 120 no. of data items can be written. data items.So, the minimum depth of the FIFO should be 32.
Sol: - The no. of data items can be read in a period of 8000 nSec = =100 Case – 10 : Specifications can be given in a different way. (Understanding
- Time required to write one data item = 1/80MHz = 12.5 nSec. - The remaining no. of bytes to be stored in the FIFO = 120 – 100 = 20. the specifications is important here)
- Time required to write all the data in the burst = 120 * 12.5 nSec. = 1500 - So, the FIFO which has to be in this scenario must be capable of storing 20 - Given the following FIFO rules, how deep does the FIFO need to be to
nSec. data items. So, the minimum depth of the FIFO should be 20. prevent underflow or overflow?
- Time required to read one data item =1/50MHz= 20 nSec. Case – 7 : fA = fB with no idle cycles in both write and read (i.e., the delay - Frequency (clk A) = frequency (clk B)/4
- So, for every 20 nSec, the module B is going to read one data in the burst. between two consecutive writes and reads is one clock cycle). - Period en_B = period clk_A*100
- So, in a period of 1500 nSec, 120 no. of data items can be written. - Writing frequency = fA = fB = 30MHz. - Duty cycle (en_B) = 25%
- And the no. of data items can be read in a duration of 1500 nSec - Burst Length = No. of data items to be transferred = 120. Sol:
=1500nSec/20nSec=75 - There are no idle cycles in both reading and writing which means that, all the - Assume some numerical values, if the specifications are in this way.
- The remaining no. of bytes to be stored in the FIFO = 120 – 75 = 45. items in the burst will be written and read in consecutive clock cycles. - Assume frequency of clk_B = 100MHz
- So, the FIFO which has to be in this scenario must be capable of storing 45 Sol: - So, the frequency of clk_A = 100MHz /4 = 25MHz.
data items.So, the minimum depth of the FIFO should be 45. - FIFO is not required if there is no phase difference between clkA and clkB. - In the specifications given, the burst length is specified indirectly. The burst
Case – 2 : fA > fB with one clk cycle delay between two successive reads - A FIFO of depth ‘1’ will be sufficient if there is some phase difference length is 100.
and writes. between clkA and clkB. - Time required to write one data item = 1/25Mhz = 40 nSec.
Sol: Case – 8 : fA = fB with idle cycles in both write and read (duty cycles of - Time required to write all the data in the burst = 100 * 40 nSec. = 4000
- This is just, to create some sort of confusion. This scenario is no way wr_enb and rd_enb can also be given in these type of questions). nSec.
different from the previous scenario (case -1), because, always, there will be - Writing frequency = fA = 50MHz. - And the duty cycle of en_B is 25 % means that, out of 4000 nSec in which
one clock cycle delay between two successive reads and writes. So, the - Reading Frequency = fB = 50MHz. the writing process is completed, reading is done only in a period of 1000
approach is same as the earlier one. - Burst Length = No. of data items to be transferred = 120. nSec (25% of 4000 nSec.)
Case – 3 : fA > fB with idle cycles in both write and read. - No. of idle cycles between two successive writes is = 1. - So, the FIFO should be capable of holding the data which is being written in
- Writing frequency = fA = 80MHz. - No. of idle cycles between two successive reads is = 3. the remaining 3000 nSec.
- Reading Frequency = fB = 50MHz. Sol: - The no. of data items can be read in a period of 3000 nSec
- Burst Length = No. of data items to be transferred = 120. - The no. of idle cycles between two successive writes is 1 clock cycle. It =3000nSec/40nSec =75So, the minimum depth of the FIFO should be 75.
- No. of idle cycles between two successive writes is = 1. means that, after writing one data, module A is waiting for one clock cycle, to
- No. of idle cycles between two successive reads is = 3. initiate the next write. So, it can be understood that for every two clock
- The no. of idle cycles between two successive writes is 1 clock cycle. cycles, one data is written.
- The no. of idle cycles between two successive reads is 3 clock cycles.

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