zao ASSEMBL Y LANGUAGE PROGRAMMING MANUAL

Copyright© 1977 by 2ilog, Inc. All rights reserved. No part of this

publication may be reproduced, stored in a retrieval system, or transmitted,
in any form or by any means, electronic, mechanical, photocopying,
recording, or otherwise, without the prior written permission of Zilog.

Zilog assumes no responsibility for the use of any circuitry other than
circuitry embodied in a Zilog product. No other circuit patent licenses 3.00.5,
are implied. REL. 2il
 TABLE OF CONTENTS

PAGE

I. INTRODUCTION •••••••••••••••••••••••••••••••••••••••••

IL. SPECIFICATION OF ZaD ASSEMBLY LANGUAGE

A. THE ASSEMBLY LANGUAGE •••••••••••••••••••' •••••••• 2
B. OPERANDS. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• • • • • • •• 4
C. RULES FOR WRITING ASSEMBLY STATEMENT~ (SYNTAX) •• ~
D. ASSEMBLY LANGUAGE CONVENTIONS................... 7
E. ASSEMBLER COMMANDS •••••••••••••••••••••••••••••• 13

III. MACROS ••••••••••••••••••••••••••••••••••••••••••••••• 15

IV. SUBROUTINES •••••••••••••••••••••••••••••••••••••••••• 18

v. ZaG CPU FLAGS •••••••••••••••••••••••••••••••••••••••• 20

VI. zaD INSTRUCTION SET •••••••••••••••••••••••••••••••••• 24

INSTRUCTION INDEX •••••••••••••••••••••••••••••••••••• 275

APPENDIX:

A. ERROR MESSAGES •••••••••••••••••••••••••••••••••• 280

C. INSTRUCTION SORT LISTING (ALPHABETICAL) ••••••••• 284
C. INSTRUCTION SORT LISTING (NUMERICAL) •••••••••••• 290

JANUARY 1978
 Z80 ASSEMBLY LANGUAGE PROGRAMMING MANUAL

INTRODUCTION:

The assembly language provides a means for writing a

program without having to be concerned with actual
memory addresses or machine instruction formats. It
allows the use of symbolic addresses to iden~ify memory
locations and mnemonic codes (opcodes and operands) to
represent the instructions themselves. Label,s (symbols)
can be assigned to a particular instruction step in a
source program to identify that step as an entry point
for use in subsequent instructions. Operands' following
each instruction represent storage locations, registers,
or constant values. The assembly language also includes
assembler directives that supplement the machine
instruction. A pseudo-op, for example, is a 8tatement
which is not translated into a machine instru~tion, but
rather is interpreted as a directive that controls the
assembly process.

A program written in assembly language is called a

source program. It consists of symbolic commands called
statemen~s. Each statement is written on a single line
and may consist of from one to four entries: A label
field, an operation field, an operand field and a
comment field. The source program is processed by the
assembler to obtain a machine language program (object
program) that can be executed directly by the Z80-CPU.

Zilog provides several different assemblers which differ

in the features offered. Both absolute and relocatable
assemblers are available with the Development and
Microcomputer Systems. The absolute assemble is
contained in ba~e level software operating in a 16K
memory space while the relocating assembler i part of
the RIO environment operating in a 32K memory space.
II SPECIFICATION OF THE Z80 ASSEMBLY LANGUAGE

A. THE ASSEMBLY LANGUAGE

The assembly language of the Z80 is de$igned to

minimize the number of different opcod~s
corresponding to the set of basic machtne
operations and to provide for a consistent
description of instruction operands. ~he
nomenclature has been defined with special emphasis
on mnemonic value and readability.

The movement of data is indicated prim4rily by a

single opcode, LD for example, regardl~ss of
whether the movement is between different registers
or between registers ~nd memory locatiOns.

The first operand of an LD instruction is the

destination of the operation, and the $econd
operand is the source of the operation. For
example:

LD A,B

indicates that the contents of the second operand,

register B, are to be transferred to the first
operand, register A. Similarly,

LD C,3FH

indicates that the constant 3FH is to be loaded

into the register C. In addition, enclosing an
operand wholly in parentheses indicate$ a memory
location addressed by the contents of the
parentheses. For example,

LD HL,(1200)

indicates the contents of memory locations 1200 and

1201 are to be loaded into the 16-bit register pair
HL. Similarly,

LD (IX+6),C

indicates the contents of the register C are to be

stored in the memory location addressed by the
current value of the 16-bit index register IX plus
6.
The regular formation of assembly instructions
minimizes the number of mnemonics and format rules
that the user must learn and manipulate.
Additionally, the resulting programs are easier to
interpret which in turn reduces programming errors
and improves the maintainability of the software.
B. OPERANDS

Operands modify the opcodes and provide the

information needed by the assembler to perform the
designated operation.

Certain symbolic names are reserved as key words in

the assembly language operand fields. They are:

I) The contents of 8-bit registers are

specified by the character corresponding
to the register names. The register names
are A,B,C,D,E,H,L,I,R.

2) The contents of 16-bit double registers

and register pairs consisting of two 8-bit
registers are specified by the two
characters corresponding to the register
name or register pair. The names of
double registers are IX,IY and SP. The
names of registers pairs are AF,BC,DE and
HL.

3) The contents of the auxiliary register

pairs consisting of two 8-bit registers
are specified by the two characters
corresponding to the register pair names
followed by an apostrophe. The auxiliary
register pair names are AF',BC',DE' and
HL'. Only the pair AF' is actually allowed
as an operand, and then only in the EX
AF,AF' instruction.

4) The state of the four testable flags is

specified as follows:

FLAG ON CONDITION
CONDITION
Carry C NC
Zero Z NZ
Sign M (minus) P (pI us)
Parity PE (even) PO (odd)
OPERAND NOTATION

The following notation is used in the description

of the assembly language:

1) r specifies anyone of the following

registers: A,B,G,D,E,H,L.
2) (HL) spe~ifies· the contents of memory at
the location addressed by the contents of
the register pair HL.
3) n specifies a one-byte expression in the
range (0 to 255) nn specifies a two-byte
expression in the range (0 to 65535).
4) d specifies a one-byte expression in the
range (-128,127).
5) (nn) specifies the contents of memory at
the location addressed by the two-byte
expression nn.
6) b specifies an expression in the range
(0,7).
7) e specifies a one-byte expression in the
range (-126,129).
8) cc specifies the state of the Flags for
conditional JR, JP, CALL and RET
instructions.
9) qq specifies anyone of the register pairs
BG, DE, HL or AF.
10) ss specifies anyone of the following
register pairs: BG,DE,HL,SP.
11) pp specifies anyone of the following
register pairs: BG,DE,IX,SP.
12) rr specifies anyone of the following
register pairs: BG,DE,IY,SP.
13) s specifies any of r,n,(HL),(IX+d),(IY+d).
14) dd specifies anyone of the following
register pairs: BG,DE,HL,SP.
15) m specifies any of r, (HL), (IX+d), (IY+d).
C. RULES FOR WRITING ASSEMBLY STATEMENTS (S¥NTAX)

An assembly language program (source program)

consists of labels. opcodes. operands. cpmments and
pseudo-ops in a sequence which defines the user's
program.

There are 74 genericopcodes (such as LD). 25

operand key words (such as A). and 694 legitimate
combinations of opcodes and operands in the zao
instruction set.

ASSEMBLER STATEMENT FORMAT:

Statements are always written in a particular

format. A typical Assembler statement is shown
below:

LABEL OPCODE OPERANDS COMMENT

LOOP: LD HL.VALUE ;GET VALUE

In this example. the label. LOOP, provides a means

for assigning a specific name to the instruction
LOAD (LD), and is used to address the statement in
other statements. The operand field contains one
or two entries separated by one or more commas.
tabs or spaces. Th~ comment field is use' by the
programmer to quickly identify the actio$ defined
by the statement. Comments must begin with a
semicolon and labels must be terminated by a colon,
unless the label starts in column No.1.
D ASSEHBLY LANGUAGE CONVENTIOnS

LABELS

A label is a syubol representing up to 16 bits of

information and is used to specify an address or
data. By using labels effectively, the uSer can
write assembly language programs more rapidly and
make fewer errors. If the programmer attempts to
use a symbol that has been defined as greater than
8 bits for an 8-bit data constant, the assembler
will generate an error message.

A label is composed of a string of one or more

characters, of which the first six must be. unique.
For exar,lple, the labels' longname' and
'longnamealso' will be considered to be the same
label. The first character must be alphabetic and
any following characters Dust be either
alphanumeric, the question mark (?) or the under
ba~ character ( ) . Any other characters with~n a
label will caus; an error. A label tan start in
any column if immediately followed by a colon. It
does not require a colon if started in column one.

The assembler maintains a location counter to

provide addresses for the symbols in the label
field. When a symbol is found in the label field,
the assembler places the symbol and the
corresponding location counter value in a symbol
tab Ie.

The symbol table normally resides in RAM, but it

will automatically overflow to disk, so there is
limit to the number of labels that can be
processed.

EXPRESSIONS

An expression is an operand entry consisting of

either a single term (unary) or a combination of
termS (binary). It contains a valid series of
constants, variables and functions that can be
connected by operation symbols. The Z80 Assembler
will accept a wide range of expressions involving
arithmetic and logical operations. The assembler
will evaluate all expressions from left to right in
the order indicated in the table below:
OPERATOR FUNCTION

+ UNARY PLUS
UHARY l1I1WS
.NOT. or \ LOGICAL NOT
.RES. RE SU 1'i
** EXPONENTIATION
liUL TI1'L I CATION
*/ DIVISION
.110D. 1l0DULO
.SHR. LOGICAL SUlfT RIGHT
.SaL. LOGICAL SHIFT LEFT
+ ADDITION
SUBTRACTION
.AND. or & LOGICAL AND
.OR. or LOGICAL OR
.XOR. LOGICAL XOR
.EQ. 0 r EQUALS
.GT. or GREATER THAN
.LT. or LESS THAN
.UGT. UNS~GNED GREATER THAN
.ULT. UNSIGNED LESS THAN

Parenthesis can be used to ensure correct

expression evaluation. Note, however, that
enclosing an expression wholly in parenthesis
indicates a memory address.

Delimiters such as spaces or commas are not allowed

within an expression since they serve to separate
the expression from other portions of the
statement.

16-bit integer arithmetic is used throughout.

Note that the negative of an expression can be

formed by a preceding minus sign -. For example:

LD HL,-OEA9H.

The five comparison operators (.EQ., .GT., .LT.,

.UGT.and.ULT.) will evaluate to a logical True (all
ones) if the comparison is true logical False
(zero) otherwise. The operators .GT. and .LT. deal
with signed numbers whereas .UGT. and .ULT. assume
unsigned arguments.

The Result operator (.RES.) causes overflow to be

suppressed during evaluation of its argum~nt, thus
overflow is not flagged with an error message.

For example:

LD BC,7FFFH+l would cause an error message,

whereas LD BC,.RES.(7FFFH+l) would not.

The l1odulo operator (.MOD.) is defined as:

X.MOD.Y. = X-Y*(X/Y) where the division (X/Y)

is integer division.

The Shift operator (.SllR.,.SllL.) shifts the first

argument right or left by the number of positions
given in the second argument. Zeros are shifted
into the high-order or low-order bits,
respec tively.

In specifying relative addressing with either the

JR (Jump Relative) or DJNZ (Decrement and Jump if
Not Zero) instructions, the Assembler automatically
subtracts the value of the next instruction's
reference counter from the value given in the
operand field to form the relative address for the
jump instruction. For example:

JR C,LOOP

will jump relative to the instruction labeled LOOP

if the Carry flag is set. The limits on the range
of a relative address is 128 bytes in either
direction from the reference counter of the next
instruction. An error message will be generated if
this range is exceeded.

The symbol $ is used to represent the value of the

reference counter of the current instruction, and
can be used in general expressions. An expression
which evaluates to a displacement in the range
<-126,+129> can be added to the reference counter
to form a relative address. For example:

JR C,$+5

will jump relative to the instruction which is

bytes beyond the current instruction.
PSEUDO-OPS (ASSEMBLER DIRECTIVES)

There are several pseudo-ops which the various

2ilog assemblers will recognize. These assembler
directives, although written much like processor
instructions, are commands to the assembler instead
of to the processor. They direct the assembler to
perform specific tasks during the assembly process
but have no meaning to the Z80 processor. These
assembler pseudo-ops are:

ORG nn Sets address reference counter to

the value nne

EQU Sets value of a label to nn in the

program: can occur only once for
any label.

DEFL nn Sets value of a label to nn and can

be repeated in the prog.ram with
different values for the same
1 ab el •

END Signifies the end of the source

program so that any follOWing
statement will be ignored. If
there is no end statement, then the
end-of-file mark in the last source
file will designate the end of the
source program.

DEFB n Defines the contents of a byte at

the current reference counter to be

DEFB 's' Defines the content of pne byte of

memory to be the ASCII
representation of character s.

DEFW Defines the contents of a two-byte

word to be nne The least
significant byte is located at the
current reference counter while the
most significant byte is located at
the reference counter plus one.

DEFS Reserves nn bytes of memory

starting at the current value of
the reference counter.

10
 DEFll 's' Defines the content of n bytes of
memory to.be the ASCII
representation of string s, where n
is the length of s and must be in
the range O<=n<-63.

BACRG flpo lip 1 ••• IIPn Declares ·the label

to be a macro name with formal
parameters Po through Pn.
Subsequent statements deffne the
body of the macro.

ENDl! Harks the end of a macro

definition.

Pseudo-ops are assembled exactly like executable

instructions, and may be preceded by a label and
followed by a comment. (The label is required for
EQU, DEFL and MACR pseudo-ops.) In the above
pseudo-op definitions, the reference counter
corresponds to the program counter and is used to
assign and calculate machine-language addresses for
the 0 b j e c t f 11 e •

CONDITIONAL PSEUDO-OPS

Conditional pseudo-ops prOVide the programmer with

the capability to conditionally include or not
include portions of his source code in the assembly
process. Conditional pseudo-ops are:

COND nn Evaluates expression nn. If the

expression is true (non-zero)~ the
COND pseudo-op is ignored. If the
expression is false (zero), the
assembly of subsequent statements
is disabled. COND pseudo-ops
cannot be nested.

ENDC Re-enables assembly of subsequent

statements.

DELIUITERS

A delimiter is used to specify the bounds of a

certain related group of characters in a s~urce
program. The delimiters recognized by the
assembler are commas or spaces. A d~limiter cannot

11
occur within an expression.

COUMENTS

Comments are not a functional part of an ~ssembly

program, but instead are used for program
documentation to add clarity, and to facilitate
software maintenance. A comment is defined as any
string following a semicolon in a line, amd is
ignored by the assembler. Comments can begin in
any column.

I/O BUFFERS

The zao Assembler uses a buffered I/O technique for

handling the assembly language source file, listing
file, ~bject file and temporary files. The
assemble~ automatically determines the available
work space and allocates the buffer sizes
accordingly. Hence there are no constraints on the
size of the assembly language source file that can
be assembled.

UPPER/LOWER CASE

The assembler processes source text which.contains

both upper and lower case alphabetic char4cters in
the following manner. All opcodes and keywords,
such as register names or condition codes, must be
either all capitals or all lower case. Label names
may consist of any permutation of upper and lower
case, however, two names which differ in case will
be treated as two different names. Thus, LABEL,
label and LaBel will be considered as three
different names. Notice that one could use a
mixture of case to allow definition of labels or
macros which look similar to opcodes, such as Push
or LdiR, without redefining the meaning of the
opcode. All assembler commands, such as*List or
*Include (see below) can be in either upper or
lower case, as can arithmetic operators suc~ as
NOT.,.AND. or .EQ., and numbers can be any mixture
of case, such as Off~fh, OAbCdH or OllOOlb.

NUMBER BASES

The Assembler will accept numbers in several

12
 different bases: binary, octal, decimal and
hexadecimal. Numbers must always start with a
digit (leading zeros are sufficient), and may be
followed immediately by a single letter which
signifies the base of the number ('B' for binary,
'0' or 'Q' for octal, 'D' for decimal and 'H' for
hexadecimal). If no base is specified decimal is
assumed. For example, the same nucber is
represented in each of the four bases:

1011100B, 134Q, 1340, 92, 92D, OSCll

E. ASSEMBLER COMMANDS

The zao Assembler recognizes several commands to

modify the listing format. An assembler cOmmand is
a line of the source file beginning with an * in
column one. The character in column two identifies
the type of command. Arguments, if any, are
separated from the command by any number of blanks
or commas. The following commands are recognized
by the assembler:

*Eject Causes the listing to advance to a

new page starting with this line.

*Heading Causes string s to be taken as a

heading to be printed at the top of
each new page. Strings s may be
any string of zero to 28
characters, not containing le~ding
blanks. This cocrnand does an
automatic Eject.

*List OFF Causes listing and printing to be

suspended, starting with this line.

*List ON Causes listing and printing to

resume, starting with this line.

*Uaclist OFF Causes listing and printing of

cacro expansions to be suspended,
starting with this line.

*Uaclist ON Causes listing and printing of

macro expansions to resume,
starting with this line.

*Include filename Causes the source file filenace to

be included in the source stream
follOWing the command statement.

13
The expected use of *Include is for files of macro
definitions, lists of EQUates, or commonly uSed
subroutines, although it can be used anywher~ in a
program that the other commands would be legal.
The filename must follow the normal convention for
specifying filenames, and furthermore only file
types 'F' through 'T' are allowed. The default
type is '5'. The included file may also contain a
*Include command, up to a nested level of four.

*Include will always try to shoe-horn the file in

inside a macro definition, and although the
*Include statement will appear in a macro
expansion, the file will not be included again at
the point of expansion. *Include works in the
expected manner in conjunction with conditional
assembly.
For example:

COND exp

*Include FILEl

ENDC

;FILEl is included only if the value of exp is

non-zero.

14
III. MACROS

Macros provide a means for the user to define his

own opcodes, or to redefine existing opcodes. A
macro defines a body of text which will be
automatically inserted in the source strea~ at each
occurrence of a macro call. In addition,
parameters provide a capability for making limited
changes in the macro at each call.

If a macro is used to redefine an existing opcode,

a warning message is generated to indicate that
future use of that opcode will always be processed
as a macro call. If a program uses macros, then
the asembly option M must be specified.

MACRO DEFINITION

The body of text to be used as a macro is tiven in

the macro definition. Each definition begins with
a MACRO statement and end with an ENDM statement.
The general forms are:

<name> MACRO [#<PO>,#<Pl>, ••• ,#<Pn>]

[<label>] ENDH

The label <name> is required, ~nd must obey all the

usual rules for forming labels. The quantity in
brackets is an optional set of parameters.

There can be any number of parameters, each

starting with the symbol #. The rest of the
parameter name can be any string not containing a
delimiter (blank, comma, semicolon) or the symbol
#. However, parameters will be scanned left to
right for a match, so the user is cautioned not to
use parameter names which are prefix substrings of
later parameter names. Parameter names are not
entered in the symbol table.

The label on an ENDM is optional, but if ona is

given it must obey all th.e usual rules for forming
labels.

Each statement between the MACRO and ENDM

statements is entered into a temporary macro file.
The only restriction on these statements is that
they do not include another macro definition.
(Nested definitions are not allowed.) They may

15
include macro calls. (Recursion is allowed.)

The statements of the macro body are not assembled

at definition time, so they will not define labels,
generate code, or cause errors. Exceptions are the
assembler commands such as *List, which are
executed wherever they occur. Within the macro
body text, the formal parameter names may occur
anywhere that an expansion-time substitution is
desired. This includes comments and quoted
strings. The symbol # may not occur except as the
first symbol of a parameter name.

Macros must be defined before they are called.

MACRO CALLS AND MACRO EXPANSION

A macro ~s called by using its name as an opcode at

any point after the definition. The general form
is:

[<label» <name> [·<SO>·,·<Sl>', •••• 'Sn>')

The <label> is optional, and <name> must be a

previously defined macro. There may be any number
of argument strings, <Sn>, separated by any number
of blanks or commas. Commas do not serve as
parameter place holders, only as string delimeters.
If there are too few parameters, the missing ones
are assumed to be null. If there are too many, the
extras are ignored. The position of each string in
the list corresponds with the position of the macro
parameter name it is to replace. Thus, the third
string in a macro call statement will be
substituted for each occurrence of the third
parameter name.

The strings may be of any length and may contain

any characters. The outer level quotes around the
string are generally optional, but are required if
the string contains delimiters or the quote
character itself. The quote character is
represented by two successive quote marks at the
inner level. The outer level quotes, if present,
will not occur in the substitution. The null
string, represented by two successive quote marks
at the outer level, may be used in any parameter
position.

After processing the Dacro call statement, the

assembler switches its input from the source file

16
to the macro file. Each statement of the macro
body is scanned for occurrences of parameter names,
and for each occurrence found, the corresponding
string from the macro call statement is
substituted. After substitution, the statement is
assembled normally.

SYllBOL GENERATOR

Every macro definition has an implicit parameter

named #$YM. This may be referenced by the user in
the macro body, but should not explicitly appear in
the lIACRO statement. At expansion time, each
occurrence of {!$YU in the definition is r,eplaced by
a string representing a 4-digit bexadecim~l
constant.

This string is constant over a given level of macro

expansion, but increases by one for each new macro
call. The most common use of {!$Yl1 is to provide
unigue labels for different expansion of the same
macro. Otherwise, a macro containing a Label would
cause multiple definition errors if it were called
more than once.

LISTING FORHAT

By default, each expanded statement is listed with

a blank STMT field. If the liaclist flag is turned
off by the NOH option or *11 OFF, then only the
macro call is listed.

17
IV. SUBROUTINES

Subroutines are blocks of instructions that can be

called during the execution of a sequence ot
instructions. Subroutines can be called from main
programs or from other subroutines. A subroutine is
entered by the CALL opcode as in:

CALL REWIND

Parameters such as those used by the macros are not

used with subroutines. When a call instruction is
encountered during execution of a program, the PC
is changed to the first instruction of the
subroutine. The subsequent address of the invoking
program is pushed on the stack. Control will
return to this point when the subroutine is
finished. The processor continues to execute the
subroutine until it encounters a RET (return)
instruction. At this point the return address is
popped off the stack into the PC, and the processor
returns to the address of the instruction following
the CALL, to continue execution from that point.

Subroutines of any size can be invoked from

programs or other subroutines of any size, without
restriction. Care must be taken when nesting
subroutines (subroutines wit·hin subroutines) that
pushes and pops remain balanced at each lev~l. If
the processor encounters a RET with an un-popped
push on the stack, the PC will be set to a
meaningless address rather than to the next
instruction following the CALL.

Tradeoffs must be considered between:

a) using a block of code repetitively in line,

and
b) calling the block repetitively as a
subroutine.

Program size can usually be saved by using the

subroutine. If the repetitive block contains N
bytes and it is repeated on " occasions in the
program,

a) MxN bytes would be used in direct

programming, while
b) 3M (for CALLS)

18
 + N (for the block)
+ 1 (for the RET)
3M+N+1 bytes would be required if using a
subroutine.

For example, for a block of 20 bytes used 5 times,

in-line programming would require 100 bytes while a
subroutine would require 36.

An added advantage of subroutines is that with

careful naming, program structures become clearer,
easier to read and easier to debug and maintain.
Subroutines written for one purpose can be employed
elsewhere in other programs requiring the same
function.

Subroutines differ from Macros in several ways:

a) Subroutine code is assembled into an object

program only once although it may be called
many times. Macro code is assembled in
line every place the macro is used.

b) Registers and pointers required by a

subroutine must be set up before the
CALL. No parameters are used and no
argument string can be issued. Macros,
through their use of parameters, can modify
the settings of registers on each
occurrence.

19
V. Z80 STATUS INDICATORS (FLAGS)

The flag register (F and F') supplies information to the

user regarding the status of the Z80 at any given time.
The bit positions for each flag is shown below:

WHERE:

C .. CARRY FLAG
N .. ADD/SUBTRACT FLAG
p/V .. PARITY/OVERFLOW FLAG
H .. HALF-CARRY FLAG
Z .. ZERO FLAG
S .. SIGN FLAG
X NOT USED

Each of the two Z-80 Flag Registers contains 6 bits of

status information which are set or reset by CPU
operations. (Bits 3 and 5 are not used.) Four of these
bits are testable (C,p/V,Z and S) for use with
conditional jump, call or return instructions. Two
flags are not testable (H,N) and are used for BCD
arithmetic.

CARRY FLAG (C)

The ~arry bit is set or reset depending on the operation

being performed. For 'ADD' instructions that generate a
carry and 'SUBTRACT' instructions that generate a
borrow, the Carry Flag will be set. The Carry Flag is
reset by an ADD that does not generate a carry and a
'SUBTRACT' that generates no borrow. This saved carry
facilitates software routines for extended precision
arithmetic. Also, the "DAA" instruction will set the
Carry Flag if the conditions for making the decimal
adjustment are met.

For instructions RLA, RRA, RLS and RRS, the carry bit is
used as a link between the LSB and MSB for any register
or memory location. During instructions RLCA, RLC sand
SLA s, the carry contains the last value shifted out of
bit 7 of any register or memory location. During

20
instructions RRCA, RRC s, SRA sand SRL s the carry
contains the last value shifted out of bit 0 of any
register or memory location.

For the logical instructions AND s, OR sand XOR s,

the carry will b~ reset.

The Carry Flag can also be set (SCF) and complemented

(CCF).

ADD/SUBTRACT FLAG (N)

This flag is used by the decimal adjust accumulator

instruction (DAA) to distinguish between 'ADD' and
'SUBTRACT' instructions. For all 'ADD' instructions, N
will be set to an '0'. For all 'SUBTRACT' instructions,
N will be set to a '1'.

PARITY/OVERFLOW FLAG

This flag is set to a particular state depending on the

operation being performed.

For arithmetic operations, this flag indicates an

overflow condition when the result in the Accumulator is
greater than the maximum possible number (+127) or is
less than the minimum possible number (-128). This
overflow condition can be determined by examining the
sign bits of the operands.

For addition, operands with different signs will never

cause overflow. When adding operands with like signs
and the result has a different sign, the overflow flag
is set. For example:

+120 = 0111 1000 ADDEND

+105 0110 1001 AUGEND
+225 1110 0001 (-95) SUM

The two numbers added together has resulted in a number

that exceeds +127 and the two positive operands has
resulted in a negative number (-95) which is incorrect.
The overflow flag is therefore set.

For subtraction, overflow can occur for operands of

unlike signs. Operands of like sign will never cause
overflow. For example:

+127 0111 1111 MINUEND

(-) '-64 1100 0000 SUBTRAHEND
+191 1011 1111 DIFFERENCE

21
The minuend sign has changed from a positive to a
negative, giving an incorrect difference. Overflow is
therefore set.

Another method for predicting an overflow is to observe

the carry into and out of the sign bit. If there is a
carry in and no carry out, or if there is no carry in
and a carry out, then overflow has occurred.

This flag is also used with logical operations and

rotate· instructions to indicate the parity of the
result. The number of '1' bits in a byte are counted.
If the total is odd, 'ODD' parity (P-O) is flagged. If
the total is even, 'EVEN' parity is flagged (P=I).

During search instructions (CPI,CPIR,CPD,CPD1) and block

transfer instructions (LDI,LDIR, LDD,LDDR) theP/V flag
monitors the state of the byte count register (BC).
When deerementing, the byte counter results in a zero
value, the flag is reset to 0, otherwise the flag is a
Logic 1.

During LD A,I and LD A,R instructions, the P/V flag will

be set with the contents of the interrupt enable
flip-flop (IFF2) for storage or testing.

When inputting a byte from an I/O device, IN r,(C), the

flag will be adjusted to indicate the parity of the
data.

THE HALF CARRY FLAG (H)

The Half Carry Flag (H) will be set or reset .depending

on the carry and borrow status between bits 3 and 4 of
an 8-bit arithmetic operation. This flag is used by the
decimal adjust accumulator instruction (DAA) .to correct
the result of a packed BCD add or subtract operation.
The H flag will be set (1) or reset (0) according to the
following table:

H ADD SUBTRACT

1 There is a carry from There is

Bit 3 to Bit 4 borrow from
bit 4

0 There is no carry There 1s no

from Bit 3 to Bit 4 borrow from
Bit 4
THE ZERO FLAG (Z)

The Zero Flag (Z) is set or reset if the result

generated by the execution of certain instructions
is a zero.

For 8-bit arithmetic and logical operations, the Z

flag will be set to a '1' if the resulting byte in
the Accumulator is zero. If the byte is not zero,
the Z flag is reset to '0'.

For compare (search) instructions, the Z flag will

be set to a '1' if a comparison is found between
the value in the Accumulator and the memory
location pointed to by the contents of the register
pair HL.

When testing a bit in a register or memory

location, the Z flag will contain the complemented
state of the indicated bit (see Bit b,s).

When inputting or outputting a byte between a

memory location and an I/O device (INlj!NDjOUTI and
OUTD), if the result of B-1 is zero, th~ Z flag is
set, otherwise it is reset. Also for byte inputs
from I/O devices using IN r,(C), the Z Flag is set
to indicate a zero byte input.

THE SIGN FLAG (S)

The Sign Flag (S) stores the state of the most

significant bit of the Accumulator (Bit 7). When
the Z80 performs arithmetic operations on signed
numbers, binary two's complement notation is used
to represent and process numeric information. A
positive number is identified by a '0' in bit 7. A
negative number is identified by a '1'. The binary
equivalent of the magnitude of a positive number is
stored in bits 0 to 6 for a total range.Df from 0
to 127. A negative number is represent~d by the
two's complement of the equivalent positive number.
The total range for negative numbers is from -1 to
-128.

When inputting a byte from an I/O device to a

register, IN r,(C), the S flag will indicate either
positive (S=O) or negative (S=I) data.
 VI. zao INSTRUCTION SET

NOTE: Execution time (E.T.) for each instruction is

given in nicroseconds for an assuned 4 MHZ clock. Total
machine cycles (M) are indicated with total clock
periods (T States). Also indicated are the nubber of T
States for each M cycle. For example:

M CYCLES: T STATES: 7(4,3) 4 MHZ E.T.: 1.75

indicates that the instruction consists of 2 machine

cycles. The first cycle contains 4 clock periods (T
States). The second cycle contains 3 clock periods for
a total of 7 clock periods or T States. The instruction
will execute in 1.75 microseconds.

Register format is shown for each instruction with the

most si~nificant bit to the left and the least
significant bit to the right.
 Z8G INSTRUCTION SET
TABLE OF CONTENTS

PAGE

-8 BIT LOAD GROUP •••••••••••••••••••••••••••• 26

-16 BIT LOAD GROUP ••••••••••••••••••••••••••• 52

-EXCHANGE, BLOCK TRANSFER

AND SEARCH GROUP •••••••••••••••••••••••••••• 76

-8 BIT ARITHMETIC AND LOGICAL GROUP •••••••••• 99

-GENERAL PURPOSE ARITHMETIC

AND CPU CONTROL GROUPS •••••••••••••••••••••• 131

-16 BIT ARITHMETIC GROUP ••••••••••••••••••••• 146

-ROTATE AND S HI FT GROUP •••••••••••••••••••••• 163

-BIT SET, RESET AND TEST GROUP ••••••••••••••• ~2

-JUMP GROU P •••••••••••••••••••••••••••••••••• 219

-CALL AND RETURN GROUP ••••••••••••••••••••••• 237

-INPUT AND OUTPUT GROUP •••••••••••••••••••••• 252

-INSTRUCTION INDEX ••••••••••••••••••••••••••• 275

 I

I
I
8 BIT LOAD GROUP
LD r, r'

,
Operation: r +- r

Format:

Opcode Operands

LD r,r

Description:

The contents of any register r' are loaded into any

other register r. Note: r,r' identifies any of the
registers A, B, C, D, E, H, or L, assembled as follows
in the object code:

Register ~'

A • 111
B • 000
C • 001
D • 010
E • 011
H • 100
L • 101

11 CYCLES: 1 T STATES: 4 4 MHZ E. T .: 1. 0

Condition Bits Affected: None

Example:

If the H register contains the number 8AH, and the E

register contains 10H, the instruction

LD H, E

would result in both registers containing 10H.

27
 LD r. n

Operation: r~n

Forma t:

Operands

LD r, n

Ia: o~r~< <01

I" : In: : : .. I
Description:

The eight-bit integer n is loaded into any register r,

where r identifies register A, B, C, D, E, H or L.
assembled as follows in the object code:

Register

A - 111
B - 000
C - 001
D - 010
E - all
H - 100
L - 101

~I CYCLES: 2 T STATES: 7(4,3) 4 MHZ E. T .: 1. 7 S

Condition Bits ~ffected: None

Example:

After the execution of

LD E, ASH

the contents of register E will be ASH.

28
LD r, (HLJ

Operation: r +- (HL)
Format:

Operands

LD r. (HL)

Description:

The eight-bit contents of memory location (HL) are

loaded into register r. where r identifies register A.
B. C. D. E. H or L. assembled as follows in the object
code:

Register r

A - III
B - 000
C - 001
D - 010
E - 011
H - 100
L - 101

11 CYCLES: 2 T STATES: 7(4.3) 4 MHZ E. T .: 1. 75

Condition Bits Affected: None

Example:

If register pair HL contains the number 75A1H. and

memory address 75A1H contains the byte 58H. the
execution of

LD C. (HL)

will result in 58H in register C.

29
 LD r, CIX+dJ

Operation: r+-(IX+d)

Format:

Operands

LD r. (IX+d)

I <<a: <<< d 0: DD

1
0:17-7 7--7< <a I
r

I : : :d: : : :. "I

Description:

The operand (IX+d) (the contents of the Index Register

IX summed with a two's complement displacement integer
d) is loaded into register r. where r identi£ies
register A. B. C. D. E. H or L. assembled as follows in
the object code:

Register !.
A = III
B .. 000
C .. 001
D .. 010
E .. 011
H .. 100
L ~ 101

M CYCLES: 5 T STATES: 19(4.4.3.5.3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

Example:

If the Index Register IX contains the number 25AFH. the

instruction

30
 LD B, (IX+19H)

will cause the calculation of the sum 25AFH + 19H, which

points to memory location 25C8H. If this address
contains byte 39H, the instruction will result in
register B also containing 39H.

31
 LD r, (IY +dJ

Operation: r ~ (IY+d)

Format:

Operands

LD r, (IY+d)

11.> >>>>:a >I FD

I0:1~<-~.1 :1: 0I
I .. :.\:< : : : I
Description:

The operand (IY+d) (the contents of Jhe Index Register

IY summed with a two's complement diiplacement integer
d) is loaded into register r, where r identifies
register A, B, C, D, E, H or L, assembled as follows in
the object code:

Register !:.

A .. 111
B .. 000
C .. 001
DOlO
E .. 011
H .. 100
L .. 101

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

32
Example:

If the Index Register IY contains the number 25AFH. the

instruction

LD B. (IY+19H)

will cause the calculation of the sum 25AFH + 19H. which

points to memory location 25C8H. If th~s address
contains byte 39H. the instruction will result in
register B also containing 39H.

33
 LD CHL1, r

Operation: (HL) ~ r

Format:

Opcode Operands

LD (HL), r

I0: 1 : 1 : 1 : 0 ~r~1
Description:

The contents of register r are loaded into the memory

location specified by the contents of thellL register
pair. The symbol r identifies register A, B, C, D, E, H
or L, assembled as follows in the object code:

Register

A - 111
B - 000
C - 001
D - 010
E - all
H - 100
L - 101

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E. T .: 1. 75

Condition Bits Affected: None

Example:

If the contents of register pair HL specifies memory

location 2146H, and the B register contains the byte
29H, after the execution of

LD (HL), B

memory address 2146H will also contain 29H.

34
LD (IX +dJ, r

Operation: (IX+d) ~ r

Format:

Opcode Operands

LD (IX+d), r

>: >>>: >I

11 0 0 DD

1>>>:a :-7r~1
0

I~<:: >1
Description:

The contents of register r are loaded into the memory

address specified by the contents of Index Register IX
summed with d, a two's complement displacement integer.
The symbol r identifies register A, B, C, D, E, H or L,
assembled as follows in the object code:

Register r

A • 111
B • 000
C • 001
D • 010
E'· 011
H • 100
L • 101

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

35
Example:

If the C register contains the byte lCH, and the Index

Register IX contains 3100H, then the instruction

LD (IX+6H), C

will perform the sum 3100H + 6H and will load lCH into
memory location 3106H.

36
LD CIY+dJ, r

Operation: (IY+d) +- r

Format:

Operands

LD (IY+d), r

11 >>>>>:a >I FD

Ia: <<<o7---;r+-1
1< : :< ::. I
Description:

The contents of register r are loaded into the memory

address specified by the sum of the contents of the
Index Register IY and d, a two's complement displacement
integer. The symbol r is specified according to the
following table.

Register

A - 111
B - 000
C - 001
D - 010
E - 011
H - 100
L - 101

U CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

37
Example:

If the C register contains the byte 48H, and the Index

Register IY contains 2AIIH, then the instruction

LD (IY+4H), C
will perform the sum 2AIIH + 4H, and will load 48H into
memory location 2A15.

38
LD (HLJ, n

Operation: (HL) <-n

Format:

Opcode Operand

LD (HL) ,n

Ia : a >>:a >>:a I 36

I" : In: : : : I
Description:

Integer n is loaded into the memory address specified by

the contents of the HL register pair.

M CYCLES: 3 T STATES: 10(4,3,3) 4 UHZ E. T .: 2. 50

Condition Bits Affected: None

Example:

If the HL register pair contains 4444H, the instruction

LD (HL), Z8H

will result in the memory location 4444a containing the

byte Z8H.

39
 LD CIX+dJ, n

Operation: (tX+d) ~n

Format:

Opcode Operands

LD (IX+d), n

< >>> >

I 1 :0 :a I DO

< <
I a: a: <a: <0 I 36
I~<:: ;'1
1~n1 : : >1
Description:

The n operand is loaded into the memory address

specified by the sum of the contents of the Index
Register IX and the two's complement displacement
operand d.

M CYCLES: 5 T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition'Bits Affected: None

Example:

If the Index Register IX contains the number 219AH the

instruc tion

LD (IX+5H), 5AH

would result in the byte 5AH in the memory address

219FH.

40
LD (IY +dJ, n

Operation: (IY+d) +-n

Format:

Operands

LD (IY+d) ,n

11»»»>1 FD

I >>>;a >>:a I
0 36

I'; : :<: : >1

1 II In: : : >1
Description:

Integer n is loaded into the memory location specified

by the contents of the Index Register summed with the
two's complement displacement integer d.

M CYCLES: T STATES: 19(4,4,3,5,3) MHZ E.T.: 4.75

Condition Bits Affected: NONE

Example:

If the Index Register IY contains the number A940H, the

instruction

LD (IY+10H), 97H

would result in byte 97 in memory location A950H.

41
 LD A, (ESC)

Operation: A ~ (Be)

Format:

Opcode Operands

LD A. (BC)

Description:

The contents of the memory location specified by the

contents of the BC register pair are loaded into the
Accumulator.

U CYCLES: 2 T STATES: 7(4.3) 4 MHZ E. T .: 1, 75

Condition Bits Affected: None

Example:

If the BC register pair contains the number 4747H. and

memory address 4747ll contains the byte 12H. then the
instruc tion

LD A. (BC)

will result in byte 12H in register A.

42
LD A, (DE)

Operation: A +- (DE)

Format:

Opcode Operands

LD A, (DE)

Description:

The contents of the memory location specified by the

register pair DE are loaded into the Accumulator.

11 CYCLES: 2 T STATES: 7(4,3) 4 UHZ E. T .: 1. 75

Condition Bits Affected: None

Example:

If the DE register pair contains the number 30A2H and

memory address 30A2H contains the byte 22H, then the
instruction

LD A, (DE)

will result in byte 22H in register A.

43
 LD A, (nn)

Operation: A ..... (nn)

Format:

Operands

LD A, (nn)

I0 : 0 >>: 1 : '0 : 1 : 0 I 3A

I~n(::: I
I~n( : : ;'1
Descript Lon:

The contents of the memory location specified by the

operands nn are loaded into the Accumulator. The first
n operand after the op code is the low ordder byte of a
two-byte memory address.

M CYCLES: 4 T STATES: 13(4,3,3,3) 4 MHZ E.T.: 3.25

Condition Bits Affected: None

Example:

If the contents of nn is number 8832H, and the content

of memory address 8832H is byte 04H, after the
instruction

LD A, (nn)

byte 04H will be in the Accumulator.

44
LD (BCl, A

Operation: (BC) +- A

Format:

Opcode Operands

LD (BC) ,A

Description:

The contents of the Accumulator are loaded into the

memory location specified by the contents of the
register pair BC.

11 CYCLES: 2 T STATES: 7(4,3) 411HZ E. T .: 1. 75

Condition Bits Affected: None

Example:

If the Accumulator contains 7AH and the BC register pair

contains 1212H the instruction

LD (BC),A

will result in 7AH being in memory location 12120.

45
 LD (DE), A

Opera tion: (DE) +- A

Format:

Operands

LD (DE) ,A

Description:

The contents of the Accumulator are loaded into the

memory location specified by the contents of the DE
register pair.

M CYCLES: 2 T STATES: 7(4,3) 4 MHZ E.T.: 1.75

Condition Bits Affected: None

Example:

If the contents of register pair DE are 1128H, and the

Accumulator contains byte AOH, the instruction

LD (DE) ,A

will result in AOH being in memory location 1128H.

46
LD (nnJ, A

Operation: (nn)+-A

Format:

Operands

LD (nn) ,A

I 0 ;a >>;a ;a >: I 0 32

l~nJ : : .. I
l~nJ : : >1
Description:

The contents of the Accumulator are loaded into the

memory address specified by the operand nn. The first n
operand after the op code is the low order byte of nn.

M CYCLES: 4 T STATES: 13(4,3,3,3) 4 MHZ E.T.: 3.25

Condition Bits Affected: None

Example:

If the contents of the Accumulator are byte D7H, after

the execution of

LD (3141H),A

D7H will be in memory location 3141H.

47
 LD A,

Operation: A~I

Format:

Operands

LD A, I

11>:1: >>: 0 0: I ED

I r:
0 :1:0 :1:0 : 1: 1 I 57

Description:

The contents of the Interrupt Vector Register I are

loaded into the Accumulator.

H CYCLES:2 T STATES: 9(4,5) 4 HHZ EoT.: 2.25

Condition Bits Affected:

S: Set if I-Reg. is negative;

reset otherwise
Z: Set if I-Reg. is zero;
reset otherwise
H: Reset
p/v: Contains contents of IFF2
N: Reset
C: Not affected

Note:

If an interrupt occurs during execution of this

instruction, the Parity flag will contain a O.

48
LD A, R

Operation: A+-R

Format:

Operands

LD A,R

\1 >>: >>: >I 0 0 ED

Ia; < 0: <<<< I 1 5F

Description:

The contents of Memory Refresh Register R are loaded

into the Accumulator.

N CYCLES: 2 T STATES: 9(4,5) 4 MHZ EoT.: 2.25

Condition Bits Affected:

S: Set if R-Reg. is negative;

reset otherwise
Z: Set if R-Reg. is zero;
reset otherwise
II: Reset
P/V: Contains contents of IFF2
N: Reset
c: Not affected

49
 LD I J A

Operation: I +-A

Format:

Operands

LD I,A

I<<<a: << >I 0 ED

Ia: < a: a: << I

0: 1 47

Description:

The contents of the Accumulator are loaded into the

Interrupt Control Vector Register, I.

N CYCLES: 2 T STATES: 9(4,5) 4 NHZ EoT.: 2. 25

Condition Bits Affected: None

50
LD R, A

Operation: R+-A

Format:

Operands

LD R,A

I<<<a; <<a; 1 I ED

I0: <n: 0: <<<1I 4F

Description:

The contents of the Accumulator are loaded into the

Memory Refresh register R.

M CYCLES: 2 T STATES: 9(4,5) 4 MHZ E.T.: 2.25

Condition Bits Affected: None

51
-16 BIT LOAD GROUP-

52
LD dd, nn

Operation: dd~nn

Fo rma t:

Operands

LD dd,

Ia : a : d: d: 0: a : a: 1I
I .. : In: : : .. I
1 : : In: : : .. I
Description:

The two-byte integer nn is loaded into the dd register

pair, where dd defines the BC, DE, HL, or SP register
pairs, assembled as follows in the object code:

Pair dd

BC 00
DE 01
HL 10
SP 11

The first n operand after the op code is the low order

byte.

M CYCLES: T STATES: 10(4,3,3) 4 MHZ E.T.: 2.SO

Condition Bits Affected: None

Example:

After the execution of

LD HL, SOOOH

the contents of the 8L register pair will be SOOOH.

53
 LD IX, nn

Operation: IX +- nn

Format:

Operands

LD I X, nn

1 >: >>>: >I

0 0 DO

o: 0 :<a: >I 0: 0: 0 21

.. I In: : : >1
., I In: II .. I
Description:

Integer nn is loaded into the Index Register IX. The

first n operand after the op code is the low order byte.

H CYCLES: T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Condition Bits Affected: None

Example:

After the instruction

LD IX,45A2H

the Index Register will contain integer 45A2H.

54
LD IY, nn

Operation: IV ~ nn

Format:

Operands

LD IY,nn

<1:1:1:1:1:0>1 FD
o: 0:<0:0:0:0 21 >1

.. I In: : : >1
.. I In: :: >1
Description:

Integer nn is loaded into the Index Register IY. The

first n operand after the op code is the low order byte.

M CYCLES: T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Condition Bits Affected: None

Example:

After the instruction:

LD IY,7733H

the Index Register IY will contain the integer 7733H.

55
 LD HL, (nn]

Operation: H ~ (nn+1). L~ (nn)

Format:

Operands

LD HL, (nn)

I 0: 0: 1: 0: 1: 0: 1:0 I 2A

l" : :n( : : .. I
I .. : : n( : : .. I
Description:

The contents of memory address (nn) are loaded into the

low order portion of register pair HL (register L), and
the contents of the next highest memory address (nn+l)
are loaded into the high order portion of HL (register
H). The first n operand after the op code is the low
order byte of nn.

M CYCLES: T STATES: 16(4,3,3,3,3) 4 MHZ E.T.: 4.00

Condition Bits Affected: None

Example:

If address 4545H contains 37H and address 4546H contains

AIH after the instruction

LD HL,(4545H)

the HL register pair will contain A137H.

56
LD dd, (nn)

Operation: ddH'~-(nn+1) ddL,*-(nn)

~:

Operands

LD dd,(nn)

1:1:1:0':1:1:0:11 ED

0:1:«1:0:1:11
.. : In: : : .. I
.. : In: : : .. I
Description

The contents of address (nn) are loaded into the low

order portion of register pair dd, and the contents of
the next highest memory address (nn+l) are loaded into
the high order portion of dd. Register pair dd defines
BC, DE, HL, or SP register pairs, assembled as follows
in the object code:

Pair dd

BC 00
DE 01
HL 10
SP 11

The first n operand after the op code is the low order

byte of (nn).

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MH~ E.T.: 5.00

Condition Bits Affected: None

57
Example:

If Address 2130H contains 65H and address 2131M contains

78H after the instruction

LD BC .. (2130H)

the BC register pair will contain 7865H.

58
LD IX, (nn)

Operation: IXH +- (nn+lt IXL +- (nn)

Format:

Operands

LD IX, (nn)

1: 1:0: 1: 1: 1:0: 1 DD

o: 0 : 1 : 0: 1 : 0 : 1 : 0 2A

': : : n: : : : I

.; .. In: : : ;.
Description:

The contents of the address (nn) are loaded into the low
order portion of Index Register IX, .and the contents of
the next highest memory address (nn+l) are loaded into
the high order portion of IX. The first n operand after
the op code is the low order byte of nn.

M CYCLES: T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affected: None

Example:

If address 6666H contains 92H and address 6667H contains

DAH, after the instruction

LD IX,(6666H)

the Index Register IX will contain DA92H.

59
 LD IY, (rnnJ

Operation: IYH+-(nn+1). IYL+-(nn)

Format:

Operands

LD IY, (nn)

«««0>1 FD

a; a; <a; <a; < 01 2A

.; ; :n:: : >1
.;; In::: ;'1
Description:

The contents of address (nn) are loaded into the low

order portion of Index Register IY, and the contents of
-the next highest memory address (nn+l) are loaded into
the high order portion of IY. The first n operand afte.r
the op code is the low order byte of nne

M CYCLES: T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affected: None

Example:

If address 6666H contains 92H and address 6667H contains

DAH, after the instruction

LD !Y, (6666H)

t-he Index Register I'Y will contain DA92H.

60
LD (nn], HL

Operation: (nn+1) +- H .. (nn)+- L

Operands

LD (nn).HL

1 0: 0: I; 0: .0;0: 1:01 22
I.. II n11 II II
I.. : :<1"1 .. I
Description:

The contents of the low order portion of register pair

HL (register L) are loaded into memory address (ntt) • and
the contents of the high order portion of HL (register
H) are loaded into the next highest· memory address
(nn+l). The first n operand after the op code is t'he
low order byte of iln.

M CYCLES: TS TATES: 16 (4,3.3.3,3) 4 MHZ E.T.: 4.00

Condition Bits Af£et~ed: None

Example:

If the content of register pair HL is 483AH. aft,er' the

instruction

LD (B229H).HL

address B229H) will contain 3AH. "and address B22AH will

contain 48H.

61
 LD (nn). de

Operation: (nn+1)+-ddH. (nn)+-ddL

Format:

Operands

LD (nn) ,dd

1> :1:0; 1:<0: ED

0;1:«0:0;1:
.. : In: : : ..
.; : In; : : ;.
Description:

The low order byte of register pair dd is loaded into

memory address (nn); the upper byte is loaded into
memory address (nn+l). Register pair dd defines either
BC, DE, HL, or SP, assembled as follows in the object
code:

BC 00
DE 01
HL 10
SP 11

The first n operand after the op code is the low order

byte of a two byte memory address.

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E~T.: 5.00

Condition Bits Affected: None

62
Example:

If register pair BC contains the number 4644H, the

instruction

LD (lOOOH),BC

will result in 44H in memory location lOOOH, and 46H in

memory location lOOlH.

63
 LD (nn), IX

Operation: (nn+1) ~ IXH. (nn) ~ IXL

Format:

Operands

LD (nn) ,IX

1 >: >:0: 1 1 : 0: 1 I DD

o: 0: 1: 0: 0: 0: 1: 0 1 22
.; : In: : : >1
.; : In: : : .. I
Description

The low order byte in Index Register IX is loaded into

memory address (nn); the upper order byte is loaded into
the next highest address (nn+1). The first n operand
after the op code is the low order byte of nn.

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affected: None

Example:

If the Index Register IX contains 5A30H, after the

instruction

LD (4392H) ,IX

memory location 4392H will contain number 30H and

location 4393H will contain 5AH.

64
LD (nnl, IV

Operation: (nn+1) ~ IYH. (nn) ~ IYL

~:

Operands

LD (nn), IY

11 >>:1: 1>:0: 1 1 FD

I0: 0: 1:0: 0; 0: 1:0 1 22

I.. : :ni::"1
1< : In:: : ;. I
Description:

The low order byte in Index Register IY is loaded into

memory address (nn); the upper order byte is loaded into
memory locat,ion (nn+l). The first n operand after the
op code is the low order byte of nn.

M CYCLES: 6 T STATES: 20(4,4,3,3,3,3) 4 MHZ E.T.: 5.00

Condition Bits Affected: None

Example:

If the Index Register IY contains 4174H after the

instruction

LJI (8838H), IY

memory location 8838H will cont.ain number 74Hand memory

location 8839H will contain 41H.

65
 LD BP, HL

Operation: SP+-HL

Format:

Opcode Operands

LD SP,HL

Description:

The contents of the register pair HL are loaded into tht

Stack Pointer SP.

M CYCLES: T STATES: 6 4 MHZ E. T .: L 50

Condition Bits Affected: None

Example:

If the register pair HL contains 442EH, after the

instruction

LD SP,HL

the Stack Pointer will also contain 442EH.

66
LD BP, IX

Operation: SP ~ IX

Format:

Operands

LD SP,IX

11 >:a >>>;a >' DO

11 >>>>:a :a >I F9

Description:

The two byte contents of Index Register IX are loaded

into the Stack Pointer SP.

M CYCLES: T STATES: 10(4,6) 4 MHZ E.T.: 2.50

Condition Bits Affected: None

Example:

If the contents of the Index Register IX are 98DAH,

after the instruction

LD SP,IX

the contents of the Stack Pointer will also be 98DAH.

67
 LD BP, IV

Operation: SP ~ IV

Format:

Opcode Operands

LD SP,IY

11>>>>>;a >I FD

I<<<<<a; >I 0 F9

Description:

The two byte contents of Index Register IY are loaded

into the Stack Pointer SP.

H CYCLES: T STATES: 10(4,6) 4 MHZ E. T .: 2 • 50

Condition Bits Affected: None

Example:

If Index Register IY contains the integer A227H, after

the instruc tion

LD SP,IY

the Stack Pointer will also contain A227H.

68
PUSH qq

PUSH qq

Operation: (SP-2)~qqL. (SP-1)~qqH

Format:

Operands

PUSH qq

11 :1:q : q :0 : 1:0 : 1 I
De!ilcription:

The contents of the register pair qq are pushed into the

external memory LIFO (last-in. first-out) Stack. The
Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first decrements th~ ~p and loads the high
order byte of register pair qq into the memory address
now specified by the SP; then decrements the SP again
and loads the low order byte of qq into the memory
location corresponding to this new address in the SP.
The operand qq identifies register pair BC. DE. RL. or
AF. assembled as follows in the object code:

Pair qq

BC 00
DE 01
HL 10
AF 11

M CYCLES: T STATES: 11(5.3.3) 4 MHZ E. T.: 2.75

Condition Bits Affected: None

Example:

If the AF register pair contains 2233H and the Stack

Pointer contains 1007H. after the instruction

PUSH AF

memory address 1006H will contain 22H. memory address

1005H will contain 33H. and the Stack Pointer will
contain 1005H.

69
 PUSH IX

Operation: (SP-2) ~ IXL. (SP-1) ~ IXH

Format:

Opcode Operands

PUSH IX

11 :1:0 >>>:a >I DO

11 :1 >: >:a >I

0 :0 E5

Description:

The contents of the Index Register IX are pushed into

the external memory LIFO (last-in, first-out) Stack.
The Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first decrements the SP and loads the high
order byte of IX into the memory address now specified
by the SP; then decrements the SP again and loads the
low order byte into the memory location corresponding to
this new address in the SP.

M CYCLES: T STATES: 15(4,5,3,3) 411HZ E. T .: 3. 75

Condition Bits Affected: None

Example:

If the Index Register IX contains 2233H and the Stack

Pointer contains 1007H, after the instruction

PUSH IX

memory address 1006H will contain 22H, memory address

1005H will contain 33H, and the Stack Pointer will
contain 1005H.

70
PUSH IV

Operation: (SP-2) +-IYL, (SP-1) +-IYH

Format:

Opcode Operands

PUSH IY

>>: >I
11 : 1 : 1 : 1 0 FD

11 :1>: >: >I

0 :0 0 E5

Description:

The contents of the Index Register IY are pushed into

the external memory LIFO (last-in, first-out) Stack~
The Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first decrements the SP and loads the high
order byte of IY into the memory address now specified
by the SP; then decrements the SP again and loads the
low order byte into the memory location corresponding to
this new address in the SP.

M CYCLES: T STATES: 15(4,5,3,3) MHZ E. T .: 3. 75

Condition Bits Affected: None

Example:

If the Index Register IY contains 2233H and the Stack

Pointer contains 1007H, after the instruction

PUSH IY

memory address l006H will contain 22H, memory address

1005H will contain 33H, and the Stack Pointer will
contain 1005H.

71
 POP qq

Operation: qqH ~ (SP+1). qqL ~ (SP)

Format:

Operands

POP qq

Description:

The top two bytes of the external memory LIFO (last-in,

first-out) Stack are popped into register pair qq. The
Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first loads into the low order portion of
qq, the byte at the memory location corresponding to the
contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of qq and the SP is now
incremented again. The operand qq identifies register
pair BC, DE, HL, or AF, assembled as follows in the
object code:

Pair !:.

BC 00
DE 01
HL 10
AF 11

M CYCLES: T STATES: 10(4,3,3) 4 MHZ E.T.: 2.50

Condition Bits Affected: None

72
Example:

If the Stack Pointer contains IOOOH, memory location

IOOOH contains 55H, and location IOOIH contains 33H, the
instruction

POP HL

will result in register pair HL containing 3355H, and

the Stack Pointer containing I002H.

73
 POP IX

Operation: IXH +- (SP+1), IXL +- (SP)

Format:

Operands

POP IX

11 :1:0 >>>:0 >I DD

P;1 >;0 ;0 ;0 ;0 >, E1

Description:

The top two bytes of the external memory LIFO (last-in,

first-out) Stack are popped into Index Register IX. The
Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first loads into the low order portion of IX
the byte at the memory location corresponding to the
contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of IX. The SP is now
incremented again.

M CYCLES: T STATES: 14(4,4,3,3) 4 M8Z E. T .: 3. 50

Condition Bits Affected: None

Example:

If the Stack Pointer contains 10008, memory location

10008 contains 558, and location 10018 contains 338, the
instruc tion

POP IX

will result in Index Register IX containing 33558, and

the Stack Pointer containing 10028.

74
POP IY

Operation: IYH +- (SP+1). IYL +- (SP)

Forma t:

Operands

POP IY

1«««0>1 FD

1«<0;0;0:0>1 E1

Description:

The top two bytes of the external memory LIFO (last-in,

first-out) Stack are popped into Index Register IY. The
Stack Pointer (SP) register pair holds the 16-bit
address of the current "top" of the Stack. This
instruction first loads into the low order portion of IY
the byte at the memory location corresponding to the
contents of SP; then SP is incremented and the contents
of the corresponding adjacent memory location are loaded
into the high order portion of IY. The SP is now
incremented again.

M CYCLES: T STATES: 14(4,4,3,3) 4 MHZ E. T .: 3. 50

Condition Bits Affected: None

Example:

If the Stack Pointer contains 1000H, memory location

1000H contains 55H, and location 1001H contains 33H, the
instruc tion

POP IY

will result in Index Register IY containing 3355H, and

the Stack Pointer containing 1002H.

75
-EXGlAr'lJ[, BLOCK TRANSFER AND SEARGI GROUP-

76
EX DE. HL

Operation: DE # HL

Format:

Operands

EX DE.HL

Description:

The two-byte contents of register pairs DE and HL are

exchanged.

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: LOO

Condition Bits Affected: None

Example:

If the content of register pair DE is the number 2822H.

and the content of the register pair HL is number 499AH.
after the instruction

EX DE.HL

the content of register pair DE will be 499AH and the

content of register pair HL will be 2822H.

77
 EX AF, AF'

Operation: AF ~ AF
Format:

EX AF,AF'

Description:

The two-byte contents of the register pairs AF and AF'

are exchanged. (Note: register pair AF' consists of
registers A' and F'.)

M CYCLES: T STATES: 4 4 MHZ E.T.: l.00

Condition Bits Affected: None

Example:

If the content of register pair AF is number 9900H, and

the content of register pair AF' is number 5944H, after
the instr uc t ion

EX AF,AF'

the contents of AF will be 5944H, and the contents of

AF' will be 9900H.

78
EXX

Operation: (BC) +> (BC'), (DE) +> (DE'), (HL) +> (HL')

Format:

Opcode Operands

EXX

Description:

Each two-byte value in register pairs BC, DE, and HL is

exchanged with the two-byte value in BC', DE', and HL',
respectively.

M CYCLES: 1 T STATES: 4 4 MHZ E. T .: 1. 00

Condition Bits Affected: None

Example:

If the contents of register pairs BC, DE, and HL are the

numbers 445AH, 3DA2H, and 8859H, respectively, and the
contents of register pairs BC', DE', and HL' are 0988H,
9300H, and OOE7H, respectively, after the instruction

EXX
the contents of the register pairs will be as follows:
BC: 0988H; DE: 9300H; HL: OOE7H; BC': 445AH; DE': 3DA2H;
and HL': 8859H.

79
 EX (SPJ, HL

Operation: H+>(SP+1) .. l+>(SP)

Format:

Operands

EX (SP) ,HL

Description:

The low order byte contained in register pair HL is

exchanged with the contents of the memory address
specified by the contents of register pair SP (Stack
Pointer), and the high order byte of HL is exchanged
with the next highest memory address (SP+l).

M CYCLES: 5 T STATES: 19(4,3,4,3,5) 4 MHZ E.T.: 4.75

Condition Bits Affected: None

Example:

If the HL register pair contains 7012H, the SP register

pair contains 8856H, the memory location 8856H contains
the byte IIH, and the memory location 8857H contains the
byte 22H, then the instruction

EX (SP),HL

will result in the HL register pair containing number

2211H, memory location 8856H containing the byte 12H,
the memory location 8857H containing the byte 70H and
the Stack Pointer containing 8856H.

80
EX (SPJ, IX

Operation: IXH -++ (SP+11, IXL -++ (SP)

Format:

Opcode Operands

EX (SP),IX

I <<a: <<< >I 0 DD

I <<<a: a: a: < I. 1 E3

Description:

The low order byte in Index Register IX is exchanged

with the contents of the memory address specified by the
contents of register pair SP (Stack Pointer), and the
high order byte of IX is exchanged with the next highest
memory address (SP+1).

M CYCLES: 6 T STATES: 23(4,4,3,4,3,5) 4 MHZ E.T.: 5.75

Condition Bits Affected: None

Example:

If the Index Register IX contains 3988H, the SP register

pair contains 0100H, the memory location 0100H contains
the byte 90H, and memory location 0101H contains byte
48H, then the instruction

EX (SP),IX

will result in the IX register pair containing number

48908, memory location 0100H containing 88H, memory
location 0101H containing 39H and the Stack Pointer
containing 0100H.

81
 EX (SPJ. IY

Operation: IYH ~ (SP+1), IYL ~ (SP)

Format:

Operands

EX (SP) .IY

1«««<11 FD

I <<<a; a; a; < 11 E3

Description:

The low order byte in Index Register IY is exchanged

with the contents of the memory address specified by the
contents of register pair SP (Stack Pointer). and the
high order byte of IY is exchanged with the next highest
memory address (SP+l).

M CYCLES: 6 T STATES: 23(4.4.3.4.3.5) 4 MHZ E.T.: 5.75

Condition Bits Affected: None

Example:

If the Index Register IY contains 3988H. the SP register

pair contains OlOOR. the memory location OlOOH contains
the byte 90ll. and memory location OlOlH contains byte
48H. then the instruction

EX (SP). IY

will result in the IY register pair containing number

4890H. memory location OlOOH containing 88H. memory
location OlOlH containing 39H. and the Stack Pointer
containing OlOOH.

82
LDI

Operation: (DE)+-(HLl. DE+-DE+l. HL+-HL+l. BC+-BC-l

Format:

Ope ode Operands

LDI

11 >: 1: >>: >

0 0 I ED

11: 0: 1: 0: 0: 0: 0: 0I AO

Description:

A byte of data is transferred from the memory location

addressed by the contents of the ilL register pair to the
memory location addressed by the contents of the DE
register pair. Then both these register pairs are
incremented and the BC (Byte Counter) register pair is
decremented.

H CYCLES: 4 T STATES: 16(4,4,3,5) 4 HHZ E. T .: 4. 00

Condition Bits Affected:

- --------------
S: Not affected
Z: Not affected
li: Reset
P/V: Set if BC-1,O;
reset otherwise
N: Reset
C: Not affected

83
Example:

If the HL register pair contains llllH, memory location

llllH contains contains the byte 88H, the DE register
pair contains 2222H, the memory location 2222H contains
byte 66H, and the BC register pair contains 7H, then the
instruction

LDI

will result in the following contents in register pairs

and memory addresses:

HL 11l2H
(llllH) 88H
DE 2223H
(2222H) 88H
BC 6H

84
LDIR
LDIR

Operation: (DE)~(HLI. DE~DE+1. HL~HL+1. BC~BC-1

Forma t:

Operands

LDIR

11: 1: 1: 0: r: 1: 0: 1I ED
I r: 0: 1: 1: 0: 0: 0: 0I BO

Description:

This two byte instruction transfers a byte of data from

the memory location addressed by the contents of the HL
register pair to the memory location addressed by the DE
register pair. Then both these register pairs are
incremented and the BC (Byte Counter) register pair is
decremented. If decrementing causes the BC to go to
zero, the instruction is terminated. If BC is not zero
the program counter is decremented by 2 and the
instruction is repeated. Interrupts will be recognized
and two refresh eyeless will be executed after each data
transfer. Note that if BC is set to zero prior to
instruction execution, the instruction will loop through
64K bytes.

For BC-O:

M CYCLES: T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25

For BC=O:

M CYCLES: T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

85
Condition Bits Affected:

s: Not affected
Z: Not affected
H: Reset
P/V: Reset
N: Reset
C: Not affected

Example:

If the HL register pair contains IIIIH, the DE register

pair contains 2222H, the BC register pair contains
0003H, and memory locations have these contents:

(llllH) aaH (2222H) 66H

(l1l2H) 36H (2223H) 59H
(l1l3H) A5H (2224H) C5H

then after the execution of

LDIR

the contents of register pairs and memory locations will

be:

HL 11l4H
DE 2225H
BC oooon
(llllH) a8H (2222H) 8aH
(l1l2H) 36H (2223H) 36H
(l1l3H) A5H (2224H) A5H

86
LDD

Operation: (DE)~(HL), DE~DE-1. HL~HL-1. BC~BC-1

Format:

Opcode Operands

LDD

I <1: <0: 1: <0: 11 ED

I 1: 0: <0: 1: 0: 0: 0I A8
Descripttion:

This two byte instruction transfers a byte of data from

the memory location addressed by the contents of the HL
register pair to the memory location addressed by the
contents of the DE register pair. Then both of these
register pairs including the BC (Byte Counter) register
pair are decremented.

~l CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Not affected
z: Not affected
H: Reset
p/v: Set if BC-1~O;
reset otherwise
N: Reset
C: Not affected

87
Example:

If the HL register pair contains IIIIH, memory location

IIIIH contains the byte 88H, the DE register pair
contains 2222H, memory location 2222H contains byte 66H,
and the BC register pair contains 7H, then the
instruction

LDD

will result in the following contents in register pairs

and memory addresses:

HL UIOH
(UIIH) 88H
DE 222lH
(2222H) 88H
BC 6H

88
LDDR

Operation: (DE)+-(HL)~ DE+-DE-1,. HL+-HL-1. BC+-BC-1

~:

Operands

LDDR

1«««0>1 ED

I<a: <<<a: a: I 0 B8
Description:

This two byte instruction transfers a byte of data from

the memory location addressed by the contents of the HL
register pair to the memory location addressed by the
contents of the DE register pair. Then both of these
registers as well as the BC (Byte Counter) are
decremented. If decrementing causes the BC to go to
zero, the instruction is terminated. If BC is not zero,
the program counter is decremented by 2 and the
instruction is repeated. Interrupts will be recognized
and two refresh eyeless will be executed after each data
transfer. Note that if BC is set to zero prior to
instruction execution, the instruction will loop through
64K bytes.

For BC-O:

M CYCLES: T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25

For BC-O:

M CYCLES: T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Reset
P/V: Reset
N: Reset

89
Example:

If the HL register pair contains 1114H. the DE register

pair contains 2225H. the BC register pair contains
0003H. and memory locations have these contents:

( 1114H) A5H (2225H) C5H

(l113H) 36H (2224H) 59H
(l112H) SSH (2223H) 66H

then after the execution of

LDDR

the contents of register pairs and memory locations will

be:

HL lll1H
DE 2222H
BC OOOOH

(l114H) A5H (2225H) A5H

(l113H) 36H (2224H) 36H
(l112H) SSH (2223H) SSH

90
CPI

Operation: A-(HLI. HL~HL+1. BC~BC-1

Operands

CPI

I<<< >>:a >I

0 ED

I<0: <a: a: a: 0>I Al

Description:

The contents of the memory location addressed by the HL

register pair is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
is set. Then HL is incremented and the Byte Counter
(register pair BC) is decremented.

M CYCLES: T STATES: 16(4,4,3,5) 4 MHZ E. T.: 4. aa

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if A=(HL);
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
P/V: Set if BC-l=a;
reset otherwise
N: Set
C: Not affected

Example:

If the aL register pair contains IIIIH, memory location

IIIIH contains 3BH, the Accumulator contains 3BH, and
the Byte Counter contains aaalH, then after the
execution of

91
 CPI

the Byte Counter will contain OOOOH, the HL register

pair will contain 1112H, the Z flag in the F register
will be set, and the P/V flag in the F register will be
reset. There will be no effect on the contents of the
Accumulator or address IlllH.

•
CPIR

Operation: A-(HL). HL~HL+1. BC~BC-1

Forma t:

Operands

CPIR

11»:0»:0>1 ED

>
I<0 >:a :a :0 I > B1

Description:

The contents of the memory location addressed by the HL

register pair is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
is set. The HL is incremented and the Byte Counter
(register pair BC) is decremented. If decrementing
causes the BC to go to zero or if A-(HL), the
instruction is terminated. If BC is not zero and
A-(HL), the program counter is decremented by 2 and the
instruction is repeated. Interrupts will be recognized
and two refresh cycles will be executed after each data
transfer. Note that if BC is set to zero before
instruction execution, the instruction will loop through
64K bytes, if no match is found.

For BC=O and A-(HL):

M CYCLES: 5 T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25

For BC-O or A-(HL):

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E. T.: 4.00

•
93
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
z: Set if A-(HL);
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
p/V: Set if BC-I-O;
reset otherwise
N: Set
C: Not affected

Example:

If the HL register pair contains IlllH, the Accumulator

contains F3H, the Byte Counter contains 0007H, and
memory locations have these contents:

(llllH) 52H
(1l12H) OOH
(11l3H) F3H

then after the execution of

CPIR

the contents of register pair HL will be 1114H, the

contents of the Byte Counter will be 0004H, the P/V flag
in the F register will be set and the Z flag in the F
register will be set.

94
CPO

Operation: A-(HLI. HL+-HL-1. BC+-BC-1

~:

Operands

CPD

1«<0»»1 ED

I< >;0 >;0 ;0 >I

0 A9

Description:

The contents of the memory location addressed by the HL

register pair is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
is set. The HL and the Byte Counter (register pair BC)
are decremented.

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E. T.: 4.00

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if A=(HL);
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
p/V: Set if BC-l=O;
reset otherwise
N: Set
C: Not Affected

Example:

If the HL register pair contains IIIIH, memory location

IIIIH contains 3BH, the Accumulator contains 3BH, and
the Byte Counter contains 0001H, then after the
ex'ecution of

95
the Byte Counter will contain OOOOH, the HL register
pair will contain 1110H, the Z flag in the F register
will be set, and the P/V flag in the F register will be
reset. There will be no effect on the contents of the
Accumulator or address llllH.
CPDR

Operation: A-(HL)I HL+-HL-1 1 BC+-BC-1

Format:

Operands

CPDR

1«<0»:0>1 ED

I<0 >>>:0 :0 >I B9

Description:

The contents of the memory location addressed by the HL

register pair is compared with the contents of the
Accumulator. In case of a true compare, a condition bit
is set. The HL and BC (Byte Counter) register pairs are
decremented. If decrementing causes the BC to go to
zero or if A=(HL), the instruction is terminated. If BC
is not zero and A-(HL), the program counter is
decremented by 2 and the instruction is repeated.
Interrupts will be recognized and two refresh eyeless
will be executed after each data transfer. Note that if
BC is set to zero prior to instruction execution, the
instruction will loop through 64K bytes, if no match is
found.

For BC-O and A-(HL):

M CYCLES: 5 T STATES: 21(4,4,3,5,5) 4 MHZ E.T.: 5.25

For BC-O or A-(HL):

M CYCLES: 4 T STATES: 16(4,4,3,5) 4 MHZ E.T.: 4.00

97
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z:i'tet i f A=(HL);
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
P/V: Set if BC-I=O;
reset otherwise
N: Set
C: Not affected

Example:

If the HL register pair contains 1118H, the Accumulator

contains F3H, the Byte Counter contains 0007H, and
memory locations have these contents:

(lll8H) 52H
(1l17H) OOH
(lll6H) F3H

then after the execution of

CPDR

the contents of register pair HL will be 1115H, the

contents of the Byte Counter will be 0004H, the P/V flag
in the F register will be set, and the Z flag in the F
register will be set.

98
•
-8 BIT ARIlHr£rIC AND LCXJlCAL Gf{)UP-

99
ADD A, r

Operation: A +- A +r

Format:

Opcode Operands

ADD A,r

Description:

The contents of register r are added to the contents of

the Accumulator, and the result is stored in the
Accumulator. The symbol r identifies the registers
A,B,C,D,E,H or L assembled as follows in the object
code:

Register

A III
B 000
C 001
D 010
E 011
H 100
L 101

M CYCLES: T STATES: 4 4 MHZ E.T. : 1. 00

Condition Bits Affected:

S: Set if resul t is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
p/V: Set if overflow;
reset otherwise
N: Reset
C: Set if carry from
Bit 7; reset otherwise

100
Example:

If the contents of the Accumulator are 44H, and the

contents of register Care IlH, after the execution of

ADD A,C

the contents of the Accumulator will be 55H.

101
ADD A, n

Operation: A+-A+n

Format:

Opcode Operands

ADD A.n

I<<a: a: a: << I 0 C6

I.. : In: : : .. I
Description:

The integer n is added to the contents of the

Accumulator and the results are stored in the
Accumulator.

M CYCLES: T STATES: 7(4.3) 4 MHZ E. T .: 1. 75

Condition Bits Affected:

s: Set if result is nega,tive;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
P/V: Set if overflow;
reset otherwise
N: Reset
C: Set i f car r y from
Bit 7; reset otherwise

Example:

If the contents of the Accumulator are 23H. after the

execution of

ADD A.33H

the contents of the Accumulator will be 56H.

102
 ADD A, (HLJ

Operation: A ~ A + (HL)

Format:

Opcode Operands

ADD A, (HL)

Description:

The byte at the memory address specified by the contents

of the HL register pair is added to the contents of the
Accumulator and the result is stored in the Accumulator.

M CYCLES: T STATES: 7(4,3) 4 MHZ E. T .: 1. 75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; ~eset otherwise
P/V: Set if overflow;
reset otherwise
N: Reset
C: Set i f car r y from
Bit 7; reset otherwise

Example:
----
If the contents of the Accumulator are AOH, and the
content of the register pair HL is 2323ll, and memory
location 2323H contains byte 08H, after the execution of

ADD A, (HL)

the Accumulator will contain ABH.

103
ADD A, (IX+dJ

Operation: A~A+(IX+d)

Format:

Operands

ADD A, (IX+d)

11 :1: 0 >>>:a >I DD

11 :a: a: a: a:<< I 0 86

I: : :< : : : I
Description:

The contents of the Index Register (register pair IX) is

added to a two's complement displacement d to point to
an address in memory. The contents of this address is
then added to the contents of the Accumulator and the
result is stored in the Accumulator.

M CYCLES: T ~TATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
P/V: Set if overflow;
reset otherwise
N: Reset
C: Set if carry from
Bit 7; reset otherwise

If the Accumulator contents are 11H, the Index Register

IX contains 1000H, and if the content of memory location

104
lOOSH is 22H, after the execution of

ADD A, (IX+SH)

the contents of the Accumulator will be 33H.

'105
ADD A, (IY+dJ

Operation: A+-A+(IY+d)

~:

Operands

ADD A, (IY+d)

11 >>>>>;a >I FD

11 :0 :a :a :a >>: 0 I 86

I~d::: .. ,
Description:

The contents of the Index Register (register pair IY) is

added to a two's complement displacement d to point to
an address in memory. The contents of this address is
then added to the contents of the Accumulator and the
result is stored in the Accumulator.

M CYCLES: T STATES: 19(4,4,3,5,3) 4 MHZ E.T.: 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
P/V: Set if overflow;
reset otherwise
N: Reset
C: Set if carry from bit 7;
reset otherwise

Example:

If the Accumulator contents are IIH, the Index Register

pair IY contains 1000H, and if the content of memory

106
location lOOSH is 22H, after the execution of

ADD A, (I Y+SH)

the contents of the Accumulator will be 33H.

107
ADC A, s

Operation: A+-A+s+CY

Format:

Operands
----
ADC A,s

The s operand is any of r,n,(HL),(IX+d) or (IY+d) as

defined for the analogous ADD instruction. These
various possible opcode-operand combinations are
assembled as follows in the object code:

ADC A, r
>:0 >>~r*:­
ADC A,n
»»»:0 CE

.. : In: : I ;.
ADC A, (HL)
<0:0:0:«<0 8E

ADC A, (IX+d)
»»>:0> DO

;a:a;a»» 8E

.; : >: : : ..
ADC A, (IY+d)
»»>:0> FD

:0;0:0»>:0 8E

I: : :d: : : ;.
*r identifies registers B,C,D,E,H,L or A assembled as
follows in the object code field above:

108
 Register

B 000
C 001
D 010
E all
H 100
L 101
A 111

Description:

The s operand, along with the Carry Flag ("C" in the F

register) is added to the contents of the Accumulator,
and the result is stored in the Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

ADC A,r 1 4 LOa

ADC A,n 2 7(4,3} L 75
ADC A, (HL) 2 7(4,3} L 75
ADC A, (IX+d) 5 19(4,4,3,5,3} 4.75
ADC A,(IY+d} 5 19(4,4,3,5,3} 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
p/V: Set if overflow;
reset otherwise
N: Reset
C: Set if carry from
Bit 7; reset otherwise

Example:

If the Accumulator contains 16H, the Carry Flag is set,

the HL register pair contains 6666H, and address 6666H
contains 10H, after the execution of

ADC A, (HL)

the Accumulator will contain 27H.

109
SUB s

Operation: A+-A-s

Format:

Operands

SUB

The s operand is any of r,n,(HL),(IX+d) or (IY+d) as

defined for the analogous ADD instruction. These
various possible opcode-operand combinations are
assembled as follows in the object code:

SUB r
<a; a; <~ r7- 0

SUB n
<<a; <a; << 0 D6

.; : In: : : ..
SUB (HL)
:a: a: <a: << 0 96

SUB (IX+d)
>;a >>>;a > DD

:a ;a >:a >>;a 96

.; : Id : : : ;.

SUB (IY+d) 11 : 1 : 1 : 1 : 1 : 1 : 0 : 1 FD

11 ; 0 : 0 : 1 : 0 ; 1 : 1 ; 0 96

I.: : :d: : ; : I

*r identifies registers B,C,D,E,H,L or A assembled as

follows in the object code field above:

110
 Register E...
B 000
C 001
D 010
E 011
H 100
L 101
A III

Description:

The s operand is subtracted from the contents of the

Accumulator, and the result is stored in the
Accumulator.

INSTRUCTION M CYCLES STATES 4 MHZ E. T.

SUB r 4 1. 00
SUB n 7 (4,3) 1. 75
SUB (HL) 7 (4,3) 1. 75
SUB (I X+d) 19(4,4,3,5,3) 4.75
SUB (I Y+d) 19(4,4,3,5,3) 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
P/V: Set if overflow;
reset otherwise
N: Set
C: Set if borrow;
reset otherwise

Example:

If the Accumulator contains 29H and register D contains

llH, after the execution of

SUB D

the Accumulator will contain 18H.

111
sac A, s

Operation: A+-A-s-CY

Format:

Opcode Operands

SBC A,s

The s operand is any of r,n,(HL),(IX+d) or (IY+d) as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

SBC A,r
:O:0»~r~
SBC A,n
>:0:««0 DE

.; : In! : : ;.
SBC A, (HL)
>>>>:a
:0 :0 9E

SBC A,(IX+d)
>:0 >>>:0 > DD

9E

I~:d: : : ;.
SBC A,(IY+d)
11 >>>>> ;0 > FD

1
1:°:°;1;1:1:1;° 9E

I : : :< : : ..
*r identifies registers B,C,D,E,H,L or A assembled as
follows in the object code field above:

112
 Register E..
B 000
C 00 1
D 010
E all
H 100
L 101
A III
Description:

The s operand, along with the Carry Flag ("C" in the F

register) is subtracted from the contents of the
Accumulator, and the result is stored in the
Accumulator.

INSTRUCTION H CYCLES STATES 4 MHZ EoT.

SBC A, r 4 1. 00
SBC A,n 7(4,3) 1. 75
SBC A, (HL) 7 (4,3) 1. 75
SBC A, (IX+d) 19(4,4,3,5,3) 4.75
SBC A, (IY+d) 19(4,4,3,5,3) 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
P/V: Set if overflow;
reset otherwise
N: Set
C: Set if borrow;
reset otherwise

Example:

If the Accumulator contains 16H, the carry flag is set,

the HL register pair contains 3433H, and address 3433H
contains 05H, after the execution of

SBC A, (HL)

the Accumulator will contain 10H.

113
AND s

Operation: A ~ A /\ 5

Format:

Opcode Operands

AND

The s operand is any of r,n,(HL),(IX+d) or (IY+d), as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

AND r
l:a>:a :a~r~
AND n
1 >>:a :a >>:a E6

.. : In: : : ;.
AND (HL)
<a: <a: a: << a A6

AND (IX+d)
1>;a >>>;a > DO

<a: r: a: a: << a A6

: : :< : :
AND (IY+d)
>>>>>: a > FD

: a >: r: r: a
0 :0 : A6

.. : :< : : :
*r identifies registers B,G,D,E,D,L or A assembled as
follows in the object code field above:

114
 Register £
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Description:

A logical AND operation is performed between the byte

specified by the s operand and the byte contained in the
Accumulator; the result is stored in the Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

AND r 4 1. 00
AND n 7(4,3) 1. 75
AND (HL) 7(4,3) 1. 75
AND (IX+d) 19(4,4,3,5,3) 4.75
AND (IX+d) 19(4,4,3,5,3) 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set
p/V: Set if parity even;
reset otherwise
N: Reset
C: Reset

Example:

If the B register contains 7BH (0111 1011) and the

Accumulator contains C3H (1100 0011) after the execution
of

AND B

the Accumulator will contain 43H (01000011).

115
OR s

Operation: A ..... A Vs

Format:

Operands

OR

The s operand is any of r,n,(HL),(IX+d) or (IY+d), as

defined for tqe analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

OR r :o»:o~r~
OR n
>>>: >>: 0 0 F6

.; : In: : : ..
OR (HL)
>: <<
:0 :1 0 : 0 86

OR (IX+d)
>: >>>:a:
0 1 DD

>>: >>:
:0 0 0 86

.. : :< : : ..
OR (IY+d) >:a :
:1 :1 :1 :1 1 FD

<a: <<a: << 0 86

.; : :< : : ;.
*r identifies registers B,C,D,E,H,L or A assembled as
follows in the object code field above:

116
 Register E-..
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Description:

A logical OR operation is performed between the byte

specified by the s operand and the byte contained in the
Accumulator; the result is stored in the Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

OR r 4 1. 00
OR n 7 (4,3) 1. 75
OR (HL) 7(4,3) 1. 75
OR (IX+d) 19(4,4,3,5,3) 4.75
OR (I Y+d) 19(4,4,3,5,3) 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Reset

Example:

If the H register contains 48H (010001000) and the

Accumulator contains 12H (00010010) after the execution
of

OR H

the Accumulator will contain 5AH (01011010).

117
XOR s

Operation: A+-Affis

Format:

Operands

XOR

The s operand is any of r,n, (HL),(IX+d) or (IY+d), as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

XOR r
l:a>:a >7-: 7-- r

XOR n
<<<a; <<< 0 EE

.; : In: : : ;.
XOR (HL)
<a; <a; <<< 0 AE

XOR (IX+d)
1 >;a >>>;a > DO

1:0: 1: 0:1:1:1: AE

.; : :<: : ;.
XOR (IY+d)
<<<<<<a; FD

<a; <a; <1: < AE

'1 I : <: I I'

*r identifies registers B,C,D,E,H,L or A assembled as
follows in the object code field above:

118
 Register E.
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Description:

A logical exclusive-OR operation is performed between

the byte specified by the s operand and the byte
contained in the Accumulator; the result is stored in
the Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

XOR r 4 1. 00
XOR n 7(4,3) 1. 75
XOR (HL) 7(4,3) 1. 75
XOR (IX+d) 19(4,4,3,5,3) 4.75
XOR (IY+d) 19(4,4,3,5,3) 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Reset

Example:

If the Accumulator contains 96H (10010110), after the

execution of

XOR 5DH (Note: 5DH = 01011101)

the Accumulator will contain CBH (11001011).

119
CP s

Operation: A- 5

Format:

Operands

CP

The s operand is any of r.n.(HL).(IX+d) or (IY+d). as

defined for the analogous ADD instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

CP r
<0; <<<--:-r;-
CP n
<<<<<<< 0 FE

.; I In! : : ;.
CP (HL)
<a; <<<<< BE
CP (IX+d)
<<a; <<<a; DD

<a; <<1: 1: 1: 0 BE
.; : :< : : : I

CP (IY+d)
«««0> FD
1: 0: 1: 1; 1: 1: 1; 0 BE
.; : :< : : ;.
*r identifies registers B.C.D.E.H.L or A assembled as
follows in the object code field above:

120
 Register !.
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Description:

The contents of the s operand are compared with the

contents of the Accumulator. If there is a true
compare. the Z flag is set. The execution of this
instruction does not affect the contents of the
Accumulator.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

CP r 1 4 LOO
CP n 2 7(4.3) 1.75
CP (HL) 2 7(4.3) L 75
CP (IX+cf) 5 19(4.4.3.5.3) 4.75
CP (IY+d) 5 19(4.4.3.5.3) 4.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
p/V: Set if overflow;
reset otherwise
N: Set
C: Set if borrow;
reset otherwise

Example:

If the Accumulator contains 63H. the HL register pair

c~ntains 6000H and memory location 6000H contains 60H.
the instruction

CP (HL)

will result in the p/V flag in the F register being

reset.

121
INC r

Operation: r~r+1

Format:

Opcode Operands

INC r

Description:

Register r is incremented. r identifies any of the

registers A,B, C,D,E,H or L, assembled as follows in the
obj ect code.

Register r

A 111
B 000
C 001
D 010
E 011
H 100
L 101

M CYCLES: T STATES: 4 4 MHZ E.T.: LOO

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
P/v: Set ~f r was 7FH before
operation; reset otherwise
N: Reset
C: Not affected

122
Example:

If the contents of register Dare 280, after the

execution of

INC D

the contents of register D will be 29H.

123
INC (HLJ

Operation: (HL) ..... (HL)+1

Format:

Opcode Operands

INC (HL)

Description:

The byte contained in the address specified by the

contents of the HL register pair is incremented.

U CYCLES: T STATES: 11(4,4,3) 4 MHZ E. T .: 2.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
P/V: Set if (HL) was 7FH before
operation; reset otherwise
N: Reset
C: Not Af f e c ted

Example:

If the contents of the HL register pair are 3434H, and

the contents of address 3434H are 82H, after the
execution of

INC (HL)

memory location 3434H will contain 83H.

124
 INC (IX+dJ

Operation: (IX+d) +- (IX+d)+1

Format:

Opcode Operands

INC (IX+d)

11 >:a >>>:a >I DO

Ia :a >>:a >:a :a I 34

I.. : :d: : : .. I
Description:

The contents of the Index Register IX (register pair IX)

are added to a two's complement displacement integer d
to point to an address in memory. The contents of this
address are then incremented.

M CYCLES: T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
p/V: Set if (IX+d) was 7FH before
operation; reset otherwise
N: Reset
C: Not affected

125
Example:

If the contents of the Index Register pair IX are 2020H,

and the memory location 2030H contains byte 34H, after
the execution of

INC (IX+I0H)

the contents of memory location 2030H will be 35H.

126
 INC CIY+dJ

Operation: (IY+d)+- (IY+d)+1

Opcode Operands

INC (IY+d)

11 >:1>>>: >I 0 FD

Ia; a: <<a: <a; 0 I 34

1< : :<: : .. I
Desc r iption:

The contents of the Index Register IY (register pair IY)

are added to a two's complement displacement integer d
to point to an address in memory. The contents of this
address are then incremented.

l-l: CYCLES: T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry from
Bit 3; reset otherwise
p/v: Set if (IY+d) was 7FH before
operation; reset otherwise
N: Reset
C: Not Affected

127
Example:

If the contents of the InAex Register pair IY are 2020H.

and the memory location 2030H contain byte 34H. after
the execution of

INC (IY+l OH)

the contents of memory location 2030H will be 35H.

128
-GENERAL PURPOSE ARIlH£fICAND CPU CONTROL GROUPS-

131
 Register !.
B 000
C 001
D 010
E all
H 100
L 101
A 111

Description:

The byte specified by the m operand is decremented.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

DEC r 1 4 1. 00
DEC (HL) 3 11(4,4,3) 2.75
DEC (IX+d) 6 23(4,4,3,5,4,3) 5.75
DEC (IY+d) 6 23(4,4,3,5,4,3) 5.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if borrow from
Bit 4, reset otherwise
p/v: Set if m was 80H before
operation; reset otherwise
N: Set
C: Not affected

Example:

If the D register contains byte 2AH, after the execution

of

DEC D

register D will contain 29H.

130
Condition Bits Affected:

S: Set if most significant bit

of Acc. is 1 after operation;
reset otherwise
Z: Set if Acc. is zero after operation;
reset otherwise
H: See instruc tion
p/v: Set if Acc. is even parity after
operation; reset otherwise
N: Not affected
C: See instruction

Example:

If an addition operation is performed between 15 (BCD)

and 27 (BCD). simple decimal arithmetic gives this
result:

15
+27
42
But when the binary representations are added in the
Accumulator according to standard binary arithmetic.

0001 0101
+0010 0111
0011 1100 3C
the SUg is agbiguous. The DAA instruction adjusts this
result so that the correct BCD representation is
obtained:

0011 1100
+0000 0110
0100 0010 • 42

133
DAA

Operation:

Format:

DAA

Description:

This instruction conditionally adjusts the Accumulator

for BCD addition and subtraction operations. For
addition (ADD, ADC, INC) Qr subtraction (SUB,
SBC,DEC,NEG), the following table indicates the
operation performed:

HEX HEX
VALUE VALUE NUMBER
C IN H IN ADDED C
BEFORE UPPER BEFORE LOWER TO AFTER
OPERATION DAA DIGIT DAA DIGIT BYTE DAA
(bit (bit
7-4) 3-0)

0 0-9 0 0-9 00 0
0 0-8 0 A-F 06 0
ADD 0 0-9 1 0-3 06 0
ADC
INC } 0
0
0
A-F
9-F
A-F
0
0
1
0-9
A-F
0-3
60
66
66
1
1
1
1 0-2 0 0-9 60 1
1 0-2 0 A-F 66 1
1 0-3 1 0-3 66 1

SUB 0 0-9 0 0-9 00 0

SBC 0 0-8 1 6-F FA 0
DEC
NEG 1 1
1
7-F
6-F
0
1
0-9
6-F
AO
9A
1
1

M CYCLES: 1 T STATES: 4 4 MHZ E.T.: LOO

132
 N!EG

Operation: A+-O-A

Forma t:

NEG

1«<0»»1 ED

I >:a ;a ;a >;a :a I
0 44

Description:

The contents of the Accumulator are negated (two's

complement). This is the same as subtracting the
contents of the Accumulator from zero. Note that 80H is
left unchanged.

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if borrow from
Bit 4; reset otherwise
P/V: Set if Acc. was 80H before
operation; reset otherwise
N: Set
C: Set if Acc. was not OOH before
operation; reset otherwise

135
CPL

Operation: A~ A
Format:

CPL

Description:

The contents of the Accumulator (register A) are

inverted (l's complement).

M CYCLES: 1 T STATES: 4 4 MHZ E. T.: 1.00

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Set
P/V: Not affected
N: Set
C: Not affected

Example:

If the contents of the Accumulator are 1011 0100, after

the execution of

CPL

the Accumulator contents will be 0100 1011.

134
Operation: CY~Cy

Format:

CCF

Description:

The Carry flag in the F register is inverted.

M CYCLES: T STATES: 4 MHZ E.T.: 1.00

Condition Bits Affected:

S: Not affec ted

Z: Not affected
H: Previous carry will be copied
P/V: Not affected
N: Reset
C: Set if CY was 0 before
operation; reset otherwise

137
Example:

If the contents of the Accumulator are

after the execution of

NEG

the Accumulator contents will be

136
 NOP

Operation:

Format:

Opcode

NOP

Description:

The CPU performs no operation during this machine cycle.

M CYCLES: T STATES: 4 MHZ E.T.: 1.00

Condition Bits Affected: None

139
SCF

Operation: CY~1

Format:

SCF

Description:

The Carry flag in the F register is set.

M CYCLES: T STATES: 4 MHZ E.T.: 1. 00

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Reset
P/V: Not affected
N: Reset
C: Set

138
 01

Operation: IFF +- 0

Format:

Opcode

DI

Description:

DI disables the maskable interrupt by resetting the

interrupt enable flip-flops(IFFl and IF12). Note that
this instruction disables the maskable interrupt during
its execution.

M CYCLES: T STATES: 4 4 MHZ E.T.: l.00

Condition Bits Affected: None

Example:

When the CPU executes the instruction

DI

the maskable interrupt is disabled until it is

subsequently re-enabled by an EI instruction. The CPU
will not respond to an Interrupt Request (INT) signal.

141
HALT

Operation:

Opcode

HALT

Description:

The HALT instruction suspends CPU operation until a

subsequent interrupt or reset is received. While in the
halt state, the processor will execute NOP's to maintain
memory refresh logic.

M CYCLES: T STATES: 4 4 MHZ E.T.: LOO

Condition Bits Affected: None

140
 1M 0

Operation:

Format:

Operands

1M

11 >>: >>:a >I

0 ED

Description:
1
0
>: :a : >>: I
0 0 0 46

The 1M 0 instruction sets interrupt mode O. In this

mode the interrupting device can insert any instruction
on the data bus for execution by the CPU. The first
byte of a multi-byte instruction is read during the
interrupt acknowledge cycle. Subsequent bytes are read
in by a normal memory read sequence.

M CYCLES: T STATES: 8(4,4) MH Z E. T .: 2 • 00

Condition Bits Affected: None

143
EI

Operation: IFF +-1

Format:

EI

Description:

The enable interrupt instruction will set both interrupt

enable flip flops (IFFI and IFF2) to a logic '1'
allowing recognition of any maskable interrupt. Note
that during the execution of this inBtruction ~nd the
following instruction, maskable interrupts will be
disabled.

M CYCLES: T STATES: 4 4 MHZ E.T.: 1.00

Condition Bits Affected: None

Example:

When the CPU executes instruction

EI
RETI

the maskable interrupt will be enabled after the

execution of the RETI instruction.

142
 1M 2

Operation:

Format:

Operands

1M

1 >:0»»1
1
:
1
ED

I >>>>;a I
0 :1 :0 5E

Description:

The 1M 2 instruction sets the vectoreed interrupt mode

2. Thi. mode allows an indirect call to any memory
location by an 8 bit vecto~ supplied from the peripheral
device. This vector then becomes the least significant
8 bits of the indirect pointer while the I register in
the CPU provides the most significant 8 bits. This
address points to an addreess in a vector table which is
the starting address for the interrupt service routine.

101 CYCLES: T STATES: 8(4,4) MHZ EoT.: 2.00

Condition Bits Affected: None

145
1M 1

Operation:

Format:

Operands

1M

11 >>: >>:a >I

0 ED

I0 >: >:a >>:a I

0 56

Description:

The 1M instruction sets interrupt mode 1. In this mode

the processor will respond to an interrupt by executing
a restart to location 0038H.

M CYCLES: T STATES: 8(4,4) MHZ E.T.: 2.00

Condition Bits Affected: None

144
-16 BIT ARIlH~£TIC GRruP-

146
Example:

If register pair HL contains the integer 4242ll and

register pair DE contains IlllH, after the execution of

ADD HL,DE

the HL register pair will contain 5353H.

ADD HL, 55

Operation: HL ...... HL+ss

Format:

Opcode Operands

ADD HL,ss

Description:

The contents of register pair ss (any of register pairs

BC,DE,HL or SP) are added to the contents of register
pair HL and the result is stored in ilL. Operand ss is
specified as follows in the assembled object code.

Register
Pair ss

BC 00
DE 01
HL 10
SP 11

M CYCLES: T STATES: 11(4,4,3) 4 MHZ E.T.: 2.75

Condition Bits Affected:

S Not affected
Z Not affected
H Set if carry out of
Bit 11; reset otherwise
p/v Not affected
N Reset
C Set if carry from
Bit 15; reset otherwise

147
Example:

If the register pair BC contains 2222H, register pair HL

contains 5437H and the Carry Flag is set, after the
execution of

ADC HL,BC

the contents of HL will be 765AH.

150
ADC HL, 88

Operation: HL+-HL+ss+CY

Format:

Operands

ADC HL,ss

I<<< >>:a >I

0 ED

1«««<°1
Description:

The contents of register pair ss (any of register pairs

BC,DE,HL or SP) are added with the Carry Flag (C flag in
the F register) to the contents of register pair HL, and
the result is stored in HL. Operand ss is specified as
follows in the assembled object code.

Register
Pair ~

BC 00
DE 01
HL 10
SP 11

M CYCLES: 4 T STATES: 15(4,4,4,3) 411HZ E.T.: 3.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if carry out of
Bit 11; reset otherwise
P/V: Set if overflow;
reset otherwise
N: Reset
C: Set if carry from
Bit 15; reset otherwise

149
Example:

If the contents of the ilL register pair are 9999H, the

contents of register pair DE are 1111H, and the Carry
Flag is set, after the execution of

SBC ilL,DE

the contents of ilL will be 8887H.

1~
sac HL, 88

Op era t ion: Hl<-Hl-ss-CY

Format:

Operands

SBC HL,ss

1
1:1:<°:1:1:°:11 ED

1°: 1»:°:°:<°\
Description:

The contents of the register pair ss (any of register

pairs BC,DE,HL or SP) and the Carry Flag (C flag in the
F register) are subtracted from the contents of register
pair HL and the result is stored in HL. Operand ss is
specified as follows in the assembled object code.

Register
Pair ~

BC 00
DE 01
HL 10
SP 11

H CYCLES: T STATES: 15(4,4,4,3) 4 HHZ LT.: 3.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Set if a borrow from
Bit 12;reset otherwise
P/V: Set if overflow;
reset otherwise
N: Set
C: Set if borrow;
reset otherwise

151
Example:

If the contents of Index Register IX are 333H and the

contents of register pair BC are 5555H, after the
execution of

ADD IX,BC

the contents of IX will be BBBBH.

154
ADD IX, pp

Operation: IX +-IX + pp

Forma t:

Opcode Operands

ADD IX,pp

11 : 1 : 0 >>>: > 0 I DO

1
0
:
0»>:0:0>1
Description:

The contents of register pair pp (any of register pairs

BC,DE,IX or SP) are added to the contents of the Index
Register IX, and the results are stored in IX. Operand
pp is specified as follows in the assembled object code.

Register
Pair ~

BG 00
DE 01
IX 10
SP 11

M CYCLES: 4 T STATES: 15(4,4,4,3) 4 HHZ E.T.: 3.75

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Set if carry out of
Bit 11; reset otherwise
p/v: Not affected
N: Reset
C: Set if carry from
Bit 15; reset otherwise

153
Example:

If the contents of Index Register IY are 333H and the

contents of register pair BC are 555H, after the
execution of

ADD IY,BC

the contents of IY will be 8888H.

156
ADD IY, rr

Operation: IY+-IY+rr

Format:

Opcode Operands

ADD IY.rr

11 >>>>>:a >I FD

1
0:0»>:0:0>1
Description:

The contents of register pair rr (any of register pairs

BC.DE.IY or SP) are added to the contents of Index
Register IY. and the result is stored in IY. Operand rr
is specified as follows in the assembled object code.

Register
Pair -!.!..
BC 00
DE 01
IY 10
SP 11

M CYCLES: T STATES: 15(4.4.4.3) 4 MHZ E.T.: 3.75

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Set if carry out of
Bit 11; reset otherwise
P/V: Not affected
N: Reset
C: Set if carry from
Bit 15; reset otherwise

155
 INC IX

Operation: IX+-IX+1

Format:

Opcode Operands

INC IX

11>:a >>>:a >I DD

I :a >:a :a :a >>I
0 23

Description:

The contents of the Index Register IX are incremented.

11 CYCLES: T STATES: 10(4,6) 4 MHZ E.T.: 2.50

Condition Bits Affected: None

Example:

If the Index Register IX contains the integer 3300H

after the execution of

INC IX

the contents of Index Register IX will be 3301H.

158
INC 88

Operation: ss~ss+1

Format:

Opcodes Operands

INC ss

Description:

The contents of register pair ss (any of register pairs

BC, DE,HL or SP) are incremented. Operand ss is
specified as follows in the assembled object code.

Register
Pair ss

BC 00
DE 01
HL 10
SP 11

M CYCLES: T STATES: MHZ E. T. 1. 50

Condition Bits Affected: None

Example:

If the register pair contains 1000H, after the execution

of

INC HL

HL will contain lOOlH.

157
 DEC ss

Op era t io n : SS +- ss -1
Format:

Opcode Operands

DEC ss

Description:

The contents of register pair ss {any of the register

pairs BC,DE,HL or SP) are decremented. Operand ss is
specified as follows in the assembled object code.

Pair ss

BC 00
DE 01
HL 10
SP 11

M CYCLES: T STATES: 4 }.1HZ E.T. : L50

Condition Bits Affected: None

Example:

If register pair HL contains 1001H, after the execution

of

DEC HL

the contents of HL will be 1000H.

160
INC IV

Operation: IY~IY+1

Format:

Opcode Operands

INC IY

I<<<<<< I 0: 1 FD

I a: <a; a; a; < I
0: 1 23

Description:

The contents of the Index Register IY are incremented.

M CYCLES: T STATES: 10(4,6) 4 MHZ E. T • : 2 • 50

Condition Bits Affected: None

Example:

If the contents of the Index Register are 2977H, after

the execution of

INC IY

the contents of Index Register IY will be 2978H.

159
 DEC IY

Operation: IY~IY-1

Format:

Operands

DEC IY

I<<<<< >I 1: 0 FD

I ;a >;a >;a >>I

0 2B

Description:

The contents of the Index Register IY are decremented.

M CYCLES: T STATES: 10 (4,6) 4 MHZ E.T.: 2.50

Condition Bits Affected: None

Example:

If the contents of the Index Register IY are 7649H,

after the execution of

DEC IY

the contents of Index Register IY will be 7648H.

162
DEC IX

Operation: IX +-IX-1

Opcode Operands

DEC IX

11 : 1 : 0 : 1 : 1 : 1 : 0 : 1 I DD

I0 : 0 : 1: 0 : 1: 0 : 1: 1 I 28

Description:

The contents of Index Register IX are decremented.

M CYCLES: T STATES: 10(4,6) MHZ E. T • : 2 • 50

Condition Bits Affected: None

Example:

If the contents of Index Register IX are 2006H, after

the execution of

DEC IX

the contents of Index Register IX will be 2005H.

161
-ROTATE JWD SHIFT GROJP-

163
Example:

If the contents of the Accumulator are

I 0I
after the execution of

RLCA

the contents of the Accumulator and Carry Flag will be

165
RLCA

Operation:

Format:
r¥EJJ A

Operands

RLCA

Description:

The contents of the Accumulator (register A) are rotated

left one bit position. The sign bit (bit 7) is copied
into the Carry Flag and also into bit O. Bit 0 is the
least significant bit.

M CYCLES: T STATES 4 4 MHZ E.T.: 1.00

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Reset
P/V: Not affected
N: Reset
C: Data from Bit 7 of Ace.

164
Example:

If the contents of the Accumulator and the Carry Flag

after the execution of

RLA

the contents of the Accumulator and the Carry Flag will

be

167
RLA

I~I
Operation: ~
A
Format:

Operands

RLA

Description:

The contents of the Accumulator (register A) are rotated

left one bit position through the Carry Flag. The
previous content of the Carry Flag is copied into bit O.
Bit 0 is the least significant bit.

t1 CYCLES: T STATES: 4 MH Z E. T.: 1. 00

Condition Bits Affected:

s: Not affected
Z: Not affected
H: Reset
P/V: Not affected
N: Reset
C: Data fro~ Bit 7 of Ace.

166
Example:

If the contents of the Accumulator are

After the execution of

RRCA

the contents of the Accumulator and the Carry Flag will

be

169
RRCA

Operation: CEJlEJA
Format:

Operands

RRCA

Description:

The contents of the Accumulator (register A) are rotated

right one bit position. Bit 0 is copied into the Carry
Flag and also into bit 7. Bit 0 is the least
significant bit.

M CYCLES: 1 T STATES: 4 MH Z E. T .: 1. 00

Condition Bits Affected:

S: Not affected
Z: Not a f f e c t.e d
H: Reset
P/v: Not affected
N: Reset
C: Data from Bit 0 of Acc.

168
Example:

If the contents of the Accumulator and the Carry Flag

are

after the execution of

RRA

the contents of the Accumulator and the Carry Flag will

be

171
RRA

Operation:

Format:

Operands

RRA

Description:

The contents of the Accumulator (register A) are rotated

right one bit position through the Carry Flag. The
previous content of the Carry Flag is copied into bit 7.
Bit a is the least significant bit.

H CYCLES: T STATES: 4 4 HHZ E.T.: 1.00

Condition Bits Affected:

S: Not affected
Z: Not affected
H: Reset
p/v: Not affected
N: Reset
C: Data froc Bit a of Ace.

170 ,
Condition Bits Affected:

S: Set if result is negativc;

rcset otherwise
z: Set if result is zero;
reset otherwise
II: Reset
P/V: Set if parity even;
reset otherwise
N: Resct
C: Data from Bit 7 of
source register

Example:

If the contents of register rare

after thc execution of

RLC r

the contents of register r and the Carry Flag will be

173
RLC r

Operation:

Format:

Operands

RLC

11 >;a ;a >;a >>I CB

I0 :0 :0 :0 :0 ~r71
Description:

The contents of register r are rotated left one bit

position. The content of bit 7 is copied into the Carry
Flag and also into bit O. Operand r is specified as
follows in the assembled object code:

Register .E.-
B 000
C 001
D 010
E 011
H 100
L 101
A III

M CYCLES: 2 T STATES: 8(4,4) 4 MHZ E.T.: 2.00

172
Example:

If the contents of the ilL register pair are 2828H, and

the contents of memory location 2828H are

after the execution of

RLC (HL)

the contents of memory location 2828H and the Carry Flag

will be

C 4 o

175
RLe (HLJ

Operation:

Format:
WEJJ (HL)

Operands

RLC (HL)

11 >;a ;a >;a >>, CB

I0 : 0 : 0 :0 : 0 >>;a , 06

Description:

The contents of the memory address specified by the

contents of register pair HL are rotated left one bit
position. The content of bit 7 is copied into the Carry
Flag and also into bit O. Bit 0 is the least
significant bit.

M CYCLES: T STATES: 15(4,4,4,3) 4 MH Z E. T .: 3. 75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Data from Bit 7 of
source register

174
Example:

If the contents of the Index Register IX are lOOOH, and

the contents of memory location l022H are

after the execution of

RLC (IX+2H)

the contents of memory location l002H and the Carry Flag

will be

177
RLe (IX+dJ

Operation: aJBJ (IX+d)

Format:

Operands

RLC (IX+d)

11 : < <<>I
0 :1 : 0 DO

11 : 1 :0 :0 >: 0 :1 :1 , CB

I~d::: .. l
I0 :0 :0 :0 :0 >: 1 :0 I 06

Description:

The contents of the memory address specified by the sum

of the contents of the Index Register IX and a two's
complement displacement integer d. are rotated left one
bit position. The content of bit 7 is copied into the
Carry Flag and also into bit O. Bit 0 is the least
significant bit.

M CYCLES: T STATES: 23(4.4.3.5.4.3) MHZ E.T.: 5.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Data from Bit 7 of
source register

176
Example:

If the contents of the Index Register IY are lOOOH, and

the contents of memory location l002H are

after the execution of

RLC (IY+2H)

the contents of memory location l002H and the Carry Flag

will be

C o

179
RLe CIY+dJ

Operation:

Format:
WBJ (IY+dl

Operands

RLC (1Y+d)

11 : 1 : 1 : 1 : 1 : 1 : 0 : 1 I FD

11 : 1 : 0 : 0 : 1 : 0 : 1 : 1 I CB

ISd::: .. \
I0 :0 :0 :0 :0 : 1 >: I 0 06

Description:

The contents of the memory address specified by the sum

of the contents of the Index Register IY and a two's
complement displacement integer d are rotated left one
bit position. The content of bit 7 is copied into the
Carry Flag and also into bit O. Bit 0 is the least
significant bit.

M CYCLES: 6 T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.: 5.75

Condition Bits Affected:

S: Set if result is negative;

reset otherwise
Z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Data from Bit 7 of
source register

178
 RL (IY+d) 1 1;1;1;1>:1:0;1 FD

1«0;°»» CB

1< : :< : : ;.
1°;0;0»»> 16

*r identifies registers B.C.D.E.H.L or A specified as

follows in the assembled object code above:

Register

B 000
C 001
D 010
E 011
H 011
L 101
A 111
Description:

The contents of the m operand are rotated left one bit

position. The content of bit 7 is copied into the Carry
Flag and the previous content of the Carry Flag is
copied into bit O.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

RL r 2 8(4.4) 2.00
RL (HL) 4 15(4.4.4.3) 3.75
RL (IX+d) 6 23(4.4.3.5.4.3) 5.75
RL (I Y+d) 6 23(4.4.3.5.4.3) 5.75

181
RL m

Operation: 18BJm
Format:

Operands

RL m

The m operand is any of r,(HL), (IX+d) or (IY+d), as

~efined for the analogous RLe instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

RL r 1 : 1 :0 :0 : 1 :0 >>I CB

a: 0: a: <o~r~
RL (HL)
1: .< a; a; <0; < 1 CB

o: >:a:<<
0: 0 0 16

RL (IX+d)
1>:a >>>: > 0 DD

1 : 1 :0 :0 >: >>
0 CB

~<: : ..
o: 0 : 0 ; 1 ; 0 >; 1:0 16

180
 RRC m

Operation: lBLB m
Format:

Operands

RRC

The m operand is any of r,(HL), (IX+d) or (IY+d), as

defined for the analogous RLC instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

RRC r
1 >: :a >: >: I
0 0 1 CB

:-7r:-
o: 0 : a: 0: 1

RRC (HL)
>: >: >>
0 :0 0 CB

>>>:0
:0 :0 :0 OE

RRC (IX+d)
1 >: >>>;a >
0 DO

1 >;a ;a >;a >> CB

7:--7<:: ;.
o;a :a; >>>: 0 0 OE

183
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Data from Bit 7 of
source register

Example:

If the contents of register D and the Carry Flag are

C o

after the execution of

RL D

the contents of register D and the Carry Flag will be

C o

182
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
z: Set if result is zero;
reset otherwise
H: Reset
P/V: Set if parity even;
reset otherwise
N: Reset
C: Data from Bit 0 of
source register

Example:

If the contents of register A are

after the execution of

RRC A

the contents of register A and the Carry Flag will be

185
 RRC (IY+d)
II»»»> FD

1 >:0:°>:°»
1 CB

1< : :< : : >

1°;°;0;°»>:° OE

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code above:

Register .E..
B 000
C 001
D 010
E all
H 100
L 101
A 111

Description:

The contents of operand m are rotated right one bit

position. The content of bit a is copied into the Carry
Flag and also into bit 7. Bit a is the least significant
bit.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

RRC r 2 8(4,4) 2.00

RRC (HL) 4 15(4,4,4,3) 3.75
RRC (IX+d) 6 23(4,4,3,5,4,3) 5.75
RRC (IHd) 6 23(4,4,3,5,4,3) 5.75

184
 RR (IY+d) <>I
11 : 1 : 1 : 1 : 1 : a FD

I<< :a >:a >>I

a CB

I : : :< : : .. I
I :a :a >>>>:a I
0 IE

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code above:

Register E.
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Description:

The contents of operand m are rotated right one bit

position through the Carry flag. The content of bit 0 is
copied into the Carry Flag and the previous content of
the Carry Flag is copied into bit 7. Bit 0 is the least
significant bit.

INSTRUCTION H CYCLES T STATES 4 HHZ E.T.

RR r 8(4,4) 2.00
RR (HL) 15(4,4,4,3) 3.75
RR (IX+d) 23(4,4,3,5,4,3) 5.75
RR (IY+d) 23(4,4,3,5,4,3) 5.75

187
RR m

Operation:
lEHjJ
m
Format:

RR m

The m operand is any of r, (HL), (IX+d), or (IY+d), as

defined for the analogous RLe instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

RR r
<<a: a: < >>I 0 CB

o: 0 : 0: 1: 1 ~r~
RR (HL)
<<a: a: <a: < 1 CB

o :a :a >>>>:a IE
RR (IX+d)
<<a: <<<a: DD

<<a: a: <a: <d CB

.; : :< : : .. \
o: a: a: <<<< I 0 IE

186
 SLA m

Operation:

Format:

Operands

SLA

The m operand is any of r. (HL). (IX+d) or (IY+d). as

defined for the analogous RLe instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

SLA r
1 >:a :a >:a: < I 1 CB

a: a: <a: o~r~1
SLA (IlL)
1: 1: 0 : 0: 1: 0: 1: 1 I CB

a: a: <a: a: << I 0 26

SLA (IX+d)
1 >:a >>>:a : DD

<<a: a: <a: < CB

.; : >: : : >
o: 0 : 1:0:0: 1: 1: 0 26

189
Condition Bits Affected:

S: Se t i f result is negative;
reset otherwise
z: Set i f result is zero;
reset otherwise
H: Reset
P/V: Se t i f parity is even;
reset otherwise
N: Reset
C: Data from Bit 0 of
source register

Exampl e:

If the contents of the HL register pair are 4343H, and

the contents of memory location 4343H and the Carry Flag
are

after the execution of

RR (HL)

the contents of location 4343H and the Carry Flag will

be

188
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
z: Set if result is zero;
reset otherwise
II: Re se t
p/V: Set if parity is even;
reset otherwise
Ii: Reset
C: Data from Bit 7

Exampl e:

If the contents of register L are

after the execution of

SLA L
the contents of register L and the Carry Flag will be

C o

191
 SLA (IY+d)
1«««0: FD

1«0:0:<0:< CB

I': : :<: : ;.
1
0:0:<0:0:« 26

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code field above:

Register E..
B 000
C 001
D 010
E 011
H 100
L 101
A 111

Description:

An arithmetic shift left one bit position is performed

on the contents of operand m. The content of bit 7 is
copied into the Carry Flag. Bit 0 is the least
significant bit.

INSTRUCTION M CYCLES T STATES 4 }1HZ E.T.

SLA r 8 (4,4) 2. 00
SLA (HL) 15(4,4,4,3) 3.75
SLA (I X+d) 23(4,4,3,5,4,3) 5.75
SLA (IY+d) 23(4,4,3,5,4,3) 5.75

190
 SRA(IY+d) 1<1:1>:1:1:0:11 FD

11 >:0: 0>:0: 1: 1I CB

I" : :< : : ;'1

I0: 0>:0: 1: 1: 1: 0I 2E

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code field above:·

Register .E.
B 000
C 001
D 010
E all
H 100
L 101
A 111

An arithmetic shift right one bit position is performed

on the contents of operand m. The content of bit a is
copied into the Carry Flag and .the previous content of
bit 7 is un~hanged. Bit a is the least significant bit.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

SRA r 8(4,4) 2.00

SRA (HL) 15(4,4,4,3) 3.75
SRA (IX+d) 23(4,4,3,5,4,3) 5.75
SRA (IY+d) 23(4,4,3,5,4,3) 5.75

193
BRA m

Operation: cS-m o~gt.:J

Format:

Operands

SRA

The m operand is any of r, (HL), (IX+d) or (IY+d) ,as

defined for the analogous RLC instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

SRA r
< < a: a: < a: < 1I CB
a;O:<O:l~r;-
SRA(HL)
<<a; a; <a; < CB
a; a; < <<<
0: 2E

SRA(IX+d)
<<a; <<<0: DO
1: 1: 0: 0: 1: 0: 1: CB
.; : :< : : ;.
a; a; <a; <<< 2E

192
 SRL m

Operation: o~
m
Format:

Operands

SRL m

The operand m is any of r, (HL), (IX+d) or (IY+d), as

defined for the analogous RLC instructions. These
various possible opcode-operand combinations are
specified as follows in the assembled object code:

SRL r 1: 1: 0: 0: 1: 0: 1: 1I CB
0: o;r;r: l;-;-r~1
SRL (HL) 1: 1; 0: 0: 1: 0: 1: 1I CB
0: 0: 1: 1: 1: 1: 1: 0I 3E
SRL (IX+d) 1 ;r :a: r; 1 >: >I
0 DD

1 >:0:0>:0>>, CB
.. : :< : : : I
a; a; <<<<< I 0 3E

195
Condition Bits Affected:

S: Set if result is negative;

reset otherwise
z: Set i f result is zero;
reset otherwise
H: Reset
p/v: Set i f parity is even;
reset otherwise
N: Reset
C: Data from Bit 0 of
source register

Example:

If the contents of the Index Register IX are lOOOH, and

the contents of memory location l003H are

after the execution of

SRA (IX+3H)

the contents of memory location l003H and the Carry Flag

will be

194
Condition Bits Affected:

S: Reset
Z: Set if result is zero;
reset otherwise
H: Reset
p/v: Set if parity ~s even;
reset otherwise
N: Reset
C: Data from Bit 0 of
source register

Example:

If the contents of register Bare

after the execution of

SRL B

the contents of register B and the Carry Flag will be

197
 SRL (I Y+d)
1«1»»>1 FD

11: <0: 0 >: < I

0: 1 CB

I.. : Ict: : : .. I
I a: a: <<<<< I 0 3E

*r identifies registers B,C,D,E,H,L or A specified as

follows in the assembled object code fields above:

Register E.
B 000
C 001
D 010
E all
H 100
L 101
A 111

Description:

The contents of operand m are shifted right one bit

position. The content of bit a is copied into the Carry
Flag, and bit 7 is reset. Bit a is the least significant
bit.

IN STRUCTION M CYCLES T STATES MHZ E.T.

SRL r 8( 4,4) 2. 00
SRL (HL) 15(4,4,4,3) 3.75
SRL (IX+d) 23(4,4,3,5,4,3) 5.75
SRL (IY+d) 23(4,4,3,5,4,3) 5.75

196
Example:

If the contents of the HL register pair are 5000H, and

the contents of the Accumulator and memory location
5000H are

Accumulator

(5000H)

after the execution of

RLD
the contents of the Accumulator and memory location
5000H will be

Accumulator

(5000H)

199
RLD

Operation: A~(HL)
Format:

Opcode Operands

RLD

1«1»»>1 ED

I0: 1: r: 0: 1: <<1I 6P

Description:

The contents of the low order four bits (bits 3,2,1 and
0) of the memory location (HL) are copied into the high
order four bits (7,6,5 and 4) of that same memory
location; the previous contents of those high order four
bits are copied into the low order four bits of ihe
Accumulator (register A); and the previous contents of
the low order four bits of the Accumulator are copied
into the low order four bits of memory location (HL).
The contents of the high order bits of the Accumulator
are unaffected. Note: (HL) means the memory location
specified by the contents of the HL register pair.

1'1 CYCLES: 5 T STATES: 18(4,4,3,4,3) 4 HHZ E.T.: 4.50

Condition Bits Affected:

S: Set if Ace. is negative after

operation; reset otherwise
Z: Set if Ace. is zero after
operation; reset otherwise
H: Reset
P/V: Set if parity of Ace. is even
after operation; reset otherwise
N: Reset
C: Not affected

198
Example:

If the contents of the HL register pair are 5000H, and

the contents of the Accumulator and memory location
5000H are

Accumulator

(5000H)

after the execution of

RRD

the contents of the Accumulator and memory location

5000H will be

Accumulator

(5000H)

201
RRD

Operation: A~(HL)
Format:

Opcode Operands

RRD

I<<< <<Q: I 0: 1 ED

I >>:a; >>>I
0 Q 67

Description:

The contents of the low order four bits (bits 3,2,1 and
0) of memory location (HL) are copied into the low order
four bits of the Accumulator (register A); the previous
contents of the low order four bits Gf the Accumulator
are copied into the high order four bits (7,6,~ ~nd 4)
of location (HL); and the previous contents of the high
order four bits of (HL) are copied into the low order
four bits of (HL). The contents of the high order bits
of the Accumulator are unaffected. Note: (HL) means
the memory location specified by the contents of the HL
register pair.

H CYCLES: T STATES: 18(4,4,3,4,31 4 MHZ E.T.: 4.50

Condition Bits Affected:

S: Set if Ace. is negative after

operation; reset otherwise
Z: Set if Ace. is zero after
operation; reset otherwise
H: Reset
P/V: Set if parity of Ace. is even after
operation; reset otherwise
N: Reset
C: Not affected

200
-BIT SEL RESET AND lEST GRa.lP-

202
 I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Example:

If bit 2 in register B contains 0, after the execution

of

BIT 2,B

the Z flag in the F register will contain 1, and bit 2

in register B will remain O. Bit 0 in register B is the
least significant bit.
BIT b, r

Operation: Z~rb

Format:

Operands

BIT b,r

I<<a: a: < >>I 0 CB

I0: 1~b~:~r7-1
Description:

This instruction tests Bit b in register r and sets the

Z flag accordingly. Operands band r are specified as
follows in the assembled object code:

Bit Tested E. Register £

o 000 B 000
1 001 C 001
2 010 D 010
3 011 E 011
4 100 H 100
5 101 L 101
6 110 A 111
7 III

M CYCLES: T STATES: 8(4,4) 4 MHZ E.T.: 2.00

Condition Bits Affected:

S: Unknown
Z: Set if specified Bit is
0; reset otherwise
H: Set
p Iv: Unknown
N: Reset
C: Not affected

203
Example:

If the HL register pair contains 4444H, and bit 4 in the

memory location 444H contains 1, after the execution of

BIT 4, (HL)

the Z flag in the F register will contain 0, and bit 4

in memory location 4444H will still contain 1. (Bit 0 in
memory location 4444H is the least significant bit.)

206
BIT b. CHLJ

Operation: Z~(HLlt,

Format:

Operands

BIT b, (HL)

11 >:a: < >>I

0: 0 CB

Description:
1
0
>~b~1 >: I 0

This instruction tests bit b in the memory location

specified by the contents of the HL register pair and
sets the Z flag accordingly. Operand b is specified as
follows in the assembled object code:

Bit Tested 1?
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

M CYCLES: T STATES: 12(4,4,4) 4 MHZ E.T.: 3.00

Condition Bits Affected:

S: Unknown
Z: Set if specified Bit is
0; reset otherwise
H: Set
P/V Unknown
H Reset
C Not affected

205
Condition Bits Affected:

S: Unknown
z: Set if specified Bit is
0; reset otherwise
H: Set
P/V: Unknown
N: Reset
C: Not affected

Example:

If the contents of Index Register IX are 2000H. and bit

6 in memory location 2004H contains 1. after the
execution of

BIT 6. (IX+4H)

the Z flag in the F register will contain O. and bit 6

in memory location 2004H will still contain 1. (Bit 0
in memory location 2004H is the least significant bit.)

208
BIT b, CIX+dJ

Format:

Operands

BIT b,(IX+d)

1 >: >>>:rJ >

0 DO

1: 1: >: >>
0 :0 0 CB

.. : :<: : "
o >:-+b~«O
Description:

This instruction tests bit b in the memory location

specified by the contents of register pair IX combined
with the two's complement displacement d and sets the Z
flag accordingly. Operand b is specified as follows in
the assembled object code.

Bit Tested 1?
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

M CYCLES: T STATES: 20(4,4,3,5,4) 4 MHZ E.T.: 5.00

Condition Bits Affected:

S: Unknown
Z: Set if specified Bit is
0; reset otherwise

207
Condition Bits Affected:

S: Unknown
z: Set if specified Bit is
OJ reset otherwise
H: Set
p/V: Unknown
N: Reset
C: Not affected

Example:

If the contents of Index Register are 2000H, and bit 6

in memory location 2004H contains 1, after the execution
of

BIT 6, (IY+4H)

the Z flag in the F register sill contain 0, and bit 6

in memory location 2004H will still contain 1. (Bit 0
in memory location 2004H is the least significant bit.)

210
BIT b, CIY+dJ

BIT b, (IY+d)

Format:

Operands

BIT b, (IY+d)

:1:1 >: >:a >I

1 FD

: 1 : a :0 >: 0 :1 :1 1 CB

~d::: >1
o >7-7b~ 1>:0I
Description:

This instruction tests bit b in the memory location

specified by the contents of register pair IY combined
with the two's complement displacement d and sets the Z
flag accordingly. Operand b is specified as follows in
the assembled object code:

Bit Tested .!?

0 000
1 001
2 010
3 011
4 100
5 1 01
6 110
7 111

M CYCLES: 5 T STATES: 20(4,4,3,5,4) 4 MHZ E.T.: 5.00

209
 SET b, (HLJ

Operation: (HL1b ~ 1

Forma t:

Operands

SET b, (HL)

11>: a: < >>I

0 : 0 CB

1< 1~b-;-;< <0I

Description:

Bit b in the memory location addressed by the contents

of register pair HL is set. Operand b is specified as
follows in the assembled object code:

Bit Tested E-
O 000
1 001
2 010
3 011
4 100
5 101
6 110
7 III
M CYCLES: T STATES: 15(4,4,4,3) 4 MHZ E. T.: 3.75

Condition Bits Affected: None

Example:

If the contents of the HL register pair are 3000H, after

the execution of

SET 4,(HL)

bit 4 in memory location 3000H will be 1. (Bit 0 in

memory location 3000H is the least significant bit.)

212
SET b, r

Ope ra tion: rb +-1

Format:

Operands

SET b,r

11 >:a :a : 1:a : 1:1I CB

11 >~b-;-:~r-:-- ,
Description:

Bit b in register r (any of registers B,C,D,E,H,L or A)

is set. Operands band r are specified as follows in
the assembled object code:

Bit b Register E..

000 B 000
001 C 001
010 D 010
011 E 011
100 H 100
101 L 101
110 A 111
111

M CYCLES: T STATES: 8(4,4) MHZ E.T. : 2.00

Condition Bits Affected: None

Example:

After the execution of

SET 4,A

bit 4 in register A will be set. (Bit 0 is the least

significant bit.)

211
Example:

If the contents of Index Register are 2000H, after the

execution of

SET O,(IX+3H)
bit 0 in memory location 2003H will be 1. (Bit 0 in
memory location 2003H is the least significant bit.)

214
SET b, CIX+dJ

Operation: (IX+d)~~1

Format:

Operands

SET b, (IX+d)

>: >>>:a >

0 DD

>: >;a >>

0 :0 CB

~d::::.
1>7-7b~l >:a
Description:

Bit b in the memory location addressed by the sum of the

contents of the IX register pair and the two's
complement integer d is set. Operand b is specified as
follows in the assembled object code:

Bit Tested .Q.

0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

M CYCLES: T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.:

5.75

Condition Bits Affected: None

213
the execution of

SET O,(IY+3H)

bit 0 in memory location 2003H will be 1. (Bit 0 in

memory location 2003H is the least significant bit.)

216
SET b, (IY+dJ

Operation: (IY+d)b +-1

Format:

Operands

SET b,(IY+d)

11>>>>>:a >I FD

11 >: >:a >>I

0 :0 CB

l~<:: .I
11 : 17-+b~1 :1 :0 I
Description:

Bit b in the memory location addressed by the sum of the

contents of the IY register pair and the two's
complement displacement d is set. Operand b is
specified as follows in the assembled object code:

Bit Tested E.
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

M CYCLES: T STATES: 23(4,4,3,5,4,3) 4 MHZ E.T.:

5.75

Condition Bits Affected: None

Example:

If the contents of Index Register IY are 2000H, after

215
 Bit Reset b Register r

0 000 B 000
1 001 C 001
i 010 D 010
3 011 E 011
4 100 H 100
5 101 L 101
6 110 A 111
7 111

Description:

Bit b in operand m is reset.

INSTRUCTION M CYCLES T STATES 4 MHZ E.T.

RES r 4 8/(4,4) 2.00
RES (HL) 4 15(4,4,4,3) 3.75
RES (IX+d) 6 23(4,4,3,5,4,3) 5.75
RES (IY+d) 6 23(4,4,3,5,4,3) 5.75
Condition Bits Affected: None

Example:

After the execution of

RES 6,D

bit 6 in register D will be reset. (Bit 0 in register D

is the least significant bit.)

218
RES b, m

Operation: sb +- 0

Opcode Operands

RES p,m

Operand b is any bit (7 through 0) of the contents of

the m operand,(any of r, (HL), (IX+d) or (IY+d»as
defined for the analogous SET instructions. These
various possible opcode-operand combinations are
assembled as follows in the object code:

RES b,r
t :1 :0 :0 : <>>I
0 CB

1;0 :~b+-:~r71
RES b,(HL)
>: >: >>I
0 :0 0 CB

:O~b~l >:01
RES b, (IX+d)
>: 0 : 1 : 1 : 1 :0 : 1 DO

>;0 : >:a >>

0 CB

I~d::: .
11 :0 7--:b~1 >:0
RES b, (IY+d)
11 >>>>>: > 0 FO

11 >: >: »
0 :0 0 CB

I~d::: .
11 : 7--:b~ 1>:a
0

217
-JlJ'P GIUJP-

219
 CC, nn

Operation: IF cc TRUE, PC +- nn

Format:

Opcode Operands

JP cc.nn

11 :1~cc~ 0 : 1:0 I
I.. : In: : : .. I
1< : :n; : : :·1
Note: The first n operand in this assembled object code
is the low order byte of a 2-byte memory address.

Description:

If condition cc is true. the instruction loads operand

nn into register pair PC (Program Counter). and the
program continues with the instruction beginning at
address nn. If condition cc is false. the Program
Counter is incremented as usual. and the program
continues with the next sequential instruction.
Condition cc is programmed as one of eight status which
corresponds to condition bits in the Flag Register
(register F). These eight status are defined in the
table below which also specifies the corresponding cc
bit fields in the assembled object code.

cc CONDITION RELEVANT
FLAG

000 NZ non zero Z

001 Z zero Z
010 NC no carry C
011 C carry C
100 PO parity odd p/v
101 PE parity even p/V
110 P sign positive S
111 U sign negative S

221
nn

Operation: PC+-nn
Format:

Operands

JP nn

I<< :a :a :a >>I
0 C3

I.. : >: : : ;'1

I.. : ,n; : : .. I
Note: The first operand in this assembled obje~t code
is the low order byte of a 2-byte address.

Description:

Operand nn is loaded into register pair PC (Program

Counter). The next instruction is fetched from the
location designated by the new contents of the PC.

M CYCLES: T STATES: 10(4,3,3) 4 MHZ E;T.: 2.50

Condition Bits Affected: None

220
 ~R e

Operation: PC+-PC+e

Forma t:

Ope ode

JR e

I :a :a >>:a :a ;a I
0 18

1~~-2: : : ;.1
Description:

This instruction provides for unconditional branching to

other segments of a program. The value of the
displacement e is added to the Program Counter (PC) and
the next instruction is fetched from the location
designated by the new contents of the PC. This jump is
measured from the address of the instruction opcode and
has a range of -126 to +129 bytes. The assembler
automatically adjusts for the twice incremented PC.

M CYCLES: T STATES: 12(4.3.5) 4 MHZ E. T .: 3. 00

Condition Bits Affected: None

Example:

To jump forward 5 locations from address 480. the

following assembly language statement is used:

JR $+5
The resulting object code and final PC value is shown
below:
Location Instruction

480 i8
481 03
482
483
484
485 PC after jump

223
M CYCLES: T STATES: 10(4,3,3) 4 MHZ E. T .: 2.50

Condition Bits Affected: None

Example:

If the Carry Flag (C flag in the F register) is set and

the contents of address 1520 are 03H, after the
execution of

JP C,1520H

the Program Counter will contain 1520H, and on the next

machine cycle the CPU will fetch from address 1520H the
byte 03H.

222
 JR C,$-4

The resulting object code and final PC value is shown

below:

Location Instruction

47C +- PC after j UClp

47D
47E
47F
480 38
481 FA (2's complement-6)

225
~R c, e

Operation: If C = 0, continue
IfC=1, PC+-PC+e
Format:

Operands

JR C,e

I >>>:
0: 0 0: 0: 0 I 38

I*:e-~ :: :.,
Description:

This instruction provides for conditional branching to

other segments of a program depending on the results of
a test on the Carry Flag. If the flag is equal to a
'1', the value of the displacement e is added to the
Program Counter (PC) and the next instruction is fetched
from the location designated by the new contents of the
PC. The jump is measured from the address of the
instruction opcode and has a range of -126 to +129
bytes. The assembler automatically adjusts for the
twice incremented PC.

If the flag is equal to a '0', the next instruction to

be executed is taken from the location following this
instruc tion.

If condition is met:

11 CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E. To : 3 • 00

If condition is not met:

11 CYCLES: T STATES: 7(4,3) MHZ E. T .: 1. 75

Condition Bits Affected: None

Example:

The Carry Flag is set and it is required to jump back 4

locations from 480. The assembly language statement is:

224
 JR NC. $

The resulting object code and PC after the jump are

shown below:

Location Instruction

480 30 +- PC after jump

481 00

227
~R Ne, e

Oper a tion: If C = 1, continue

If C = 0, PC ~ PC + e
Fo rmat:

Opcode Operands

JR NC,e

I0:0 >>: 0:0: 0:01 30

I-:-+-:e-~ : : .. I
Description:

This instruction provides for conditional branching to

other segments of a program depending on the results of
a test on the Carry Flag. If the flag is equal to '0',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
The jump is measured from the address of the instruction
opcode and has a range of -126 to +129 bytes. The
assembler automatically adjusts for the twice
incremented PC.

If the flag is equal to a '1', the next instruction to

be executed is taken from the location following this
instruc tion.

If the condition is met:

1-1 CYCLES: 3 T STATES: 12(4,3,5) 4 HHZ E.T.: 3.00

If the condition is not met:

11 CYCLES: T STATES: 7(4,3) MHZ E. T .: 1. 75

Condition Bits Affected: None

Example:

The Carry Flag is reset and it is required to repeat the

jump instruction. The assembly language statement is:

226
 JR Z,$ +5

The resulting object code and final PC value is shown

below:

Location Instruction

300 28
301 03
302
303
304
305 PC after jump

229
~R z, e

Operation: If Z = O. continue
If Z = 1, PC +- PC + e
Format:

Operands

JR Z,e

I >: >: ;a:

0: 0 0 0 0, 28

1*:e-2: :: :·1
Description:

This instruction provides for conditional branching to

other segments of a program depending on the results of
a test on the Zero Flag. If the flag is equal to a '1',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
Th'e jump is measured from the address of the instruc tion
opcode and has a range of -126 to +129 bytes. The
assembler automatically adjusts for the twice
incremented PC.

If the Zero Flag is equal to a '0', the next instruction

to be executed is taken from the location following this
instr uc tion.

If the condition is met:

M CYCLES: 3 T STATES: 12(4,3,5) 4 MHZ E. T.: 3.00

If the condition is not net:

M CYCLES: T STATES: 7(4,3) MHZ E. T .: 1. 75

Condition Bits Affected: None

Example:

The Zero Flag is set and it is required to jump forward

5 locations from address 300. The following assembly
language statement is used:

228
 JR NZ,$-4

The resulting object code and final PC value is shown

below:

Location Instruction

47C PC after jump

47D
47E
47F
480 20
481 FA (2' complement-6)

231
~R NZ, e

Operation: If Z = 1, continue
If Z = 0, PC +- PC + e
Format:

Opcode Operands

JR NZ,e

I >:
0 :0 0 :0 :0 : 0 :0 , 20

1-7-+-: e 2
- : : : :. I
Description:

This instruction provides for conditional branching to

other segments of a program depending on the results of
a test on the Zero Flag. If the flag is equal to a '0',
the value of the displacement e is added to the Program
Counter (PC) and the next instruction is fetched from
the location designated by the new contents of the PC.
The jump is measured from the address of the instruction
opcode and has a range of -126 to +129 bytes. The
assembler automatically adjusts for the twice
incremented PC.

If the Zero Flag is equal to a '1', the next instruction

to be executed is taken from the location following this
instruc tion.

If the condition is Det:

M CYCLES: 3 T STATES: 12(4,3,5) 4 HHZ E.T.: 3.00

If the condition is not met:

H CYCLES: T STATES: 7(4,3) MHZ E. T .: 1. 75

Condition Bits Affected: None

Exampl e:

The Zero Flag is reset and it is required to jump back 4

locations frOD 480. ~he assembly language statement is:

230
 (IX)

Operation: PC+-IX

Format:
Operands

JP (IX)

11 :1:0 >:< >

1:0 I DD

11 :1:1:0 >:0 : 0 >I E9

Description:

The Program Counter (register pair PC) is loaded with

the contents of the IX Register Pair. The next
instruction is fetched from the location designated by
the new contents of the PC.

M CYCLES: T STATES: 8(4,4) MHZ E.T.: 2.00

Condition Bits Affected: None

Example:

If the contents of the Program Counter are 1000H, and

the contents of the IX Register Pair are 4800H, after
the execution of

JP (IX)

the contents of the Program Counter will be 4800H.

233
(HLJ

Operation: PC+-HL

Format:

Operands

JP (ilL)

Description:

The Program Counter (register pair PC) is loaded with

the contents of the HL register pair. The next
instruction is fetched from the location designated by
the new contents of the PC.

M CYCLES: T STATES: 4 MHZ E. T.: 1.00

Condition Bits Affected: None

Example:

If the contents of the Program Counter are 1000H and the

contents of the HL register pair are 4800H, after the
execution of

JP (HL)

the contents of the Program Counter will be 4800H.

232
 D~NZJ e

Operation:

Format:

DJNZ e

Ia; a; a; <a; a; a; 0 I 10

1*~-2: :: :11

Description:

This instruction is similar to the conditional jump

instructions except that a register value is used to
determine branching. The B register is decremented and
if a non zero value remains, the value of the
displacement e is added to the Program Counter (PC).
The next instruction is fetched from the location
designated by the new contents of the PC. The jump is
measured from the address of the instruction opcode and
has a range of -126 to +129 bytes. The assembler
automatically adjusts for the twice incremented PC.

If the result of decrementing leaves B with a zero

value, the next instruction to be executed is taken from
the location following this instruction.

If B"O:

M CYCLES: T STATES: 13(5,3,5) 4 MHZ E. T .: 3. 25

I f B-O:

M CYCLES: T STATES: 8(5,3) MHZ E. T .: 2. °°

Condition Bits Affected: None

Example:

A typical software routine is used to demonstrate the

use of the DJNZ instruction. This routine moves a line
from an input buffer (INBUF) to an output buffer

235
(IY)

Operation: PC+-IY

Format:

Operands

JP (IY)

1«««0>1 FD

I<<<a; <a; 0 > 1 E9

Description:

The Program Counter (register pair PC) is loaded with

the contents of the IY Register Pair. The next
instruction is fetched from the location designated by
the new contents of the PC.

M CYCLES: T STATES: 8(4,4) MHZ E.T.: 2.00

Condition Bits Affected: None

Example:

If the contents of the Program Counter are 1000H and the

contents of the IY Register Pair are 4800H, after the
execution of

JP (IY)

the contents of the Program Counter will be 4800H.

234
-00 JV{) REIU~ GIUJP-

237
 (OUTBUF). It moves the bytes until it finds a CRt or
until it has moved 80 bytes, whichever occurs first.

LD B,80 ;Set up counter

LD HL,Inbuf ;Set up pointers
LD DE,Outbuf

LOOP: LD A, (HL) ;Get next byte from

;input buffer
LD (DE) ,A ;Store in output buffer
CP ODH ;ls it a CR?
JR Z,DONE ;Yes finished
INC HL ;Increment pointers
INC DE
DJNZ LOOP Loop back i f 80
bytes have not
been moved
DONE:

236
Example:

If the contents of the Program Counter are IA47H, the

contents of the Stack Pointer are 3002H, and memory
locations have the contents:

Location Contents

lA47H CDH
lA48H 35H
lA49H 2lH

then if an instruction fetch sequence begins, the

three-byte instruction CD352lH will be fetched to the
CPU for execution. The mnemonic equivalent of this is

CALL 2l35H

After the execution of this instruction, the contents of

memory address 300lH will be lAH, the contents of
address 3000H will be 4AH, the contents of the Stack
Pointer will be 3000H, and the contents of the Program
Counter will be 2l35H, pointing to the address of the
first opcode of the subroutine now to be executed.

239
CALL nn

Format:

Operands

CALL nn

I <<a: a: <<a: 1 I CD

I .. :In: : : .. I
I.. : In: : : :'1
Note: The first of the two n operands in the assembled
object code above is the least significant byte of a
two-byte memory address.

Description:

The current contents of the Program Counter (PC) are

pushed onto the top of the external memory stack. The
operands nn are then loaded into the PC to point to the
address in memory where the first opcode of a subroutine
is to be fetched. (At the end of the subroutine,a
RETurn instruction can be used to return to the original
program flow by popping the top of the stack back into
the PC.) The push is accomplished by first decrementing
the current contents of the Stack Pointer (register pair
SP), loading the high-order byte of the PC contents into
the memory address now pointed to by the SP; then
decrementing SP again, and loading the low-order byte of
the PC contents into the top of stack. Note: Because
this is a 3-byte instruction, the Program Counter will
have been incremented by 3 before the push is executed.

M CYCLES: T STATES: 17(4,3,4,3,3) 4 MH Z E. T .: 4. 25

Condition Bits Affected: None

238
the push is executed. Condition cc is programmed as one
of eight status which corresponds to condition bits in
the Flag Register (register F). These eight status are
~fined in the table below, which also specifies the
corresponding cc bit fields in the assembled object
code:

cc Condition Relevant
Flag

000 NZ non zero Z

001 Z zero Z
010 NC non carry C
011 C carry C
100 PO parity odd p/V
101 PE parity even p/V
110 P sign positive S
111 M sign negative S

If cc is true:

M CYCLES: 5 T STATES: 17(4,3,4,3,3) 4 MHZ E. T.: 4.25

If cc is false:

M CYCLES: T STATES: 10(4,3,3) 4 MHZ E. T .: 2.50

Condition Bits Affected: None

Example:

If the C Flag in the F register is reset, the contents

of the Program Counter are 1A47H, the contents of the
Stack Pointer are 3002H, and memory locations have the
contents:

Location Contents

1A47H 04n
1A48H 35H
1A49H 21n
then if an instruction fetch sequence begins, the
three-byte instruction 0435210 will be fetched to the
CPU for execution. The mnemonic equivalent of this is

CALL NC,2135H

241
CALL CC, nn

Operation: IF cc TRUE: (SP·t) +- PC H

(SP·2) +- PC l - PC +- nn
Format:

Opcode ~erands

CALL cC,nn

I < ~:cc7--+< a: I
1 0

I.. I In: : : >1

I.. I In: : : >1
Note: The first of the two n operands in the assembled
object code above is the least significant byte of the
two-byte memory address.

Description:

If condition cc is true, this instruction pushes the

current contents of the Program Counter (PC) onto the
top of the external memory stack, then loads the
operands nn into PC to point to the address in memory
where the first opcode of a subroutine is to be fetched.
(At the end of the subroutine, a RETurn instruction can
be used to return to the original program flow by
popping the top of the stack back into PC.) If
condition cc is false, the Program Counter is
incremented as usual, and the program continues with the
next sequential instruction. The stack push is
accomplished by first decrementing the current contents
of the Stack Pointer (SP), loading the high-order byte
of the PC contents into the memory address now pointed
to by SP; then decrementing SP again, and loading the
low-order byte of the PC contents into the top of the
stack. Note: Because this is a 3-byte instruction, the
Program Counter will have been incremented by 3 before

240
 RET

Operation: PCL+-(SP), PCH+-(SP+l)

Format:

RET

Description:

The byte at the memory location specified by the

contents of the Stack Pointer (SP) register pair are
moved to the low order eight bits of the Program Counter
(PC). The SP is now incremented and the byte at the
memory location specified by the new contents of the SP
are moved to the high order eight bits of the PC. The
SP is now incremented again. The next op code following
this instruction will be fetched from the memory
location specified by the PC. This instruction is
normally used to return to the main line program at the
completion of a routine entered by a CALL instruction.

M CYCLES: T STATES: 10(4,3,3) 4 MHZ E. T.: 2.50

Condition Bits Affected: None

Example:

If the contents of the Program Counter are 3535H, the

contents of the Stack Pointer are 2000H, the contents of
memory location 2000H are B5H, and the contents of
memory location 2001H are 1BH, then after the execution
of

RET

the contetns of the Stack Pointer will be 2002H and the

contents of the Program Counter will be 1BB5H, pointing
to the address of the next program opcode to be fetched.

243
After the execution of this instruction, the contents of
memory address 300lR will be lAR, the contents of
address 3000R will be 4AR, the contents of the Stack
Pointer will be 3000R, and the contents of the Program
Counter will be 2l35R, pointing to the address of the
first opcode of the subroutine now to be executed.

~2
M CYCLES: 3 T STATES: 11(5,3,3) 4 MHZ E. T.: 2.75

If cc is false:

~I CYCLES: T STATES: 5 4 MHZ E.T.: 1.25

Condition Bits Affected: None

Example:

If the S flag in the F register is set, the contents of

the Program Counter are 3535H, the contents of the Stack
Pointer are 2000H, the contents of memory location 2000H
are B5H, and the contents of memory location 2001H are
18H, then after the execution of

RET M

the contents of the Stack Pointer will be 2002H and the

contents of the Program Counter will be 18B5H, pointing
to the address of the next program opcode to be fetched.

245
RET cc

Operation: IF cc TRUE: PCl +- (SPI, PC H+- (SP+I)

Format:

RET cc

Description:

If condition cc is true, the byte at the memory location

specified by the contents of the Stack Pointer (SP)
register pair are moved to the low order eight bits of
the Program Counter (PC). The SP ~s now incremented and
the byte at the memory location specified by the new
contents of the SP are moved to the high order eight
bits of the PC. The SP is now incremented again. The
next op code following this instruction will be fetched
from the memory location specified by the PC. This
instruction is normally used to return to the main line
program at the completion of a routine entered by a CALL
instruction. If condition cc is false, the PC is simply
incremented as usual, and the program continues with the
next sequential instruction. Condition cc is programmed
as one of eight status which correspond to condition
bits in the Flag Register (register F). These eight
status are defined in the table below, which also
specifies the corresponding cc bit fields in the
assembled object code.

Condition Relevant
Flag

000 NZ non zero z

001 Z zero z
010 NC non carry C
011 C carry C
100 PO parity odd p/V
101 PE parity even p/V
110 P sign positive s
111 M sign negative s
If cc is true:

244
B generates an interrupt and is acknowledged. (The
interrupt enable out. lEO. of B goes low. blocking any
lower priority devices from interrupting while B is
being serviced). Then A generates an interrupt.
suspending service of B. (The lEO of A goes 'low'
indicating that a higher priority device is being
serviced.) The A routine is completed and a RETl is
issued resetting the lEO of A. allowing the B routine to
continue. A second RETl is issued on completion of the
B roatine and the lEO of B is reset (high) allowing
lower priority devices interrupt access.

~7
RETI

Opera tion: Return from interrupt

Format:

RETI

11»»»>1 ED

I >: :a >>:a >I

0 0 40

Description:

This instruction is used at the end of a maskable

interrupt service routine to:

1. Restore the contents of the Program Counter (PC)

(analogous to the RET instruction)

2. To signal an I/O device that the interrupt routine

has been completed. The RETI instruction also
facilitates the nesting of interrupts allowing higher
priority devicess to temporarily suspend service of
lower priority service routines. Note: This
instruction does not enable interrupts which were
disabled when the interrupt routine was entered.
Before doing the RETI instruction, the enable
interrupt instruction (EI) should be executed to
allow recognition of interrupts after completion of
the current service routine.

M CYCLES: T STATES: 14(4,4,3,3) 4 MH Z Eo T .: 3.50

Condition Bits Affected: None

Example:

Given: Two interrupting devices, A and connected in a

daisy chain configuration with A having a higher
priority than B.
A

~ I_IE_'I_-,-_ _I_E_0-J~
INT~ 246
order-byte first. and 0066H will be loaded onto the
Program Counter. That address begins an interrupt
service routine uhich ends with RETN instruction. Upon
the execution of RETN. the former Program Counter
contents are popped off the external memory stack.
low-order first. resulting in a Stack Pointer contents
again of lOOOH. The program flow continues where it
left off with an opcode fetch to address lA45H.

249
RETN

Operation: Return from non maskable interrupt

Format:

RETN

11 >>:a >>:a >I ED

I >:a :a :a >:a >I

0 45

Description:

This instruction is used at the end of a non-maskable

interrupt service routine to restore the contents of the
Program Counter (PC) (analogous to the RET instruction).
The state of IFF2 is copied back into IFFl so that
maskable interrupts are enabled immediately following
the RETN if they were enabled before the non-maskable
interrupt.

M CYCLES: T STATES: 14(4,4,3,3) 4 MHZ E.T.: 3.50

Condition Bits Affected: None

Example:

If the contents of the Stack Pointer are 1000H and the

contents of the Program Counter are lA45H when a non
maskable interrupt (NMI) signal is received, the CPU
will ignore the next instruction and will instead
restart to memory address 0066H. That is, the current
Program Counter contents of lA45H will be pushed onto
the external stack address of OFFFH and OFFEH, high
order-byte first, and 0066H will be loaded onto the
Program Counter. That address begins an interrupt
service routine which ends with RETN instruction. Upon
the execution of RETN, the former Program Counter
contents are popped off the external memory stack,
low-order first, resulting in a Stack Pointer contents
again of 1000H. The program flow continues where it
left off with an opcode fetch to address lA45H.

248
Example:

If the contents of the Program Counter are lSB3H, after

the execution of

RST 18H (Object code 1101111)

the PC will contain 0018H, as the address of the next

opcode to be fetched.

251
RST p

Format:

Opcode

RST p

Description:

The current Program Counter (PC) contents are pushed

onto the external memory stack, and the page zero memory
lQcation given by operand p is loaded into the PC.
Program execution then begins with the opcode in the
address now pointed to by PC. The push is performed by
first decrementing the contents of the Stack Pointer
(SP), loading the high-order byte of PC into the memory
address now pointed to by SP, decrementing SP again, and
loading the low-order byte of PC into the address now
pointed to by SP. The ReSTart instruction allows for a
jump to one of eight addresses as shown in the table
below. The operand p is assembled into the object code
using the corresponding T state. Note: Since all
addresses are in page zero of memory, the high order
byte of PC is loaded with DOH. The number selected
from the "p" column of the table is loaded into the
low-order byte of PC.

--L
DOH 000
08H 001
10H 010
18H 011
20n 100
2!ln 101
30Il 110
38H 111

11 CYCLES: T STATES: 11(5,3,3) MHZ E. T .: 2.75

260
-INPUT AND aJTPlJT GIUIP-

252
 I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
 IN r, [CJ

Operation: r ~ (C)

Format:

Operands

IN r,(C)

11 >>: >>: >I0 0 ED

10 : 1 ~r~ 0 : 0 : 0 I
Description:

The contents of register C are placed on the bottom half

(AD through A7) of the address bus to select the I/O
device at one of 256 possible ports. The contents of
Register B are placed on the top half (A8 through A15)
of the address bus at this time. Then one byte from the
selected port is placed on the data bus and written into
register r in the CPU. Register r identifies any of the
CPU registers shown in the following table, which also
shows the corresponding 3-bit "r" field for each. The
flags will be affected, checking the input data.

Reg.

B 000
C 001
D 010
E 011
H 100
L 101
A 111

M CYCLES: T STATES: 12(4,4,4) 4 ~mz E. T .: 3. 00

254
IN A, (n)

Operation: A.- (n)

Fo rmat:

Operands

IN A, (n)

I<< >>;a >>I

0 DB

I~<::"I
Description:

The operand n is placed on the bottom half (AO through

A7) of the address bus to select the I/O device at one
of 256 possible ports. The contents of the Accumulator
also appear on the top half (A8 through A15) of the
address bus at this time. Then one byte from the
selected port is placed on the data bus and written into
the Accumulator (register A) in the CPU.

M CYCLES: T STATES: 11(4,3,4) 4 MHZ E. T .: 2. 75

Condition Bits Affected: None

Exampl e:

If the contents of the Accumulator are 23H and the byte

7BR is available at the peripheral device mapped to I/O
port address 01R, then after the execution of

IN A,(OIH)

the Accumulator will contain 7BH.

253
 INI

Operation: (HL) ~ (e) , B ~ B-1, HL ~ HL + 1

Format:

INI

11 >>: >>:a >I0 ED

11 :0 >: :a ;0 >: I
0 Q A2

Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B may be
used as a byte counter, and its contents are placed on
the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are then placed on the address bus
and the input byte is written into the corresponding
location of memory. Finally the byte counter is
decremented and register pair HL is incremented.

M CYCLES: T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown
Z: Set if B-l-O;
reset otherwise
H: Unknown
ply: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H, the contents of

register Bare 10H, the contents of the HL register pair
are 1000H, and the byte 7BH is available at the
peripheral device mapped to I/O port address 07H, then

256
Condition Bits Affected:

S: Set i f input data is negative;

reset otherwise
z: Se t i f input data is zero;
reset otherwise
H: Reset
P/V: Set i f parity is even;
reset otherwise
N: Reset
C: Not affected

Example:

If the contents of register Care 07H, the contents of

register Bare lOH, and the byte 7BH is available at the
peripheral device mapped to I/O port address 07B, then
after the execution of

IN D,(C)

255
 INIR

Operation: (HL)+-(C), 8+-8-1, HL+-HL+1

Format:

INIR

I<>: >>: >I

1 0 0 ED

Ir; 0 : r; < 0 :a >;a I 82

Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B is used
as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are placed on the address bus and
the input byte is written into the corresponding
location of memory. Then register pair HL is
incremented, the byte counter is decremented. If
decrementing causes B to go to zero, the instruction is
terminated. If B is not zero, the PC is decremented by
two and the instruction repeated. Interrupts will be
recognized and two refresh cycles will be executed after
each data transfer. Note that if B is set to zero prior
to instruction execution, 256 bytes of data will be
input.

I f B=O:

H CYCLES: T STATES: 21(4,5,3,4,5) 4 HHZ E.T.: 5.25

I f B=O:

H CYCLES: T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

258
after the execution of

un
memory location lOOOH will contain 7BH, the HL register
pair will contain lOOlH, and register B will contain
OFH.

257
 IND

Operation: (HL)+-(C), B +- B-1, HL+-HL-1

Format:

IND

I<<< >>;a >I 0 ED

1<0>:0>:0;<01 AA

Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B may be
used as a byte counter, and its contents are placed on
the top half (A8 through A15) of the address bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are placed on the address bus and
the input byte is written into the corresponding
location of memory. Finally the byte counter and
register pair HL are decremented.

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown
Z: Set if B-l-O;
reset otherwise
H: Unknown
ply: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H, the contents of

register Bare 10H, the contents of the HL register pair
are 1000H, and the byte 7BH is available at the

260
Condition Bits Affected:

S: Unknown
Z: Set
H: Unknown
p/V: Unknown
N: Set
C: llot affected

Example:

If the contents of register Care 07H. the contents of

register Bare 03H. the contents of the HL register pair
are lOOOH. and the following sequence of bytes are
available at the peripheral device mapped to I/O port of
address 07H:

SlH
A9H
03H

then after the execution of

INIR

the HL register pair will contain l003H. register B will

contain zero. and memory locations will have contents as
follows:

Location Contents

lOOOH SlH
lOOlH A9H
l002H 03H

259
 INDR

Operation: (HL)+-(C), 8+-8-1. HL+-HL-1

Format:

INDR

I<<<a: << >I 0 ED

I<a: r; <<a; < I 0 BA

Description:

The contents of register C are placed on the bottom half

(AD through A7) of the address bus to select the I/O
device at one of 256 possible ports. Register B is used
as a byte counter, and its contents are placed on the
top half (A8 through A15) of the address. bus at this
time. Then one byte from the selected port is placed on
the data bus and written to the CPU. The contents of
the HL register pair are placed on the address bus and
the input byte is written into the corresponding
location of memory. Then HL and the byte counter are
decremented. If decrementing causes B to go to zero, the
instruction is terminated. If B is not zero, the PC is
decremented by t~o and the instruction repeated.
Interrupts will be recognized and two refresh cycles
will be executed after each data transfer. Note that if
B is set to zero prior to instruction execution, 256
bytes of data will be input.

I f B=O:

M CYCLES: T STATES:21(4,5,3,4,5) 4 MHZ E.T.: 5.25

I f B=O:

M CYCLES: T STATES: 16(4,5,3,4) 4 UHZ E.T.: 4.00

262
peripheral device mapped to I/O port address 07H, then
after the execution of

IND
memory location 1000H will contain 7BH, the HL register
pair will contain OFFFH, and register B will contain
OFH.
 OUT (n), A

Operation: (n) +- A

Format:

Operands

OUT (n),A

I<<a >;a ;a >>, 03

Description:
I~<:: ;.)
The operand n is placed on the bottom half (AO through
A7) of the address bus to select the I/O device at one
of 256 possible ports. The contents of the Accumulator
(register A) also appear on the top half (A8 through
A15) of the address bus at this time. Then the byte
contained in the Accumulator is placed on the data bus
and written into the selected peripheral device.

M CYCLES: T STATES: 11(4,3,4) 4 MHZ E.T.: 2.75

Condition Bits Affected: None

Example:

If the contents of the Accumulator are 23H, then after

the execution of

OUT (OIH),A

the byte 23H will have been written to the peripheral

device mapped to I/O port address 01H.

264
Condition Bits Affected:

S: Unknown
Z: Set
H: Unknown
ply: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H, the contents of

register Bare 03H, the contents of the HL register pair
are lOOOH, and the following sequence of bytes are
available at the peripheral device mapped to I/O port
address 07H:

5111
A9H
03H

then after the execution of

INDR

the HL register pair will contain OFFDH, register B will

contain zero, and memory locations will have contents as
follows:

Location Contents

OFFEH 03H
OFFFH A9H
lOOOH 5111

263
Condition Bits Affected: None

Example:

If the contents of register Care 01H and the contents

of register Dare SAH. after the execution of

OUT (C).D

the byte SAH will have been written to the peripheral

device mapped to I/O port address 01H.

266
OUT (el, r

Operation: (e) +- r

Format:

Operands

OUT (C) ,r

I<<< >>;a >I 0 ED

10: 1 ~r~o: 0: 11
Description:

The contents of register C are placed on the bottom half

(AO through A7) of the address bus to select the I/O
device at one of 256 possible ports. 'The contents of
Register B are placed on the top half (A8 through A15)
of the address bus at this time. Then the byte
contained in register r is placed on the data bus and
written into the selected peripheral device. Register r
identifies any of the CPU registers shown in the
following table, which also shows the corresponding
3-bit "r" field for each which appears in the assembled
object code:

Register

B 000
C 001
D 010
E 011
H 100
L 101
A 111

11 CYCLES: T STATES: 12(4,4,4) 411HZ E. T.: 3.00

265
59H, then after the execution of

OUTI

register B will contain OFH, the HL register pair will

contain 1001H, and the byte 59H will have been written
to the peripheral device mapped to I/O port address 07H.

268
OUTI

Operation: (C)~(HL). B~B-1, HL~HL+1

Format:

Opcode

OUT!

I<<< >>:a >I0 ED

I< >:a :a :a >>I

0 A3

Description:

The contents of the HL register pair are placed on the

address bus to select a location in memory. The byte
contained in this memory location is temporarily stored
in the CPU. Then, after the byte counter (B) is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its
decremented value is placed on the top half (A8 through
A15) of the address bus. The byte to be output is
placed on the data bus and written into selected
peripheral device. Finally the register pair HL is
incremented.

M CYCLES: T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown
Z: Set if B-1-0;
reset otherwise
H: Unknown
ply: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H, the contents of

register Bare 10H, the contents of the HL register pair
are 1000H, and the contents of memory address 1000H are

267
Condition Bits Affected:

S: Unknown
z: Set
H: Unknown
p /V: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H. the contents of

register Bare 03H. the contents of the HL register pair
are lOOOH. and memory locations have the following
contents:

Location Contents

lOOOH 5iH
lOOlH A9H
l002H 03H

then after the execution of

OTIR

the HL register pair will contain l003H. register B will

contain zero. and a group of bytes will have been
written to the peripheral device mapped to I/O port
address 07H in the following sequence:

5iH
A9H
03H

270
OTIR

Operation: (C)+-(HL), B+-B-H HL+-HL+1

Format:

OTIR

1«<0»:0>1 ED

I <a: <<a; a: <11 83

Description:

The contents of the HL register pair are placed on the

address bus to select a location in memory. The byte
contained in this memory location is temporarily stored
in the cpu. Then, after the byte counter (B) is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its
decremented value is placed on the top half (AB through
A15) of the address bus at this time. Next the byte to
be output is placed on the data bus and written into the
selected peripheral device. Then register pair HL is
incremented. If the decremented B register is not zero,
the Program Counter (PC) is decremented by 2 and the
instruction is repeated. If B has gone to zero, the
instruction is terminated. Interrupts will be recognized
and two refresh cycles will be executed after each data
transfer. Note that if B is set to zero prior to
instruction execution, the instruction will output 256
bytes of data.

If B-O:

M CYCLES: T STATES: 21(4,5,3,4,5) 4 MHZ E. T.: 5.25

I f B-O:

M CYCLES: T STATES: 16(4,5,3,4) 4 MHZ E.!.: 4.00

269
register Bare IOH, the contents of the HL register pair
are IOOOH, and the contents of memory location IOOOH are
59H, after the execution of

OUTD

register B will contain OFH, the HL register pair will

contain OFFFH, and the byte 59H will have been written
to the peripheral device mapped to I/O port address 07H.

272
aUTO

Operation: (C)+-(HL), 8+-8-1, HL+-HL-1

Format:

OUTDo

11 >>:°>>: 1I 0: ED

1 1:0;1:°:1:°;1;11 AB

Description:

The contents of the HL register pair are placed on the

address bus to select a location in memory. The byte
contained in this memory location is temporarily stored
in the CPU. Then, after the byte counter (B) is
decremented, the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter, and its
decremented value is placed on the top half (AB through
A15) of the address bus at this time. Next the byte to
be output is placed on the data bus and written into the
selected peripheral device. Finally the register pair
HL is decremented.

M CYCLES: 4 T STATES: 16(4,5,3,4) 4 MHZ E.T.: 4.00

Condition Bits Affected:

S: Unknown
Z: Set if B-1-0j
reset otherwise
H: Unknown
p/V: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H, the contents of

271
Condition Bits Affected:

S: Unknown
z: Set
H: Unknown
p /V: Unknown
N: Set
C: Not affected

Example:

If the contents of register Care 07H. the contents of

register Bare 03H. the contents of the HL register pair
are lOOOH. and memory locations have the following
contents:

Location Contents

OFFEH 5lH
OFFFH A9H
lOOOH 03H

then after the execution of

OTDR

the HL register pair will contain OFFDH. register B will

contain zero. and a group of bytes will have been
written to the peripheral device mapped to I/O port
addres 07H in the following sequence:

03H
A9H
5lH

274
OTDR

Operation: (C)+-(HL). 8+-8-1. HL+-HL-1

Format:

OTDR

1«««0:11 ED

I <0: <<<0: <11 BB

Description:

The contents of the HL register pair are placed on the

address bus to select a location in memory. The byte
contained in this memory location is temporarily stored
in the CPU. Then. after the byte counter (B) is
decremented. the contents of register C are placed on
the bottom half (AO through A7) of the address bus to
select the I/O device at one of 256 possible ports.
Register B may be used as a byte counter. and its
decremented value is placed on the top half (A8 through
A15) of the address bus at this time. Next the byte to
be output is placed on the data bus and written into the
selected peripheral device. Then register pair HL is
decremented and if the decremented B register is not
zero, the Program Counter (PC) is decremented by 2 and
the instruction is repeated. If B has gone to zero. the
instruction is terminated. Interrupts will be
recognized and two refresh cycles will be executed after
each data transfer. Note that if B is set to zero prior
to instruction execution, the instruction will output
256 bytes of data.

I f B-O:

M CYCLES: T STATES: 21(4,5,3,4,5) 4 MH Z E. T .: 5 • 25

I f B"O:

M CYCLES: T STATES: 16(4.5.3,4) 4 MHZ E. T.: 4.00

273
EX (SP),IX Exchange the location (SP)
and IX 81
EX (SP),IY Exchange the location (SP)
and IY 812
EX AF,AF' Exchange the contents of AF and AF' 78
EX DE,HL Exchange the contents of DE and HL 77
EXX Exchange the contents of
BC,DE,HL with contents of
BC' ,DE' ,HL' respectively 79
HALT HALT (wai-t for interrupt or reset) 14P
1M 0 Set interrupt mode 0 143
1M I Set interrupt mode I , 1~
1M 2 Set interrupt mode 2 145
IN Ii., (n) Load the Acc. with
input from device n " 253
IN r, (C) Load the Reg. r with
input from device (C) 254
INC (HL) Increment location (HL) 124
INC IX Increment IX 1513
INC (IX+d) Increment location (IX+d) 125
INC IY Increment IY 159
INC (IY+d) Increment location (IY+d) 12'7
INC r Increment Reg. r 122
INC ss Increment Reg. pair ss 15'7
IND Load location (HL) with
input from port (C),
decrement HL and B 260
INDR Load location (HL) with
input from port (C),
decrement HL and decrement B,
rep eat un til B• 0 .. •.. . .• 262
INI Load location (HL) with
input from port (C);
and increment HL and decrement B 256
INIR Load location (HL) with
input from port (C),
increment HL and decrement B,
repeat until B.O 258
JP (HL) Unconditional Jump to (HL) 232
JP (IX) Unconditional Jump to (IX) 233
JP (IY) Unconditional Jump to (IY) 234
JP cc,nn Jump to location nn
if condition cc is true 221
JP nn Unconditional jump to location nn 220
JR C,e Jump relative to
PC+e if carry· I 224
JR e Unconditional Jump
relative to PC+e ~ 223
JR NC,e Jump relative to
PC+e if carry.O 226

276
 zao-cpu INSTRUCTION SET

ALPHABETICAL
ASSEMBLY MNEMONIC OPERATION PAGE

ADC HL,ss Add wi th Carry Reg. pair ss to HL .••..•.......... 149

ADC A,s Add with carry operand s to Acc •.•••.••........... 108
ADD A,n Add value n to Acc 102
ADD A,r Add Reg. r to Acc 100
ADD A, (HL) Add location (HL) to Acc •••••••.•..•.••••••••.•••••..••• 103
ADD A, (IX+d) Add location (IX+d) to Acc •...............•...•..•..•• 104
ADD A, (IY+d) Add location (IY+d) to Acc •........................... 106
ADD HL,ss Add Reg. pair ss to Hr. .......••.•.•••...................•. 147
ADD IX,pp Add Reg. pair pp to IX ..........................•.....•..• 153
ADD IY,rr Add Reg. pair rr to I Y 155
AND s Logical ' AND' of operand sand Acc •••••.••...... 114
BIT b, (HL) Test BIT b of location (HL) .••..••••••••.••..•..•••••• 205
BIT b, (IX+d) Test BIT b of lociition (IX+d) 207
BIT b, (IY+d) Test BIT b of location (IY+d) 209
BIT b,r Test BIT b of Reg. r 203
CALL cc,nn Call subroutine at location nn if
con d i t ion c c i s t rue 240
CALL nn Unconditional call subroutine
at location nn 238
CCF Complement carry flag 137
CP s Compare operand s. wi th Acc 120
CPD Compare location (HL) and Acc.
decrement HL and BC 95
CPDR Compare location (HL) and Acc.
decrement HL and BC,
repeat until BC.O 97
CPI Compare location (HL) and Acc.
increment HL and decrement BC 91
CPIR Compare location (HL) and Acc.
increment HL, decrement BC
repeat until BC·O, 93
CPL Complement Acc. (l's comp) 134
DAA Decimal adjust Acc 132
DEC m Decrement operand m 129
DEC IX Decrement IX 161
DEC IY Decrement IY 162
DEC 88 Decrement Reg. pair 88 160
DI Disable interrupts 141
DJNZ e Decrement B and Jump
relative if B·O 235
EI Enable interrupts 142
EX (SP),HL Exchange the location (SP)
and HL 80

275
LDI Load location (DE) with location (HL),
increment DE,HL, decrement BC .•...•...•........ ~ .•. a3
LDIR Load location (DE) with location (HL),
increment DE,HL, decrement
BC and repeat until BC=O .•...••.................•....... 85
NEG Negate Acc. (2's complement) •..•...•.•••••......••... 13!l
NOP No operation •....................•..•.••••.•••••.•..•.••••..••.•. 139
OR s Logical 'OR' of operand sand Acc •.............. 116
OTDR Load output port (C) with location (HL)
decrement HL and B,
rep eat un til B= 0 273
OTIR Load output port (C) with location (HL),
increment HL, decrement B,
rep eat un til B= 0 269
OUT (C),r Load output port (C) with Reg. r .....••.••........ 26!/
OUT (n),A Load output port (n) with Acc •..•.•••..•........... 264
OUTD Load output port (C) with location (HL),
decrement HL and B....•.•••••.••..•••••.••.•...•••...••••.••• 271
OUTI Load output port (C) with location (HL),
increment HL and decrement B 267
POP IX Load IX with top of stack 74
POP IY Loa d I Y wit h top 0 f s t a c k .. . . . . . . . . . .. .. . . . . . . .. . .. 75
POP qq Load Reg. pair qq with top of stack 72
PUSH IX Load IX onto stack 70
PUSH IY Load IY onto stack •.•..•••••.••.•••••••..•••.....•........... 71
PUSH qq Load Reg. pai.r qq onto stack 69
RES b,m Reset Bit b of operand m ...................••..•..••..•. 217
RET Return from subroutine 243
RET cc Return from subroutine if condition
c c i s t rue 244
RETI Return from interrupt 246
RETN Return from non maskable interrupt ..•.••...•.•.. 248
RL m Rota te left through carry operand m •••••••••••• 180
RLA Rotate left Acc. through carry ......•....•..•..•.•. 166
RLC (HL) Rotate location (HL) left circular ...•.•..•••... 174
RLC (IX+d) Rotate location (IX+d) left circclar ........•.. 176
RLC (IY+d) Rotate location (IY+d) left circular 178
RLC r Rotate Reg. r left circular 172
RLCA Rotate left circular Acc 164
RLD Rotate digit left and right
between Acc. and location (HL) ..........•.......•... 198
RR m Rotate right through carry operand m 186
RRA Rotate right Acc. through carry 170
RRC m Rotate operand m right circular 183

278
JR NZ,e Jump relative to
PC+e if non zero (Z-O) ................•..........•....••.. 230
JR Z,e Jump relative to
PC+e if zero (Z-1) ....•...................................... 228
LD A, (BC) Load Ace. with location (BC) ...•.....•......•........ 42
LD A, (DE) Load Ace. with location (DE) 43
LD A,I Load Ace. with I 48
LD A,(nn) Load Ace. with location nn .........•....••..••...•.... 44
LD A,R Load Ace. with Reg. R 49
LD (BC) ,A Load location (BC) with Ace •......................... 45
LD (DE) ,A Load location (DE) with Ace •......................... 46
LD (HL),n Load location (HL) with value n 39
LD dd,nn Load Reg. pair dd with value nn 53
LD dd,(nn) Load Reg. pair dd with location (nn>. 57
LD HL, (nn) Load HL with location (nn) 56
LD (HL),r Load location (HL) with Reg. r ......•...•.......... 34
LD I,A Load I with Ace 50
LF IX,nn Load IX with value nn 54
LD IX, (nn) Load IX with location (nn) 59
LD (IX+d),n Load location (IX+d) with value n 40
LD (IX+d),r Load location (IX+d) with Reg. r •.•............... 35
LD IY,nn Load IY with value nn 55
LD IY,(nn) Load IY with location (nn) 60
LD (IY+d) ,n Load location (IY+d) with value n 41
LD (IY+d),r Load location (IY+d) with Reg. r 37
LD (nn),A Load location (nn) wi th Ace. 47
LD (nn),dd Load location (nn) with Reg. pair dd 62
LD (nn),HL Load location (nn) with HL 61
LD (nn),IX Load location (nn) with IX 64
LD (nn),IY Load location (nn) with IY 65
LD R,A Load R wi th Ace. 51
LD r,(HL) Load Reg. with location (HL) ...•................. 29
LD r,(IX+d) Load Reg. with location (IX+d) 30
LD r,(IY+d) Load Reg. with location (IY+d) 32
LD r,n Load Reg. with value n 28
LD r , r ' Lo ad Reg. r wi t h Reg. r' 27
LD SP,HL Load SP with HL 66
LD SP,IX Load SP with IX ...•...•...........•....•...................... 67
LD SP,IY Load SP with IY 68
LDD Load location (DE) with location (HL),
decrement DE,HL and BC ...............................••.. 87
LDDR Load location (DE) with location (HL),
decrement DE,HL and BC;
repea t un til BC-O 89

277
 APPENDIX A
ERROR MESSAGES AND EXPLANATIONS

1) WARNING - OPCODE REDEFINED

Indicates that an opcode has been redefined by
a macro so that future uses of the opcode will
~esult in the appropriate macro call. This
message may be suppressed by the NOW option.
2) NAME CONTAINS INVALID CHARACTERS
Indicates that a name (either a label or an
operand) contains illegal characters. Names
must start with an alphabetic character and
any following characters must be either
alphanumeric (A ••• Z or 0 ••• 9), a question mark
(1) or an underbar ( ).
3) INVALID OPCODE
Indicates that the opcode was not recognized.
Occurs when the opcode contains an illegal
charac ter (incl ud ing no.n-pr in ting con tro 1
characters), when the opcode is not either all
upper case or all lower case, or when macros
are used and the M option is not specified.
4) INVALID NUMBER
Indicates an invalid character in a number.
Occurs when a number contains an illegal
character (including non-printing control
characters) or a number contains a digit not
allowed in the specified base (e.g., 8 or 9 in
an octal number or a letter in a hexadecimal
number where the trailing H was omitted.)
5) INVALID OPERATOR
Indicates use of an invalid operator in an
expression. Occurs when an operator such as
AND or XOR is misspelled or contains illegal
characters.
6) SYNTAX ERROR
Indicates the syntax of the statement is
invalid. Occurs when an expression is
incorrectly formed, unmatched parenthesis are
found in an operand field, or a DEFM string is
either too long (greater than 63 characters)
or contains unbalanced quotes.
7) ASSEMBLER ERROR
Indicates that the assembler has failed to
process this instruction. Usually occurs when
an expression is incorrectly formed.
8) UNDEFINED SYMBOL
Indicates that a symbol in an operand field

280
RRCA Rotate right circular Acc •.•.•........•..•..•.....•... 168
RRD Rotate digit right and left
between Acc. and location (HL) ........•...........• 200
RST P Restar t to location p .....•................•.............. 250
SBC A, s Subtract operand s
from Acc. with carry 112
SBC HL,ss Subtract Reg. pair ss from
HL with carry 151
SCF Set carry flag (C-l) 138
SET b,(HL) Set Bit b 0 f l o cat ion ( HL) 212
SET b,(IX+d) Set Bit b of location (IX+d). 213
SET b, (IY+d) Set Bit b of location (IY+d) 215
SET b, r Set Bit b of Reg. r 211
SLA m Shift operand m left arithmetic 189
SRA m Shift operand m right arithmetic 192
SRL m Shift operand m right logical 195
SUB s Subtract operand s from Acc 110
XOR s Exclusive 'OR' operand sand Acc 118

279
 bytes). The line will be truncated.
16) MACRO STACK OVERFLOW
Indicates that the depth of nesting of macro
calls has exceeded the macro parameter stack
buffer capacity. Occurs when the sum of the
parameter string lengths (plus some additional
information for each macro call) is longer
than the buffer (currently 256 bytes), which
often happens if infinitely recursive macro
calls are used. The macro call which caused
the error will be ignored.
17) INCLUDE NESTED TOO DEEP
Indicates that a *Include command was found
which would have caused a nesting of included
source files to a depth greater than four,
where the original source file is considered
to be level one. The command will be ignored.
18) GLOBAL DEFINITION ERROR
Indicates that either a label was present on a
GLOBAL pseudo-op statement, or there was an
attempt to give an absolute value to a GLOBAL
symbol in a relocatable module. The latter
case is not allowed since all GLOBALs in a
relocatable module will be relocated'by the
Linker. May occur either after a GLOBAL
pseudo-op or after an EQU or DEFL statement
which is attempting to absolutize a
relocatable GLOBAL symbol.
19) EXTERNAL DEFINITION ERROR
Indicates that either a label was present on
an EXTERNAL pseudo-op statement, or there was
an attempt to declare a symbol to be EXTERNAL
which had previously been defined within the
module to have an absolute value. May occur
due to a misspelling or other oversight.
20) NAME DECLARED GLOBAL AND EXTERNAL
Indicates that the name was found in both a
GLOBAL pseudo-op and an EXTERNAL pseudo-op
which is contradictory. May occur due to a
misspelling or other oversight.
21) LABEL DECLARED AS EXTERNAL
Indicates that a name has been declared in
both an EXTERNAL pseudo-op and as a label in
this module. May occur due to a misspelling
or other oversight.
22) INVALID EXTERNAL EXPRESSION
Indicates that a symbol name which has been
declared in an EXTERNAL pseudo-op is
improperly used in an expression. May occur
when invalid arithmetic ope~ators are applied
to an external expression or when the mode of

~2
 was never defined. Occurs when a name is
misspelled or not declared as a label for. an
instruction or pseudo-ope
9) INVALID OPERAND COMBINATION
Indicates that the operand combination for
this opcode is invalid. Occurs when a register
name or condition code is missspelled or
incorrectly used with the particular opcode.
10) EXPRESSION OUT OF RANGE
Indicates that the value of an expression is
either too large or too small for the
appropriate quantity. Occurs on 16-bit
arithmetic overflow or division by zero in an
expression, incrementing the reference counter
beyond a 16-bit value, or trying to use a
value which will not fit into a particular
bit-field - typically a byte.
11) MULTIPLE DECLARATION
Indicates that an attempt was made to redefine
a label. Occurs when a label is. misspelled,
or mistakenly used several times. The
pseudo-op DEFL can be used to assign a value
to a label which can then be redefined by
another DEFL.
12) MACRO DEFINITION ERROR
Indicates that a macro is incorrectly defined.
Occurs when the M option is not specified but
macros are used, when a macro is defined
within another macro definition, when the
parameters are not correctly specified, or an
unrecognized parameter is found in the macro
body.
13) UNBALANCED QUOTES
Indicates that a string is not properly
bounded by single quote marks or quote marks
inside a string are not properly matched in
pairs.
14) ASSEMBLER COMMAND ERROR
Indicates that an assembler command is not
recognized or is incorrectly formed: The
command must begin with an asterisk (*) in
column one, the first letter identifies the
command, and any parameters such as 'ON','OFF'
or a filename must be properly delimited. The
command will be ignored.
15) MACRO EXPANSION ERROR
Indicates that the expansion of a single line
in a macro has overflowed the expansion
buffer. Occurs when substitution of parameter
causes the line to increase in length beyond
the capacity of the buffer (currently 128
 APPENDIX B
INSTRUCTION SET ALPHABETICAL ORDER
2-BO CRUSS ASSEMBLER VERSION 1.06 OF 06/18176
07109176 10=22 :47 OPCOOE L ISTlNG
LUC 08J COOt: STMT SOURCE STATEMENT LOC 08J CODE STMT SOURCE STATEMENT

0000 liE 1 ADC A,IHLl 001C CB56 70 8IT 2,CHL!

0001 DDlIE05 2 ADC A, CIX+INDI 007E DOC80556 71 BIT 2,CIX+INDI
0004 FD8E05 3 ADC A,CIY+INDI 0082 FDCB0556 72 BIT 2,IIY+INDI
0007 8F 4 AOC A,A 0086 C851 13 BIT 2,A
0008 118 5 ADC A,8 0088 CB50 74 BIT 2,B
0009 89 6 ADC A,C OOBA CB51 75 BIT 2,C
OOOA BA 1 ADC A,D OOBC CB52 76 BIT 2,0
0008 8B B ADC A,E OOBE C853 71 8IT 2,E
OOOC 8C 9 AOC A,H 0090 CB54 78 BIT 2,H
0000 80 10 ADC A, L 0092 C855 79 8IT 2,L
OOOE CE20 11 ADC A,N 0094 C85E 80 8IT 3'Ct Ll
0010 ED4A 12 AOC HL,8C 0096 ODCB055E Bl BIT 3,1 X+INDI
0012 ED5A 13 AOC HL,DE 009A FDCB055E 82 BIT 3,llY+INOI
0014 ED6A 14 ADC HL,HL 009E C85F B3 BIT 3,AI
0016 ED7A 15 ADC HL, SP OOAO C858 114 BIT 3,B
00111 86 16 ADD A,IHL I 00A2 CB59 85 BIT 3,C
0019 DOB605 11 ADO A,CIX+INDI 00A4 CB5A 86 BIT 3,0
001C FD8605 18 ADO A,IIY+INDI 00A6 CB5B 87 BIT 3,E
001F B7 19 ADO A,A 00A8 CB5C 8B 8IT 3,H
0020 80 20 ADO A,B OOAA C85D 69 BIT 3,L
0021 61 21 ADO A ,C OOAC CB66 90 8IT 4,C!\tLl
0022 62 22 ADO A,D OOAE DDC80566 91 8IT 4,IIX+INDI
0023 63 23 AOD A ,E 00B2 FDCB0566 92 8IT 4,IIY+INDI
0024 84 24 ADO A,H 00B6 C8b7 93 BIT 4,A
0025 85 25 ADD A,L OOBB CB60 94 BIT 4,8
0026 C620 26 ADO A,N OOBA CB61 95 BIT 4,C
0026 09 27 ADD HL,8C OOBC CB62 96 BIT 4,0
0029 19 28 ADD HL,OE OOBE CB63 97 8IT 4,E
002A 29 29 ADO HL,HL OOCO CB64 96 8IT 4,H
0028 39 30 ADD HL, SP 00C2 CB65 99 8IT 4,L
002C 0009 31 ADD IX,BC 00C4 CB6E 100 !lIT 5tllitLl
002E 0019 32 ADD IX,OE 00C6 DDC8056E 101 81T 5,IIX+INDI
0030 0029 33 ADD IX,IX OOCA FDC8050E 102 8IT 5, ClY+INDI
0032 0039 34 ADO IX,SP OOCE C86F 103 BIT 5,A
0034 FOOII 35 ADD IY,BC 0000 CBb6 104 BIT 5,8
0030 F019 30 ADO IY,OE 0002 C809 105 8IT 5,C
0038 F029 37 ADO IV"V 0004 CB6A 106 8IT 5,0
003A F0311 36 ADO IV,SP 0006 CB6B 101 8IT 5, E
003C A6 39 AND CHLI 0008 C86C 108 BIT 5,H
0030 DOA605 40 AND II X+INOI OOOA CB60 109 BIT 5,L
0040 FOA605 41 AND IIY+INDI OODC CB76 110 8IT 60lljiLl
0043 Al 42 AND A OODE ODCB0576 111 lilT 6,IIX+INDI
0044 AO 43 AND 8 00E2 FDCB0576 112 !lIT 6,IIY+INOI
0045 Al 44 AND C 00E6 CB77 113 !lIT 6,A
0046 A2 45 AND 0 00E8 CB10 114 BIT 6,B
0041 A3 46 AND E OOEA CBll 115 BIT 6,C
0046 A4 47 AND H OOEC C872 116 BIT 6,0
0049 A5 48 AND L OOEE CB13 117 BIT 6,E
004A H2O 49 AND N OOfO Cll14 118 BIT 6,H
004C CB46 50 BIT O,IHLI 00F2 CB15 119 BIT 6,L
004E DOCB05't6 51 BIT O,IIX+INOI 00f4 CB7E 120 BIT 7,CfiLl
0052 FOCB0546 52 BIT 0,( IY+INOI 00F6 00CB057E 121 BIT 7,IIX+INOI
0056 CB47 53 BIT O,A OOFA FOCB057E 122 BIT l,IIV+INDI
0056 CB40 54 8IT 0,8 OOfE CBlf 123 BIT 7,A
005A CB41 55 BIT O,C 0100 C618 124 BIT 7,B
005C CB42 56 BIT 0,0 0102 C879 125 BIT 7,C
005E C843 51 61T O,E 0104 CB1A 126 BIT 1,0
0060 CB't4 5B BIT O,H 0106 C618 127 BIT l,E
0062 CB45 59 BIT O,L 0106 CB1C 128 BIT l,H
0064 C84E 60 BIT l,CHU 010A CBID 129 8IT l,l
0006 00CB05'tE 61 BIT l,CIX+iNOI 010C OC8405 130 CAll C,~N
006A fOC805'tE 62 BIT l,CIY+INOI 010f FC8't05 131 CALL M,NN
006E CB4F 63 BIT l,A 0112 048405 132 CAll NC,NN
0010 CB4B 64 8IT l,B 0115 CDB405 133 CALL NN
0072 CB49 65 BIT l,C 0118 C't8405 134 CAll NZ,NN
0014 CB4A 66 8IT I,D 0118 F48405 135 CAll P,~
0016 CB4B 67 BIT l,E 011E ECB405 136 CAll PE,NN
0078 Cll4C 68 8IT l,H 0121 E48't05 137 CAll PO,NN
007A CB40 69 BIT l,l 012't CC8405 138 CAll Z,NN

284
 an operand m~st be either absolute or
relocatable.
23) INVALID RELOCATABLE EXPRESSION
Indicates than an expression which contains a
relocatable value (either a label or the
reference counter sumbol $ in a relocatable
module) is improperly formed or used. May
occur when invalid arithmetic operators are
applied to a relocatable expression or when
the mode of an operand must be absolute.
Remember that all relocatable values
(addresses) must be represented in 16 bits.
24) EXPRESSION MUST BE ABSOLUTE
Indicates that the mode of an expression is
not absolute when it should be. May occur
when a relocatable or external expression is
used to specify a quantity that must be either
constant or representable in less than 16
bits.
25) UNDEFINED GLOBAL(S)
Indicates that one or more sumbols which were
declared in a GLOBAL pseudo-op were never
actually defined as a label in this module.
May occur due to a misspelling or other
oversight.
26) WARNING - ORG IS RELOCATABLE
Indicates that an ORG statement was
encountered in a relocatable module. This
warning is issued to remind the user that the
reference counter is set to a relocatable
value, not an absolute one. May occur when
the Absolute option is not specified for an
absolute module. This warning may be
suppressed by the NOW option.

283
 Z-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18176
01109176 10J22JIo7 opeOOE LISTING
Loe 08J CODE STMT SOURCE STATEMENT Loe OBJ eOOE STMT SOURCE STATEMENT

022E
022F
70
3E20
277
278
LO
LO
A,L
A,N
02 AS
02AB
OD6E05
FD6E05
3'06
3'07
LO
LO t:::~:::g:
0231 '06 279 LO B,(HLI 02AE 6F 3'08 LO L,A
0232 00'0605 280 LO B,(JX"INOI 02AF 68 3'09 LO L,8
0235 FOlo605 281 LO B,II\'.. INOI 0280 69 350 LO L,e
0238 '07 282 LO B,A 02B1 6A 351 LO L,O
0239 '00 l83 LO 8,8 0282 6B 352 LO L,E
023A '01 28'0 LO B,e 02B3 6e 353 LO L,H
0238 '02 285 LO B,O 02BIo 6D 35'0 LO L,L
023e '03 286 LO B,E 02B5 2E20 355 LO L,N
0230 '0'0 287 LO B,H,NN 02B7 ED7B81005 356 LO SP,UINI
OnE '05 '288 LO B,L 0288 F9 357 LO SP,H~
023F 0620 289 LO B,N 028e OOF9 358 LO SP,Il(
02'01 EDitB81005 290 LO Be,INNI 028E FDF9 359 LD SP, It
0245 018'005 291 LO Be,NN 02eo 318'005 360 LO SP,Nr,!
0210B 4E 292 LD e,lHlI 02e3 EOU 361 LOO
0249 00loE05 293 LO e,( IXHNDI 02es ED88 362 LODR
0210e FOloE05 29'0 LO e,IIYHNOI 02e7 EDAO 363 LOI
0210F 'oF 295 LO e,A 02e9 EOBO 36'0 LOIR
0250 '08 296 LO e,B 02e8 EOIoIo 365 NEG
0251 49 297 LO e,e 02eo 00 3bb Nap
0252 loA 298 LO e,o 02eE B6 361 OR (HLI
0253 loB 299 LO e,E 02eF 00B605 368 OR IIXt>t NOI
0254 Ioe 300 LO e,H 0202 FOB605 369 OR (lY" NOI
0255 '00 301 LO e,L 0205 B7 370 OR A
0256 OE20 302 LO e,N 0206 BO 371 DR B
025B 56 303 LD O,lHlI 02D7 Bl 372 OR e
0259 OD5605 30'0 LO O,IIXHNDI 0208 B2 373 OR 0
025e F05605 305 LO 0,( IY+INOI 0209 B3 37'0 OR E
025F 57 306 LO O,A 020A Bio 375 OR H
0260 50 307 LO O,B 020B B5 376 OR L
0261 51 3011 LO !;l,e 020C Fb20 377 OR N
0262 52 309 LO D,O 020E EOBB 378 DTOR
02b3 53 310 LO O,E 02EO EOB3 379 OUR
02blo 5'0 311 LO O,H 02E2 E079 380 DUT (CI,A
02b5 55 312 LO O,L 02E1t EOlol 381 OUT ICI.B
0266 1620 313 LO O,N 02E6 EDit9 382 OUT lel.C
026B E05BBIo05 31'0 LO DE, (I'll'll 02E8 E051 383 OUT (CHO
026e 118'005 315 LO OE,NN 02EA ED59 38'0 OUT I"I.E
026F 5E 316 LO E,IHll 02Ee ED61 385 OUT (el,H
0270 005E05 317 LO E,( IX+INOI 02EE E069 386 OUT ICHL
0273 F05E05 318 LO E,IIY+INOI 02FO 0320 387 OUT N,A
0216 SF 319 LO E,A 02F2 EOA8 388 OUTO
0277 58 320 LO E,B 02F1t EOA3 389 DUll
0278 '59 321 LO E,e 02F6 Fl 390 POP AF
0279 5A 322 LO E,O 02F7 e1 391 POP Be
027A 5B 323 LO E,E 02F8 01 392 POP OE
0278 5e )Z1o LO E,H 02F9 El 393 POP HL
027e 50 325 LO E,L 02FA OOEI 394 POP IX
0210 lE20 326 LO E,N 02Fe FOEI 395 POP IY
027F 66 327 LO H,lHlI 02FE F5 396 PUSH AF
02'clO 006605 328 LO H, (IX+INOI 02FF e5 397 PUSH Be
0283 F06605 329 LO H,( I Y+I NOI, 0300 05 398 PUSH DE
0286 67 330 LO H,A 0301 E5 399 PUSH HL
0287 60 331 LO H,8 0302 OOE5 '000 PUSH IX
0288 61 332 LO H,e 030'0 FOES '001 PUSH IY
0289 62 333 LO H,O 0306 CB86 '002 RES O,(~LI
028A 63 33'0 LO H,E 0308 00C80586 '003 RES 0, Illx+INOI
028B 6'0 335 LO H,H 030e FDCB0586 '00'0 RES O,lIiY+INOI
028e 65 336 LO H,L 0310 eB87 405 RES O,A
0280 2620 337 LO H,N 0312 C880 1o0b RES O,B
028F 2A81005 338 LO HL,INNI 031'0 CB81 '001 RES o,e
0292 218'005 339 LO HL,NN 0316 C882 408 RES 0,0
0295 EOIt7 3'00 LO I,A 0318 C883 '009 RES O,E
0297 002A8405 3'01 LO IX,INNI 031A CB810 '010 RES O,H
029B 00218'005 3'02 LO IX,NN 031C CB85 411 RES O,L
029F F02A81005 3'03 LO IY, (I'll'll 031E CB8E '012 RES 1,(HI-I
0243 FD2181005 3'0'0 LO IY,NN 0320 ooeB058E '013 RES l,llXHNDI
02A7 6E 310S LO L,IHLJ 032'0 FOC8058E 'olio RES 1, I I"'''INOI

286
 %-80 CROSS ASS EMBLER VERSION 1.06 OF 06/18176
u7l09176 10:22:47 OPCOOE liStiNG
LOC 08J CODE STMT SOURCE STATEMENT LOC OtlJ CODE 5TMT SOURCE STATEMENT

0127 3F 139 CCF OUF 2C 208 INC L

0128 8E 140 CP IHlI 0190 3j 209 INC SP
0129 008EOS 141 CP IIX+INOI 0191 EOU 210 INO
012C F08EOS 142 CP IIY+INOI 0193 E08A 211 INOR
012F 8F 143 CP A 0195 EOA2 212 INI
0130 88 144 CP 8 0197 E082 213 INIR
0131 89 14S CP C 0199 E9 214 JP IHlI
8A 146 CP 0 019A 00E9 215 JP (IX!
0132
0133 88 147 CP E 019C FoE9 210 JP IIY I
0134 8C 148 CP H 019E OA8405 217 JP C,NN
0135 80 149 CP L OlAl FA1I40S 218 JP M,NN
0136 FE20 ISO CP N 01A4 028405 219 JP NC,NH
0138 EoA9 151 CPO OlA7 C38405 220 JP NN
013A Eo1l9 152 CPOR OlAA C28405 221 JP NZ,NH
013C EOA1 153 CPI DUO F28405 222 JP P,NN
DUE EOlll 154 CPIR 0180 EA8405 223 JP PE,NH
0140 2F- ISS CPL 0183 E28405 224 JP PO,NH
01U 27 150 OAA 0180 CA8405 225 JP Z,NN
0142 35 157 DEC IHlI 0189 3112E 220 JR C,OIS
0143 003505 158 DEC IIX+1NOI 0188 182E 227 JR DIS
0146 F03S05 159 DEC IIY+INOI 0180 302E 228 JR NC,OIS
0149 3D 100 DEC A 018F 202E 229 JR HZ,OIS
014A 05 101 DEC 8 01Cl 282E 230 JR Z,olS
0148 08 102 DEC 8C 01C3 02 231 Lo 18CI,A
014C 00 163 DEC C 01C4 12 232 LO IDE I ,A
0140 IS 164 DEC 0 01C5 77 233 LO I HL),A
014E 18 165 DEC DE 01C6 10 234 LO IHlI,B
014F 10 166 DEC E 01C7 II 235 LO IHL),C
01S0 25 167 DEC H 01C8 72 230 LO IHlI,O
DIS 1 28 108 DEC HL 01C9 73 231 LO I.HU,E
0152 0028 169 DEC IX 01CA 14 238 LO IHU,H
0154 F028 170 DEC IY 01C8 75 239 LD IHLI,L
0156 20 171 DEC L 01CC 3620 2...0 LO IHU,N
0157 38 172 DEC SP InCE 001105 241 LO IIX+IHOI,A
0158 F3 173 OJ OlDl 007U05 2...2 LD IIX+IHOI,8
01S9 102E 174 OJNZ DIS 0104 D07105 243 LO I JX+lHDI,C
0158 F8 175 EJ 01D7 001205 2...... LO IJX+IHO),O
DISC E3 176 EX ISPI,HL 01DA OD7305 24S LO I JX+INOI,E
0150 00E3 177 EX ISPI,JX 0100 001405 246 LO IIX+INOI,H
015F FoE3 178 EX ISPI,JY DIED 007505 2...1 LO (lX+JNOI,L
0161 08 119 EX ",F,AF' 01E3 00360520 2...& LO IIX+INoI,N
0162 E8 180 EX oE,HL OlE7 Fo1105 2...9 Lo IJY+INoI,A
0163 09 181 EXX OlEA F01005 250 LO IIY+1NoI,B
010'" 16 182 HALT OlEO FOll05 251 LO IJY+IHOI.C
0165 EO"'o 183 JM 0 01FO F07205 252 LD IIY+JHD),D
0161 EDS6 18... 1M 1 01F3 F07305 253 LD IIY+JND),E
0169 E05E 185 1M 2 01F6 FD7405 25... LD IJY+lHol,H
0168 E0711 186 IN A.ICI 01F9 FD7505 . 2S5 LD IIY+INDI.L
016D D820 187 IN A,{N) OlFC F0360520 256 LD IIY+IHDI,N
016F ED40 188 IN 8.ICI 0200 328405 257 LD INNI,A
0171 ED"t8 189 IH C,ICI 0203 ED438405 2S8 Lo IHNI,&C
0173 E050 190 JH D,ICI 0201 EDS3&...05 259 LD INNI,DE
0115 E058 191 IN E,ICI 0208 228405 260 LD tNNl,HL
0117 ED60 192 IN H,ICI 020E DD228,.05 261 LD INNI,IX
0179 ED68 193 IN L,ICI 0212 FD228...05 262 LD INNI,IY
0178 3't 19... INC IHL'I 0216 ED738,.05 263 LD IHHI,SP
011C DD3... 05 195 INC IIX+JHDI 02lA UA 264 LD A,(8C)
011F F03it05 196 IHC IIY+lHOI 0218 lA 265 LD A,IOEI
0182 3C 19' IHC A 021C 7E 266 LD A.IHll
0183 04 198 INC 8 021D DD1EOS 261 LD A. nX+INOI
018,. 03 199 IHC 8C 0220 F07E05 268 LO A.IIY+INOI
0185 OC 200 INC C 0223 3A8... 05 269 LD A,INHI
0186 14 201 IHC 0 0226 lF 210 LD A,A
0181 13 202 JHC DE 0227 78 211 LD A.8
0188 1C 203 JHC E 0228 79 272 LD A,C
0189 24 204 INC H 0229 lA 213 LO A.D
018A 23 20S INC HL 022A 78 27"t LD A,E
0188 OD23 206 IHC IX 0228 lC 21!j LD A.H
0180 FOB 2117 IHC IY 022C EDSl 216 LD A,I

285
 2-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18116
01l0911b 10:22:47 OPCOOE LISTING
lot OBJ COOl: STMT SOURCE ST ATEMENT lOC OBJ CODE STMT SOURCE STATEMENT

0440 9A 553 SBC A,O 04EA CBED 622 SET 5,l

U44E 9B 554 SBC A,E UltEC C8F6 b23 SET 6,IHll
04itF 9C 555 SBC A,H 04EE OOC805Fb 624 SET 6,IIX+INOI
0450 90 556 SBC A,l 04f2 FOCB05F6 625 SET 6,(IY+INOI
0451 OE20 557 SBC A,N 04F6 CBF7 626 SET 6,A •
0453 EO'o2 558 SBC Hl,BC 04f8 CBfO 627 SET 6,B
0455 E052 559 SBC Hl,OE 04FA CBFl 628 SET 6,C
E062 560 SBC Hl,Hl 04fC CBF2 629 SET 6,0
0457
E072 561 SBC Hl,SP 04fE CBF3 630 SET 6,E
0459
045B 37 562 SCf 0500 C8F,. 631 SET 6,H
045C CBC6 563 SET O,(HU 0502 CBf5 632 SET 6,l
045E 00CB05C6 5b4 SET O,IIX+INOI 0504 CBfE b33 SET 7,IHll
0462 FOCB05C6 5b5 SET O,IIY+INOI 0506 00CB05FE b34 SET 7, IIX~INOI
046b CBC7 Sb6 SET O,A 050A FOCB05fE 635 SET 7,(IY+INOI
04b8 CBCO 5b7 SET O,B 050E CBFF 636 SET 7,A
046A C8Cl 568 SET O,C 0510 CBF8 b37 SET 7,B
046C CBe2 Sb9 SET 0,0 0512 CBf9 638 SET 7,C
0'o6E CBC3 570 SET O,E 0514 CBfA 639 SET 7,0
0470 CBC4 571 SET O,H OS16 CBFB 640 SET 7,E
0472 CBC5 572 SET O,l 0518 CBFC 641 SET 7,H
0474 CIlCE 573 SET 1,IHlI 051A CBFO 642 SET 7,l
0476 00CIl05CE 574 SET 1,( IX+INOI 051C CB26 643 SlA IHlI
047A FOCB05CE 575 SET 1,IIY+INOI 051E 00CB0526 644 SlA II X+I NOI
047E C8CF 516 SET I,A 0522 FOCB0526 645 SlA IIY+INOI
U480 C8ca 517 SET 1,8 0526 C827 646 SLA A
0482 CIlC9 578 SET 1,C 0528 CB20 b47 SLA 8
0484 CllCA 579 SET 1.0 052A CB21 648 SlA C
0'086 CIlCB 580 SET I.E 052C CB22 649 SlA 0
0488 C8ce 581 SET 1.H 052E CB23 b50 SlA E
048A caCo 582 SET 1.l 0530 C824 651 SlA H
048C CIl06 583 SET 2,IHU 0532 CB25 652 SLA l
0'o8E 00CB0506 584 SET 2,(IX+JNOI 0534 CB2E 653 SRA IHlI
0492 FOCIl0506 585 SET 2,(IY+JNOI 0536 00CB052E 65'0 SRA IIX+INOI
0496 CB07 586 SET 2.A 053A fOCB052E 655 SRA 11Y+INOI
0498 CBOO 587 SET 2.B 053E CB2F 656 SRA A
049A CBOI 588 SET 2.C 0540 CB28 657 SRA B
049C CBu2 589 SET 2.0 0542 CB29 658 SRA C
049E C803 590 SET 2,E 0544 CB2A 659 SRA 0
04AO C804 591 SET 2 .• H 0546 CB2B 660 SRA E
04A2 CB05 592 SET 2.l 0548 CB2C bbl SRA H
04A'o CIl08 593 SET 3 B 05/tA CB20 662 SRA l
0'oA6 CBOE 59'0 SET 3.IHll 05'oC CUE 663 SRl IHlI
0'oA8 00C8050E 595 SET 3,IIX+INOI 05'tE OOCB053E 66,. SRl IIX+1NOI
O'oAC FOCB050E 596 SET 3,IIY+INOI 0552 FOCB05lE 665 SRl 11Y+INDI
0'080 CBOF 597 SET 3,A 0556 CB3F 666 SRl A
0'082 CB09 598 SET 3,C 0558 CB38 667 SRl B
0'oB4 CBOA 599 SET 3.0 055A CB39 668 SRl C
04B6 CB08 600 SET 3. E 055C CB3A 669 SRl 0
0'oB8 CBOC 601 SET 3.H 055E ClUB 670 SRl E
04BA C8UO 602 SET 3.L 0560 C53C 671 SRL H
O'oBC C8E6 603 SET 'o,IHU 0562 CB30 672 SRl L
O'oBE 00C805E6 60'0 SET 'o.IIX+INOI 056'0 96 673 SUB IHlI
04C2 FOCB05E6 b05 SET 4.IIY+INOI 0565 009605 674 SUB 11X+1~01
0'oC6 C8E7 606 SET 'o.A 056B F09605 675 SUB IIY+JNOI
04C8 CBEO 607 SET 4,B 056B 97 676 SUB A
O'oCA CBEI 608 SET 'o.C 056C 90 677 SUB B
O'oCC CBE2 609 SET '0,0 0560 91 678 SUB C
04CE CBE3 610 SET 4.E 056E 92 679 SUB 0
0't00 CBEIt 611 SET 'o.H 056F 93 6ao SUB E
0402 CBES 612 SET 4,l 0570 94 681 SU8 H
0'004 CIlEE 613 SET 5.IHLI 0571 95 682 SUIl L
0'006 OOCBOSEE 61'0 SET s,IIX+lNOI 0572 0620 683 suu N
040A FOCB05EE 615 SET 5,II.Y+INOI 057'0 AE 68'0 XOR IHLI
O'oUE CBEf 616 SET 5.A 0575 00AE05 685 XOR 11X+INOI
04EO C8E8 617 SET 5.B 0578 FOAE05 686 XOR I JY+IliIOI
04E2 CBE9 618 SET 5.C 0578 AF 687 XOR A
04E'o C8EA 619 SET 5.0 057C A8 688 XOK B
0'oE6 CIlE8 620 SET 5.E 0570 A9 689 XOR C
04E8 CBEC 621 SET 5.H 057E AA 690 XOR 0

288
 2-80 (.1l0SS ASS EMBlEIl VERS ION 1.06 OF 06118176
07109116 10:U:41 OPCODI: LISTING
lO(. OIlJ CODE STMT SOURCE STATEMENT lO(. OBJ CODE STMT SOURCE STATEIl4ENT

0328 (.B8F 41!> RES I,A 03(,11 1'8 4114 RET M

(.B1I8 416 RES l,B 03(.9 DO 485 RET N(.
032A
032(, (.B1I9 417 RES 1,(. 03(.A CO 4a6 RET NZ
OnE (.BIIA 418 RES 1,0 03(,8 1'0 487 RET P
0330 (,118 a 419 RES I, E 03(.C .E8 488 RET PE
0332 CIISC 420 RES I,H 03CO EO 489 RET PO
0334 CB80 421 RES l,l 03CE C8 490 RET Z
0336 (,896 422 RES 2,1 Hl I 03(.1' E040 491 RETI
0338 00C80596 423 RES 2,IIX+INOI 0301 E045 492 RETN
onc FOC80596 424 RES 2,lIY+INOI 0303 C816 493 Rl IHLl
0340 C8'H 425 RES 2,A 0305 00C80516 494 Rl lIX+INOI
0342 CB90 426 RES 2,8 0309 FOC80516 495 Rl IIY+INO I
0344 C891 421 RES 2,C 0300 C817 49b Rl A
0346 (,892 428 RES 2,0 0301' C810 491 Rl 8
0348 C893 429 RES 2,E 03El (.Bll 498 Rl C
034A C894 430 RES 2,H 03E3 C812 499 Rl 0
034C C895 431 RES 2,l 03E5 CBl3 500 Rl E
034E CB9E 432 IlES 3,IHLI 03E7 CB14 501 Rl H
0350 00CB059E 433 RES 3,IIX+INOI 03E9 C815 502 Rl l
0354 FOCB059E 434 RES 3,IIY+INOI 03EB 11 503 RlA
0358 CB9F 435 RES 3,A 03EC CB06 504 RlC IHLI
035A CB98 436 IlES 3,B 03EE 00CB050b 505 RlC IIX+INOI
035C CB99 431 RES 3,C 031'2 FOC8050b 50b RlC IIY+lNOI
035E CB9A 438 RES 3,0 031'6 CBOl 507 RlC A
0360 CB9B 439 RES 3,E 031'8 C800 508 RlC 8
0362 C89C 440 KES 3,H 03FA C801 509 RlC C
03b4 C890 441 RES 3,l 03FC CII02 510 RlC 0
0366 CBA6 442 RES 4,IHLI 03FE CB03 511 RlC E
03b8 DOCII05A6 443 RES 4,IIX+INOI 0400 CB04 512 RlC H
036C FOCB05A6 444 RES 4,IIY+lNOI 0402 CB05 513 RlC l
0310 CIIA7 445 RES 4,A 0404 07 514 RlCA
0372 CBAO 446 RES 4,B 0405 EDbF 515 RlO
0374 CBAI 447 RES 4,e 0407 C8lE H6 RR IHLI
0376 CBAZ 448 RES 4,0 0409 00C8051E 517 RR lIX+INO I
0318 CBU 449 RES 4, E 0400 FOC805lE 518 RR IIY+INOI
037A CBA4 450 RES 4,H 0411 CBlF 519 RR A
037C CBA5 451 RES 4,l 0413 CB18 520 RR B
031E CBAE 452 RES 5,lHLI 0415 CII19 521 RR C
0380 00CB05AE 453 RES 5,IIX+INOI 0417 CBLA 522 RR 0
0384 FOCBD5AE 454 RES 5,IIY+INOI 0419 CBIB 523 RR E
0388 CBAF 455 RES 5,A 041B CBIC 524 RR H
038A C8A8 456 RES 5,8 0410 CBlO 525 RR l
038C CIIA9 457 RES 5,C 0411' LF 526 RRA
038E CIIAA 458 RES 5,0 0420 C80E 521 RRC IHLl
0390 CIlAIl 459 RES 5, E 0422 DOC8050E 528 RRC IIX+INOI
0392 C8AC 460 RES 5,H 0426 FOC8050E 529 RRC IIY+INOI
0394 C8AO 4bl RES 5,l 042A C80F 530 RRC A
0396 CIIB6 462 RES b,lHLI 042C CB08 531 RRC B
0398 00C805Bb 4b3 RES 6,lIX+INUI 042E CB09 532 RRC C
039C FOCB05B6 46.. RES 6,IIY+INOI 0430 CBOA 533 RRC 0
03AO CIIB7 465 RES 6,A 0432 CIl08 534 RRC E
03A2 CBBO 4b6 RES 6,B 0434 C80C 535 RRe H
03 A" CBBI ..67 RES 6,C 0436 CBOO 536 RRC l
03A6 CBB2 468 RES b,O 0438 01' 531 RRCA
03A8 CB83 4b9 RES b, E 0439 E061 538 RRO
03AA CB84 470 RES 6,H 043B C7 539 RST 0
03AC CBB5 471 RES 6,l 043C 07 540 RST 10H
03AE CII8E 472 RES 7,IHU 0430 OF 541 RST 18H
0380 00CIl0511E 473 RES 7,IIX+INOI 043E E7 542 RST 20H
0384 FOC8058E 474 RES 7,lIY+INOI 0431' H 543 RST 28H
0388 CBIIF 415 RES 7,A 0440 1'1 544 RST 30H
038A C888 476 RES 7,8 0441 FF 545 RST 38H
038C C889 477 RES 7,C 0442 CF 546 RST 8
038E CB8A 418 RES 7,0 0443 9E 541 S8C A,IHLl
03CO CB8B 479 RES 7, E 0444 DD9E05 548 S8C A, I IX+INOI
03C2 C8BC 480 RES 7,H 0447 F09E05 549 S8C A,IIY+INOI
03C.. (.BBO 481 RES l,l 044A 91' 550 SIlC A,A
03C6 C9 482 RET 044B 9B 551 S8C A,8
03C 1 DB 483 RET 0.. 4C 99 552 SBC A,C

287
 APPENDIX C
INSTRUCTION SET NUMERICAL ORDER

1-80 CROSS ASSEM8L£R VERSION 1.04 OF 04/18174

07109174 10:20: 50 .opeODE LISTING
LOC 08J CODE STMT SOURCE STATEMENT LOC 08J CODE STMT SOURCE STATI!MENT

0000 00 1 HOP 0063 '05 70 LO 8,L

0001 018'005 2 LO 8CtNN 006'0 '06 71 LO 8r1"LJ
000'0 02 3 LO 18C),A 0045 '07 72 LO 8,A
0005 03 '0 INC 8C 0066 '08 73 LO C,8
0006 0'0 5 INC 8 0067 '09 7'0 LO C,C
0007 05 4 DEC 8 0068 loA 75 LO C,O
0008 0620 7 Lo 8tN 0069 '08 76 LO C,E
OOOA 07 8 RLCA 006A 4C 77 Lo C,H
0008 08 9 EX AF,AF' 0068 '00 71l LO CtL
OOOC 09 10 ADO HL,8C 006C 4E 79 Lo CrlHl)
0000 OA 11 LO A t 18c) 0040 'oF 80 Lo etA
OOOE 08 12 DEC Be 004E 50 81 Lo 0,8
GOOF OC 13 INC C 006F 51 82 LO otC
0010 00 1'0 DEC C 0070 52 83 LO 0,0
0011 OE20 15 LO C,N 0071 53 8'0 Lo OtE
0013 Of 14 RRCA 0072 5'0 85 LO o,H
001'0 102E 17 OJNl DIS 0073 55 86 Lo o,L
0016 118'005 18 LO oEtNN 007'0 56 87 Lo OtIH!.,1
0019 12 19 Lo 10EI,A 0075 57 88 Lo o,A
OOlA 13 20 INC DE 0076 58 89 Lo Et8
0018 14 21 INC 0 0077 59 90 Lo E,C
001C 15 22 DEC 0 0078 SA 91 LO ftO
0010 1620 23 Lo DtN 0079 58 92 Lo E,E
001F 17 24 RLA 007A 5C 93 LO E,H
0020 182E 25 JR DIS 0078 50 9'0 LD E,L
0022 19 26 ADD HL,oE 007C 5E 95 Lo E,h~LJ
0023 lA 27 Lo A,loEI 0070 SF "96 LD Et~
002'0 18 28 DEC DE 007E 60 97 LD H,a
0025 IC 29 INC E 007F 61 98 Lo H,C
0026 10 30 DEC E 0080 62 99 Lo H,D
0027 lE20 31 LO E,N 0081 63 100 Lo HtE
0029 IF 32 RRA 00112 6'0 101 Lo H,H
002A 202E 33 JR Nl,olS 0083 65 102 Lo H,L
002C 218405 3'0 Lo HL,NN 00114 66 103 Lo H,IHILI
002F 228405 35 Lo INNI,HL 0085 67 10'0 LD- H,A
0032 23 36 INC HL 0086 68 105 Lo L,8
0033 2'0 37 INC H 0087 69 106 Lo L,C
003'0 25 38 DEC H 0088 6A 107 LD L,O
0035 2420 :19 LO H,N 0089 68 108 Lo L,E
0037 27 40 DAA 008A 4C 109 Lo LtH
0038 282E '01 JR l,OIS 0088 60 110 Lo L,L
003A 29 42 ADO HL,HL oose 6E 111 Lo L,IHlI
0038 2A8405 43 Lo HLtINN! 0080 6F 112 Lo LtA
003E 28 4'0 DEC HL 008E 70 113 Lo IHU,,8
003F 2C 'oS INC L 008F 71 114 LD IHlIi,C
00'00 20 46 DEC L 0090 72 115 Lo IHLhO
0041 2ElO 47 Lo L,N 0091 73 114 Lo IHLI,E
0043 2F 48 CPL 0092 7'0 117 Lo IHlIi,H
00'04 302E 49 JR NC,DIS 0093 75 118 LD IHL),L
00'06 318'005 50 Lo SP,NN 0094 76 119 HALT
00'09 328405 51 LD INNI tA 0095 77 120 LD IHLJ"A
004C 33 52 INC SP 0096 78 121 lO A,a
00'00 3'0 53 INC IHLI 0097 79 122 Lo A.C
OOltE 35 5'0 DEC IHlI 0091l 7A 123 lD A.D
004F 3620 55 LIT IHl),N 0099 7a 12'0 LD A,E
0051 37 56 SCF 009A 7C 125 LD A.H
0052 382E 57 JR C,DI S 009a 70 126 LD AtL
0054 39 58 ADD HL.SP 009C 7E 127 lD A.IHLI
0055 3A8405 59 LD A.(NNI 0090 7F 128 lD A.A
0058 38 60 DEC SP 009E 80 129 ADD A.8
0059 3C 61 INC A 009F 81 130 ADD A.e
005A 3D 62 DEC A OOAO 82 131 ADD A,D
0058 3E20 63 LD A,N OOAI 83 132 ADO A.E
0050 3F 64 CCF 00A2 84 133 ADD A.H
DOSE 40 65 lo 8.a 00A3 85 134 ADD AtL
005F 41 66 lD 8,C 00A4 86 US ADD A.IHLI
0060 42 67 LD 8.0 00A5 87 136 ADD A.A
0061 43 68 lD 8.E 00A6 88 137 AOC A,8
0062 44 69 LO B.H,NN GOA? 89 138 AGe A.e

290
 I-eo CROSS ASSEMBLER VERSION 1.06 OF 06/18176
07/09116 10:22 :47 OPCOOI: LISTING
LuC UllJ CODE ::'TMT SOURCE S1 ATEMENT

057F AB 691 XOR E

0~80 AC 692 XOR H
0581 AD 693 XUI< L
0582 H2O 694 XOR N
0584 695 NN DEFS 2
6\16 INO HIU 5
697 M EIlU 10H
698 N EQU 20H
699 01 S EQU 30H
700 END

289
 2-80 CROSS ASSEII8lER VERSION 1.06 Of 06/18176
07109176 10:20:50 .OPCOOE LI STlNG
lOC 08J CODE STilT SOURCE STATEMENT laC 08J COOl: STilT SOURCE STATE"ENT
277 RR II 0202 CB65 3lt6 81T It,l
0178 C818
011A C819 278 RR C 020" C866 3lt7 BU ",(lfll
C8lA 279 RR 0 0206 C867 3lt8 lilT ",A
017C 81T 5,8
017E t818 280 RR E 0208 C86B 3't9
281 RR H 020A C869 350 lilT 5,C
0180 C81C
282 RR l 020C t86A 351 81T 5,0
0182 t8l0
C81E 283 RR (HlI 020E C868 352 8IT 5,E
0181t
C81F RR A 0210 tB6C 353 8U 5,H
0186 28"
Olaa t820 285 SU 8 0212 t860 351t 81T 5,l
018A t821 286 SU t 021lt C86E 355 8IT 5,(Mll
018C C822 2117 SlA 0 0216 C86F 356 8ll 5,A
OlaE CII23 288 SlA E 0218 t870 357 81T 6,8
0190 C82't 289 SlA H 02lA C811 3511 81T 6,C
0192 C825 290 SlA l 021C C872 359 8U 6,0
C826 291 SlA (HlI 021E C813 360 81T 6,E
019"
0196 C827 292 SU A 0220 C871t 361 8U 6,H
0198 C828 293 SRA 8 0222 t875 362 8IT 6,l
019A t829 291t SRA C 0221t t876 363 81T 6,HIll
019C C82A 295 SRA 0 0226 C877 361t 8IT 6,A
019E CII28 296 SRA E 0228 C878 365 8IT 7,8
0140 C82t 297 SRA H 022A C879 366 81T 7,C
OlA2 C820 298 SRA l 022C C8lA 367 8ll 7,0
CII2E 299 SRA (HLI 022E C878 368 8IT 7,E
OlA"
OlA6 C82f 300 SRA A 0230 CB7C 369 BIT 7,H
OlA8 CB38 301 SRl B 0232 CB70 370 8ll 7,l
OlAA CB39 302 SRl C 0231t CUE 371 BIT 7,Cllll
OlAC CB3A 303 SRl 0 0236 CB7F 372 BIT 7,A
OlAE CBlB 30lt SRl E 023B CB80 373 RES O,B
1)180 CB3C 305 SRl H 023A CB81 37" RES O,C
01B2 CB30 306 SRl l 023C CB82 375 RES 0,0
OlB" CB3E 307 SRl (Hll 023E CB83 376 RES O,E
01B6 CB3F 308 SRl A 02ltO CB81t 377 RES O,H
01B8 CBltO 309 81T O,B 02lt2 C885 378 RES O,l
018A CB"l 310 BIT O,C 021t" CB86 379 RES O,(HlI
01BC CBlt2 311 811 0,0 02"6 CB87 380 RES O,A
OUE C8lt3 312 BIT O,E 02ltB C888 381 RES 1,8
01CO 313 8IT O,H 02ltA C889 382 RES 1,C
C8""
01C2 C8lt5 31lt 81T O,l 02"C CBU 383 RES 1,0
01C" C8"6 315 BIT O,(HlI 02"E CBBB 38" RES l,E
UIC6 CBIt7 316 8IT O,A 0250 CBBC 385 RES l,H
01U CB"II 317 81T 1,8 0252 CBIIO 386 RES 1,l
01CA CB"9 318 B11 1,C 025" CBBE 387 RES 1,CHlI
UICC C8"A 319 8IT lt~ 0256 CB8F 388 RES 1,A
OlCE CB"B 32U BJT 1,E 0258 C890 389 RES 2,8
UIOO C8"C 321 8IT ltH 025A C891 390 RES 2,C
Ol02 CB"U 322 B11 l,l 025C CB92 391 RES 2,0
OlD" C8"E 323 81T l,(HlI 025E CB93 392 RES 2,E
0106 C8"F 32" 8IT loA 0260 CB9It 393 RES 2,H
0108 CB50 325 81T 2,8 0262 e895 39" RES 2,l
010A CB51 326 BIT 2,e 026" eB96 395 RES 2,(Hll
010e eB52 327 8IT 2,0 0266 e897 39t> RES 2,A
010E C853 328 81T 2,E 0268 e898 397 RES 3,8
OlEO C854 329 811 2,H 026A CB99 398 RES 3,C
OlE2 C855 330 8IT 2,l 026e C89A 399 RES 3,0
OlE" C856 331 BIT 2,(HlI 026E C898 "00 RES 3,E
01E6 CB57 332 1111 2,A 0270 C89C "01 R.ES 3,H
01E8 C858 333 811 3,8 0272 C890 "02 RES 3,l
OlEA e859 3l" 81T 3,C 027" CB9E "03 RES 3,(H!ll
OLEC CB5A 335 8ll 3,0
8IT 3,E
027t> CB9F
ClIAO
"04 RES 3,A
OlEE: C858 336 0278 "05 RES ",8
UIFO C85e 337 8ll 3,H 027A C8Al loOt> RES ",e
.01F2 C850 318 81T 3,l 027C e8A2 "07 RES ",0
01FIt C85E 339 8ll 3, (HlI 027E C8A3 "08 RES ",E
OlF6 C85F 3"0 OIT 3,A 0280 CBA" "09 RES ",H
01F8 CB60 3"1 81T ",B 0282 eU5 "10 RES ",l
01FA e861 3"2 IIIT ",e 028" C8A6 "11 RES ",(HLI
OlFC CB62 3lt3 8IT ",0 0286 CBAl "12 RES ",A
OlH eB63 3't" BIT ",E 0288 CBA8 "13 RES 5,8
02(10 eB61t 3lt5 BIT ",H 028A ellA9 u. RES 5,e

292
 1-80 CROSS ASS EM8lER VERS ION 1.06 OF 06/18116
07109116 10=20=50 .OPCOOE LISTING
lOC 06J CODE STMT SOURCE STATEMENT lOC OBJ CODE SIMT SOURCE STATEMENT

00A8 aA 139 AOC A,O 00F8 DO 208 RET NC

00A9 88 140 AOC A. E OOFC 01 209 PDP DE
OOAA 8C 141 AOC A,H OOFO 028405 210 JP NC,NN
00A6 80 142 AOC A,l 0100 0320 211 OUT N, A
OOAC 8E 143 AOC A,IHLI 0102 048405 212 CAll NC,NN
OOAO 8f 144 AOC A,A 0105 05 213 PUSH DE
OOAE ·90 145 SU6 6 0106 0620 214 SUB N
OOAF 91 146 SU8 C 0108 01 215 RST 10H
OOBO 92 147 SU6 0 0109 08 216 RET C
OOBI 93 148 SUB E 010A 09 217 EXX
00B2 94 149 SUB H 010B oA8405 218 JP C,NN
00B3 95 150 SUB l 010E OB20 219 IN A,N
00B4 96 151 SU8 (HLI 0110 OC6405 220 CAllC,NN
00B5 97 152 SUB A 0113 OE20 221 SBC AtN
00B6 98 153 SBC A, B OU5 Of 222 RST 18H
0061 99 154 SBC AtC OU6 EO 223 RET PO
0088 9A 155 SBC A,O 0117 El 224 POP Hl
00B9 9B 156 SBC At E 0118 E28405 225 JP PO,NN
OOBA 9C 157 S8C A, H DUB E3 226 EX I SPI ,Hl
OOBB 90 158 SBC A, l OUC E48405 227 CAll POtNN
OOBt 9E 159 S8C A, I HLI OUF E5 228 PUSH Hl
OOBO 9f 160 SBC A, A 0120 E620 229 AND N
OOBE AO 161 AND B 0122 E7 230 RST 20H
OOIlF AI 162 AND C 0123 E8 231 RET PE
OOCO A2 163 AND 0 0124 E9 232 JP (HLI
OOCI A3 164 AND E 0125 EA8405 233 JP PE,NN
00C2 A4 165 AND H 0128 EB 234 EX OEtHl
00C3 A5 166 AND l 0129 EC8405 235 CAll PE,NN
00C4 A6 167 AND IHLI 012C EE20 236 XOR N
00C5 A7 168 AND A 012E EF 237 RST 28H
00C6 A8 169 XOR 8 012F FO 238 RET P
00C7 A9 170 XOR C 0130 F1 239 POP AF
00C8 AA 111 XOR 0 0131 F28lt05 240 JP P tNN
00C9 A8 172 XOR E 0134 F3 241 01
OOCA AC 173 XOR H 0135 F48405 242 CAll P,NN
OOCB AD 174 XOR l 0138 F5 243 PUSH AF
ootC AE 175 XOR (Hl I 0139 F620 244 OR N
OOCO Af 176 XOR A 013B F7 245 RST 30H
OOCE BO 117 OR B 013C Fa 246 RET M
OOCF 81 178 OR C 0130 F9 247 lO SPtHl
0000 B2 179 OR 0 DUE FA8lt05 2'08 JP M,NN
0001 B3 180 OR E 0141 FB 249 EI
0002 B4 181 OR H 0142 FC8405 250 CALL MtNN
0003 85 182 OR l 0145 H2O 251 CP N
000'0 116 183 OR I HLI 0141 FF 252 RST 38H
0005 B7 184 OR A o lit 8 CBOO 253 RlC B
0006 B8 185 CP B 01'oA CBOI 25'0 RlC C
0007 B9 186 CP t 014C C802 255 RlC 0
0008 8A 187 CP 0 014E CB03 256 RlC E
0009 BB 18B CP E 0150 CB04 257 RlC H
OOOA BC 189 CP H 0152 CB05 258 RlC l
0008 BO 190 CP l 0154 CB06 259 RlC (HLI
OOOC BE I'll tP (HLI 0156 CB07 260 RlC A
DODD BF 192 CP A 0158 CB08 261 RRC B
OOOE CO 193 RET NZ 015A CB09 262 RRC C
OOOf Cl 194 POP BC 015C CBOA 263 RRC 0
OOEO C28405 195 JP NZ,NN 015E CBOB 264 RRC E
OOEl OB405 196 JP NN 0160 CBOC 265 RRC H
00E6 C48405 191 CAll NZ,NN 0162 CBOO 266 RRC l
00E9 C5 198 PUSH BC 0164 CBOE 267 RRC (HLI
DOE A C620 199 ADD A,N 0166 CBOF 268 RRC A
OOEC C7 200 RST 0 0168 CB10 269 Rl B
OOEO C8 201 RET Z 016A CBll 270 Rl C
OOEE C9 202 RET 016t CB12 271 Rl 0
OOEF CA8405 203 JP Z,NN 016E CB13 272 Rl E
00f2 CC8'o05 204 CALL Z ,NN 0170 CB14 273 Rl H
00F5 C08405 205 CAll NN 0172 CB15 274 Rl l
00F8 CE20 206 AOC A,N 011't C816 275 Rl (HLI
OOFA CF 207 RST 8 0176 C817 276 Rl A

291
 1-80 CROSS ASS EM8LER VERSION 1.06 OF 06/18176
07/09176 10120150 .OPCOO!: LISTING
LaC OBJ CODE STHT SOURCE STATEMENT LOC 08J COOf STMT SOURCESUTEMllNT

030A 00C80576 553 81T6,IIX+INO) 0494 E089 622 CPaR

Q30E 00CB057E 554 8IT 7, I IX+INO) 0496 f08A 623 INOR
03E2 00CB0586 555 RES 0,1 lX+INO. 0498 E088 624 OTOR
03E6 00C8058E 556 RES l,IIX+INO. U'o9A FOO9 625 ADD IY,8C.
03EA 00C80596 557 RES 2,(lX+INO. 049C F019 626 ADD lY.OS
03EE 00C8059E 558 RES 3,IlX+INO. 049E F0218405 621 LO IY,NN
03F2 OOC805A6 559 RES 4,IIX+INO. 04A2 F0228405 628 LO INNhl'Y
U3F6 ODC805AE 560 RES 5, I IX+INO. 04A6 F023 629 INC IY
03FA 00C80586 561 RES 6,11 X+INO. 04A8 F029 630 ADD IY,JY
00C8058E 562 RES 7, I lX+INO. 04U F02U'o05 631 LO IY,INN)
03FE
00C805C6 5.3 SET 0, I JX+INO. 04AE F028 612 DEC IY
0402
00C805CE 564 SET 1,1 lX+INO. 0480 F03'o05 633 INC ClY+liNO.
040.
040A 00C80506 565 SET 2,1 lX+INO. 0'083 F0350S 634 DEC IIY+~NO.
00CB050E 566 SET 3,1 IX+INO. 0'oB6 F0360520 635 LO I IY+IO. ,N
O'tOE
0'012 00C805E6 567 SET 4,C lX+INO. 0't8A F039 636 ADD IY,SPi
00C805EE 568 SET 501 IX+lNO) 048C F04605 631 LO 8,ClYtjINO.
0416
041A 00C805F6 569 SET 6,(lX+INO. 048F F04E05 638 LO C,IlY+'INO.
041E 00C805FE 570 SET 7,ClX+INOI 04C2 F05605 639 LO O,IlY+!INO)
0422 E040 571 IN 8,IC) 04C5 F05EOS 640 LO E,llY+'IND.
0424 ED41 572 OUT IC.,8 04t8 FD6605 641 LO H, I IY+!INO.
0426 E042 573 S8C HL,8C 04C8 F06E05 642 LO L, I Iy+',INO.
0428 E04384.:>5 514 LO CNNh8C 04CE FD7005 643 LO IlY+INbl,8
0401 F07105 644 LO IIY+INbhC
042C
042E
E044
ED4S
575
576
NEG
RETN 0404 F07205 645 LO I IY+IN ,0•
0430 E046 571 1M 0 0407
040A
F0730S
F07405
646
647 LO (lY+lN hH
g
LO IIY+IN .,E
0432 E047 578 LO I,A
043'0 E048 579 IN C,CC) 0400 F07505 .48 LO 1I.,+INp.,L

t~ ~~:~~~r.~o~
0436 E049 580 OUT CC. ,C 04EO F07705 649
0'038 E04A 581 AOCHL,8C 04E3 F07E05 .50
043A ED4884U5 582 LO BC,INNI 04E6 F08605 651 ADD A,IIY!+INO.
043E E040 583 RETl 04E9 F08E05 652 AOC A,ClY~INO.
0440 E050 584 IN O,IC. 04EC F09605 653 SU8 IlY+INO.
04't2 EOSI 585 OUT IC. ,0 04EF F09E05 654 S8C A,ClYi+lNO)
0444 ED 52 586 S8C HL,OE 04F2 FOA605 655 AND I IY+I~O.
0446 E0538405 587 LO INNI,OE O'tF5 FOAE05 656 XOR IlY+INO)
0444 E056 588 1M 1 04F8 F08605 651 OR IIY+INIU
044C E057 589 LO A,I 04F8 F08E05 658 CP IIY+INIH
044E E058 590 IN E,IC. 04FE FOEI 659 POP IY
0450 E059 591 OUT IC. ,E 0500 FOE3 660 EX ISPI,IY
0452 E05A 592 AOC HL,OE 0502 FOE5 661 PUSH IY
0454 E0588405 593 LO OE,INIH 05O't FOE9 662 JP l i n
0458 E05E 594 1M 2 0506 FOF9 661 LO SP,IY
0'o5A ED60 595 IN H,IC. 0508 FOC80506 664 RLC IIY+IllO.
045C ED61 596 OUT IC. ,H 050C FOC8050E 665 RRC IlY+ItO.
045E E062 597 S8C HL,HL 0510 FDC80516 666 RL ClY+IN •
0460 ED67 598 RRO 051'0 FOC8051E 667 RR I IY+IN~.
0462 E068 599 IN L,CC. 0518 FOC80526 668 SLA IlY+I O.
0464 E069 600 OUT ICI,L 051C FOC8052E 669 SRA IlY+ItlO.
0466 ED6. 601 AOC HL,HL 0520 FDC8053E 670 SRL IlY+I~O)
0468 E06F 602 RLO 0524 FOC80546 671 8IT O,ClYHNO.
046A E072 603 S8C HL,SP 0528 FDC8054E 672 8IT 1,IIYt!NO.
046C E073a405 604 LO INNhSP 052C FOC80556 673 81T 2,IIYt!NO.
0470 E078 605 IN A,IC. 0530 FOC8055E 6\4 BIT 3, (lYt!NO.
0472 E079 606 OUT CC. ,A 0534 FOC80566 675 8IT 4,IIYt!NO.
0474 EOlA 607 AOC HL,SP 0538 FOC8056E 676 8IT 5, I IYt!NO.
0476 ED 788'oU5 608 LO SP,INN. 053C FOC80516 677 8IT .6, II ytiNO.
047A EOAO 609 LOI 0540 FOCB057E 678 8IT 1,1 IYHNO.
041C EOAl 610 CPI 054'0 FOCB0586 619 RES 0, I IYtINO)
047E EOA2 611 INI 0548 FOCB058E 680 RES l,ClYtINO.
0't80 EOA3 612 OUTl 054C FOCB0596 681 RES 2~ I IYHNO.
0'082 EOA8 613 LOO 0550 FDCB059E 682 RES 3,1 lYtINO.
0484 EOA9 614 CPO 0554 FOCB05A6 6413 RES 4,llYtlNO.
0486 EOAl 615 INO 0558 FOCB05AE 68'0 RES 5, I IY.... NO.
0488 EOAB 616 OUTO 055C FOC805B6 685 RES 6,ClVHNO.
048A E080 611 LOIR 0560 FDCB05BE 686 RES 7, II V+INO.
048C E081 618 CPIR 0564 FDC805C6 687 SET 0, ClVtlNO.
O't8E E082 619 INIR 0568 FOCB05CE 688 se T l,IlV+INO.
0490 EOU 620 OTiR 056C FDCB05D6 6lJ9 SET 2,IIVHND.
0'092 EOB8 621 LOOR 0510 FOC8050E 690 SET 3,IIY+INDJ

294
 2-80 CROSS ASSEMBLER VERSION 1.06 OF 06/18176
01109116 10:20:50 .OPCOOE LISTING
LOC OBJ CODE STMT SOURCE STATEMENT LOC 08J CODE STMT SOURCE STATEM~NT

028C CbAA 415 RES 5,0 0316 C8EF 484 SET 5, A

028E CBAB 416 RES 5,E 0318 CBFO 485 SET 6,8
0290 CBAC 411 RES 5,H 031A CBFl 486 SET 6,C
0292 CBAO 418 RES 5, L OllC CBF2 481 SET 6,0
0294 CBAE 419 RES 5,IHlI 031E CBF3 488 SET 6,E
0296 C8AF 420 RES 5,A 0320 CBF4 489 SET 6, H
0298 CBBO 421 RES 6,B 0322 CBF5 490 SE T 6, L
029A CBIlI 422 RES 6,C 0324 CBF6 491 SET 6,IHlI
029C CBB2 423 RES 6,0 0326 CBF1 492 SET 6,A
029E CIlB3 424 RES 6, E 0328 CBF8 493 SET 1,B
02AO CBB4 425 RES 6.H 032A CBF9 494 SET 1.C
02A2 CIlB5 426 RES 6,L 032C CBFA 495 SET 1,0
02A4 CBB6 421 RES 6,IHll 032E CIlFB 496 SE T 1, E
02A6 CBBl 428 RES 6,A 0330 C8FC 491 SET 1, H
02A8 CIlBil 429 RES 1,8 0332 CBFO 498 SET 1,L
02AA CBB9 430 RES 1.C 0334 C8FE 499 SET 1,IHLI
02AC CIl8A 431 RES 1,0 0336 CIlFF 500 SET 1,A
02AE CBBIl 432 RES 1, E 0338 0009 501 ADO IX,BC
02BO CBBC 433 RES 1,H 033A 0019 502 ADO IX,OE
02B2 CBBO 434 RES 1,L 033C 00218405 ,03 LO IX,NN
02114 CBBE 435 RES l,(HlI 0340 00228405 504 LO INNltlX
02B6 CIlBF 436 RES 1, A 0344 u023 505 INC IX
0288 CBCO 431 SET 0, Il 0346 0029 506 ADO IX, IX
02BA CBCl 438 SET O,C 0348 002A8405 501 LO IX,INNI
02BC CBC2 439 SET 0,0 034C 002B 508 DEC IX
02BE CBC3 440 SET O,E 034E 003405 509 INC IIX+INOI
02CO CBC4 441 SET O,H 0351 003505 510 DEC IIX+INOI
02C2 CBC5 442 SET 0, L 0354 00360520 511 LO IIX+INOI,N
02C4 CBC6 443 SET O,(HLI 0358 0039 512 ADO IX,SP
02CO CBC 1 444 SET O.A 035A 004605 513 LO B,IIX+INOI
02C8 CBC8 445 SET I.B 0350 004E05 514 LO C,IIX+INOI
02CA CBC9 446 SET I,C 0360 005605 515 LO 0,1 IX+INOI
02CC CBCA 441 SET 1,0 0363 005EO, 516 LO E,lIX+INOI
02CE CIlCB 448 SET I,E 0366 006605 511 LO H,IIX+INOI
0200 C8CC 449 SET I,H 0369 OOoE05 518 LO L.lIX+INOI
0202 C8CO 450 SET I,L 036C 001005 519 LO IIX+INOI,B
0204 C8CE 451 SET 1,IHlI 036F 001105 520 LO IIX+INOI,C
0206 C8CF 452 SET I,A 0312 001205 521 LO IIX+INOI,O
02011 C800 453 SET 2,B 0315 001305 522 LO IIX+INOI,E
020A CBol 454 SET 2,C 0318 001405 523 LO IIX+INOI,H
020C CIl02 455 SET 2,0 0318 001505 ,24 LO IIX+lNOI,L
020E CB03 456 SET 2,E OHE 001105 525 LO IlX+INOJ,A
02EO CB04 451 SET 2,H 0381 001E05 526 LO A,IIX+INOJ
02E2 C805 458 SET 2, L 0384 008605 521 ADD A,lIX+INOJ
02E4 C806 459 SET 2,IHll 0387 008E05 528 AOC A,(IX+INOI
02E6 CBOl 460 SET 2,A 038A 009605 529 SUB IIX+ INO I
02E8 CB08 461 SET 3 B 0380 009E05 530 SBC A,lIX+INOI
021:A C809 462 SET 3,C 0390 00A605 531 AND IIX+lNOI
02EC C80A 463 SET 3,0 0393 00AE05 532 XOR IIX+INOJ
02EE C80B 464 SET 3, E 0396 008605 533 OR IIX+lNOI
02FO CBOC 465 SE T 3,H 0399 00BE05 534 CP IIX+INOJ
02F2 CBOO 466 SET 3,L 039C DOE 1 535 POP IX
02F4 CBOE 461 SET 3,( Hll 039E OOEl 536 EX I SP I, I X
02F6 CBOF 468 SE T 3, A 03AO 00E5 531 PUSH IX
02F8 CBEO 469 SET 4,B 03A2 00E9 538 JP IIXI
02FA CBEl 410 SET 4,C 03A4 00F9 539 LO SP, IX
02FC CBE2 471 SET 4,0 03A6 00CB0506 540 RLC IIX+INOJ
02FE CBE3 412 SET 4,E 03AA 00CB050E 541 RRC lIX+INOI
0300 CBE4 413 SET 4,H 03AE 00CIl0516 542 RL IIX+INOI
0302 CBE5 414 SET 4,L 03B2 00CB05H 543 RR IIX+INOI
0304 CBE6 415 SET 4, I Hli 0386 00CB0526 544 SLA IIX+lNOI
0306 CBEl 416 SET 4,A 03BA 00CB052E 545 SRA IIX+JNOJ
0308 CBE8 411 SET 5,B 03BE 00CB053e 546 SRL IIX.+INOI
030A CBE9 478 SET 5. C 03C2 00C80546 541 BIT O,lIX+INOI
030C CBEA 419 SET 5,0 03C6 00CB054E 548 81T 1,IIX+INOI
030E CBeB 480 SET 5,E 03CA 00CB0556 549 BIT 2,(IX+INOI
0310 CBEC 481 SET 5,H 03CE 00CB055E 550 BIT 3,IIX+lNOI
0312 CIlEO 482 SET 5,l 0302 00CB0566 551 BIT 4,IIX+INOI
0314 CBEE 4lU SET 5,IHll 0306 OOCB056E 552 BIT 5, II X+INOI

293
 MAIN REG SET ALTERNATE REG SET
~~
ACCUMULATOR FLAGI ACCUMULATOR FLAGS
A F A' F'

}--' PURPOSE
REGISTERS

INTERRUPT MEMORV
VECTOR REFRESH
I
)R". PURPOSE
REGISTERS

PROGRAM COUNTER PC

zao-cpu REGISTER CONFIGURATION

ASCII CHARACTER SET (7-BIT OODE)

HEXADECIMAL COLUMNS

~
.
0 1 2 3 4 5 8 7

.
5 4 3 2 1
LSD 000 001 010 0" 100 '01 "0 111
HEX=DEC HEX' DEC HEX· DEC HEX' DEC HEX' DEC HEX· DEC
o o o o p
0 0 0 0 0 00 0 0 0000 NUL DLE
,
SP 0
11,048,576
22.097,152
166.536
2131,072
14,086
28.192
1261
2612
1
2
111
32 2 2
1 1
2
0001
00'0
SOH
STX
DCl
DC2
1
2
A
B
0
R : q

:
33,145,728 3196.808 312.288 3168 3 48 3 3 ETX # 3 S
3 0011 DC3 C
44,194,304 4262.144 416,384 41.024 4 64 4 4
4 0'00 EOT DC4 S 4 D T t
55,242.880 5321,680 520,490 51,290 5 90 5 5
5 E U
66,291,456
77.340,032
6393,216
7458.152
624,575
728,672
61,538
7',782
8
7
95 6
1121
6
1
5
8
0'0'
0110
ENG
ACK
NAK
SYN '~" 6 F V f
88.388,608 8524,288 832.168 82.048 8 '28 6 8 7 0111 BEL ETB 7 G W 8 w
99,437.184 9581,824 936,864 82,304 9 '44 8 8 8 1000 BS CAN ( 8 H X h
A 10,485.160 A 865,380- A 40.960 A 2,680 A 160 A 10 9 1001 HT EM I 9 I Y i
811,534.336
C12,582.912
8120.896
C78••432
845.058
C 49.152
82,81.
C 3.072
8
C
11. 8
192 C
11
12
A 'DID LF SUB J Z i ~
013,631.488 D 86',II6lI D 53,248 D 3,328 D 206 D '3 B '011 VT ESC K I k
E14.680,064
F15.728,640
0123
BYTE
E9'7.604
F983.040
4567
E57,344
F.1,440
0123
E3.664
F3.840

BYTE
4567
E
F
224 E
240 F
0123
BYTE
4587
14
15
C
D
E
F
1100
1101
1110
1111
FF
CR
SO
SI
FS
GS
RS
VS
.
-
I
<
>
?
L
M
N
0 -
\
J
I
I
m
I

-
DEL,

POWERS OF 2 POWERS OF 16
2" n 16"
256 8 zO '1s" 1 0
512 8 z4 "8' 18 1
1024 10 z8 "82 258 2
2048 11 2'2.,&3 4086 3
4086 12 2'6'1&4 lll5538 4
8192 13 :z3l.,&6 1048578 5
18384 14 2'4·1&6 18777218 8
32788 15 z26"87 2884364158 7
lll5638 18 z32·188 4294987298 8
131072 17 z38,,&, 88 719478738 9
262144 18 z40"8'o 1099611 B27 778 10
524288 19 z44',8" 17692188044418 11
1048578 20 z48"8 12 28147497671011158 12
2097152 21 z82"8 13 4 603 599 827 370 498 13
4194304 22 zIi8'18'4 72057594 037 927 938 14
838880S 23 zSO',8 15 1152921 504 808 8415 978 16
18777218 24

296
 ,-80 CROSS ASSEM8LER VERSION 1.06 OF 06/18/16
01109116 10:20:50 .OPCOOE LISTING
LOC 08J COOE STMT SOURCE STATEMENT

0574 FOC805E6 691 SET 401 IY+lNO)

0518 FOC805EE 692 SET 5,( IY+INOI
057C FOC805F6 693 SET 6,IIY+INDI
0580 FOC805FE 694 SE T 7,11 Y+ I NO)
0584 695 NN OEFS 2
696 IND EQU 5
691 M EQU 10H
698 N EQU 20H
699 01 S EQU 30H
100 END

295