Application Note AN5, Digital Electronics Laboratory, 2019

Finite State Machines with Quartus State Machine

Editor
Mun’im Zabidi, Musa Mokji, Izam Kamisian, Norhafizah Ramli

Abstract
This articles introduces the reader to the concepts of finite state machines and their rapid implementation using
Quartus state machine editor.
1 Department of Electronic and Computer Engineering, School of Electrical Engineering, Faculty of Engineering
*Corresponding author: [email protected]

1. Introduction Next State Logic

The next state logic determines what the next state will be
Designing a finite state machine (FSM) is a common task
when a clock pulse arrives. The decision is based on the
for a digital logic engineer. The two basic types of FSM
present state and input received from the outside world.
are Moore and Mealy, shown in Figure 1 and 2. Any FSM
contains three basic components: state register, next state Output Logic
logic and output logic. Output logic controls the outside world. Moore type FSM
determines the system output based only on the present
state (or the current value of flips-flops). Mealy type FSM de-
Next
Inputs State Output
state
register logic
termines the output based on present state and the present
logic Next Present Moore
state state outputs input. Due to this difference, Moore type FSM is easier to
design, while Mealy type FSM is usually more efficient. Both
Clk types are widely used. Advanced FSMs may have both kinds
Figure 1. Basic Moore type state machine. of outputs such as in Figure 3.

Mealy
Mealy
output
Present outputs
logic
Next state
Inputs State
state
Next Next register
Inputs State Output logic Moore
state state Moore
Next register Present logic Mealy output
logic outputs
state state outputs logic
Clk
Clk
Figure 3. FSM with both Moore and Mealy outputs.
Figure 2. Basic Mealy type state machine.
Finite state machines are modeled by state diagrams
State Register which describe the state changes that happen as inputs are
The state register is simply a few flip-flops which store the received.
present state. The present state is the value of the flip-flop
at any given time while the next state is the value after re-
ceiving a clock edge. A FSM with n flip-flops has 2n differ-
ent states. The number of states is limited or finite, thus
the name finite state machine. For example, an FSM with 2
flip-flops are limited to 4 states because they can only have
4 values: 00, 01, 10 and 11.
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2. Moore-type Vending Machine Table 1. State description.

The vending machine in Figure 4 is a very common example Symbol Meaning

used to demonstrate the concept of finite state machines. S0 No money received
The vending machine releases a package of product (gum, S5 5¢ received
soda, etc) after it has received 15 cents in coins [1]. S 10 10¢ received
The machine has a single coin slot that accepts nickels S 15 15¢ received
(5¢) and dimes (10¢), one coin at a time. A mechanical sen-
sor indicates whether a dime or a nickel has been inserted
into the coin slot. The controller’s output causes a item of
product to be released down a chute to the customer. The More on this later.
machine does not give change. From either state S 5 or state S 10 , more coins can be in-
serted. A nickel causes the FSM to advance to the immedi-
ately succeeding state. A dime causes the FSM to advance
Nickel
two states ahead. At state S 10 , either a dime or a nickel
Vending Release
machine advances the FSM to state S 15 , represented by the arrow
Dime
controller labeled N + D.
At state S 15 , the FSM outputs the Release (R) signal which
causes the gum to be delivered. Then the FSM is restored to
the initial condition by an unconditional transition to state
S 0 . This unconditional action is represented by the arrow
Coin Chute labeled 1 (or unlabeled).
An enhanced vending machine state diagram is shown
Figure 4. Vending machine abstract view. in Figure 6. In this version, only arrows representing state
transitions are shown. An unlabeled arrow is assumed to be
The Moore machine symbolic state diagram for the vend- an unconditional transition, e.g. S 15 → S 0 . The enhanced
ing machine is shown in Fig. 5. Each state represents how state diagram updates the labels for S 0 → S 5 and S 5 → S 10
much money has been deposited into the vending machine. transitions to resolve conflicts.

Reset
Reset
D'N'
S0
S0

D'N
N
D'N'
S5 D
S5 D

D'N
N
D'N' D S10
D S10

N+D
N+D
S15
S15 1
[R]
[R]
Figure 6. Enhanced state diagram for vending machine.
Figure 5. The state diagram for vending machine.

The next step in the design process is to enter the design

The FSM starts at initial state S 0 which means no money
using Quartus State Machine Editor.
has been deposited. If a nickel (N )) was inserted, the FSM
goes to state S 5 . This is shown by the arrow labeled N . If a
dime (D) was inserted in state S 0 , the FSM goes to state S 10 ,
represented by the arrow labeled D. If nothing was received,
the FSM stays at state S 0 , represented by the arrow looping
to itself labeled D 0 N 0 .
The state machine assumes N and D can never occur
at the same time. Although this assumption may simplify
manual design of the state machine, it may cause conflicts.

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3. Create a New Project 4. Design Entry

Launch the new project wizard in Quartus. 1. From the top menu, choose File å New å State Machine
File.

Figure 8. New state machine.

2. From the toolbar, select the State Tool.

Figure 7. New project wizard Page 1.

 After entering the folder name and project name, click

Finish
.
You can skip all the other pages. For this experiment,
the device type is not important. Figure 9. State tool.

3. When the icon changes, click four times to get four

states. These are placeholders. You can place them
any way, any where in the editor.

Figure 10. Four placeholder states.

You can skip Step 2 and 3. You can always add or delete
states during Step 8.

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4. From the toolbar, select the State Machine Wizard 6. In the Inputs tab, click once on the <New> cell.
tool.
 Confirm editing of an existing design then click
OK .

Figure 14. The Inputs tabs initial condition.

Figure 11. Select the State Machine Wizard.

Add two new inputs, N and D.

Figure 15. Inputs N and D are added.

Figure 12. Confirm edit of current state machine. 7. In the Outputs tab, click on the <New> cell and add
the output R.
5. In dialog box that appears, choose the General tab.
Make sure the bottom checkbox is checked. This al-
lows you to simplify the state diagram by not showing
arrows pointing back to the source state.

Figure 16. The output R is added.

8. The States tab defines all states in the machine. Here,

rename all states to S0, S5, S10 and S15. The table
should appear as in Figure.

Figure 13. General tab of State Machine Wizard.

Figure 17. States tab of State Machine Wizard.

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 Finite State Machines with Quartus State Machine Editor — 5/10


9. The Transitions tab define state-to-state transitions. 11. All information have been entered. Click OK
! We
Enter the transitions to get the table in Figure 18. should get Figure 20.

Figure 20. Quartus rearranged states.

12. Save the state machine file.

Figure 18. Transitions tab of State Machine Wizard.

The vending machine has only six transitions. Each row

in the table represents one transition with a source state,
destination state and the Verilog expression representing
the Boolean equation. In Verilog, AND, OR and NOT use the
operators &, | and ~, respectively.
From S 0 in the original state diagram, the arrow labeled
N goes to S 5 and the arrow labeled D goes to S 10 . In the
original design, we assume N and D are never active to-
gether. Quartus does not accept this assumption. The State
Machine Editor will give an error unless we label the tran-
sitions as D and N & ~D (Boolean N D 0 ). Alternatively, we
can label the transitions as N and D & ~N (Boolean D N 0 ).
The non-ambiguity rule for S 0 is also applied to transi-
tions from state S 5 .
For the S 10 to S 15 transition, the expression N|D repre- Figure 21. Save the file.
sents Boolean N + D.
The transition from S 15 to S 0 is unconditional. It is la-
13. From the toolbar, click Generate HDL File. A dialog
beled “1” in the state diagram (or unlabeled). In the Transi-
box will appear. The choice would not make any dif-
tions table, leave the cell blank.
ference, so choose Verilog HDL anyway.
10. The Actions tab defines the outputs. In the original
state diagram, the output R is active in state S 15 . En-
ter the actions like in Figure 19. The value “1” in the
Output Value cell means the output is active uncondi-
tionally during S 15 . This is also called a Moore output.
Figure 22. Generate HDL.
(To create a Mealy output, enter the Boolean expres-
sion the Output Value cell.)

Figure 19. Actions tab defines state machine outputs. Figure 23. Choose any language you like.

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13. After the HDL file is generated, add the file to the 5. Simulation
project.
In order to simulate the design, we will enter the input sim-
ulation waveform.

1. Choose File å New å University Program  VWF to

create a new file (see Figure 27) then click OK
.

Figure 24. Add the Verilog file to current project.

14. Set the state machine file as the top-level entity. Note:
you can do this step any time after creating a new
state machine file but it must be before compiling the
HDL file.

Figure 25. Set vendingmoore.smf as top level entity.

Figure 27. Create new waveform file.

15. Compile the generated HDL code.

2. Simulation waveform editor window will appear such

shown in Figure 28.

Figure 26. Compilation report.

After a successful compilation, you are now ready to

simulate the vending machine.

Figure 28. Blank waveform.

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 Finite State Machines with Quartus State Machine Editor — 7/10

3. Choose Edit å Grid Size... 8. Follow these steps:


(a) Set the Filter to Pins:all


(b) Click List

(c) Click the >>
button

(d) Click OK
on the Node Finder window

Figure 29. Set Grid size to 40 ns.

4. Choose Edit å Set End Time...

Figure 32. Node finder dialog.

Figure 30. Set end time to 800 ns. 9. We will be brought back at the
 Insert Node or Bus box
as shown in Figure 33, click OK
.

5. Go to View å Fit in Window to get the Vector Wave-

form at the workspace. We can also adjust the view
at our convenience through Zoom In and Zoom Out
tool.

6. Go to Edit å insert and click insert node or bus. A

pop-up dialog box will appear as shown in Figure 31.

Figure 33. Adding multiple nodes.

10. At this stage we will see five signals on the waveform

editor.

Figure 31. Insert node dialog.


7. Click Node Finder..
. A pop-up box will appear as
shown in Figure 32. Figure 34. Waveform after inserting nodes.

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 Finite State Machines with Quartus State Machine Editor — 8/10

11. Click on the clock signal, then the Overwrite Clock 14. Click run functional simulation icon on the toolbar.
tool. Next, set the clock period to 40 ns. If the simulation is successful, a new window will ap-
pear showing the result of simulated waveforms.

Figure 38. Simulation output waveform.

Figure 35. Set the clock period to 40 ns.

12. For the remaining signals, set the values according to

Figure 36.

Figure 36. Simulation input waveform.

13. Choose File å Save as.... A pop-up box will appear as

shown in Figure 37, click Save
.

Figure 37. Save the vector waveform.

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6. Mealy-type Vending Machine 4. In the States tab, enter the following states.

The Mealy type vending machines solves the same task us-
ing only three states (Figure 39). This section of the appli-
cation note only points the differences. Unless otherwise
mentioned, use the same settings as the Moore machine.

Reset

S0

D/R D'N Figure 41. Mealy states.

N+D/R S5 D 5. In the Transitions tab, enter the following states.

D'N

S10

Figure 39. The state diagram for vending machine.

1. From the top menu, choose File å New å State Machine

File.

2. In the State Machine Wizard, use the same settings in

General and Inputs tabs as the Moore type vending Figure 42. Mealy transitions.
machine.

3. In the Outputs tab, enter the R as output. Make sure 6. In the Actions tab, enter the following states.
the output is registered.

Figure 40. Mealy output must be registered. Figure 43. Mealy actions.

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 Finite State Machines with Quartus State Machine Editor — 10/10


7. Clicking OK
aftering entering all the information References
above gives the following state diagram.
[1] Randy H. Katz and Gaetano Borriello. Contemporary
Logic Design. 2nd ed. Pearson, 2004.
[2] Designing State Machines for FPGAs. Application Note
130. Actel Corporation. Sept. 1997. URL: https://www.
microsemi.com/document-portal/doc_view/130043-
state-machine-an.

[3] Munim Zabidi, Izam Kamisian, and Ismahani Ismail.

The Art of Digital Design. 2019.
[4] Introduction to the Quartus® II Software. Version 10.
Altera. 2010. URL: https://www.intel.com/content/
dam / www / programmable / us / en / pdfs / literature /
manual/intro_to_quartus2.pdf.

Figure 44. Mealy state diagram.

8. Save the file as vendingmealy.smf

9. Set vendingmealy.smf as Top Level Entity

10. General HDL.

11. Compile.

12. Simulate. You should get the same output as Figure

38.

Moore vs Mealy
This summary assumes the reader knows the difference
between Mealy and Moore outputs.
Moore outputs are locked to the state. When asserted,
Moore outputs are high as long as the FSM is in the partic-
ular state regardless of input changes. In Actions tab of the
State Machine Wizard, enter 1 in the Output Value column.
Refer Figure 19.
Mealy outputs asserted when certain conditions are met
in a state. In Actions tab of the State Machine Wizard, en-
ter the required Boolean expression in the Output Value
column. Refer Figure 43.
Mealy outputs are glitchy. To make the outputs easier to
analyze, set Mealy outputs as Registered in the Outputs tab
in the State Machine Wizard. If you do not set it as registered,
you must understand the effects of propagation delay, setup
time and hold time of flip-flops to predict when the outputs
are valid.

Figure 45. Unregistered Mealy outputs: the circles indicate

valid outputs. In Quartus, zoom in to inspect actual output
values during the rising edge of the clock.

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