EE1005 – Digital Logic Design

Lecture 29
 Outline
• Design of Sequential Circuits
– Design with D Flip Flop
– Excitation Table
– Design with JK Flip Flop
– Design with T Flip Flop

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 2

 Design of Sequential Circuits
• The design of a clocked sequential circuit starts from a set of
specifications/word description and ends with a logic
diagram or a list of Boolean functions from which the logic
diagram can be obtained
• A synchronous sequential circuit is made up of flip-flops and
combinational gates
– The design of the circuit consists of choosing the flip-flops and then
finding a combinational gate structure that, together with the flip-
flops, produces a circuit which fulfills the stated specifications
• The number of flip-flops is determined from the number of
states needed in the circuit
• The combinational circuit is derived from the state table by
evaluating the flip-flop input equations and output equations
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 3
 Steps to Design a Sequential Circuit
• The procedure for designing synchronous sequential
circuits can be summarized by a list of recommended
steps:
1) From the word description and specifications of the desired
operation, derive a state diagram for the circuit
2) Reduce the number of states if necessary
3) Assign binary values to the states
4) Obtain the binary-coded state table
5) Choose the type of flip-flops to be used
6) Derive the simplified flip-flop input equations and output
equations
7) Draw the logic diagram

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 4

 Example 1
• Design a sequential circuit that detects a
sequence of three or more consecutive 1’s in
a string of bits coming through an input line
(in other words design a sequence detector)

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 5

 Example 1 Solution
• 1 input, 1 output, 4 states, 2 flip flops
• Whenever a 0 is at input return to state S 0 and output
is 0
• When a 1 is at input move to next state (S0 to S1, S1 to
S2, S2 to S3)
• The output is 1 when three consecutive 1’s are
detected
• If more 1’s after the three consecutive 1’s then remain
on the same state (S3 in this case) and output is 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 6

 Example 1 Solution
• State Diagram and State Table
0/0
• Design with D Flip Flop
– The next state and Flip Flop input 1/0
equation are same for D flip flop 00 01
0/0
1/0
0/1
0/0

11 10
1/0

1/1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 7

 Example 1 Solution
• Design with D Flip Flop
– Flip Flop input equations
and output equation
A = DA = Ax + Bx
– Obtained by using k – map

B = DB = Ax + B’x

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal

y = AB 8
 Example 1 Solution
• Circuit Diagram

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 9

 Example 1 Solution
• In the designed circuit the output is only depending on the flip flop
states (A and B)
• A and B can only change at the clock edge
• So, the designed circuit is a moor machine

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 10

 Design with JK and T Flip Flop
• The design of a sequential circuit with flip-flops other
than the D type is complicated by the fact that the
input equations for the circuit must be derived
indirectly from the state table
• When D -type flip-flops are employed, the input
equations are obtained directly from the next state
• This is not the case for the JK and T types of flip-flops
• In order to determine the input equations for these flip-
flops, it is necessary to derive a functional relationship
between the state table and the input equations
• This is done with the help of excitation tables
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 11
 Excitation Table (JK Flip Flop)
• For JK Flip Flop Q(t+1) = JQ’ + K’Q
Q = 0; Q(t+1) = 0 Q = 1; Q(t+1) = 0
Q’ = 1, K’Q = 0 Q’ = 0, JQ’ = 0
J must be 0, K can be 0 or 1 K must be 1, J can be 0 or 1

Q = 0; Q(t+1) = 1 Q = 1; Q(t+1) = 1
Q’ = 1, K’Q = 0 Q’ = 0, JQ’ = 0
J must be 1, K can be 0 or 1 K must be 0, J can be 0 or 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 12

 Excitation Table (T Flip Flop)
• For T Flip Flop Q(t+1) = T  Q
Q = 0; Q(t+1) = 0 Q = 1; Q(t+1) = 0
T must be 0 T must be 1

Q = 0; Q(t+1) = 1 Q = 1; Q(t+1) = 1
T must be 1 T must be 0

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 13

 Design with JK Flip Flop (1/4)
• Example 2
– Design a sequential circuit given by the
following state table

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 14

 Design with JK Flip Flop (2/4)
• Example 2 (Solution)
– Flip flop inputs will be obtained by using the
excitation table of JK flip flop
Present State Input Next State Flip Flop Inputs
A B x A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 15
 Design with JK Flip Flop (3/4)
• Example 2 (Solution)
– Flip flop inputs equations JA = Bx’
– Obtained by using k-maps
Present Next
Input Flip Flop Inputs
State State
A B x A B JA KA JB KB KA = Bx
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
JB = x
0 1 1 0 1 0 X X 0
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
KB = A’x’+Ax
1 1 0 1 1 X 0 X 0
KB = (Ax)’
1 1 1 0 0 X 1 X 1
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 16
 Design with JK Flip Flop (4/4)
• Circuit Diagram

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 17

 Design with T Flip Flop (1/5)
• Example 3
– Design a 3 bit binary up counter
– 3 bit binary up counter is a circuit which can
count from 0 to 7 in ascending order
– The count is updated on every clock pulse and
after the count reaches at 7, the counting starts
from 0 again

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 18

 Design with T Flip Flop (2/5)
• Example 3 (Solution)
– No input/output is required
– At every clock pulse the circuit should move to next state
– 3 bit counter, so 8 states are needed (can count from 0 to 7)
– 8 states  3 flip flops
Present State Next State
A2 A11 A00 A22 A1 A00
0 0 0 0 0 1
0 0 1 0 1 0 000 001 010 011
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0 111 110 101 100
1 1 0 1 1 1
1 1 1 0 0 0
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 19
 Design with T Flip Flop (3/5)
• Example 3 (Solution)
– Flip Flop inputs are obtained by using
excitation table of T flip flop
Present State Next State Flip Flop Inputs
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 20

 Design with T Flip Flop (4/5)
• Example 3 (Solution)
– Flip Flop inputs equations
– Obtained by using k-maps
Present State Next State Flip Flop Inputs TA2 = A1A0
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1 TA1 = A0
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1 TA0 = 1
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 21
 Design with T Flip Flop (5/5)
• Example 3 (Solution)
– Circuit Diagram

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 22

 Practice Problem 1
• Draw a finite state machine (only the state
diagram) to detect the sequence 011.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 23

 Practice Problem 2
• Draw a finite state machine (only the state
diagram) to detect the sequence 101.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 24

 Practice Problem 2
• Draw a finite state machine (only the state
diagram) to detect the sequence 00110.

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 25

EE1005 – Digital Logic Design

Lecture 30
 Outline
• Registers
– Registers with Parallel Load
• Shift Registers
– Serial Transfer
– Serial Addition
– Comparison of Serial and Parallel Adder

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 27

 Sequential Circuits
• Circuits that include flip‐flops are usually
classified by the function they perform rather
than by the name of the sequential circuit
• Two such circuits are
– Registers
• Group of flip flops capable of storing binary
information
– Counters
• A counter is essentially a register that goes through a
predetermined sequence of binary states

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 28

 Registers
• A register is a group of flip‐flops, each one of which shares a
common clock and is capable of storing one bit of
information
• An n – bit register consists of a group of n flip‐flops capable
of storing n bits of binary information
• In addition to the flip‐flops, a register may have
combinational gates that perform certain data‐processing
tasks
• In its broadest definition, a register consists of a group of flip‐
flops together with gates that affect their operation
– The flip‐flops hold the binary information, and the gates determine
how the information is transferred into the register

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 29

 Simple 4 – Bit Register
I0 D A0
• A simplest register is a group of flip flops
>R
without any additional gates
• All the flip flops share a common clock
• A 4 – bit register is shown I1 D A1

• At positive edge the inputs I0, I1, I2 and I3 are >R

transferred to register
• The outputs A0, A1, A2 and A3 can be sampled I2 D A2
any time >R
• The clear_b input is active low
– When connected to logic 1 the register performs
I3 D A3
normal operation
– When connected to logic 0 it clears all the bits >R
(make all the output bits equal to 0)

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal clk Clear_b 30

 Register with Parallel Load
• Registers with parallel load are a fundamental building block
in digital systems
– A clock signal supplies the train of pulses
– Another control signal will decide which operation will be
performed
• The transfer of new information into a register is referred to
as loading or updating the register
• If all the bits of the register are loaded simultaneously with a
common clock pulse, we say that the loading is done in
parallel
• This can be done by applying a Clock pulse to clk input and a
load input to all data inputs

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 31

 4 – Bit Register with Parallel Load
• The additional gates are forming a 2 to 1
MUX
• The load input to the register determines
the action to be taken with each clock
pulse
– When the load input is 1, the data at the
four external inputs are transferred into the
register with the next positive edge of the
clock
– When the load input is 0, the outputs of the
flip‐flops are connected to their respective
inputs
• The feedback connection from output to
input is necessary because a D flip‐flop
does not have a “no change” condition

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 32

 Shift Register
• A register capable of shifting the binary information held in each cell
to its neighboring cell, in a selected direction, is called a shift register
• The logical configuration of a shift register consists of a chain of flip‐
flops in cascade, with the output of one flip‐flop connected to the
input of the next flip‐flop
• The serial input determines what goes into the leftmost flip‐flop
during the shift
• The serial output is taken from the output of the rightmost flip‐flop

Serial SI SO Serial
D D D D Output
Input
>C >C >C >C

Clk

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 33

 Serial Transfer
• The datapath of a digital system is said to
operate in serial mode when information is
transferred and manipulated one bit at a
time
• Information is transferred one bit at a time
by shifting the bits out of the source register
and into the destination register

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 34

 Serial Transfer with Shift Registers
• We have a clock signal
• We have another shift control signal
– When shift control is 1, data will be shifted,
otherwise no shift
• In order to keep the contents of A
unchanged, connect the SOA to SIA

SIA SOA SIB SOB

Shift Register A Shift Register B

CLK CLK
Clock
Shift CLK
Control

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 35

 Serial Transfer Example
• A = 1011
• B = 0010
• Serially transfer the contents of A to B while keeping the
contents of A unchanged
– 2, four bit shift registers will be used
– Shift control signal will be kept 1 for 4 clock cycles
– Following table is indicating the values of A and B after every CLK pulse
Pulse Shift Register A Shift Register B
Initial Value 1 0 1 1 0 0 1 0
After T1 1 1 0 1 1 0 0 1
After T2 1 1 1 0 1 1 0 0
After T3 0 1 1 1 0 1 1 0
After T4 1 0 1 1 1 0 1 1
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 36
 Serial Addition
• Operations in digital computers are usually done in parallel
because that is a faster mode of operation
• Serial operations are slower because a datapath operation
takes several clock cycles
• But serial operations have the advantage of requiring fewer
hardware components
• Two 4 bit numbers can be added serially by following these
steps
– Two 4 – bit numbers are placed in 4 bit shift registers (A & B)
– Bits are added starting from LSB
– The sum bit is fed back to shift register A
– The carry is placed in a 1 bit register and then fed to full adder

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 37

 Serial Addition with D Flip Flop

Numerical example is
on next slide

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 38

 Serial Addition with D Flip Flop
(Example)
A = 1011 B = 0010
• Sum is stored in A
• So after 4 pulses, A+B will be stored in A
• We also suppose that there is no serial input applied at register B.
Pulse Shift Register A Shift Register B x y z S C Q

Initial Values 1 0 1 1 0 0 1 0 - - - - - 0

After T1 1 1 0 1 0 0 1 1 0 0 1 0 0

After T2 0 1 1 0 0 0 1 1 0 0 1 1

After T3 1 0 1 1 0 0 0 1 1 0 0

After T4 1 1 0 1 1 0 0 1 0 0

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 39

 Serial Addition with JK Flip Flop (1/2)

JQ = xy
KQ = x’y’ = (x + y)’
S=xyQ
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 40
 Serial Addition with JK Flip Flop (2/2)
JQ = xy KQ = (x + y)’ S=xyQ

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 41

Comparison of Serial and Parallel Adder

• Comparing the serial adder with the parallel adder, we note

several differences
– The parallel adder uses registers with a parallel load, whereas the
serial adder uses shift registers
– The number of full‐adder circuits in the parallel adder is equal to
the number of bits in the binary numbers, whereas the serial
adder requires only one full‐adder circuit and a carry flip‐flop
– Excluding the registers, the parallel adder is a combinational
circuit, whereas the serial adder is a sequential circuit which
consists of a full adder and a flip‐flop that stores the output carry
– In serial adder the result depends on the present inputs, as well
as on previous inputs that are stored in flip‐flops

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 42

 Universal Shift Register
• If the flip‐flop outputs of a shift register are accessible, then
information entered serially by shifting can be taken out in
parallel from the outputs of the flip‐flops
• If a parallel load capability is added to a shift register, then data
entered in parallel can be taken out in serial fashion by shifting
the data stored in the register
• A register capable of shifting in one direction only is a
unidirectional shift register
• One that can shift in both directions is a bidirectional shift
register
• If the register has both shifts and parallel‐load capabilities, it is
referred to as a universal shift register

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 43

 Capabilities of Universal Shift Register

1) A clear control to clear the register to 0

2) A clock input to synchronize the operations
3) A shift‐right control to enable the shift‐right operation and the
serial input and output lines associated with the shift right
4) A shift‐left control to enable the shift‐left operation and the
serial input and output lines associated with the shift left
5) A parallel‐load control to enable a parallel transfer and the n
input lines associated with the parallel transfer
6) n parallel output lines
7) A control state that leaves the information in the register
unchanged in response to the clock

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 44

 4 Bit Universal Shift Register
• A four bit universal shift register contains four 4-to-1 MUX and
four D flip flops
• Block diagram of a four bit universal shift register is shown below
• There are two selection lines S0 and S1
• The modes of operation are listed in the table below

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 45

 4 Bit Universal Shift Register
Parallel Outputs

A3 A2 A1 A0

Q Q Q Q
Clear_b
^ D ^ D ^ D ^ D

Clock

S1 y y y y
S0 4x1 MUX 4x1 MUX 4x1 MUX 4x1 MUX

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Serial Input
Shift Right I0
I3 I2 I1
Parallel Inputs Serial Input
EE1005 - DLD Shift Left 46
Course Instructor : Muhammad Sajid Iqbal
 Practice Problem 1
• Draw the logic diagram of a four‐bit register
with four D flip‐flops and four 4 × 1
multiplexers with mode selection inputs S1
and S0. The register operates according to
the following function table.
S1 S0 Register Operation
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0 (synchronous with the clock)
1 1 Load parallel inputs

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 47

 Practice Problem 1 (Solution)
S1 S0 Register Operation
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0 (synchronous with the clock)
1 1 Load parallel inputs

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 48

 Practice Problem 2
• Draw the logic diagram of a four‐bit register
with four D flip‐flops and four 4 × 1
multiplexers with mode selection inputs S1
and S0 . The register operates according to
the following function table.
S1 S0 Register Operation
0 0 No change
0 1 Complement the four outputs
1 0 Clear register to 0 (asynchronous)
1 1 Load parallel inputs

EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 49

 Practice Problem 3
• Design a universal shift register having three
selection lines (S2, S1, S0) with the following
capabilities.
S2 S1 S0 Register Operation
0 0 0 No change
0 0 1 Complement the four outputs
0 1 0 Shift Left
0 1 1 Shift Right
1 0 0 Rest to 0
1 0 1 Set to 1
1 1 0 Load Parallel Input
1 1 1 No change
EE1005 - DLD Course Instructor : Muhammad Sajid Iqbal 50