Kharkov National University of Radioelectronics

Centre for Education in English

Course: “System-on-chip”

Laboratory Work
Report #2

Student: Teacher:
Gr. КІУКІі-16-3 Prof. Eugenia Litvinova
Name

Kharkov 2020
Task of the Lab#2:
Using cloud service http://www.edaplayground.com create the following
projects.
You can login this service using Facebook or Google account.

Example 1. Adder project

Use the following test data:
A1_in <= '1';
A2_in <= '1';
A3_in <= '1';

A1_in <= '1';

A2_in <= '0';
A3_in <= '1';

-- Testbench for SUM gate -- Simple SUM gate design

library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity testbench is entity Full_Adder is

-- empty port (X, Y, Cin: in std_logic; -- Inputs
end testbench; Cout, Sum: out std_logic); -- Outputs
end Full_Adder;
architecture tb of testbench is
architecture Equations of Full_Adder is
-- DUT component signal A1, A2, A3: std_logic;
component Full_Adder is begin – Parallel assignment statements
port( Sum <= X xor Y xor Cin;
X, Y, Cin: in std_logic; -- Inputs A1 <= X and Y; -- gives g
Cout, Sum: out std_logic); -- Outputs A2 <= X and Cin;
end component; A3 <= Y and Cin;
Cout <= A1 or A2 or A3;
signal A1_in, A2_in, A3_in, C1_out, S1_out: end Equations;
std_logic;

begin

-- Connect DUT
-- DUT instantiation
DUT: Full_Adder port map(A1_in, A2_in,
A3_in, C1_out, S1_out);

process
begin
A1_in <= '1';
A2_in <= '1';
A3_in <= '0';
 wait for 1 ns;

A1_in <= '0';

A2_in <= '0';
A3_in <= '1';
wait for 1 ns;

A1_in <= '0';

A2_in <= '1';
A3_in <= '1';
wait for 1 ns;

wait;
end process;
end tb;

Add Results and waveform.

Example 2. Scalable Ripple Carry Adder

Use the following test data:
r_ADD_1 <= "11";
r_ADD_2 <= "01";

r_ADD_1 <= "10";

r_ADD_2 <= "11";

r_ADD_1 <= "01";

r_ADD_2 <= "10";

r_ADD_1 <= "11";

r_ADD_2 <= "01";

library ieee; library IEEE;

use ieee.std_logic_1164.all; use IEEE.std_logic_1164.all;

entity ripple_carry_adder_tb is entity full_adder is

end ripple_carry_adder_tb; port (i_bit1, i_bit2, i_carry: in std_logic; -- Inputs
o_sum, o_carry: out std_logic); -- Outputs
architecture rtl of ripple_carry_adder_tb is end full_adder;

constant c_WIDTH : integer := 2; architecture Equations of full_adder is

signal A1, A2, A3 : std_logic; -- input signals
signal r_ADD_1 : std_logic_vector(c_WIDTH- begin -- Parallel assignment statements
1 downto 0) := (others => '0'); o_sum <= i_bit1 xor i_bit2 xor i_carry;
signal r_ADD_2 : std_logic_vector(c_WIDTH- A1 <= i_bit1 and i_bit2; -- gives g
1 downto 0) := (others => '0'); A2 <= i_bit1 and i_carry;
signal w_RESULT : std_logic_vector(c_WIDTH A3 <= i_bit2 and i_carry;
downto 0); o_carry <= A1 or A2 or A3;
end Equations;
component ripple_carry_adder is ----------------------------------------------------------------
generic ( library ieee;
g_WIDTH : natural use ieee.std_logic_1164.all;
);
port (
 i_add_term1 : in entity ripple_carry_adder is
std_logic_vector(g_WIDTH-1 downto 0); generic (
i_add_term2 : in g_WIDTH : natural := 2
std_logic_vector(g_WIDTH-1 downto 0); );
-- port (
o_result : out std_logic_vector(g_WIDTH i_add_term1 : in std_logic_vector(g_WIDTH-
downto 0) 1 downto 0);
); i_add_term2 : in std_logic_vector(g_WIDTH-
end component ripple_carry_adder; 1 downto 0);
--
begin o_result : out std_logic_vector(g_WIDTH
downto 0)
-- Instantiate the Unit Under Test (UUT) );
UUT : ripple_carry_adder end ripple_carry_adder;
generic map (
g_WIDTH => c_WIDTH architecture rtl of ripple_carry_adder is
)
port map ( component full_adder is
i_add_term1 => r_ADD_1, port (
i_add_term2 => r_ADD_2, i_bit1 : in std_logic;
o_result => w_RESULT i_bit2 : in std_logic;
); i_carry : in std_logic;
o_sum : out std_logic;
-- Test bench is non-synthesizable o_carry : out std_logic);
process is end component full_adder;
begin
r_ADD_1 <= "00"; signal w_CARRY : std_logic_vector(g_WIDTH
r_ADD_2 <= "01"; downto 0);
wait for 10 ns; signal w_SUM : std_logic_vector(g_WIDTH-1
r_ADD_1 <= "10"; downto 0);
r_ADD_2 <= "01";
wait for 10 ns; begin
r_ADD_1 <= "01";
r_ADD_2 <= "11"; w_CARRY(0) <= '0'; -- no carry
wait for 10 ns; input on first full adder
r_ADD_1 <= "11";
r_ADD_2 <= "11"; SET_WIDTH : for ii in 0 to g_WIDTH-1
wait ; generate
end process; i_FULL_ADDER_INST : full_adder
port map (
end rtl; i_bit1 => i_add_term1(ii),
i_bit2 => i_add_term2(ii),
i_carry => w_CARRY(ii),
o_sum => w_SUM(ii),
o_carry => w_CARRY(ii+1)
);
end generate SET_WIDTH;

o_result <= w_CARRY(g_WIDTH) & w_SUM;

-- VHDL Concatenation

end rtl;

Add Results and waveform.