Ordering number : ENA0692

LV5609LP
Bi-CMOS LSI

Vertical Clock Driver for CCD http://onsemi.com

Overview
The LV5609LP is vertical clock driver for CCD.

Functions
• Ternary output ×2ch
• Binary output ×2ch
• SHT output ×1ch
• Output ON resistance : 30Ω typ

Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = VM = 0V
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VDD max 6 V
VH max 20 V
VL max -10 V
VH-VL max 24 V
Allowable power dissipation Pd max with specified substrate * 0.8 W
Operating temperature Topr -20 to +80 °C
Storage temperature Tstg -40 to +125 °C
* : Specified substrate : 40×50×0.8mm3, glass epoxy four-layer (2S2P) board

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Allowable Operating Ratings at Ta = 25°C, VSS = VM = 0V

Ratings
Parameter Symbol Conditions Unit
min typ max
Supply voltage VDD 2.0 3.3 5.5 V
VH 15 17 V
VL -8.5 -7.5 -4 V
VH-VL 23.5 V
CMOS input High voltage VINH 0.8VDD VDD V
CMOS input Low voltage VINL -0.1 0.4 V

Semiconductor Components Industries, LLC, 2013

August, 2013 32207 MS PC 20060719-S00002 No.A0692-1/8
 LV5609LP
Electrical Characteristics at Ta = 25°C, VDD = 3.3V, VSS = 0V, VH = 15V, VL = -7.5V, VM = 0V,
Unless otherwise specified
Ratings
Parameter Symbol Conditions Unit
min typ max
Static current drain IDD VDD pin 1 μA
IH VH pin 10 μA
IL VL pin 1 μA
Dynamic current drain IDD VDD pin See *1 and *2. 1 mA
IH VH pin See *1 and *2. 2.4 4.5 mA
IL VL pin See *1 and *2. 3 5 mA
Output ON resistance RL IO = +10mA 20 30 Ω
RM IO = ±10mA 30 45 Ω
RH IO = -10mA 30 40 Ω
RSHT IO = -10mA 30 40 Ω
Propagation delay time TPLM No load 200 ns
TPMH No load 200 ns
TPLH No load 200 ns
TPML No load 200 ns
TPHM No load 200 ns
TPHL No load 200 ns
Rise time TTLM VL → VM V1, V3 See *1. 800 ns
VL → VM V2, V4 See *1. 800 ns
TTMH VM → VL V1, V3 See *1. 800 ns
TTLH VL → VH SHT See *1. 200 ns
Fall time TTML VM → VL V1, V3 See *1. 800 ns
VM → VL V2, V4 See *1. 800 ns
TTHM VH → VM V1, V3 See *1. 800 ns
TTHL VH → VL SHT See *1. 200 ns
*1 : Refer to the CCD equivalent load shown below.
*2 : Refer to the timing waveform on Page 7.

2000pF 2000pF

1000pF
V1 V4
(Ternary) (Ternary)

3000pF 3000pF SHT

1000pF 1600pF
V2 V3
(Binary) (Binary)

2000pF 2000pF

No.A0692-2/8
 LV5609LP
Package Dimensions
unit : mm (typ)
3322 Pd max – Ta
1.0
Specified circuit board : 40×50×0.8mm3, glass epoxy

Allowable power dissipation, Pd max – W

TOP VIEW SIDE VIEW BOTTOM VIEW four-layer (2S2P) board
(0.125) With specified substrate

(0.13)
3.5 0.8
13 18
12
(C0.116) 19
0.6
3.5

7 24
0.4
6 1 0.36
0.4 0.5 (0.5)

SIDE VIEW 0.2 Independent IC

0.15
0.83

0.07
(0.035)

0.25 0
– 20 0 20 40 60 80 100
SANYO : VCT24(3.5X3.5)X01 Ambient temperature, Ta – °C

No.A0692-3/8
 LV5609LP
Pin Assignment

VDD
VSS
NC

NC

NC

NC
24 23 22 21 20 19

VL 1 18 XSHT

SHT 2 17 XV4

V4 3 16 XSG3

V3 4 15 XV3

V2 5 14 XV2

V1 6 13 XSG1

7 8 9 10 11 12
VM

NC

VH

NC

NC

XV1
Top view

Pin Function
Pin No. Name Mode
1 VL Lo power for output (-7.5V system)
2 SHT Level shift output (binary VH, VL)
3 V4 Level shift output (binary VM, VL)
4 V3 Level shift output (ternary VH, VM, VL)
5 V2 Level shift output (binary VM, VL)
6 V1 Level shift output (ternary VH, VM, VL)
7 VM GND for output
8 NC
9 VH Hi power supply for output (15V system)
10 NC
11 NC
12 XV1 V1 transfer pulse input
13 XSG1 V1 read pulse input
14 XV2 V2 transfer pulse input
15 XV3 V3 transfer pulse input
16 XSG3 V3 read pulse input
17 XV4 V4 transfer pulse input
18 XSHT SHT pulse input
19 NC
20 VDD Power supply for input buffer (3.3V system)
21 VSS GND for input buffer
22 NC
23 NC
24 NC

No.A0692-4/8
 LV5609LP
Block Diagram

VDD Level Shift VH

20 9
& Output Buffer
0.1μF Input Buffer 1μF

XV1 12
30 6 V1
XSG1 13

XV2 14 30 5 V2

VM
7

XV3 15
30 4 V3
XSG3 16

XV4 17 30 3 V4

XSHT 18 30 2 SHT

VSS
21
VL
1
1μF

Logical Function Table

Input Output
XV1 XSG1 XV2 V1 V2
XSHT SHT
XV3 XSG3 XV4 V3 V4
L L X X VH X X
L H X X VM X X
H L X X VL X X
H H X X VL X X
X X L X X VM X
X X H X X VL X
X X X L X X VH
X X X H X X VL

No.A0692-5/8
 LV5609LP
Timing Chart

VDD
XV1 to XV4 50% 50%
VSS
XSG1 VDD
50% TPHM
XSG3
TTHM
VSS
TPMH

TTMH
VH
TTLM TTML
90%
TPLM TPML
V1
VM 10%
V3 90%

VL 10%

TTLM TTML
TPLM TPML
VM
V2 90%
V4
VL 10%

VDD
XSHT 50% 50%
VSS

TTLH TTHL
TPLH TPHL
VH
90%
SHT

VL 10%

No.A0692-6/8
 LV5609LP
CCD Equivalent Load Measurement Timing Waveform

63.5μs 127μs
2μs

XV1

XV2

XV3

XV4

XSG1
2.5μs

XSG3 63.5μs
2μs 2.5μs
16.7ms

XSHT

Enlarged View of overlapped portion

XV1

XV2

XV3

XV4

0μs 0.7μs 1.4μs 2.1μs 2.8μs 3.5μs 4.2μs 4.9μs

No.A0692-7/8
 LV5609LP

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PS No.A0692-8/8