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AX88179 USB Type-C Plug Connector Reference Schematic

D D

Page 1 Page 2
System Block (This Page) AX88179 UA2/UA3
EEPROM
25MHz Crystal
USB Type-C Plug/RJ-45 Connectors
Power Circuit
RT8075

Page 3
Revision History
C C

EEPROM

Gigabit
AX88179

USB3.0
Type C

RJ-45
Plug
XTAL25M
RT8075
B B

5V to 3.3V&1.2V
Dual channel out
voltage

Note:
1.Please refer to AX88179 USB 3.0 to Gigabit Ethernet Application Design Note
for more AX88179 PCB layout design notes.

2.Please deliver us your AX88179 schematic and PCB layout file

A
for further review. A

ASIX ELECTRONICS CORPORATION

Title
System Block
Size Document Number Rev
B 1.00
AX88179 USB Type-C Plug Connector Schematic
Date: Friday, September 26, 2014 Sheet 1 of 3
5 4 3 2 1
 5 4 3 2 1

USB Type-C Plug Connector *Note2-14 Signle RJ-45 Connector integrated Gigabit magnetic
C N1 25MHz +/- 30ppm Crystal *Note2-1 Optional for ESD Optional for EMI *Note2-2 (Turns Ratio 1CT:1CT) & Ethernet LED Circuit for AX88179 UA2/UA3
G ND A1 B12 G ND
SSRX+ GND GND U3
A2 B11 SSTX+_USB3.0 R6 NC,1M CM1 LECM2012H-900QT,Choke Active LED
SSRX- TX1+ RX1+
A3 B10 SSTX-_USB3.0 M DI3- 1 10 M DI3- M DI3- 1 4 MDI3-_T MFA_0
VB US_IN TX1- RX1- LINE_1 NC_1 1 2
A4 B9 VB US_IN MDI3+ 2 9 MDI3+ DVCC_33
VBUS VBUS Y1 G ND LINE_2 NC_2 G ND
A5 B8 3 8
D+ CC SUB2 XTL25P M DI2- GND_1 GND_2 M DI2- MDI3+ MDI3+_T
A6 B7 1 4 4 7 2 3
D- D+ NC MDI2+ LINE_3 NC_3 MDI2+ 4 3
A7 B6 5 6
D- NC R2 200 XTL25N LINE_4 NC_4 R14 330R
A8 B5 2 3
VB US_IN SBU1 VCONN VB US_IN NC,ESD Protect CM3 LECM2012H-900QT,Choke
A9 B4
C54 R27 C53 VBUS VBUS 25M CRYSTAL M DI2- MDI2-_T
A10 B3 U4 1 4
RX2- TX2- C51 C52 C14 C16 1 2 J1
A11 B2
10nF 5.1K 10% 10nF G ND RX2+ TX2+ G ND M DI1- M DI1- LA1S109-43LF

Ethernet CHASSIS GND

A12 B1 1 10
GND GND 10nF 10nF 15pF 15pF MDI1+ LINE_1 NC_1 MDI1+ MDI2+ MDI2+_T
2 9 2 3

P14

P13

P16
USB Type-C Plug G ND LINE_2 NC_2 G ND 4 3
3 8
M DI0- GND_1 GND_2 M DI0- Yellow
4 7
MDI0+ LINE_3 NC_3 MDI0+ CM4 LECM2012H-900QT,Choke MDI3-_T
5 6
LINE_4 NC_4 M DI1- MDI1-_T MDI3+_T P10
D 1 4 D
NC,ESD Protect 1 2 MDI2-_T P9
L4 GB100505D110TW MDI2+_T P8
MDI1+ MDI1+_T P7
2 3

USB CHASSIS GND

L3 GB100505D110TW 4 3 P6
VB US_IN VBUS_5V R9 1M MDI1-_T P5
CM5 LECM2012H-900QT,Choke MDI1+_T P4
C15 C13 M DI0- MDI0-_T C33 C37 MDI0-_T P3
1 4
1 2 MDI0+_T P2
4.7uF/16V/X5R 0.1uF R20 0.1uF 1uF P1 Green

40
35
33
30
28
22
*Note2-3 U2

9
MDI0+ 2 3 MDI0+_T
4 3

P12

P11

P15
4.7K

GND12A_RX
GND12A_RX
GND12A_TX
GND12A_TX
GND33A
GNDK
GND
SELF_PWR 20 63 M DI3-
VBUS_5V R 4 4.7K SELF_PWR MDIN3 MDI3+
21 62
D+ VBUS MDIP3 M DI2- DVCC_33
23 60
D- D+ MDIN2 MDI2+ Link LED
24 59
SSTX- D- MDIP2 M DI1- MFA_1
27 57
Optional for EMI *Note2-4 SSTX+ 29
SSTX- MDIN1
56 MDI1+
SSRX- SSTX+ MDIP1 M DI0-
32 54
CM2 NC,SCM2012-900,Choke *Note2-6 SSRX+ 34
SSRX- MDIN0
53 MDI0+
SSRX+ MDIP0 DVCC_33 R25 330R
D- 1 4 D- Reset Circuit R10 C5
1 2 C12 *Note2-13 14 MFA_0
DVCC_33 XTL25N MFA_0 MFA_1 1M 0.1uF
39 13
D+ NC,2pF D+ XTL25P XTL25N MFA_1 MFA_2 Yellow LED D1 Act_Link_LED R3 330R
2 3 38 8
4 3 XTL25P MFA_2 MFA_3 Green LED USB3.0_LED R26 330R
7
R19 *Note2-7 MFA_3 D2
*Note2-5 R7 22R 42 G PIO_0 TP1
NC,10K *Note2-8 50
CK25_OUT AX88179 GPIO_0/PME
6
5 G PIO_1 TP2
CK25_IN GPIO_1
CM6 NC,DLP11TB800UL2,Choke
RESET_N
R24 2.49K1% 47
RSET_BG UA2/UA3 GPIO_2
4 G PIO_2
G PIO_3
TP3
TP4
3
SSTX-_USB3.0 C49 0.1uF SSTX- SSTX- EECS GPIO_3
1 4 17
1 2 EECK EECS
16
C22 EED IO EECK
15
SSTX+_USB3.0 C50 0.1uF SSTX+ 2 SSTX+ EEDIO
4 3
3
NC,0.1uF RESET_N 18
TEST_N5
52
51 R8 NC,4.7K
*Note2-4:
RESET_N TEST_N4
EXTWAKE_N 41
EXTWAKE_N TEST_X
46 R23 4.7K When you need to mount the CM2/CM6/CM7 chokes, please remember to cut
CM7 NC,DLP11TB800UL2,Choke 2
TCLK_1 TEST_N2
36 the D+/D-/SSTX+/SSTX-/SSRX+/SSRX- traces below the CM2/CM6/CM7 chokes.
1 11
SSRX- SSRX- TCLK_0 TEST_N1
1 4 44
1 2 TEST_N3

VCC12A_RX
VCC12A_TX
68 64 *Note2-5:

VCC33A_G
VCC33A_X

VCC12A_X
TCLK_EN TEST_N6
66

VCC33IO
TEST0

VCC33A

VCC12A
VCC12A
C C

VCC3IO
VCC3IO
SSRX+ 2
4 3
3 SSRX+ 67
TEST1 The C12 cap between the D+ and D- pins is used to filter the common-mode

VCCK
VCCK
VCCK
VCCK
noise and should be placed as close as AX88179 pin #23 and #24.
R5

25
49
58
43
12
37

31
26
48
61
55

10
19
45
65
4.7K AX88179 QF
Optional for USB-IF test *Note2-6:
93C56A or 93C66A EEPROM *Note2-9 The RC reset circuit is optional for AX88179 applications. You can

U SBVCC_33

U SBVCC_12
ETHVCC_33

ETHVCC_12
EXTWAKE_N

DV CC_33

DV CC_12
reserve the RC reset circuit on your AX88179 schematic to fine tune
DVCC_33
the reset timing if necessary.
R21
DVCC_33 R1 NC,Button part
4.7K DV CC_33
C40
*Note2-7:
U5
EECS R22 0.1uF
The R7 resistor should be near to AX88179 CK25_OUT pin.
8 1
C4 VCC CS EECK
7 2 NC,4.7K
NC SK EED IO
6 3
0.1uF ORG DI
5
GND DO
4 *Note2-8:
AT93C66A R17 33R *Note2-12 The R24 resistor of RSET_BG signal MUST be 2.49K 1%.
*Note2-9:
*Note2-1:
The AX88179 supports 16-bit mode 93C56/93C66 EEPROM. The R1 resistor is
The 1M feedback resistor is optional for 25MHz crystal circuit. The reference 25MHz crystal is the NSK
mounted to set AT93C66A EEPROM to 16-bit mode.
NXK25.000AC12F-KAB6 SMD 25MHz crystal with CL 12pF and Drive Level 350uW. The 25MHz clock signals
should be within 25MHz +- 30ppm. *Note2-10:
All power pins should be implemented with a by-pass capacitor, and
*Note2-2: the by-pass capacitors should be as close as the power pins.
When the CM1/CM3/CM4/CM5 chokes are unmount, pin #1 and pin #2 traces of CM1/CM3/CM4/CM5 chokes locations
should be short together, and pin #3 and pin #4 traces of CM1/CM3/CM4/CM5 chokes locations should be *Note2-11:
short together. The R15,C19 R11,C17 resistor and capacitors are optional for fining tune
B B
the DVCC_33 and DVCC_12 power up sequence timing. (Refer to below
*Note2-3: "DVCC_33 & DVCC_12 Output Power Timing Setting" table for details.)
For the bus-power applications, the SELF_PWR signal should be pulled down; for the self-power applications,
the SELF_PWR signal should be pulled high and the VBUS signal can be pulled high directly. DVCC_33 & DVCC_12 Output Power Timing Setting
DVCC_33 & DVCC_12 Mount R11,R15 with 0 ohm resistors
without delay Unmount C17, C19

Power Circuits and By-pass Capacitors *Note2-10

Delay DVCC_33 Mount R15 with 4.7K ohm resistor and
U1 L2 L5 GB100505D110TW mount C19 with 0.1uF
DV CC_33 U SBVCC_33
VBUS_5V 8 RT8075 10 2.2uH
VIN1 LX1 C20 R18 C8 C10 C26 C30
C1 C2 3.3V_EN 1 Delay DVCC_12 Mount R11 with 4.7K ohm resistor and
EN1 10pF 453K1% 10uF/6.3V/X5R 0.1uF 10uF/6.3V/X5R 0.1uF mount C17 with 0.1uF
4.7uF/16V/X5R 0.1uF
2 R16 100K1%
FB1
Exposed Pad

L1
VBUS_5V DV CC_12
3
VIN2 2.2uH L8 GB100505D110TW
*Note2-12:
C6 C9
1.2V_EN 6
EN2 LX2
5 C18 R13 C7 C3 DV CC_33 E THVCC_33 Please reserve the EXTWAKE_N circuit location if you need to run
20pF 10uF/6.3V/X5R 0.1uF C48 C47 C45 the USB-IF compliant test (mount R22 4.7K resistor and mount a Button
4.7uF/16V/X5R 0.1uF 4 220K1% C44
GND 10uF/6.3V/X5R 0.1uF 0.1uF part at R21 location). Don't need mount R21, R22 in production.
7 R12 220K1% 10uF/6.3V/X5R
GND

FB2

*Note2-13:
9

RT8075 WDFN_10L 1A 3X3 For on-board design, please make sure AX88179 USB 3.0 signals
Optional for fining tune (SSTX+-/SSRX+-) are connected to correct USB 3.0 signals (SSRX+-/SSTX+-)
L7 GB100505D110TW
power up sequence timing DV CC_33 E THVCC_33 DV CC_12 U SBVCC_12 of USB host/hub controller. The AX88179 USB 2.0 D+/D- signals should
R15 0R C19 NC,0.1uF C36 C46 C21 C25 C34 C35 be connected to the USB 2.0 D+/D- signals of USB host/hub controller,
A A
VBUS_5V 3.3V_EN C23 C41
0.1uF 0.1uF 10uF/6.3V/X5R 0.1uF 10uF/6.3V/X5R 0.1uF
respectively.
0.1uF 0.1uF
R11 0R C17 NC,0.1uF
VBUS_5V 1.2V_EN
L6 GB100505D110TW
*Note2-14:
*Note2-11 E THVCC_12 Please double check the pin definition of the preferred USB Type-C Plug
C28 C32 Connector datasheet to design the USB Type-C Plug Connector circuit.
DV CC_12 U SBVCC_12 E THVCC_12
10uF/6.3V/X5R 0.1uF The pins naming of USB Type-C Plug Connector are defined based on
C24 C11 C42 C27 C29 C38 C39 C31 C43
USB host controller pins naming. ASIX ELECTRONICS CORPORATION
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Title
AX88179/USB Type-C Plug
Size Document Number Rev
Custom 1.00
AX88179 USB Type-C Plug Connector Schematic
Date: Friday, September 26, 2014 Sheet 2 of 3
5 4 3 2 1
 5 4 3 2 1

Revision History
Revision Date Comment
D D
V1.00 2014/09/26 1. This schematic was modified based on the AX88179_PCB20_
DEMO_BOARD_REFERENCE_SCHEMATIC_V202 schematic.
2.Replaced the USB 3.0 Connector circuit with USB Type-C Plug
Connector circuit.

C C

B B

A ASIX ELECTRONICS CORPORATION A

Title
Revision History
Size Document Number Rev
A 1.00
AX88179 USB Type-C Plug Connector Schematic
Date: Friday, September 26, 2014 Sheet 3 of 3
5 4 3 2 1