Peripheral Technical Manual

Processor
Interface Guide

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Advanced Micro Devices

Peripheral Processor
Interface Guide
Technical Manual
The International Standard of
Quality guarantees a 0.05% AQL on all
electrical parameters, AC and DC,
over the entire ope~e.

©1985 Advanced Micro Devices, Inc.

The material in this document is subject to change without notice.

Advanced Micro Devices cannot accept responsibility for use of any circuitry
described other than circuitry embodied in an Advanced Micro Devices' product.
The applications software contained in this publication are for illustration
purposes only and Advanced Micro Devices makes no representation or
warranty that such programs will be suitable for the use specified
without further testing or modification.

Printed in U.S.A.
 TABLE OF CONTENTS

Page
1.0 INTRODUCTION .................................................................... . 1-1
Intended Audience ................................................................ . 1-1
Goal Of This Book ................................................................ . 1-1
Why AMD Is Publishing- This Manual ................................................ 1-1
Designer's Role In Intelligent Peripheral Environment..... ............. .. ....... ....... 1-1
Organization Of This Book . . . . . . . . .. . . .. . . .. . . .. . . . . .. . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . 1-1
How To Use This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SECTION A: INTERFACING

2.0 THE INTERFACE PROBLEM ........................................................ . 2-1

2.1.0 Timings-Setup And Hold Times ................................................... . 2-1
2.2.0 Metastable Operation ............................................................. . 2-3
2.3.0 Bus Structures ................................................................... . 2-4
Multibus ....................................................................... . 2-5
iSBX Bus ...................................................................... . 2-5

3.0 RELATED DESIGN ISSUES .....................................'.................... . 3-1

3.1 OSCILLATOR CONSIDERATIONS ................................................... . 3-1

3.1.1 MOS Oscillators .................................................................. . 3-5
3.1.2 Overtone Crystal Oscillator ........................................................ . 3-6

3.2 TEMPERATURE CONSIDERATIONS ................................................. . 3-7

SECTION B: 16-BIT PROCESSORS

4.0 INTERFACING TO THE 8086/80186................................................... 4-1

4.1 8086 OVERVIEW ................................................................... 4-1

4.2 THE 8086 AND Z8000 PERIPHERALS ................................................ 4-1

4.2.1 Z8000 Peripherals Without Interrupts ................................................ 4-1
4.2.2 Z8000 Peripherals With Interrupts ................................................... 4-3
Discrete Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
PAL Implementation ............................................................. 4-3
4.2.3 The 8086 And AmZ8530 Interface ................ . . . .. . . . . . . .. . . . . . .. . . .. .. . . . . . . .. . 4-4

4.3 THE 8086 AND AMD PROPRIETARY PERIPHERALS .................................. 4-8

4.3.1 The 8086 To Am7990 LANCE Interface ................................. _. . . .. . . . . . . . 4-8
4.3.2 The 80186 To Am7990 LANCE Interface ............................................. 4-11
4.3.3 The 8086 To AmZ8052 CRTC Interface.............................................. 4-12
4.3.4 The 80186 To AmZ8068 Data Ciphering Processor Interface ........................... 4-15
4.3.5 The 8086 And Am9513A System Timing Controller Interface ........................... 4-16
4.3.6 The 8086 To Am9516 Universal DMA Controller Interface. ............................. 4-17
Am9516 in MIN. Mode ........................................................... 4-17
Discrete Design ................................................................. 4-17
PAL Design ........................................................ _............ 4-17
Am9516 in MAX. Mode .......................................................... 4-18
 Page
4.3.7 The 80186 To Am9516A Universal DMA Controller Interface ........................... . 4-21
4.3.8 The 8086/8088 To Am9518/AmZ8068/Am9568 Interface .............................. . 4-22
4.3.9 The 8086 And Am9519A Interrupt Controller Interface ................................ . 4-32
4.3.10 The 80286 To Am9568 Data Ciphering Processor Interface ............................ . 4-33

5.0 INTERFACING TO THE 8088 ........................................................ . 5-1

5.1 OVERVIEW OF THE 8088 .......................................................... . 5-1

5.2 THE 8088 AND Z8000 PERIPHERALS ............................................... . 5-1

5.3 THE 8088 AND AMD PROPRIETARY PERIPHERALS ................................. . 5-1

5.3.1 The 8088 And AmZ8052 CRT Controller ............................................ . 5-1
5.3.2 The 8088 And AmZ8068 Data Ciphering Processor .................................. . 5-10
5.3.3 The 8088 And Am9513A System Timing Controller ................................... . 5-19
5.3.4 The 8088 And Am9516 Universal DMA Controller .................................... . 5-19
5.3.5 The 8088 And Am9517A Interface .................................................. . 5-23
5.3.6 The 8088 And Am9519A Interrupt Controller ......................................... . 5-23

6.0 INTERFACING TO THE 68000 ....................................................... . 6-1

6.1 OVERVIEW OF THE 68000 ......................................................... . 6-1

6.2 THE 68000 AND AMZ85XX PERIPHERALS .......................................... . 6-1

6.2.1 The 68000 And AmZ8530 Without Interrupts ......................................... . 6-1
6.2.2 The 68000 And AmZ8530 With Interrupts ........................................... . 6-2
SSI/MSI Implementation ......................................................... . 6-2
6.2.3 The 6800 And AmZ853 With Interrupts Via PAL Implementation ....................... . 6-5

6.3 68000 AND AMD PROPRIETARY PERIPHERALS ..................................... . 6-7

6.3.1 68000 And Am7990 LANCE Interface ............................................... . 6-7
6.3.2 68000 And AmZ8052 CRT Controller Interface ....................................... . 6-9
6.3.3 68000 And AmZ8068 Data Ciphering Processor Interface ............................. . 6-12
6.3.4 68000 And Am9513A System Timing Controller Interface ............................. . 6-17
6.3.5 68000 And A SINGLE Am9516 DMA Controller Interface .............................. . 6-18
6.3.6 68000 And Dual Am9516 DMA Controllers Interface .................................. . 6-21
Without Other Bus Masters ...................................................... . 6-21
With Other Bus Masters ......................................................... . 6-21
6.3.7 68000 And Am9519A Interrupt Controller Interface ................................... . 6-23

SECTION C: 8-BIT PROCESSORS

7.0 INTERFACING TO THE Z80 ....................... . . . . .. .. . . . . . .. .. . . . . . . . . . . . . . . . .. . 7-1

7.1 OVERVIEW OF THE Z80 ............................................................ 7-1

7.1.1 The Z80 And Am9511A Arithemetic Processor........................................ 7-1
7.1.2 The Z80 And Am9512 Arithemetic Processor......................................... 7-2
7.1.3 The Z80 And Am9513A System Timing Controller..................................... 7-3
7.1.4 The Z80 And Am9517A DMA Controller.............................................. 7-6
7.1.5 The Z80 And Am9568 Data Ciphering Processor With The Am9517 DMA Controller ...... 7-9
7.1.6 The Z80 And Am9518/AmZ8068 Data Ciphering Processor ............................ 7-15
7.1.7 The Z80 And Am9519A Interrupt Controller........................................... 7-23
 Page
S.O INTERFACING TO THE SOS5 ......................................................... 8-1

S.1 OVERVIEW OF THE SOS5 ........................................................... 8-1

8.1.1 The 8085 And Am9511A Arithemetic Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1.2 The 8085 And Am9512 Arithemetic Processor.. .. ..... ..... .. .. . .......... . ... ...... . 8-2
8.1.3 The 8085 And Am9513 System Timing Controller. .. .. .. .. .... ... .. ... . .... . .. . ..... .. 8-3
8.1.4 The 8085 And Am9517A DMA Controller. .. .. .. .. ... .. ... .. . . .. ....... .... . ... .. . .. . . 8-4
8.1.5 The 8085 And Am9518 Data Ciphering Processor. .. ...... .. .. ... ...... .... . ... ... .. . . 8-5
8.1.6 The 8085 And Am9519A Interrupt Controller.... ....... .. . .. .. .. .... ... .... . . .. ... ... . 8-6

9.0 INTERFACING TO THE MC6S09 ...................................................... 9-1

9.1 OVERVIEW OF THE MC6S09 ........................................................ 9-1

9.1.1 The MC6809 and Am9511A Floating Point Processor.................................. 9-1
9.1.2 The MC6809 and Am9512 Floating Point Processor.... . . .. .. .... .. . .. . . .. ... ... ... .. . 9-1
9.1.3 The MC6809 and Am9517A DMA Controller. . .. ... .. .. .. . ... ... .. .. .. . . .... . .. ... . .. . 9-3
9.1.4 The MC6809 and Am9519A Interrupt Controller.. .. ..... . .. .. .. .. .. ... . . .. ... ... .. . ... 9-5

10.0 INTERFACING TO THE S051 ......................................................... 10-1

10.1 OVERVIEW OF THE S051 ........................................................... 10-1

10.1.1 The 8051 And Am9518 Data Ciphering Processor.. ...... .. .. .. .. .. ... .. .. ... . .. .. . .. . 10-1

11.0 INTERFACING TO THE ZSOOO........................................................ 11-1

11.1 OVERVIEW OF THE ZSOOO .......................................................... 11-1

11.1.1 The 28000 And Am7990 LANCE .................................................... 11-1
11.1.2 The 28000 And Am28068 Data Ciphering Processor .................................. 11-1
11.1.3 The 28002 And Am9511 A Floating Point Processor ................................... 11-1
11.1.4 The 28002 And Am9512 Floating Point Processor . .. .. .. .. .. .. .. . .. .. .. .. .. .. . .. . .. . .. 11-6
11.1.5 The 28000 And Am9513 System Timing Controller.................................... 11-7
11.1.6 The 28000 And Am9519A Interrupt Controller........................................ 11-8

SECTION D: BUS INTERFACING

12.0 MULTIBUS TO AM9516 INTERFACE .................................................. 12-1

1.0 INTRODUCTION We have a tradition of designing advanced peripherals which
are more powerful and sophisticated than the industry-
OBJECTIVE standard devices they replace. Because of our position in pe-
ripheral designs, it is appropriate that we should talk about
Supporting the CPU with modern, smart peripheral devices is
peripheral interfacing.
the most effective way to optimize a microprocessor-based
system. Working with the CPU, intelligent devices unburden
the processor by performing tasks such as counting or Direct
DESIGNER'S ROLE IN THE INTELLIGENT
Memory Access (DMA), but at a much higher throughput than PERIPHERAL ENVIRONMENT
a MOS microprocessor working alone. While the selection of a CPU is usually based on complex soft-
ware issues, sometimes even by corporate edicts, peripheral
Indeed, in cases such as high speed counting or contrOlling an
selection is governed more by performances and "features for
advanced CRT display, the job simply could not be done by
cost" considerations. It is the peripherals in most cases that will
using a MOS CPU alone. Furthermore, the modern breed of
greatly distinguish the final product. For example, the presence
peripherals has broken old design barriers by performing com-
of an Am8052 CRT Controller has a much greater impact on a
plex tasks such as linked-list DMA, which, in the Am9516 for
workstation than the kind of microprocessor used.
example, can easily be implemented for control of data infor-
mation. The entire complex task can be done in an advanced The specification of peripherals is squarely the designer's job.
peripheral device with a single instruction from the CPU. While the choice of interesting devices is almost an over-
whelming one, the supporting application information is usually
Unfortunately, exponential increases in system performance
available only for connecting a CPU to its family of peripherals.
do not come without cost. Sophisticated peripherals are more
Because of this, some designers are under the impression that
complex, more difficult to understand and often more ex-
it is difficult to mix and match CPUs and peripherals; that is, to
pensive than the CPU itself. A careful cost/benefit analysis will
use Z8000 peripherals with the 8086 or 68000; or to connect
quickly tell the prudent design engineer if a particular device is
8080/8086 peripherals to the Z80, Z8000, 6800, or 68000.
the best solution. This guide addresses the first and second
considerations. Although such cross-breeding is more complex than the tradi-
tional family connection, most of the difficulties stem from the
INTENDED AUDIENCE need to understand the idiosyncrasies of different manufactur-
The materials presented here assume an understanding of ers' devices and their sometimes confusing documentation.
digital design, a working knowledge of commercial CPUs, and The actual hardware needed to match peripherals to a
familiarity with the peripherals discussed. "foreign" CPU, or a CPU to "foreign" peripherals, is usually
quite Simple. Sometimes by incorporating a few TTL SSI/MSI
Detailed product specifications of any AMD device discussed packages or even a single PAL device is all that it takes.
here are available by calling your local sales office (see inside
back cover) or our Literature Department at (408) 749-2264.
ORGANIZATION OF THIS BOOK
This book is organized into three sections:
WHY AMD IS PUBLISHING THIS MANUAL
Due to its very broad product line, Advanced Micro Devices is Section A Discusses the general interface problem.
in a unique position to help designers understand Section B Interfacing today's three most common 16-bit
CPU/peripheral interfaces. AMD not only makes the old 8080 processors: the 8086, the 68000, and the
and 8085 processors, but also the newer Z8000 micros and the Z8000.
state-of-the-art iAPX86 machines. More importantly, we want Section C Interfacing with commercial 8-bit processors
to make designing with our devices as easy as possible. such as the Z80, the 8085, the 6809, the 8088,
and the 8051.
The Am9500 series is AM D's peripheral flagship. The
Am9511A is the only general purpose floating point processor In sections Band C, after a brief overview of the particular
on the market. The 8087 is faster, but works as a dedicated CPU, all interfaces to that microprocessor are explained. In
co-processor to the 8086. The Am9513A is the most versatile turn, each individual micro/peripheral interface is presented by
counter/timer on the market. Both the Am9517 A and the discussing :
Am9519A are one generation beyond the 8257 and the 8259 1) The peripheral itself.
that they respectively replace. The Am9516, a 16-bit Universal 2) Any critical timing constraints peculiar to the device.
DMA Controller, is in a class by itself. 3) Any required software initialization.
AMD is also an active participant in the Z8000 design sphere, 4) The system's interrupt structure (if any).
with the AmZ80XX series of peripherals several of which have 5) Bus structures.
become quite popular. Both, the AmZ8030 Serial Communica- 6) A complete block diagram with all interconnections.
tion Controller, an improved variation of the well-received Z80-
SIO, and the AmZ8036 Counter/Pia, which combines parallel
I/O with three 16-bit counters, have no equivalent in other mi-
croprocessor lines. The Z8038/8060 bidirectional FIFO buffers
offer unique solutions to the problem of buffering between dif-
ferent systems. The AmZ8016, brother of the Am9516,
represents a new level of DMA sophistication. The Am8052
CRT Controller is another device that is in a class by itself.

1-1
HOW TO USE THIS BOOK discusses that microprocessor. All interfaces to that CPU listed
The digital design engineer should first review Section A and in this book will be found there.
takes notes on some of the interfacing problems to watch out For answers to more technical questions, please call the AMD
for. Sale Office in your area (see inside back cover) and ask to
For those who are designing around a particular processor with speak to a Field Applications Engineer.
added features to the system. turn to the specific section that

1-2
 SECTION A
INTERFACING

2.0 THE INTERFACE PROBLEM II. METASTABLE OPERATION

Several problems are associated with interfacing a peripheral When to expect a cause of problem and the solutions.
device to a CPU when the two families are not designed to be
pin to pin compatible. One major problem involves the various III. BUS STRUCTURES
control signals that each chip uses. What's more, the popular i. MULTIBUS
MOS microprocessors differ not only in their instruction set and ii. iLBX
internal architecture, but also in their 1/0 interface signals and iii. iSBX Multichannel
timing, and in the way they handle DMA and interrupts. Part of
the pin incompatibility involves genuine signal differences or
2.1 TIMING
timing differences. Some pin to pin differences require nothing
more than name changes.
SETUP AND HOLD TIMES
If one remembers nothing else from this book, one should
PROBLEMS TO LOOK FOR WHEN remember the following: The most common interfacing error is
INTERFACING the violation of setup and hold times! More specifically, three
areas of setup and hold time relationships need close atten-
The following is a list of areas to watch out for when interfacing,
tion, and we will discuss them after a brief overview.
and are discussed in detail:
Setup and hold time are the minimum time the proper signal
I. TIMING must be on the bus before and after the strobe. Minimum setup
A. Setup and hold times and hold time criterion must be met for proper interface opera-
tion. When interfacing involves direct hookup, individual
CS setup and hold to strobe.
specification can be looked up and the worse case calculated
ii. Address setup and hold to strobe.
to meet timing requirements. If the interface involves additional
iii. Data setup and hold to strobe (rising or falling)
components, such as buffers or transceivers, the data to strobe
Note: Strobe may be RD, WR, or OS.
timing relationship may change and correction by delay
B. Pulse widths devices such as flip-flops or latches may be necessary to bring
AS or ALE pulse widths. the system circuit within timing requirements. The following are
ii. RD, WR, OS pulse widths. areas that need special attention:
Pulse widths can usually be stretched by inserting i) Chip select (CS) setup and hold time to strobe. (Figure
Wait States if necessary. 2.1a)
C. Interrupts Here we use RD as the strobe. Ts is the minimum CS to
Interrupt structures vary. Mixing interrupt structures strobe setup time. TH is the minimum hold time. Com-
is the toughest because two or more different sets of parisons are made in conditions where these require-
timings may need to be generated. ments are not met and could lead to the wrong device
being selected (Figures 2.1 band 2.1 c).

cs

RD

02188A-1

Figure 2.1a

2-1
 CS
\
II
it
....
,. Ts ...-
...... Tpw -?-

RD
~
02188A-2
Figure 2.1b

1 f
Tpltl + Ts

CS

RD \ I
02188A-3

Figure 2.1c

Note that it is often assumed that CS and RD or CS and Address hold time will not be met if CS is, due to internal
W R are simply gated together. This is true for most periph- delay, late in going high. This can be compensated by
erals but not in all cases. Check the manufacturer's delaying the WR strobe. Failure in meeting either require-
specification. It is often possible to implement and simplify ment will result in incorrect addressing.
the design but manufacturers do not guarantee operation iii) Data setup and hold times to strobe (WR).
in these unusual modes. (Figures 2.1d and 2.1e)
ii) Address setup and hold times,to strobe. The data setup and hold times are measured with respect
(Figures 2.1d and 2.1e) to the rising edge of the strobe. The data is represented
The figures illustrate the relationships between strobe to here as a window. If the strobe goes high too late, data hold
address setup and hold, and CS. Address setup time is time will not be met, and incorrect data may be read. This
measured with respect to the leading edge of the strobe. If may happen if the strobe is purposely delayed to meet
the strobe is not sufficiently delayed, after the address is Address setup and hold times. The data can be latched to
valid, the address setup time requirement will not be met. allow a larger window so that data hold time can be met.

2-2
 ADDR

cs

\viR

DATA --( ~r-

02188A·4
Figure 2.1d

ADDR ..t....;L..lL-"-I"-----

cs

\viR

DATA

02188A-5
Figure 2.1e

Latches and flip-flops are normally considered bi-stable

2.2 METASTABLE OPERATION devices, since they have two unconditionally stable operating
Metastable conditions occur in all flip-flops when the active points, either HIGH or LOW. There is, however, a third operat-
clock edge samples the input at exactly the same time the input ing point when the cross-coupled arrangement is exactly bal-
changes state. When this happens, the cross-coupled latch at anced. This operating point is stable only if there is no noise in
the output can reach a balanced, symmetrical condition in the system and the system is perfectly balanced. The condition
which it will remain for some arbitrary time before returning to is called metastable (meta=Greek for "between"). A metas-
its proper state. This problem is faced by designers when table condition will last only long enough for the circuit to fall
interfaCing asynchronous digital signals. Although most difficul- into one of the two stable operating pOints. This period can be
ties can be overcome somewhat easily, there is a more funda- many micro-seconds, or milliseconds, for devices as fast as a
mental problem that defies a perfect solution. The following is a 74874 flip-flop. If a flip-flop has reached the balanced, metas-
general overview of the metastable problem. table condition, it may remain in this state for an undetermined
time, perhaps 1000 times longer than its normal response
speed. Previously, the designer of asynchronous system had
only one remedy for the metastable problem; two or more
synchronizer flip-flops could be cascaded. This can reduce the
probability of a metastable output but will also increase the
throughput delay.

2-3
WHEN TO EXPECT THIS TO CAUSE A "Going metastable" here means that the synchronizer output is
PROBLEM? within a mid-level or oscillation range for an unpredictable time.
In most digital systems, certain asynchronous events Most occurrences will last less than 50 ns, but may occasion-
(keystrokes, incoming data, interrupts) must be synchronized ally last much longer - perhaps many microseconds. This cer-
to the computer clock. The textbook solution is a fast, clocked tainly can upset the timing chain.
flip-flop, like the 74S74, in which the asynchronous signal is A metastable latch or flip-flop has an unpredictable delay and
applied to the 0 input and clocked with the system clock. This will therefore change its output at a time that differs from the
usually results in a perfectly synchronized output. value obtained from the worst case timing analysis. In a slow
If the data sheet specified a setup time requirement (3 ns), this system this usually doesn't matter, but in a fast system it can
means that any signal that arrives at least 3 ns before the clock lead to a "crash".
edge will achieve the intended result, i.e., an High will set, an
Low will reset the flip-flop. Great for synchronous systems! But SOLUTIONS
what happens when the asynchronous input violates this setup We cannot eliminate the basic problems but we can reduce the
time requirement and changes less than 3 ns before the clock probability in two ways:
edge? Most of the time, nothing. The actual moment where the 1) Cascade two or more synchronizer flip-flops, which is the
flip-flop samples the 0 input is somewhere in the guaranteed method employed in all "metastable free" systems.
range, i.e., somewhere less than 3 ns before the clock. So the
2) Use flip-flops that are less prone to metastable operation
flip-flop makes the decision. It either senses the change on the
than the popular 74S74. For example, the AMD Am29821-
asynChronous input and therefore changes the Q output, or it
26 registers are "metastable-hardened". They show no os-
ignores the change and doesn't change the Q output. So the
cillations and only a minimal increase in output delay when
only thing lost is one clock cycle. Unfortunately that's not al-
hit right in the window.
ways true. If the 0 input changes exactly at the same moment
that the flip-flop makes its deciSion, it might transfer exactly the Metastable operation is an inherent, so far incurable disease of
amount of energy to kick the output latch into the metastable all asynChronous interfaces. Once understood, the problem
balanced condition, from which it will recover after an unpre- can be handled by reducing its probability to an acceptable
dictable delay (measured in nanoseconds, microseconds or level. AMO's Am29821-26 registers vastly minimize this
even milliseconds). problem. The Am29800 registers, while not totally immune to
this problem, are "metastable hardened" by means of a unique
Any latch, flip-flop or register has a "moment of truth" some-
circuit design that reduces both the probability and the delay of
where inside the guaranteed range of setup time where it ac-
any metastable condition. An artificially induced metastable
tually makes up its mind. If the input changes at that very
condition that failed to produce any output oscillation merely
moment, the output is no longer synchronous. This "moment of
increased the clock-to-output delay by 6 ns. This is an improve-
truth" is a very short window. For TIL flip-flops, it is of the order
ment of many orders of magnitude over previously available
of 10 ps; for MOS devices, it is more like 50 ps to 100 ps.
deSigns.
For purposes of this discussion, this timing window will be
called "t".
2.3 BUS STRUCTURES
Here are two extreme examples. In each case there is a need
In the course of interfacing, special attention must be applied
to synchronize asychronous inputs that have no phase or fre-
to the different standard bus systems. They are standard be-
quency relationship with the computer clock.
cause they have the acceptance and support of the industry;
• Data signal derived from a disk, roughly 6 MHz wilh enough different because each evolved to satisfy a particular function.
frequency modulation and jitter to make it totally asynchro-
Bus systems are developed to increase the flexibility and ex-
nous to the 10 MHz computer clock.
pandability of the mother board. They are also developed to cut
Every time the Data Signal falls into the "window", the probabil- cost and hardware overheads. Since each bus structure has its
ity of hitting the window is t divided by the clock period, or even unique area of operation, each must be carefully matched for
simpler: clock frequency times t. proper interfacing.
M Metastable Rate f(O) .f(C).t The following are brief explanations on different major bus
f(O) Device Frequency 6 MHz . 10 MHz . structures and areas of their involvement:
10 ps
ftC) Clock Frequency 600 Hz BIG MULTIBUS VS LITTLE MULTIBUS
The synchronizer goes metastable 600 times per second. The big Multibus architecture connects the single board com-
puter with its CPU, memory and I/O to the outside world. The
• Keyboard entry: one keystroke per second synchronized
so-called little multibus is the bus between the CPU and the
with a 100 kHz clock.
other components on the single board computer.
M = Metastable Rate = 1 Hz. 105 Hz . 10 ps = 10-6 Hz
The synchronizer goes metastable with a statistical probability
of once per 106 sec., i.e., once every six weeks (assuming 5
eight-hour days/week).

2-4
MULTIBUS iSBX
The Multibus evolved, in structure, from 8-bit to 16-bit capabil- The iSBX bus provides users with a low cost, on-board expan-
ity; and in architecture, expansion via the iSBX bus and Multi- sion solution for Multibus single board computers. The iSBX
channel bus, and iLBX bus. Expansions were necessary boards allow addition in the areas of parallel I/O, serial I/O,
because a single system bus structure was no longer capable peripheral controllers, and high-speed math, without going to
of supporting the demands of today's high-speed, high- the expense of additional full Multibus board. iSBX bus com-
performance VLSI microprocessor technology, and its increas- patible boards enable users to buy exactly the capabilities they
ingly complex configurations. require for their Multibus systems, which keeps both system
size and system cost at a minimum.
iLBX
The iLBX bus provides users the architectural solution that MULTICHANNEL
extends the high performance benefits of a processor's on- Multichannel bus provides users with a separate path for DMA
board local bus to off-board memory resources. Powerful iLBX I/O block transfers. The new VLSI microprocessors that
system modules can be created using the bus to connect a process data at very high rates require the connection of
single board computer and multiple memory cards. The iLBX numerous high-speed I/O devices to the system bus. The Mul-
bus preserves the advantages in performance and architecture tichannel bus provides for high speed block transfers of data
of on-board memory, while allowing a wide range of memory over an 8/16-bit wide data path between peripherals and single
capabilities to match application requirements. board computer resources.
Motorola has its own equivalents to these busses. The signals
and interfaces are slightly different but the functions are similar,
and the objective of higher throughput is the same.

2-5
3.0 RELATED DESIGN ISSUES necessary to use TTL gates for satisfactory operation: Unfor-
tunately , a large value resistor R is not adequate for biasing a
This chapter shows other related areas that the designer TTL gate into active region. Low values of R, however, produce
should consider. a considerable Signal feedback, thus reducing the gain. The
arrangement shown in Figure 3-1 c was originally suggested by
3.1 OSCILLATOR Dr. Newel of CTS, Knights, Inc., and seems to be reasonably
CONSIDERATIONS acceptable. Measurements on this configuration showed slight
Basically, a crystal oscillator can be thought of as a closed-loop improvement in stability, however, it needs an extra resistor
system composed of an amplifier and feedback network from input to ground.
containing the crystal. Amplitude of oscillation builds up to the A more elaborate scheme of biasing is shown in Figure 3-1d.
point where non-linearities decrease the loop gain to unity. The This circuit works very well with 74L804 but not with 74804.
frequency adjusts itself so that the total phase shift around the Although there is no free running or relaxation oscillation pres-
loop is 0 or 360 degrees. The crystal which has a larger reac- ent when the crystal is disconnected, this circuit has a serious
tance frequency slope, is located in the feedback network at a defect that it sometimes changes its mode of oscillation from
point where it has the maximum influence on the frequency of 3rd harmonic to fundamental. These observations were con-
oscillation. A crystal oscillator is unique in that the impedance firmed with Dr. Newel, who also noted similar results. This
of the crystal changes so rapidly with frequency that all other configuration has been regarded as undesirable in our applica-
circuit components can be considered to be of constant reac- tion since it needs a greater number of external components.
tance. This reactance is calculated at the nominal frequency of
the crystal. The frequency of oscillation will adjust itself so that EXPERIMENTAL RESULTS
the crystal presents a reactance to the circuit which will satisfy The models described in Figures 3-1b and 3-1c have been
the phase requirement. If the circuit is such that a loop gain of thoroughly tested to determine with reasonable assurance that
greater than unity does not exist at the frequency at which the the circuit will perform properly when produced in quantity.
phase requirement can be met, oscillation will not occur. Also, the stability of frequency of oscillation with respect to
Applying the principles of oscillator design usually is difficult variation in supply voltage and temperature is within the accep-
because many factors play an important part. As a result, the table limit. 8ince the oscillator is a part of the whole clock
design of crystal oscillators is often a "cut and try" procedure. A generator chip, it is important to find out how much current it
popular method, which is highly experimental, consists of takes and how this current can be optimized. The oscillator
giving a qualitative explanation of how the circuit works and circuit will require two buffers, one for driving the internal gates
presenting a number of typical schematic diagrams for that and the other to supply outside the chip, each having the
oscillator configuration. The configuration used depends capacity to sink at least 24 mA. A 74804 having six inverters
mainly on the type of application. The use of logic gates as each with current sinking capacity of 20 mA has been used to
crystal oscillators is common in systems where the oscillator evaluate the performance of the oscillator. Adhering to parts
outputs must drive digital hardware. These oscillators are very made by the AMD process, a 748158 with select and strobe
simple but are prone to problems with respect to free-running lines connected to GND was used to give four inverters similar
and spurious oscillations. These problems, however, can be to those in 74804. Only three of the gates are used, one biased
eliminated by proper design 0.1 the feedback network. to act as the oscillator and the other two as buffers and the rest
of the gates are connected to remain in the high state. Initially,
A basic, low frequency, gate oscillator is shown in Figure 3-1a.
a biasing resistor of 390 ohms is used for the model of Figure
R1 is used to bias the gate near a point where it can operate as
3-1b and subsequent performance with a 680 ohm; bias resis-
a linear amplifier and R2 is used to raise the effective output
tor has also been examined. To find the mode of oscillation to
impedance of the gate. The gate provides the necessary gain
which the circuit is locked, different combinations of C1 and C2
and produces a phase shift of 180 degrees. The network con-
are chosen and different frequency XTAL is plugged into the
sisting of C1, C2 and the crystal produces an additional 180
circuit. Table 3-1 shows the typical results where C2 has been
degree phase shift. The crystal looks inductive and is resonant
kept constant.
with capacitors C1 and C2. The frequency of oscillation auto-
matically adjusts itself so that this is true, therefore, the combi- When this type of data was taken with other values of C2, it is
nation of crystal and C1 alone has a net inductive reactance at observed that:
the operating frequency. Current 11 lags voltage e2 by 90° and a) The circuit oscillates even without the crystal; the frequency
voltage e1 being developed across C1 lags current 11 by 90°, of oscillation, the natural frequency, can be chosen by
making it 180° behind e2. This explanation is valid only at low varying C1 and C2.
frequencies where the gate produces no phase shift. In more
usual cases some phase compensation is necessary and oc- b) When the crystal is inserted in the circuit, the frequency of
curs at the input of the pi network due to the presence of R2. At oscillation is locked to either fundamental or some overtone
high frequencies, R2 in fact can be considered as the output of the XTAL depending on the natural frequency of the
impedence of the gate and does not need to be added exter- circuit.
nally. In its simplest form, the gate oscillator thus can be shown c) The natural frequency of the circuit needs to be slightly
as in Figure 3-1 b. For frequencies higher than a few MHz, it is lower than the frequency at which the crystal is desired to
be operated.

3-1
 Rl R

Cl +
0
I_e1 It e2
I C2
I-- C1 I C2

(0.) (b)

2.4 k 1 k k

Rl

01
20 Pf
T
~
k
I C1 I-- C2 I--
47 pf 75 Pf
I
--
(C) (d)

02188A-6
Figure 3-1

Table 3-1

Frequency of Oscillation in MHz

C1 p F C2 p F Without 17 MHz 27 MHz 36 MHz =40MHz
XTAL XTAL XTAL XTAL XTAL
0 47 58.425 STOP STOP STOP STOP
18 42.959 41.980 44.998 5 45.974 44.260
39 36.380 51.7153 44.998 5 37.582 39.833 3
47 34.651 51.715 3 44.998 5 36.000 3 39.8333
150 25.393 25.857 27.000 3 36.0003 39.8333
330 15.917 17.2271 27.0003 19.924 16.080
510 14.114 17.2261 14.999 15.110 14.938
620 11.106 17.226 1 12.954 11.989 1 13.2651
750 9.346 17.226 1 13.822 9.111 9.065

NOTES:
(1) XTAL working at fundamental mode.
(3) XTAL working at third overtone.
(5) XTAL working at fifth overtone.

3-2
Since C1 and C2 are connected outside the chip, the customer Measurements of deviation in frequency in PPM (Parts per
has the flexibility of choosing his operating frequency and trim million) due to change in supply voltage and measurements of
to the accuracy he desires. A series of graphs as shown in current taken by both the oscillator and the two buffer circuits
Figure 3-1 e can also be specified to the customer for selecting are also made for both models and the typical results are given
the natural frequency of oscillation for a particular bias resis- in Table 3-2.
tance used.

40

74S04
R = 390 OhM

30

20

10

o
100 200 300 400 500
IfH3-1E C1 In pf :>

02188A-7

Figure 3-1e

3-3
 Table 3-2

I
R1 n R2 n Vee ICC. InA fo PPM/vnlt
MODEL Vt)lts @ 2S·C KHz (S.5V--4.5v)

I
with a
390 -
5.5
5
I
38.4
34.2
36001.361 II
147/36

single
reSistor 390 - 5.5 38.3 i
biaSing

680
5
5.5
34.1
37.7
27000.853
I 90/27

36001.372 12/36
5 33.3

680 - 5.5 37.0 27000.834 46/27

5 33.1

II 1.5K 5.!) 36
2.4K
with 36001.270 89/36
two 5 31.4
resistor
biasinq
2.4K 1.5K 5.5 33.8
27000.503 20/27
5 30.1

10% increase in Icc has been observed at 125°C. Icc depends CONCLUSION
on the biasing resistor to some extent but to a larger extent on The result of these brief experiments demonstrated the perfor-
the gates used. For example, keeping the buffer gates the mance of the simple oscillator of Model I is satisfactory and
same (74S04), if the oscillator section is changed from 74S04 adequate for general purposes. The Model II oscillator is more
to 74LS04, about 8 mA of current can be saved. Using a higher stable in the sense that it does not oscillate when the XTAL is
value of bias resistor in Model I can apparently improve the not in the circuit. It has a smaller Icc figure but it needs an extra
stability factor (PPM), but it has the adverse effect of decreas- resistor. Since the bias resistors are connected outside the
ing the equivalent negative resistance of the oscillator. The chip, the customer has the optipn to choose his model.
equivalent negative resistance of an oscillator is a measure of
Since the buffer gates need to sink 24 mA each, only the
the highest crystal resistance that can be used without stop-
74S04 type of gates are to be used. Some amount of current
ping the oscillation. It has been found that by increasing the
can be reduced by using high resistance values in the oscillator
bias resistance from 390 ohms to 680 ohms, the negative
gate. At times the oscillator works even with 74LS04 or 74S04
resistance has decreased by 24 ohms at 36 MHz and by 60
type of gate, but the performances at high frequency and low
ohms at 27 MHz.
temperature with 4.5v Vee are poor. This is due to the higher
Measurements of the performance of the oscillator at 125°C propagation delay in the gates. A 74S04 type of gate (4K ohms
and at -55°C have been made. A maximum deviation in fre- on the base of the input transistor and 1.6K ohms on the phase
quency of 7 PPM has been observed by varying temperature splitter) made in Schottky process will have less propagation
from -55°C to 125°C with 5.5v Vee at 36 MHz. delay and work satisfactorily as an oscillator with a reduction of
at least 5 mA in current.
No reliable measurement has been made on the drive level of
the crystal. Dr. Newel has confirmed that the drive level for the
crystal in theSe models is quite safe.

3-4
 necessary RC phase lag. This scheme does reduce frequency
3.1.1 MOS OSCILLATORS stability slightly and increases crystal power dissipation. To
While gate oscillators are quite popular, they can cause prob- ensure that oscillations start when power is applied, RFB dc-
lems ranging from temperamental operation to lack of oscilla- biases A1 's input and output for Class A operation. A1 's output
tion. The gain elements are the primary problem source and it is not logic-level compatible, so A2 increases the amplitude to
is not possible to reliably identify the analog characteristics of a full rail-to-rail swing. A2 also minimizes circuit rise and fall
digital gates, and there is no guarantee that gates from various times and buffers the oscillator output. With 74C Series CMOS
manufacturers will produce the same results when plugged inverters, this circuit has a maximum operating frequency of
into the oscillator circuit. Furthermore, some circuits seem to about 2 MHz. High performance CMOS such as those found
favor certain gate locations within the IC package. on modern peripherals have CMOS oscillators that operate up
There are four major reasons for crystal resonant frequencies to 20 MHz. For higher frequency operation, ECl devices can
be used to integrate 20-MHz Pierce oscillators (Figure 3-1.1b).
drift:
- Aging
- Temperature change
- Supply-voltage or load variations
- Mechanical disturbances
For good frequency stability and reasonably simple circuit
design, a Pierce-type oscillator that employs discrete compo-
nents should be' considered.
The Pierce-type oscillator is specially good for controlling tem-
perature effects. Other advantages are:
- lower power dissipation above 20M Hz.
- Paralleled fixed and variable capacitors allow fine
frequency trimming. Trimming with variable capacitor, of
15 to 40 pf in value, in series with the crystal.
1 M
Gain is not as high as other types of oscillators but Zin is
higher. High gain transistors can be used in either single or
multiple stage amplifiers.
o t;
MHz _ '" 2eo pF
- Closely resembles the type AMD uses. Rs = 24~
Figure 3-1.1 a shows a typical Pierce-type oscillator using B
series CMOS inverters. The disadvantage of this circuit is A1 's 02188A-8
low gain. To increase the loop gain, however, A1 's output resis-
tance Ro serves in place of a discrete resistor to develop the Figure 3-1.1a

sv
o

P.
o sv

o
6 PSIO
~o4 10116 ---~---t
2 PSIO ---0
1

E,
10116 12 10116
(TTL>
ITI 0.1 uF DR DR DR
l 10216 10216
10

R,2.2k
BUFFER

~0.1 uF

'---------__.----l0 I---_--"Nv-.J
C. ITI C,
470 PF~ 20 MHz
R, = 7
-L 0.001 uF

Figure 3-1.1b 02188A-9

3-5
The three line receivers reside in one DIP, and all are series It should be noted here that the total capacitance should in-
cascaded to develop sufficient circuit gain. This design also clude the Cin of the part, and not just the values of the bypass
includes a buffer-circuit arrangement, for applications that in- capacitors used in the circuit. Cin of the part should be in the
volve other than ECl devices. Because the Pierce oscillator range of 5 to 10pf. Use manufacturer's recommended
and TTL are not compatible, due to the logic family's poor > capacitors for proper oscillation but use total capaCitance in
switching parasitics at low signal amplitudes, the buffer also calculations.
provides a means of employing a high-frequency IC-based
Pierce oscillator in a TTL system. One can provide frequency- Table 3-3 shows the frequency shift sensitivity to the supply
trimming capability by connecting a variable capacitor (15 to 40 voltage, in a Pierce-type oscillator.
pf) in series with the crystal.

Table 3-3

Frequency Sensitivity To Supply Volto.ge

Frequency Shift
b,. F (PPM)
Circuit (For b,. Vcc = 2V DC)
Pierce lIE 1 MHz 0.9
lIE 20 MHz 1.5
lIE 4 kHz 0
lIE 1 MHz o.t series resono.nce 0.8
lIE CMOS 1 MHz 3
lIE ECl 20 MHz 2

3.1.2 OVERTONE CRYSTAL

.... -,
OSCILLATOR Fundamental
Due to processing limitations during manufacture, the maxi-
Third harmonic
mum resonant frequency of most quartz crystals is approxi-
mately 20 MHz. For frequencies above 20 MHz, or if using a Fifth harmonic
crystal with a fundamental frequency that is too low for an '''',
application, the third harmonic of that frequency can be used. ,I'~ ~'", '
Figure 3-1.2a shows how a square wave corresponds to a
fundamental sine wave with odd harmonics. The square wave
has only odd harmonics, and when we add the first and third
" I : \,1
\
\<C:,' '1
....
\
harmonics together, the superpositioning produces a \ I
waveform that is more square than sinusoidal (Figure 3-1.2b). \ I
\ I
Figure 3-1.2c shows an overtone crystal oscillator with MECl
10,000 devices. The MECl circuits in crystal oscillators has " ...
several advantages over conventional circuitry. When a 1/1005
second gate is used as a buffer for the oscillator, there is
minimum frequency change with output loading. Also, the high 02188A-10
input impedance and 0.8 voit logic swing prevent the possibility Figure 3-1.2a
of overdriving the crystal. In addition, this particular circuit is
frequency insensitive to +/-20% power supply variations, and
the frequency versus temperature characteristics closely follow
the crystal characteristics. The circuit in Figure 3-1.2c employs
an adjustable resonant tank circuit which insures operation at
.... -
./15t
... lst + 3rd

the desired crystal overtone. C1 and l1 form the resonant tank

circuit, which, with the values specified, has a resonant fre-
quency adjustable from approximately 50 MHz to 100 MHz.
Overtone operation is accomplished by adjusting the tank cir-
cuit frequency at or near the desired frequency. The tank circuit
exhibits a low impedance shunt to off-frequency oscillations,
suppressing the first and fifth harmonic; and a high impedance
to the desired frequency, allowing feedback from the output. Figure 3-1.2b 02188A-11

3-6
 frequency Range. 20 MHz to 100 MHz
depending on crystal
9 - 35 pf frequency and tank
tuning

OUT

---<0 OUT
LI Vss IS 0. -1.3 Volt
Rp RP supply obtained to
C1 one of the following Methods'
(A) Internal V ss supply
9 - 35 pf
(B) Gate V ss supply

uH for 50-100 MHz

V ss
In MCI0116
1.0 uH for 20-50 MHz

Rp = 510 OhMS to 'tE

or 50 OhMS to V
I O.001 uf

TT
IFM3-12C
02188A-12
Figure 3-1.2c

Operation in this manner guarantees that the oscillator will of the completed assembly and specification of the conditions
always start at the correct overtone. in which the device will function properly. As devices become
both smaller and more complex and the requirement for high
The values of inductor and capacitor to be used are calculated
speed operation becomes more important, heat dissipation will
by using the following formula:
become an ever more critical parameter.
1
Thermal resistance is defined as the temperature rise per unit
f= 27T\!CL L1
power dissipation above some reference condition. The unit of
measure is typically 'C/watt. The relationship between junction
3.2 TEMPERATURE temperature and thermal resistance is given by:
CONSIDERATIONS Tj = Tx + Pd' R JX (1)
where Tj junction temperature
DEFINITION OF THERMAL RESISTANCE Tx reference temperature
Pd power dissipation
THERMAL RESISTANCE R JX thermal resistance
The reliability of an integrated circuit is largely dependent on X some defined test condition.
the maximum temperature which the device will attain during
In general, one of the following three conditions is defined for
operation. Because the stability of a semiconductor junction
measurement of thermal resistance:
declines with increasing temperature, knowledge of the ther-
mal properties of the packaged device becomes an important RJC- Thermal resistance measured with reference to the tem-
factor during device design. In order to increase the operating perature at some specified point on the package
lifetime of a given device, the junction temperatures must be surface.
minimized. This demands knowledge of the thermal resistance RJA-Thermal resistance measured with respect to the (still
air) temperature of a specified volume of still air.

3-7
RJA- Thermal resistance measured with respect to the silicon die. Indeed, it seems likely that the initial thermal
(moving air) temperature of air moving at a specified response of a powered device can be directly related to the
velocity. quality of the die attach bond.
The relationship between RJA is
EXPERIMENTAL METHOD
RJA = RJC + RCA The technique for measurement of thermal resistance involves
where RCA is a measure of the heat dissipation due to natural the identification of a temperature-sensitive parameter on the
convection (still air) or forced convection (moving air) and the device and monitoring this parameter while the device is
effect of heat radiation and mounting techniques. RJC is de- powered. For bipolar integrated circuits the forward voltage of
pendent solely on material properties and package geometry; the substrate isolation diode provides a convenient parameter
RJA include the influence of the surface area of the package to measure and has the advantage of a linear dependence on
and environmental conditions. Each of these definitions of ther- temperature. MaS devices which do not have an accessible
mal resistance is an attempt to simulate some manner in which substrate diode present greater measurement difficulties and
the package device may be used. may require simulation through use of a specially designed
The thermal resistance of a packaged device, however mea- thermal test die. Choice of the parameter to be measured must
sured, is a summation of the thermal resistances of the individ- be made with some care to insure that the results of the mea-
ual components of the assembly. These in turn are functions of surement are truly representative of the thermal state of the
the thermal conductivity of the component materials and the device being investigated. The measurement of the substrate
geometry of the heat flow paths. Like other material properties, isolation diode which is generally diffused across the area of
thermal conductivity is usually temperature dependent. For the die yields a weighted average of the condition of the indi-
alumina and silicon, two common package materials, this de- vidual junctions across the die surface. Measurement of a
pendence can amount to a 30% variation in thermal conductiv- more local source would yield a less generalized result.
ity over the operating temperature range of the device. The For those MaS devices for which no useful parameter is avail-
thermal resistance of a component is given by able, simulation is accomplished by using the thermal test die.
The basis for this test die is a 2 mil square cell containing an
L
R=K(T)A isolated diode and a 1 k10hm resistor. The resistors are inter-
connected from cell to cellon the wafer before it is cut into
where L length of the heat flow path multiple arrays of the basic unit cell. In use, the device is
A cross-sectional area of the heat flow powered via the resistors with voltage or current adjusted for
path the proper level and the voltage drop of the individual diodes is
K(T) thermal conductivity as a function of monitored as in the case of actual devices.
temperature
Prior to the thermal resistance test, the diode voltage/ tempera-
and the overall thermal resistance of the assembly ture calibration must be determined. This is done by measuring
(discounting convective effects) will be: the forward voltage at 1 mA current level at two different tem-
L peratures. The diode calibration factor is then:
R=LRn=L~
T
But since the heat flow path through a component is influenced V
by the materials surrounding it, determination of L and A is not
always straightforward. in units of "C/mV. For most diodes used for this test the volt-
age/temperature relationship is linear and these two
A second factor that effects the thermal resistance of a
measurement points are sufficient to determine the calibration.
packaged device is the power dissipation level and, more par-
The actual thermal resistance measurement has two alternat-
ticularly, the relationship between power level and die
ing phases: measurement and power on. The device under
geometry, i.e. power distribution and power density. By rear-
test is pulse powered with an ON duty cycle of 99% and a
rangement of equation 1 to
repetition rate of <100 Hz. During the brief OFF states the
1 1 device is reverse-biased with almA current and the voltage
Pd = R:;x- (Tj - Tx) = ~ (Tj - Tx)
drop is measured. The series of voltage readings are averaged
over short periods and compared to the voltage reading ob-
the relationship between Pd and Tj can be more clearly seen.
tained before the device was first powered ON. The thermal
Thus, to diSSipate a greater quantity of heat for a given
resistance is then computed as:
geometry, Tj must increase and, since the individual Rn will
also increase with temperature, the increase in Tj will not be a
linear function of increasing power levels.
A third factor of concern is the quality of the material interfaces.
where K, calibration factor
In terms of package construction, this relates specifically to the
Vi initial forward voltage value
die attach bond, and for those packages having a heatsink, the
V, current forward voltage value
heatsink attach bond. The quality of the die attach bond will
most severely influence the package thermal resistance as this
VH heating voltage
IH heating current
is the area which first impedes the transfer of heat out of the

3-8
The pulsing measurement is continued until the device has use of heaters attached to the metal fixture, the "case" temper-
reached thermal equilibrium and the final value measured is ature may be maintained at any specified value above arnbi-
the equilibrium thermal resistance of the device under test. ent. The requirements for measurement of R JA (moving air)
When the end result desired is RJA (still air), the device and are rather more complex. They involve the use of a small wind
the test fixture (typically a standard burn-in socket) are tunnel with capability for monitoring air pressure, temperature
enclosed in a box containing approximately 1 cubic foot of air. and velocity in the area immediately surrounding the device
For RJC measurements the device is attached to a large metal tested. Standardization of this last test requires much careful
heatsink. This ensures that the reference point on the device attention.
surface is maintained at a constant temperature. Through the AMO's parts are designed not to exceed 160°C junction tem-
perature, at the maximum ambient temperature. Table 3.4 lists
the thermal resistance for packages currently in production.

3-9
 SECTION B
16-BIT PROCESSORS

4.0 INTERFACING TO THE 4.2 8086 AND Z8000

8086/80186 PERIPHERALS
28000 peripherals may be interfaced to the 8086 in many
4.1 8086 (ALSO CALLED iAPX 86) ways. One thing distinguishes the Z80xx peripherals from
OVERVIEW others is~at they require data to be valid prior to the falling
The 8086 is a general purpose 16-bit microprocessor CPU. edge of DS during a write. The way to go about meeting this
The CPU has a 16 bit data bus multiplexed with 16 address requirement is to use a 74LS74 to delay the falling edge of WR
outputs. There are 4 additional address lines (segment ad- and OR RD with WR. By using the asynchronous ready mode
dresses which are multiplexed with STATUS) that increase the of the 8284A and the other half of the 74LS74, one Wait State
memory range to 1 Mbyte. 8086 addresses are specified as is inserted in both the read and write cycles, and thus stretches
bytes. In a 16 bit word, the least significant byte has the lower DS to meet the minimum pulse width requirements. In the ex-
address and the most significant byte has the higher address. amples that follow, one assumes that there are other devices in
This is compatible with 8080, 8085, 280 and PDP11 address- the system that require the use of the Am9519A. In another
ing schemes but differs from the 28000 and 68000 addressing. example, the Am9519A is not needed to interface the peripher-
als interrupt structure. INTA is tied high since the vector will be
The data bus is "asynchronous", i.e., the CPU machine cycle
supplied by the Am9519A. The interrupt service routine can
can be stretched without clock manipulation by inserting Wait
read the peripheral status to determine the cause of the inter-
states between T2 and T3 of a read or write cycle to accom- rupt. The service routine should also clear IP and IUS before
modate slower memory or peripherals. Unlike the 68000, the returning to mainline code. Note, since INTA is tied High, IUS
8086 has separate address space for 1/0 (64 kBytes).
needs not be cleared. If INTA is activated, IUS must also be
The 8086 can operate in MIN. or MAX. mode. Maximum mode cleared.
offloads certain bus control functions to a peripheral device
Many of the design examples in this manual use PAL devices.
and allows the CPU to operate efficiently in a co-processor
PAL devices, in many cases, will be the most cost effective
environment. A brief discussion on both the MIN. and MAX. solution. The SSI examples show what is being accomplished
modes are as follows:
much clearer than by using a PAL device, which is a black box
MIN. mode: 1/0 addressing is defined by a High or the to many. Gates are often left over from one circuit which can be
101M output, and activated by the R D out- used to implement other circuits. Whether to use a PAL device
put for reading from memory, or 1/0 or ac- or do a discreet design is an individualistic choice and is not
tivated by the WR output for writing to always clear-cut. As a general rule, if you can replace four or
memory or 1/0. more packages, use a PAL device.
DMA: The Bus is requested by activating the HOLD input to
the 8086. Bus Grant is confirmed by the HLDA output 4.2.1 8086 TO Z8000 PERIPHERALS
from the 8086. WITHOUT INTERRUPTS
MAX. mode: 1/0 operation is controlled by two outputs This interface is designed to work with both the 5 MHz and 8
(8086 plus from the 8288. MHz 8086 (Figure 4-2.1a). It is also compatible with the iAPX
8288) 10RC: active during Read from 1/0 186. The 5 MHz CPU should use 4 MHz peripherals and the 8
10WC : active during Write to 1/0 MHz should use 6 MHz peripherals. A timing diagram for this
M RDC: active during Read from memory interface is shown in Figure '4-2.1 b.
MWTC: active during Write to memory Chip Select (CS) is latched on the falling edge of ALE in the
DMA: The Bus is requested and Bus Grant is acknowledged 28000 peripherals. Alternate address decoding schemes may
on the same pin (RQ/GTO OR RQ/GT1) through a be used. Care must be taken to meet the CS setup time with
pulsed handshake. respect to the rising edge of AS (falling edge of ALE). Reset is
accomplished on the 280xx peripherals by asserting AS and
INTERRUPTS IN MIN. AND MAX. MODES: DS simultaneously. This is accomplished by the two NOR
Interrupt is requested by activating the INTR or NMI inputs to gates shown. Reset may be done by software, thus eliminating
the 8086. the extra gates. The SCC and CIO will always recognize a
software reset, so a hardware reset needs not be imple-
Interrupt is acknowledged by the INTA pin on a MIN. mode mented.
8086 or by the INTA pin on the 8288 in MAX. mode.
Note: There is no RD or 10RC during the interrupt-
acknowledge sequence.

4-1
 +5V

74lS04 L INTA
DT/R R/ii
",..

CS
M/iO G2A 0
A15 GI 0
AI4 G28 0
AI3 C 74lS138 0
AI2 B P
Al1 A iD
P
AD,
vt ~ AD,

Am8086
ADO
~ .,.,- ADO AmZ80XX.
ALE
AS
AD
n ~
PRE 14lS02
r- D a ~ os
74lS74
~
rt>
74lS04
CP
ClR
Q

..... Y
WR
RESET
....
I
ClK ClK RESET

READY READY
RDY I t"-
OUT
PClK ClK
.....v RES
~-v"
8284A AEii; t--

a
ASYNC t--
~ CSYNC r--
FIC t--
T ... 7'
~ 02188A 13
Figure 4-2.1a

~ ALE \

~
Tl T3 Tw

1
'w'R

DS

READY /
02188A-14
Figure 4-2.1 b

4-2
A 74LS74 is used to delay the falling edgeofWR; RD is ORed 4.2.2 8086 TO Z8000 PERIPHERALS
with WR by the flip-flop which takes the advantage of the
preset overriding clear. By using the asynchronous ready
WITH INTERRUPTS
mode of the 8284A, one Wait State is inserted in both the read Z8000 peripherals maybe interfaced to the 8086 with other
and write cycles. This stretches DS to meet the minimum pulse devices in the system. In the example given here (Figure 4-
width requirements. 2.2), it is assumed that other devices in the system require the

When programming this part, it is important not to violate the

Am9519A Interrupt Controller. The zaoxx peripheral gener-
ates an interrupt (INT) and since INTA is tied high the vector
recovery time when two successive I/O operations are to be will be supplied by the Am9519A. The interrupt service routine
performed. Intervening instruction fetches will usually be suffi-
can read the peripheral status to determine the cause of the
cient; however, NOP's may need to be inserted with faster interrupt. INT is cleared with software.
processors. Block I/O instructions should also be avoided.
Consult individual data sheets for the recovery time on each FF1 and the NOR gates delay the falling edge of DS and
part. The SCC has an unusually long recovery time of 6 supply hardware reset as discussed in Chapter 4.2.1. The
PCLKS which is 13 CPU clocks. This is the simplest level of hardware to insert one Wait state is not shown. The second
interface, as the interrupts were not used. Note that INTACK conversion necessary is to make the two CPU Interrupt Ac-
must be tied high when not used. knowledge pulses appear as one INTA pulse to the peripheral.
This is done by FF2 in this example. Although this design was
for 8 Mhz, it also works at 5 Mhz.

DT/R R/'W
-
INTR +5V INTA
......
...., .... CS
-
MIlD G2A ......
...., CS GINT -
ALE
..
G 1---1\ 74LS ~ C/i) AM9519A
IREQ I - - INT

AD15
A I 74LS
~ 373
hi 138 RD 'WR
L; ;:=..
INTA

~I
AD8 V
8086 ....
8 MHz A -: G74LS t-.
AMZ80XX

l\r
r 373
V
.... 7- t-
AD7
V ADO
INTA
RD
D fR Q
10-
V LD\)
PR
FF2
<J-
~~ ...... AS

CLK-- t o - CP
CP FFl QI-~
'/ ~» ... -DS
'WR
t-r>~
02188A·15
Figure 4-2.2

4-3
4.2.3 THE 8086 AND AmZ8530 must be inserted. This design is the same when interfacing to
INTERFACE the 186. It requires no additional Wait States. Diagrams in
Figure 4-2.3b show the connections for 74LS74 in both 5 MHz
Most common systems demultiplex address and data. The
and 8 MHz operations of the 8086. Figure 4-2.3c is an alternate
AmZ85XX Family of peripherals was developed to be compati- implementation which can be used in place of the logic in the
ble with these systems. These devices are identical to the dotted area in Figure 4-2.3a.
Z8000 peripherals as far as functionality, but the bus interface
has been changed. Note that the falling edge of W R must be delayed to meet data
setup time requirements. A Wait State must be inserted (not
Interface between the 8086 and the AmZ8530 peripheral shown) to meet pulse width requirements during a write. See
device shows how to take advantage of the AmZ85XX interrupt the Z80XX interface for discussion of recovery time.
structure. INTA CK is generated by the 8086's firstl NTA pulse.
This allows about 800 nsec for the interrupt daisy-chain to The Am29841 is a high speed 1O-bit latch with high drive capa-
settle. The second INTA pulse is then gated to the RD pin bility. Other latches may be used instead. Most designers latch
which places the vector on the bus. At 8 MHz, two Wait States BHE even though S7 is the same, the few extra bits become
quite useful when trying to keep parts count down.

illiG
I

AD..
AD 10
A.

...
_I ~ --
-" r
A.-A"
j,

r
~".
~".
r--v
,-0--0
r--"
~
~

V
.1
-v

LI liE~ ~~
ALE fi
L LE

AD,
ADO
A.

...
j,

I'
Anl2I141 "O-A. , j.,

...
l Die
O£~
..1- D,
1011 D.
5MH1 AmZIS30
r
7.~ ~. ~
1
INTR
7j...,_ "'I
,- - -
I
- - - - - - ..,, iiii

RESET
... ,
I
I
I I
PRE

,,
I
I '-- D Q INTACK
RESET
I
FRDM.Z14A
7.LS7.
I I
, [~r-
I
7US02 I

-~
I
iNiA
- - - - 'J...-
-
L..
iiii iiii
7:-_
r-D Q

7US7.
fUl- r- ep
ClR
ii iNR

WR ...to.
..... J

02188A-16
Figure 4-2.38

4-4
 _125n8_

~~~~ I
\
INTA ______ ..JI \
L_
186
\ 8 MHz~325

INTA, \~ ________ 8_X_'2_5_~_,_ooo

__ 8MHz
ns_ _ _ _ _ _ _ _ _ _ _ _ 8086
_ _ _ _ _ _ _ _ _-J
I
\ 6.200

~--------------~
= 12oon9 5MHz B086
I
RESET - - - - - - - - , RESET

PRE PRE
o a 0 a INTA2
INTA --i::><>-,-t-t CP INTA CP Q
74LS74

8MHz8086 5MHz80B6
Figure A Figure B

Figure 4-2.3b 02188A-17

----
RESET
D Q
2 INTACK

CP 1i CP
CLR 1 CLR
INTA

RD

INTA

Q1

----
Q =INTACK
2
RD
02188A·18
Figure 4-2.3c

4-5
The sample assembly initialization routine, Figure 4-2.3d, for Channel B were for testing only, and are not intended as
takes into account the READIWRITE recovery time and has realistic examples. Also, Figure 4-2.3e shows a sample in-
been tested in an 8 MHz system. The interrupt service routines itialization sequence written in "C".

AMC AMDOS 8/8 64K, Version 2.00 - 9/26/80

type int8530.a86
THIS ROUTINE WRITTEN FOR THE 8086
INITIALIZES THE 8530 SCC FOR ASYNCHRONOUS
OPERATION AT 9600 BAUD.
REGISTER USAGE
AX INPUT AND OUTPUT DATA
BX COUNTER
DX ADDRESS OF PORT
BP POINTER TO MEMORY
CMD EQU OF902H ;COMMAND/STATUS PORT
DATA EQU OF900H ~DATA PORT
TAB EQU OFFSET TABLE
ET EQU OFFSET ETB
ORG OlOOH
START: MOV DX,CMD ~GET ADDRESS OF CMD PORT
IN AL,DX ~READ STATUS TO SET STATE
MOV BX,ET-TAB ~GET TABLE LENGTH
MOV BP,TAB ~POINT TO TABLE
RPT: MOV AL,[BP] ~GET DATA FROM TABLE
OUT DX,AL ~OUTPUT ADDRESS OF REGISTER
INC BP ~INCREMENT TABLE POINTER
MOV AL, [BP] ~GET DATA
OUT DX,AL ~OUTPUT DATA TO REGISTER
INC BP ~INCREMENT TABLE POINTER
DEC BX ~COUNT-l
JZ RPT ~REPEAT IF NOT DONE
~PROGRAM CONTINUES AS DESIRED

TABLE DB 009H ;ADDRESS WR9

DB OCOH ~RESET COMMAND
DB 003H ~ADDRESS WR3
DB 041H ~# OF BITS ETC.
DB 004H ~ADDRESS WR4
DB 04CH ~DATA
DB 005H ~ADDRESS WR5
DB 028H ~BITS/CHAR AND TXEN
DB OOBH ~ ADDRESS WRll
DB 056H ~SELECT BAUD GEN
DB OOCH ~ADDRESS WR12
DB OOCH ~UPPER TC
DB OODH ~ADDRESS WR13
DB OOOH ~LOWER TC
DB OOEH ~ADDRESS WR14
DB 007H ~SET DTR AND ENABLE BAUD GEN
ETB:
END

Figure 4-2.3d

4-6
/***************************************************************************/
'* Initializing the ArnZ8530 asynchronuously .. /
, (using pointer referring to me~ory map I/O device) */
1***************************************************** **********************/

#include "stdio.h"
#define spaddress Ox22F85 /* status port address */
#define dpaddress Ox22F87 /* dataport address */
#define rxbit 2 /* receive ready bit */
#define txbit 1 /* transmit ready bit */
#define tablesize 16

main ()
(

unsigned char table[tablesize];

unsigned long *ptspa, *ptdpa;
unsigned char value;
int i;

/* data table for initialization */

table[O]=Ox9; /* address IVR9 */

table[l ]=OxCO; /* hardware reset SCC */
table[2]=Ox3; /* address WR3 */
table[3]=Ox41; /* set # of bits etc. */
lble[4]=Ox4; /* address ,'1R4 */
.able [5 ]=Ox4C; /* misc mode */
cable[6]=Ox5; /* address HR5 */
table[7]=Ox28 ; /* bits/char and TXEN */
table[8]=OxB; /* address liRll */
table[9]=Ox56; /* select baud generator */
table[lO]=Oxc; /* address WR12 */
table[ II ]=OxC; /* upper TC */
tabl e[l2] =OxD; /* address \'l'R13 */
table[l3]=0; /* lower TC */
table[l4]=OxE; /* address WR14 */
table[15]=Ox7; /* set DTR/REQ enable baud generator */

/* output data from table to perform initialization */

ptspa=spaddress; /* pointer to status port address */
ptdpa=dpaddress; /* pointer to data port address */
value=*ptspa; /* read status to set the set state machine */
for (i=O; i<tablesize; i++) /* perform initialization */
*ptspa=table[i];

/* receive and echo character routine */

for ( ; )
( while «(*ptspa) & rxbit) 0) ; /* wait for receive ready bit */
value=*ptdpa; /* receive character */
while « (*ptspa) & txbit) 0) ; /* wait for transmit ready bit */
*ptdpa=value; /* transmit character */

Figure 4-2.3e

4-7
4.3 THE 8086 AND AMD The 8086 to LANCE interface requires a different Bus Request
handshake, depending on whether the 8086 is configured in
PROPRIETARY PERIPHERALS MAX. or MIN. mode. The 8086 has a bidirectional signal for
both Bus Request and Bus Grant (RQ/GT). Both Bus Request
4.3.1 8086 And Am7990 LANCE (RQ), and Bus Grant (GT) tolfrom 8086 are one CPU clock
wide, and are synchronous to the CPU clock. Figure 4-3.1 a
The LANCE. Am7990, has been designed to be interfaced
easily with the popular 16-bit microprocessors (8086/80186, shows a PAL design for the conversions in MAX. mode. This
68000, Z8000', LSI-11"). Most of the interface logic is em- PAL device is utilized to include other external logic require-
bedded inside the chip and is program selectable. ments for interfacing the LANCE to 8086. The interface dia-
gram is similar to the one for the 80186 to LANCE interface
Although the LANCE itself has a multiplexed bus, it can easily (Chapter 4.3.2) except for the changes made in programming
be interfaced to demultiplexed buses with a minimal amount of the PAL device. Interface timing diagram is shown in Figure
effort. The following designs assume that the processor and 4-3.1b.
the LANCE reside on the same board. Address buffers and Figure 4-3.1c shows a block diagram on the 8086 to Am7990
data transceivers are set up to be shared between the proces- interface, in MIN. mode. The interface also employs a PAL
sor and the LANCE. All of these designs use PALs to reduce device to minimize parts count. The PAL equations are given in
the parts count. Figure 4-3.1 d.

8086 CI,K

-i>o-l
ClK

AmPAL16R4
86/90.PAL
(lOll) iiOJG'f GT HOLD HOLD (LANCE)

~ (OC)
AI iiL5i HlDA (LANCE)

AHPAlt6U RASOUL OSKOUY

PATOOt HARCH 20, t98~

8086 RQ/GT CONVERSION TO LANCE HOlD/HlDA

ADVANCED MICRO DEVICES

CLIC MC HOLD aT NC tiC MC HC NC GND

HC MC NC ii!Dl D2 R2 iT NC Me VCC

Rl :. HOLD
D2 :a r;
R2 :a Rl102 + rrlD2
HLDA .. GT1 ii2 • HLDAlDi

This PAL converts the request and grant (RQ/GT) of 8086,

when configured in maximum mode. to the LANCE Am7990
HOLO/HLOA. 80th request (input to 8086) anet grant (output
from 8086) are one clock wide and ar. synchronous to the
CPU clock.

02188A-19

Figure 4-3.1a 8086 RGI GT, Am7990 HOLOI HLDAConverslon PAL device

4-8
 elK
(INPUT)

HOLD
(INPUT)

Ai (OUTPUT)

52 (OUTPUT)

R2 (OUTPUT)

RQGT (INPUT)

HlDA (OUTPUT)

02188A-20
Figure 4-3.1b AmPAL16R4, 8086 (Max. Mode) LANCE Interface Timing Diagram

~A 0-,5 ft Vcc Vee

LII£ t liLA 16-1'

129843~h 1L£ 2:a43 1 129863 ;~ -

1ir 1l" "'1t-
I II ~J,.

l~ LdL~
----1
-.:!.~
To Sy.w..
ve ,. 16-1, o\D 0-15 ~ NJ D 0-7

1
-
iii: r-
LHIN %NTR !NT
cc L-iollll
Iiffii iNl'A
iii! 8259A
JRD
H -
iNfii
IIo\U
TaJ(

HLD.\
HIIlD
--f>
>- ~ jijj

1
r IIAUl

iUA
<J- KiD 7990
8086
L-- L£ f
HI.IIf\
jijj
iii!
jijj PAL16L8 R
iii! 85/90.PAL _
~cc
DEN lIEN
M. AS
j\L£ ALE iiiiS iiiiS
DTIR ,--
DTR REIID REIID
RD CPURDY
8284 iiUOiiY iiUOiiY
RESET
~r~~ L:

Lc
I
I
r FROM SYSTEM

REiff
02188A-21
Figure 4-3.1 c

4-9
PAL16L8 KHUYNH NGUYEN
PAT
FILE: 86-90-A.PAL AUG '85
8086 MINIMUM MODE TO LANCE INTERFACE
AMD

ALE /AS DTR NC NC DEN NC /READY HLDA GND

NC /DPURDY READ /R /T /DAS /WR /RD LE VCC
/LE = /ALE + /AS
/CPURDY = /READY

; CPU (86) IS BUS MASTER

IF (/HLDA) DAS = RD + WR
IF (/HLDA) /READ = DTR
IF (/HLDA) T = DTR
IF (/HLDA) R = /DTR * DEN
; LANCE IS BUS MASTER

IF (HLDA) RD = READ * DAB

IF (HLDA) WR = /READ * DAS

Figure 4-3.1 d

4-10
4.3.2 80186 TO Am7990 LANCE is because the LANCE tristates ALE, the 186 does not. The
INTERFACE INTR, READY, and HOLD signals from the LANCE are open
drain and should be pulled up. The BMl signal from the
Similar to the 8086 to Am7990, this interface uses a PAL
LANCE or BHE from the 186 along with AO can be used to
device design to reduce the parts count. Figure 4-3.2a shows
decode the data transfer type (Word/Byte). The external ad-
the interface block diagram. 80186/LANCE address and data
dress buffers and data transceivers are enabled by the LANCE
buses can be connected directly together since they both have
and the 186. The buffers and transceivers are enabled by
multiplexed buses. It seems natural to program the LANCE for
whichever device is the master. The user should program the
ALE output. However, the PAL device equations or indeed a
BCON, BSWP to 0, and ACON to 1 in CSR3.
discrete design is easier if AS (CSR3, ACON=l) is used. This

.(>. ADDRESS
BUS
.t. ~
DATA
BUS

. .., Vcc
"'7
Am29841
LE
Am29841
LE
I ~
~; Am29863J

AD15-ADo
.Ii
~
i it -"\
..
ADR

DAL 15-DALo

A19-A16 A19-A16

i5AiJ
DALO
fVCC
LE IT IR
ALE ALE lAS AS
DT/R DTR IDAS DAS
Fffi IRD PAL16L8 READ READ
186/90.PAL
WR
DEN
IWR
DEN
fVCC
ARDY ARDY IREADY FiEA5Y
HLDA ICS LANCE
80186
j Am7990
HLDA
.... iiL5A
........
PCSo CS
SRDY

INTO

BHE
rv ~
fVCC READY -
FROM SYSTEM
iN'fR

BM1

A TVCC
HOLD Hoi])

vccI
RES iiESE'i'

~0-1
021BBA-22
Figure 4-3.2a 80186 to Am7990 Interface

4-11
4.3.3 THE 8086 AND Am8052 CRTC SLAVE READS AND WRITES
INTERFACE #21 C S set-up time to the trailing edge of AS (minimum
The 16-bit multiplexed addressldata bus of the 8086 is directly o ns). The 8086-2 provides a set-up time of 28 ns
connected to the multiplexed address/data lines of the Am8052 of ADo-15 before the trailing edge of ALE. Let us
(Figure 4-3.3a). The upper address (7 bit for segmented mode assume 0 ns of minimum propagation delay since
or 8 bit for linear mode) is strobed out on the lower half of the neither the inverter nor the driver specifies one.
bus (ADo_?) and is stored in a register (Am29823). The The maximum propagation delay allowed for the
Am8052 may be programmed for segmented or linear mode decoder is, therefore, 28 ns (68 ns - 40 ns). The
depending on whether address roll-over is desired. The regis- decode time for the Am29806/809 decoders is
13 ns.
ter output is enabled (DE =Low) when the Am8052 is bus
master. Clocking is enabled (EN=Low) when RlW is Low #22 CS hold time after the trailing edge of AS
while the Am8052 is bus master (upper address update cycle). (minimum 25 ns). The 8086-2 provides a minimum
The trailing edge of Address Strobe clocks the register. address hold time of 33 ns.
RD and WR from the 8086.are logically ORed to generate DS. #23 cio set-up time before the trailing edge of AS
ALE is inverted and connected to AS of the Am8052. DT/A" is (minimum 0 ns). The 8086-2 provides an address
also inverted to form RlW. All three signals are passed through set-up time of 28 ns.
a three-state buffer which is enabled when the 8086 is bus #24 clo hold time after the trailing edge of AS
master. MemoryllO (MilO) is pulled High when the Am8052 is (minimum 25 ns). The 8086-2 provides a minimum
bus master since the Am8052 only addresses memory. address hold time of 33 ns.

BUS CLOCK #25 Delay from CS to DS (minimum 30 ns). The worst

case (shortest delay) can be calculated as:
The Bus Master timing is synchronized to the bus clock (CLK
1) of the Am8052. In order to get a similar and synchronous (TCLCH - TCHLL) + TCLRL + (28 ns - 13 ns) =
bus timing when the 8086 or the Am8052 is driving the bus, the (68 ns - 55 ns) + 10 ns + (28 ns - 13 ns) = 37 ns.
Am8052 bus clock can be connected to the 8086 bus clock. #26 Access time (maximum 150 ns). The 8086-2 ex-
However, in proportional spacing applications, the video timing pects an 110 access time no longer than:
must be derived from the bus clock and therefore the bus clock
2 • TCLCL - TCLRL - TDVCL =
must be synchronized to the character clock (CLK 2).
2· 125 ns - 100 ns - 20 ns = 130 ns.
For these applications the Am8152A153A provides the
This means that one Wait State must be inserted.
synchronized clocks (CLK1,CLK2) with the right timing and DC
specification. #27 Data hold time (minimum 10 ns). The 8086-2 re-
quires a max data hold time of 0 ns, i.e. no hold
In non-proportional spacing applications, the Am8052 can
time.
operate with the 8086 bus clock if the duty cycle is adjusted. In
this case, the Am8152A153A cannot be used as the clock #28+ RlW DS. Since DTi"R is connected to the R/W
driver, and a separate clock driver needs to be provided. This 29 input of the CRTC, this timing is not guaranteed by
clock driver must provide a clock satisfying the special clock design.
input specification (MOS specification) such as clock High and #32 Data hold time during slave writes (minimum 20
Low width and voltage, and capable of driving the input capaci- ns). The 8086-2 provides at least 38 ns.
tance of the Am9516A. Most CMOS drivers or a discrete clock
#33 Data set-up time in slave writes (minimum 90 ns).
driver shown in Figure 4-3.3b satisfies these specifications.
The 8086-2 provides more than one clock period
This deSign must be changed for different frequencies. Figure
(125 ns) data set-up time.
4-3.3c shows circuitry which adjusts the duty cycle for the
Am8052. The required delay time needs to be adjusted for the #34 The Am8052 requires a minimum Data Strobe
chosen bus clock frequency. pulse width of 100 ns. The 8086-2 provides
TWLWH = 2 • TCLCL - 40 ns = 210 ns.
DETAILED TIMING ANALYSIS #35 Recovery time (minimum 330 ns). The 8086-2 pro-
The following timing analysis is based on an 8-MHz 8086-2 vides more than 3 clock periods = 375 ns.
and an 8-MHz Am8052. At this frequency the minimum clock
High (TCHCL) and Low (TCLCH) times for the 8086-2 become
43 ns and 68 ns, respectively. Some of the subsequent calcula-
tions are based on these values for TCHCL and TCLCH. Num-
bers beside each timing analysis are data sheet parameter
numbers.

4-12
 0 MilO AS DS Riw
Vee

A19 - 16

IAm298~ ~
D OE EN CP I
AD 15 - o
k; lr ~
/
AD 15 - o

L~
MilO
0 -V CHIP
SELECT
DECODER

Am29809
AD,

'---- ciD
CS

8086-2 '---< Am8052

-
ALE AS

RD ~ t> DS
WR 74lS244
DTiFf Riw
EN

HlDA BAI

HOLD BRO

I ClK I
ClK
I lOGIC I ClK

8284

02188A-23

Figure 4-3.3a 8086-Am8052 Interface

4-13
 120
r-~~--~------~-----o+5V

22pF 470 22
CLK1/CLK2
TTL TO Am8052
COMPATIBLE (VOL < 0.3V)
CLOCK (VOH > 4.0V)
OSCILLA-
22pF 22
TOR

02188A-24

Figure 4-3.3b

JUlJL
j ~ SUl.JL
CLK
CLK •

DELAY-LINE

CLK JUlJL
1 c:h--n SUl.JL CLK·

02188A-25

Figure 4-3.3c Duty Cycle Adjustment for the Am8052

4-14
4.3.4 iAPX186 TO AmZ8068 DATA At lower CPU clock rates the timing is less critical because the
specified time relationship between clock and data strobe
CIPHERING PROCESSOR INTERFACE
becomes wider (timing parameter 45 of the data sheet).
The iAPX186 can operate in two basic modes Minimum Mode
or Maximum Mode. The maximum clock for operating without a Wait State can be
calculated like this: The RD width is specified as 2· TClCl-
In Maximum Mode the 8288 Bus Controller provides command 50 ns for the iAPXI86. The WR width is2' TClCl- 40 ns. The
and control timing. smaller R D width is used for the calculation. At an 8-MHz
In Minimum Mode the bus timing of the iAPX186 is slightly clock, the 186 generates an R D signal 200 ns wide. The
different from the 8086 bus timing. Figure 4-3.4a shows the AmZ8068 requires a minimum data strobe width of 200 ns for a
interface logic. The maximum clock rate for the DCP is 4 MHz, Status Register access. The system can, therefore, operate up
resulting in a maximum CPU clock rate of 8 MHz. No Wait to this clock rate without a Wait State.
States are required. The Clock Synchronizer used is shown in Figure 4-3.4a. Figure
An AmZ8068 must be used in this application because of the 4-3.4b illustrates how this logic synchronizes the data strobe to
wider range in delay time from clock to the read or write control the clock. DCP ClK(I) and DCP ClK(2) show the possible
signal delay with respect to the clock. This parameter is speci- phases of the CPU clock before synchronization. At the end of
fied for the iAPX186 as 10 to 55 ns. The AmZ8068 requires a cycle Tl the clock is synchronized. No Wait State is allowed
delay of 0 to 50 ns at 4 MHz, the Am9568 0 to 30 ns at 4 MHz. when accessing the DCP. (An odd number of Wait States
Because of two delays in the clock path (Inverter and D-Flip- would synchronize the data strobe to the wrong edge of the
Flop) and only one delay in the control signal path (AND gate), clock.)
the timing tolerance of these signals at the DCP is decreased See the Am9518, Am9568, AmZ8068 DCP Manua/for more on
to 0 to 45 ns. this part.

~ ADDR/DATAo_7
ADo-AOr
~
, M~-M~
l\r----------------------------------•..,ll
J5CS
r-------------------------------------~~
RD
WR
-
~--------------~I~/~r-----------------~~
DT/R ......------------1 >c>---------t MR/W

ALE
......-----.---------~ ~~----------------~~
ArnZ8068
iAPX186

elK OUT 1 - - - -.....----1

02188A-26

Figure 4-3.4a iAPXI86-DCP Interface (Minimum Mode)

4-15
 ClKOUT

ALE ~~__________________________________

Q1 ~~______________________________

DCP ClK(1)'

DCP ClK(2)'

RD/WR

'DCP ClK (1) AND (2) SHOW TWO PHASES OF DCP ClK

02188A-27

Figure 4_3_4b DCP ClK Synchronization Timing (No Wait States)

4,3,5 THE 8086 AND Am9513A This interface is straightforward. The diagram in Figure 4-3.5
shows that data is transmitted directly between the processor
SYSTEM TIMING CONTROLLER and the Am9513A. The 25LS373's latch the address decoded
INTERFACE by the 74LS138.

r-
Va Y15

G Am25LS373
D. 015
OE ~

r- G
Yo Y7
Am25LS373
OE

20pF rrloh-l
~ ~
20PF

74LS138

ALE 1--'~---4
C/O

IO/Mf-----l 1 - - - - - 1 G, Am95131\ x, I--

Yo P-- CS x,I---....I
G2A G 28
5 L-_
1---"1
OUT, .•

Am8086 W 5/L-_
1_--"1
GATE, ••
A ~ " 5 L-_
SOURCE, .• 1---"1
ADo-AD , • Ky ____________________'/ DBo.1•

RD ~ V RD
FOUTI----
~ ~

02188A-28

Figure 4-3.5

4-16
4.3.6 THE 8086 AND Am9516 Both interface examples accomplish two major functions. First,
UNIVERSAL DMA CONTROLLER when the Am9516 is bus master, it converts RD and WR into
INTERFACE Rfii and DS, and vice versa when the Am9516 is not the bus
master. Secondly the buffer controls, TBEN and REBN, are
generated from DEN and DT/R.
Am9516 IN MIN. MODE
Figure 4-3.6a illustrates the interface of the Am9516 to the The two examples show different types of latches and
8086 in the MIN. mode configuration. Figure 4-3.6c illustrates transceivers and there are many more to choose from. The
the interface in MAX. mode. The interfaces could be accom- designer selects those that best meet system requirements
plished by using rather complex implementation of standard while trying to minimize the number of different parts that must
SSI/MSllogics. Examples here replace the logic portion with a be stocked.
PAL device. The MIN. Mode uses the PAL device 16L8. This is
a good example of "GARBAGE COLLECTION". It reduces the
amount of real estate, interconnections, parts, and part types.

HOLD BREQ
HLDA BACK
~~

8086 Am9516
HLDA
DT/A DTI ITBEN TliER
lIDI IDEN IRBEN RBEJiI
ALE ALEP ALE 0 ALE

AmPAL16L8 IS~ -
ADo BIO ...oL B/W
RD IRD IDS ~ I>S
WR IWR IRW ~ R/W
ALE

MIlO M/iO CS

~
It I

~ ~
I G
Am25LS373
LATCH
yr"I Am2949
A TRANSCEIVER
I Am25LS138
DECODER
~

MIlO RnWA

02188A-29

Figure 4-3.6a The Am9516 UDC to 8086 CPU Interface (Minimum Mode)

4-17
AmPAL16L8 PALASM FILE

PAL16L8
PAT001
Am9516 to 8086 min mode interface chip
Advanced Micro Devices

NC ALED ALEP HLDA BW ADO DT /DEN /SEL GND

NC /RBEN /RD ALE AO /RW /DS /WR /TBEN VCC

IF (/HLDA) DS = RD + WR
IF (/HLDA) RW = DT
IF (/HLDA) TBEN = /DT * /SEL * DEN
IF (/HLDA) RBEN = DT * /SEL * DEN
IF (HLDA) RD = /RW * DS
IF (HLDA) WR = RW * DS
ALE = /ALEP * /ALED
AO = /ADO * /BW * HLDA * ALED +
ADO * BW * HLDA * ALED +
/ADO * /HLDA * ALEP +
AO * /ALEP + AO * /ALED
DESCRIPTION

THIS PAL CONVERTS THE CONTROL SIGNALS TO INTERFACE THE 8086 IN

MIN MODE TO THE Am9516 DMA CONTROLLER. ANOTHER EXAMPLE SHOWS HOW
THIS IS DONE IN MAX MODE.

Figure 4-3.6b

device to the MAX. Mode protocol for bus exchange. The

Am9516IN MAX. MODE
74LS03s are used to aid in this function. The timing waveform
This MAX. mode interface between the 8086 and Am9516
illustrates what happens in detail. The basic philosophy is that
(Figure 4-3.6c) also uses a PAL device to reduce component
a rising edge on the HOLD input generates a pulse that is one
count.
clock wide. The CPU samples this pulse and, in response,
The example makes several assumptions which result in a issues a one-clock-wide pulse. The 16R4 uses this response
slightly more complex design than absolutely necessary. The pulse to generate HLDA. When the Am9516 has completed the
8086 is assumed to be in MAX. Mode, and the design has to be necessary transfer, HOLD transitions High to Low. This gener-
compatible with a Multibus or similar interface; the 16R4 and ates another pulse to the CPU Signalling that the Am9516 is
8288 could be eliminated if this is not the case. done and that the CPU may continue.
The 16R6 (Figure 4-3.6c) is a PAL device that performs a The second function of the 16R4 is the conversion of Rm, DS
function similar to the 8288, that is, it converts the processor's and MilO into the Multibus compatible signals IMRDC,
status signals and clock into control signals. In this case, the IMWTC, IIORC, and IIOWC, when HLDA is High. It is possible
signals are, Rm, and Data Strobe (DS), Interrupt Acknowl- to collapse the 74LS03s into the PAL device, thus reducing the
edge (INTA) and Peripheral Acknowledge (PACK). This PAL external logic required to only one open collector inverter. The
device, Figure 4-3.6e, basically generates ZBUS Signals for disadvantage, however, is that it adds two additional clocks for
Zilog peripherals. In the example, it connects to the Am9516 the bus exchange overhead, one during acquisition of the bus
(UDC). The DMA Controller is very similar to the AmZ8016 and one on bus release. For block transfers, this is not signifi-
except its bus interface has been modified to interface to non- cant but it may be undesirable when performing single trans-
multiplexed buses. This was changed from the previous design fers, or short burst, or when in Demand Mode. To eliminate the
using a 16R8 to eliminate problems due to skew between OSC 74LS03, change the equation for R2 to
and CLK.
IRl * ID2 + Rl * D2,
The 16R4, Figure 4-3.6d, has two functions. The first is con-
and then drive the I[RQ/Gn line with a 74LS05 from the R2
necting the MIN. Mode protocol of the Am9516 or similar
output.

4-18
 C[j(
ClOCK

l
ClK
74LS03 1
ClK
10. HOLD BREQ

~ -
HlDA BACK
AmPAL16R4
es
IR,
IiQ/ilf
-~ ----.
--
IR. P/D
8066 IRQGT
CPU
t
H

CEN
lOB
8288 ~
10E elK

'--+ ClK liEN i+-'I-HlDA Am9516

!Ii !Ii MJml: IMRDC IRW R/W UDC
S1 S1 ~ IMWTC IDS tiS
SO SO RHfC /lORC IMIO M/m
RlWC IIOWC
~
l~
l IlOCK 10E ~
IRDY
1m{ ClK IRW

~ IS,
150 IDS
IIACK ~
IS. lAS r-+
AmPAL16R6

02188A·30
Figure 4-3.6c

AmPALl6R4 PALASM File

B> Type Am95l6 PAL
PALl6R4

8086 to Am95l6 interface

Advanced Micro Devices
CLK /RQGT HOLD NC NC NC /RW /DS MIO GND
fOE /MWTC /MRDC HLDA /D2 /R2 /Rl /IOWC /IORC VCC
IF (HLDA) IORC /MIO * DS * /RW
IF (HLDA) IOWC /MIO * DS * RW
IF (HLDA) MRDC MIO * DS * /RW
IF (HLDA) MWTC MIO * DS * RW
Rl := HOLD

R2 := /Rl
D2 := Rl

/HLDA := /Rl + /D2 * /HLDA +

/RQGT * /HLDA
DESCRIPTION
THIS DEVICE CONVERTS THE MIN MODE SIGNALS HOLD AND HLDA TO THE
MAX MODE /RQGT PROTOCOL_ ADDITIONALLY IT GENERATES THE 8288
EQUIVALENT CONTROL OUTPUTS /MRDC, /MWTC, /IORC, AND /IOWC_ THIS
PAL WAS USED TO CONNECT THE Am95l6 TO THE 8086 IN MAX MODE_
Figure 4-3.6d

4-19
AmPAL16R6 PAL DESIGN SPECIFICATION
PAT 005 BY JOE BRCICH 5/10/83
8086 TO 85XX PERIPHERAL INTERFACE & JAMES WILLIAMSON 7/21/83
ADVANCED MICRO DEVICES

CLOCK RESET CLK ISO /Sl /S2 /LOCK NC NC GND

fOE /AS /P1 /RW /DS /po /IACK /RDY CLKD VCC
PO :- /RESET * SO * /PO * /P1 +
/RESET * Sl * /PO * /P1 +
/RESET * S2 * /po * /P1 +
/RESET * SO * P1 +
/RESET * Sl * P1 +
/RESET * S2 * P1
P1 := /RESET * PO * /P1 +
/RESET * P1 * SO +
/RESET * P1 * Sl +
/RESET * P1 * S2
DS := /IACK * /PO * P1 * SO * /Sl * S2 +
/IACK * /po * P1 * ISO * Sl * S2 +
lACK * SO * Sl * S2 * PO * /P1 * LOCK +
DS * SO * Sl * S2
DS * SO * /Sl * S2
DS * ISO * Sl * S2

RW := SO * /Sl * S2
lACK :- /RESET * SO * Sl * S2 * /PO * /P1 * /LOCK
/RESET * lACK * SO * Sl * S2 * PO * /P1 * /LOCK
/RESET * lACK * LOCK * /DS
/RESET * lACK * /LOCK * DS * /PO * P1
RDY :- /RESET * SO * /Sl * S2 * PO * P1 +
/RESET * ISO * Sl * S2 * PO * P1 +
/RESET * RDY * SO * /Sl * S2 +
/RESET * RDY * ISO * Sl * S2 +
/RESET * lACK * SO * Sl * S2 * DS +
/RESET * RDY * SO * Sl * S2
/CLKD -CLK

AS = /CLKD * PO * /P1 * /IACK * CLK

DESCRIPTION
THIS PAL TRANSLATES 8086 BUS SIGNALS INTO COMPATIBLE SIGNALS
FOR THE 9516. IT IS ALSO APPLICABLE TO 85XX PERIPHERALS BY
ALTERING /RW AND /DS TO /RD AND /WR. ONE FLIP FLOP IS AVAILABLE
TO GIVE THE NECESSARY DELAY TO THE FALLING EDGE OF /WR. THE DATA
STROBE TIMING FOR A WRITE CYCLE IS DELAYED UNTIL THE FALLING EDGE
OF T2 TO MEET THE REQUIREMENTS OF THE 85XX PARTS. THIS DESIGN
ASSERTS RDY TO DEMAND ONE WAIT STATE FROM. THE 8086. THIS WAIT
STATE IS NOT LONG ENOUGH FOR DESIGNS WHICH USE AN 8 MHz 8086.
THEREFORE, WITH AN 8 MHz CPU, 85XXA PERIPHERALS SHOULD BE USED.
AS AN ALTERNATIVE, THREE WAIT STATES CAN BE USED BY ALTERING THE
RDY EQUATION. THIS PAL ALSO TRANSFORMS THE 8086 TWO CYCLE
INTERRUPT ACKNOWLEDGE INTO A SINGLE CYCLE OF THE TYPE NECESSARY
FOR 85XX PARTS. THIS IS MADE POSSIBLE BY SAMPLING THE LOCK
STATUS, PO, P1, AND lACK SIGNALS.

NOTE; THE CLK SIGNAL MUST BE EXTERNALLY INVERTED.

FIgure 4-3.6e

4-20
4.3.7 80186 TO Am9516 UNIVERSAL This interface accomplishes two major control transformations.
First, it converts R D and W R into RIW and DS when the 80186
DMA CONTROLLER is Bus Master, and vice versa when the Am9516 is Bus Master.
The addition of the Am9516 to an 80186 design is a natural Secondly, the transceiver control signals, TBEN and RBEN,
choice in systems requiring four channels of DMA. Figure 4- are generated from DEN and DT/R. This example shows only
3.7a shows the interface between the 80186 and the Am9516 one possible configuration. Other configurations can be made
with a PAL device. PCS5 is programmed to provide a latched as dictated by system requirements. A PAL device is used here
A1 Signal. to reduce board space. MSI and SSI could also be used.

16MHz
o
~lJ
ARDY D OH WAIT
74LS74
CP

pcs, P/D
pCSo
HOLD BREO
HLDA BACK
Vee Vee

80186 Am9516
DT/II HLDA
DT ITBEN 'I1!EN
\lEIiI IDEN IRBEN I!BER
ALE ALEP ALED ALE
AmPAL16L8 ISEL C!
A4
ADo BW BIW
lID IRD IDS DB
WR IWR IRW R/W
ALE
Si MIll:)

CLKOUT CP 0 CLOCK
AD1,-ADo 74LS74
QQ AD1,-ADo

t CD

{
,

ARDY IIDWR
I G

"
Am25LS373
LATCH
1D

10

.1
MIll:) A4
~;II TRANSCEIVER
Am2949

02188A-31

Figure 4-3.7a

4-21
AmPAL16L8 PALASM File

PAL16L8
PATOOl
Arn9516 to 80186 interface chip
Advanced Micro Devices

NC ALED ALEP HLDA BW ADO DT /DEN /SEL GND

NC /RBEN /RD ALE AO /RW /DS /WR /TBEN VCC

IF (/HLDA') DS = RD + WR
IF (/HLDA) RW = DT
IF (/HLDA) TBEN = /DT * /SEL * DEN
IF (/HLDA) RBEN = DT * /SEL * DEN
IF (HLDA) RD = /RW * DS
IF (HLDA) WR = RW * DS
ALE = /ALEP * /ALED
AO = /ADO * /BW * HLDA * ALED +
ADO * BW * HLDA * ALED +
/ADO * /HLDA * ALEP +
AO * /ALEP +
AO * /ALED

DESCRIPTION

THIS PAL CONVERTS THE CONTROL SIGNALS TO INTERFACE THE 80186 TO

THE Arn9516 DMA CONTROLLER. OTHER EXAMPLES SHOW HOW THIS IS DONE
FOR THE 8086 IN MIN AND MAX MODES.

Figure 4·3.7b

4.3.8 8086/8088 TO (MAS). Similar to the interface discussed above, the clock rate
is limited by the clock Low and High widths and the require-
Am9518/AmZ8068/Am9568 INTERFACE
ments of the DCP The Am9518 needs a minimum clock High
Interfacing the DCP family to 8086 or its 8-bit bus equivalent, width of 150 ns determining a maximum clock rate of 2.3 MHz.
the 8088, is straightforward. In systems with CPU clock rates The minimum clock Low width of 275 ns and the DCP
up to 3 MHz, the Am9568 can be directly interfaced to the CPU speCification of 0 - TWL - 100 ns provides a margin of 275 ns -
(Figures 4-3.8a and 4-3.8b). The clock rate is limited to 3 MHz lIOns - 100 ns = 65 ns.
because of the 33%/66% duty cycle (33% High, 66% Low) of
the CPU clock and to satisfy the minimum clock High time of The AmZ8068 requires a minimum clock High width of 115 ns,
115 ns of the Am9568. The second critical parameter is the resulting in the same maximum clock rate as in interfacing to
relationship between the clock and Data Strobe. The Am9568 the Am9568 (3 MHz). The specification about the synchroniza-
requires a delay of the rising edge of MRD or MWR to the tion of clock and data strobe is less critical in this interface (0 -
falling edge of the clock of 0 - TWL - 85 ns. TWL is the clock TWL - 65 ns) so the margin becomes 32 ns.
Low width. In this interface the minimum clock Low width is 207 An 8086/8088 system with clock rates larger than the rates
ns. This determines a maximum delay of up to 122 ns. The mentioned above requires more sophisticated interface logic.
CPU is specified to have a "Control Active Delay" of IOta 110 The DCP clock must not exceed 4 MHz (3 MHz for the
ns. With a margin of 12 ns, it is obviously impossible to in· Am9518), the Address Strobe width has to be satisfied, and the
crease the system clock by modifying its duty cycle. Data Strobes must be synchronous to the clock. The case in
Figures 4-3.8c and 4-3.8d show a similar interface using the which the DCP clock is divided down by two from the CPU
Am9518 and the AmZ8068. This interface needs additional clock is discussed below.
logic to convert the Read or Write strobes into a ReadlWrite An application where the DCP runs asynchronously from the
(R/W) and a Data Strobe (MDS) and to invert the Address 8086 clock is not discussed here. Ideas can be taken from the
Latch Enable to generate a Master Port Address Strobe chapter on iSBX Bus to Am9568 interface.

4-22
 ~.I
ADDRESS
. i,. 1.
ADa-AD15 i··fI DECODER
-EN
r MCS

~
IORC MRD

Am9568
A CONTROL ~ AIOWC MWR

8086 , , 8288

ALE MALE

ClK ClK
I
I osc
I ClKMAX = 3 MHz (Am9568

02188A-32

Figure 4-3.8a Direct Interface 8086-Am9568 (Maximum Mode)

ADDRE~
DECODER I.
ADa-AD15 iti" . , EN r J.ICS

Am9568
M/iO

RD MRD

8086
WR MWfi

ClK ClK

ALE MALE

I OSC
I ClKMAX = 3 MHz (Am9568)

02188A-33

Figure 4-3.8b Direct Interface 8086-Am9568 (Minimum Mode)

4-23
 ADDRESS
...
ADa-AD15 "" """"",,""
,. DECODER
EN r'- MCS

.4 CONTROL ...
IORC
AIOWG ::::n--. MDS
Arn95181
ArnZ8068
8086 8288
~>'.:: .. " .} DTiR MRiW
~ r

ALE -{) MAS

ClK ClK
T

I osc
I ClKMAX = 2.3 MHz (Am951 8)
ClKMAX = 3 MHz (AmZ8068)

Figure 4-3.8c Direct Interface 8086-Am9518/AmZ8068 (Maximum Mode)

ADDRESS/DATA
.i .1
ADo-AD7 ... :",:,
,.> MPo-MP7

A1DRE~
ADa-AD15
DECODER L MCS
-"C
r EN r
M/iO
t Arn95181
8086 ArnZ8068
AD
WR
I MIlS

DT/R MR/W

ClK ClK

ALE ~ MAS

I OSC
I ClKMAX = 2.3 MHz (Am951 8)
ClKMAX=3 MHz (AmZ8068)

02188A-35

Figure 4-3.8d Direct Interface 8086-Am9518/AmZ8068 (Minimum Mode)

4-24
8086/8088 - Am9518/AmZ8068 (FIGURES Master Port Data Strobe (MDS) is active if either Input/Output
4- 3.8e AND 4-3.8f) Read Control (IORC) or Advanced Input/Output Write Control
The Control/Key Mode input (CIK) is wired Low to select the (AIOWC) are active. The AIOWC has a wider Low width than
Multiplexed Control Mode. In this mode the address to the IOWC (Input/Output Write Control) and so gives a wider mar-
internal registers of the DCP, MP1 and MP2, is multiplexed with gin in interfacing.
the data byte on the eight bidirectional lines of the Master Port In Minimum Mode (Figure 4-3.Se), RD and WR are logical
bus. MP1 and MP2 are latched on the rising edge of MAS ORed to generate MOS. The timing is the same as in Maximum
(Master Port Address Strobe), to select the internal register for Mode.
subsequent data transfer cycles.
MAS is the inverted Address Latch Enable of the SOS6 bus. 8086/8088 - Am9568 (FIGURE 4-3.8a)
The state of MCS (Master Port Chip Select) is aso latched at CPU clpck rates above 4.44 MHz (above 5.S MHz for the
the rising edge of MAS. In the Minimum Mode of the SOS6 AmZS06S) require use of the Am956S instead of the Am951S,
(MN/MX =High) MCS may only go Low during Input/Output because TWA (Master Port Address Strobe width) becomes
cycles (M/IO=Low); therefore, M/IO enables the address critical with increased clock rate, as shown below:
decoder in Minimum Mode. Am951S: TWA = 115 ns
The Read/Write input (MR/W) is connected to Data AmZS06S: TWA = SO ns
Transmit/Receive (DTIR). DTIR satisfies the setup and hold Am956S: TWA = 40 ns
time requirements of MRiW. SOS6/SOSS: TLHLL = 115 ns at 4.44 MHz
SOS6/SOSS: TLHLL = SO ns at 5.S0 MHz
SOS6/SOSS: TLHLL = 4S ns at S.OO MHz

ADDRESS/DATAo_7
ADo-AD15 _______~__~____~~_~/I
A16-A19
\1---- .. ~ MPo-MP7

M/iO
10--------.1 MeS

DT/R ><>------------.>1 MR/W

80861 Am95181
8088 RD
WR I---------J)----------+I MDSAmZ8068
ALE ><:>-----------I~I MAS

-----------, I

I
I
I
elK 1+~~_+...--__1
J:L"~~
_ _ _ ..:.;;; _ _ _ _ _ JI elK

Vcc

02188A-36

Figure 4-3.8e 8086/8088-Am9S18/AmZ8068 Interface (Minimum Mode)

4-25
 ADDRESS/DATAo_7
\r____________________________ -,{IM~-M~

25
MCS

74LS04
28
DEN DTIR MR/W
8086 Am95181
8288 474LS08
IORC 6 26 AmZ8068
5 Ml)5
AIOWC
BUS
CONTROLLER
74LS04
27
ALE MAS

----------,I
ifi
I 14
CLK

13
MN/MX CLKI. .------------------~----~~~-.M1
C/K

02188A-37

Figure 4-3.8f 8086/8088-Am9518/AmZ8068 Interface (No Wait State)

TLHll is the Address Latch Enable width (ALE) of the 8086. In a system where the DCP runs at a divided system clock, a
For CPU clock rates above 7 MHz, one Wait State has to be clock synchronizer is required. Without a synchronizer the
inserted during Control Register Reads (timing parameter 44). rising edge of the Data Strobes (MDS, MRD and MWR) would
The interface block diagram is shown in Figure 4-3.8g. be synchronous to either the falling or rising edge of the divided
clock. Two simple Clock Synchronizers are used in these in-
NOTE terfaces, one is designed for an even number, the other is
In the interfaces shown, the number of Wait States designed for an odd number of Wait states. The DCP clock is
must be the same for all read or write accesses to the synchronized to the Data Strobes at the falling edge of the
DCP, because the Clock Synchronizer is designed for CPU clock at the end of the CPU cycle T1 (Figures 4-3.Bh and
either an even or an odd number of Wait States. 4-3.Bj). At this edge, the state of the DCP clock is forced to a
low (ClK SYNC A in Figure 4-3.Bh) or to a High (ClK SYNC B
CLOCK SYNCHRONIZATION in Figure 4-3.Bj), depending on the number of Wait states in-
A very important factor in designing the interface to the BOB6 is serted. DCP ClK 1 and 2 show the two possible phases of the
that the rising edge of MDS must be synchronous to the falling DCP clock and how the Clock Synchronizer adjusts the phase.
edge of the DCP clock (timing parameter 45).

4-26
 ADDRESS/DATAo_7
ADo-AD15 11'------.1\1 MPo-MP7
A16-A19

25
MCS

26
IORC MRD
8288
28
AIOWC MWR
80861
8088 BUS Am9568
CONTROLLER

27
ALE MALE

CLK~---------~--~ C/K
MN/MX

02188A-38

Figure 4-3_8g 8086/8088-Am9568 Interface (1 Wait State)

4-27
 CPU ClK

ALE ~~____________________________________

::::: ~,...-------,.\,----,;~~; ~ ~
IORC, AIOWC \ r
...11
\~-----------------------
Ql _ _ _ _

• DCP ClK (1) AND (2) SHOW TWO PHASES OF DCP ClK

02188A·39

Figure 4-3.Bh DCP ClK Synchronization Timing (No Wait States, ClK SYNC A)

CPU ClK

ALE
r\
"",,,,,. ~
~ ;
~ ~
I
DCP ClK (2)'

IORC,AIOWC
\
Ql
I \
• DCP ClK (1) AND (2) SHOW TWO PHASES OF DCP ClK

02188A·40

Figure 4-3.8j DCP ClK Synchronization Timing (1 Wait State, ClK SYNC B)

4-28
DATA CIPHERING SPEED - The Clear Encryption key is loaded through the Master
The data ciphering speed of the DCP is limited by the byte Port by issuing the command "11 H". After the command is
transfer capability of the 8086 bus. A high-performance DMA entered, the Status Register content is read out. Only the
like the AM9516 increases the throughput as shown in the Command Pending bit should be set (40H). If other bits
following table: are set, the program sets the error flag "CODE" to FFH
and terminates. If the status is correct, eight bytes of key
8086 clock DMA clock DCP clock N T are strobed in through the Master Port in eight output
8 MHz 4 MHz 4 MHz 36 0.78 MByte/s instructions. The Key is "8001010101010101 H". The most
6 MHz 6 MHz 3 MHz 18 1.05 MByte/s significant byte is loaded first.
8 MHz no DMA 4 MHz 70 0.42 MByte/s - The status of the DCP is checked, the Command Pending
bit and the parity error bits should be reset (OOH)·
The formula for calculating the throughput is:
- The encryption is started by entering the command "Start
T ~ (8 • f) I (N + 5) MByte/s Encryption" (41 H)·
T ~ Throughput in MByte/s - One block of data (8 bytes) is strobed into the Master Port.
N ~ Number of clock cycles per 8 byte transfer The source is the byte string "PLAIN". In this example, the
5 ~ Internal operation time (5 clocks per block) plain text is: "OOOOOOOOOOOOOOOOH"·

f ~ DCP clock in MHz - Loop 3 is executed until the Busy bit of the Status Register
shows the encryption is done.
8 ~ 8 data bytes per block
- One block of ciphered data is read out of the Master Port
The first two cases in the table above are fast enough to and transferred to the program location "CIPHER". The
encrypt and decrypt the data transferred to or from a 5 1/4-inch ciphered text should be: "95A8D72813DAA94DH".
Winchester Disk Controller "on the fly" (5 MBitis ~ 0.625
MByte/s). - The Status Register is checked; only the Start Entered bit
should be set (80H).
TESTING - The encryption session is stopped by issuing the com-
The interface of Figures 4-3.8f and 4-3.8g and both Clock mand "Stop Encryption" (EOH).
Synchronizers were built and tested using the software - After that the status should be OOH; all flags are reset.
described below.
The program can be used to decrypt data, if two program
- The DCP is reset by software writing "OOH" to the Com- locations are changed:
mand Register.
- The "Enter Key" command of location 011 OH has to be
- The ciphering mode is selected by writing "18H" into the changed to 12H ("Load Clear D-Key Thlough Master
Mode Register. Here the mode is: Master Port-only config- Port"). I
uration, Electronic Code Book (ECB) and Encryption.
- The Start Command of location 0131 H has to be changed
to 40H ("Start Decryption"). After running the program, the
error flag in "CODE" should be reset (OOH).
This test was performed to verify the communication between
the 8086 and the DCP. By providing clear and encrypted data
for the key shown, users should be able to verify operation of
any variation to the design. The software was kept simple to
avoid dependence on other hardwares in the system.

4-29
 ~SM86 VER 1. 0 SOURCE: APPL8068.ASM

~----------------------------------------------------
JUERGEN STELBRINK 4-12-83
ADVANCED MICRO DEVICES

8086 TO AM9518 (AMZ8068) INTERFACE TEST PROGRAM

;--------------------------------------------------------------------------
ADDRESSES OF THE DCP (EVEN ADDRESSES)

FC00 MPSEL EQU 0FC00H BASE ADDRESS OF MASTER PORT

FC02 MPCOM EQU MPSEL+2 COMMAND REGISTER (WRITE ONLY)
FC02 MPSTAT EQU MPSEL+2 STATUS REGIS1'ER (READ ONLY)
FC06 MPMODE EQU MPSEL+6 MODE REGISTER (READ AND WRITE)
FC00 MPINP EQU MPSEL INPUT REGISTER (WRITE ONLY)
FC00 MPOUT EQU MPSEL OUTPUT REGISTER (READ ONLY)
0018 ECB EQU 18H ENCRYPT, MP ONLY, ECB
0080 KEYI EQU 80H KEY: 8001010101010101H
0001 KEY2 EQU IllH

ORG 100H

0U0 BA 02 FC BEGIN: MOV DX,MPCOM DX: POINTER TO PORT ADDRESS

0103 B0 00 MOV AL,0 SOFTWARE RESET
0105 EE OUT DX,AL

0106 BA 06 FC MOV DX,MPMODE

0U9 B0 18 MOV AL,ECB SELECT MODE
010B EE OUT DX,AL

010C BA 02 FC MOV DX,MPCOM

010F B0 11 MOV AL,11H LOAD CLEAR E-KEY THROUGH MP
0111 EE OUT DX,AL

0112 BA 02 FC MOV DX,MPSTAT

0115 EC IN AL,DX READ STATUS
0116 3C 40 CMP AL,40H 40= CP SET
0118 75 5F JNE "ERROR

011A B0 80 MOV AL,KEYI LOAD 1. KEY BYTE

011C BA 00 FC MOV DX,MPINP
011F EE OUT DX,AL OUTPUT 1. KEY BYTE
1<1120 B9 07 00 MOV CX,7 LOAD COUNTER FOR NEXT 7 BYTES KEY
0123 B0 01 MOV AL,KEY2 FOLLOWING KEY DATA
13125 EE LOOPl: OUT DX,AL
'1126 E2 FD LOOP LOOPI

0128 BA 02 FC MOV DX,MPSTAT

012B EC IN AL,DX READ STATUS
012C 3C 00 CMP AL,0 FLAGS RESET?
012E 75 49 JNE ERROR

0130 BA 02 FC MOV DX,MPCOM

0133 B0 41 MOV AL,41H START ENCRIPTION
0135 EE OUT DX,AL

0136 B9 08 00 MOV CX,8 8 BYTES (1 BLOCK) OUTPUT

Figure 4-3.8k

4-30
ASM86 VER 1.0 SOURCE: APPL8068.ASM

0139 88 130 00 MOV 8X,0 INITIALIZE POINTER

013C 8A 013 FC MOV DX, Mpj NP
013F 2E 8A 87 81 01 LOOP2 : MOV AL,PLAIN[8X) LOAD DATA
0144 43 INC 8X INCREMENT POINTER
0145 EE OUT DX,AL WRITE PLAIN DATA
13146 E2 F7 LOOP LOOP2

0148 8A 02 FC MOV DX,MPSTAT

0148 EC LOOP3 : IN AL,DX WAIT UNTIL ENCRYPTIDN IS DONE
014C 24 20 AND AL,20H TEST 8USY 8IT
fl14E 75 F8 JNZ LOOP3

0150 89 08 00 MOV CX,8 8 8YTES (1 BLOCK) INPUT

13153 B8 1313 130 MOV BX,fl INITIALIZE POINTER
13156 8A 013 FC MOV DX,MPOUT
0159 EC LOOP4: IN AL,DX READ ENCRYPTED DATA
015A 2E 88 87 89 01 MOV CIPHER[BXj ,AL STORE DATA
015F 43 INC BX INCREMENT POINTER
131613 E2 F7 LOOP LOOP4

0162 BA 02 FC MOV DX,MPSTAT

0165 EC IN AL,DX TEST STATUS REGISTER
13166 3C 813 CMP AL,8flH 80= START ENTERED
0168 75 0F JNE ERROR

016A BA 02 FC MOV DX,MPCOM

016D B0 E0 MOV AL,0E0H STOP ENCRYPTION
fl16F EE OUT DX,AL

0170 BA 132 FC MOV DX,MPSTAT

13173 EC IN AL,DX TEST STATUS ~EGISTER
0174 3C 130 CMP AL,fl ALL BITS MUST BE RESET
13176 75 01 JNE ERROR
0178 C3 RET

13179 80 FF ERROR: MOV AL,0FFH LOAD ERROR CODE

017B 2E A2 80 01 MOV CODE,AL
017F C3 RET

13180 00 CODE DB 00H ERROR CODE

0181 00 00 00 013 00 00 PLAIN DB 00H,00H,0GH,G0H,GGH,0GH,00H,00H PLAIN TEXT
130 00
0189 12 23 34 45 56 67 CIPHER DB 12H,23H,34H,45H,56H,67H,78H,89H CIPHER TEXT
78 89

END

END OF ASSEMBLY. NUMBER OF ERRORS: 0

Figure 4-3-8k (continued)

4-31
4.3.9 THE 8086 AND Am9519A The discussion so far has been centered on the Interrupt Ac-
knowledge response. When programming the Am9519A, a
INTERRUPT CONTROLLER INTERFACE careful timing analysis shows that, for a 5 MHz CPU, the
This interface illustrates the use of the Am9519A Interrupt Con- Am9519A-l should be used or a Wait State inserted. For the 8
troller with the 8086 (Figure 4-3.9a). The Am9519A has many MHz CPU, a Wait State will be required. This is due to the
advantages over the 8259A. However, some external logic is uncertainty of where the IRD pulse occurs with respect to the
required. The purpose of this logic is to convert the two inter- clock. This will result in the data-to-clock setup time not being
rupt acknowledge cycles from the 8086 into one. Those met in some cases. The best resolution is to insert a Wait State
familiar with the Am9519A may question this since the for programmed 1/0.
Am9519A can be programmed to accept two interrupt ac- (option)
knowledge pulses. The reason for choosing this approach is The Am9519A interface illustrates two options to this logic. The
faster response time. The Am9519A requires the first interrupt first is an AND gate inserted into the interrupt request line. This
acknowledge pulse to be 900 nsec in order to resolve priority, allows users to dynamically mask channels in the Am9519A
therefore, Wait States would need to be inserted. However, the without hanging the system up. Without this gate, it is neces-
simple logic shown eliminates the need for Wait States and sary to disable CPU interrupts, change the mask register, and
meets the Am9519A timing requirements. re-enable CPU interrupts. This hang up occurs if the CPU
The gate shown by dotted lines is optional. Its purpose is to masks off a channel which is causing the GINT to be active.
prevent interrupts when the CPU does a write to the Mask The CPU recognizes the interrupt before the mask removes
Register. This can be done in software by disabling interrupts the request. When the interrupt acknowledge cycle starts, and
whenever a write to the Interrupt Mask Register (IMR) is done. since the channel was masked, the Am9519A will assert pause
indefinitely.
The second option is an alternate way to convert the proces-
sor's two acknowledge pulses into one acknowledge pulse.
The timing diagram illustrates the difference. User should
choose the one that eliminates Wait States.

-
MilO
I
G2A

vt
AD ,S
AD.
I'v- V'"
r-
Am25LS373

G
-"""
V
74LS138

CS
ALE - :I
'-- G I
V ~ Am25LS373
I
I
Am8086
IV' Ao
I
C/O
Am9519A-1
I
I
AD7
ADD
vt ~ AD7
ADD
~
INTR
-
I"'" Cl----l GINT
INTA FIGURE A OR B j -~ INTA
-
RD AD
-
WR WR

CLK

RESET

READY
CLK

RESET
READY
OUT
8284A

RDY 1 PAUSE

02188A-41
Figure 4-3.9a

4-32
 INTA
\
INTA1
\ 8 x 125 = 1000ns 8MHz 8086
/
INTA2 \ 6 x 200 = 1200no 5MHz 8086
/
RESET - - - - - - - - , RESET

PRE PRE
o a 0 a INTA2
INTA --t;><>-.......-t--f INTA CP Q
74LS74

BMHz8086 5MHz8086
Figure A Figure B

02188A-42
Figure 4-3.9b

4.3.10 iAPX286 TO Am9568 DATA thus satisfying the setup and hold time requirements of the
82284. Two Wait States are inserted.
CIPHERING PROCESSOR INTERFACE
Half of the PAL device operates as a bidirectional Ad-
This interface is designed for an 8-MHz CPU where the DCP is
dress/Data Multiplexer. During the Address Latch Enable ac-
synchronously operating at the maximum clock rate of 4 MHz.
tive phase, the state of AI and A2 is transferred to the ADI and
Block diagram for the interface is shown in Figure 4-3.1 Oa. The
AD2 pin of the PAL device. The DCP latches this two bit-
Am9568 requires a narrower width of address strobe than the
address with the falling edge of ALE.
Am9518. This works comfortably with the 60 ns address strobe
width of an 8-MHz CPU. When IORC and CSL are active, the states of ADI and AD2
are passed to Dl and D2 respectively. The DCP Register can
The Multibus' Mode Select input of the Bus Controller 82288 is
be read. If IOWC and CSL are active, the data path is turned
tied Low to optimize the command and control signals for short
around: Dl and D2 are inputs, ADI and AD2 are outputs.
bus cycles. The Command Delay (CMDLY) becomes active
High for one 16-MHz clock cycle whenever the DCP is selected The Address Hold Time of the PAL device is sufficient because
to delay the Read and Write strobes by 125 ns. This satisfies the address information is passed to ADI and AD2 whenever
the timing requirement of the minimum delay between ALE IORC'CSL or IOWC*CSL are not true, i.e. whenever data is
inactive and Read or Write strobe active of the DCP. An open not transferred between the CPU and the DCP.
collector gate must be added to allow other peripherals to drive The Read Data Hold Time requirement of 5 ns of the Am9568
this input. is satisfied by the propagation delay of the PAL device.
The ALE, IORC and IOWC outputs of the 82288 are wired The Read Data Hold Time requirement of 5 ns of the iAPX286
directly to the DCP. ALE strobes a D-Flip-Flop to store the state is also satisfied by the PAL device.
of Chip Select for the entire cycle.
The Master Port Chip Select (MCS) input of the DCP is con-
0'3 and the latched Chip Select CSL are ANDed externally to nected to the unlatched address decoder output.
generate the Synchronous Ready for the 82284. The 82284
'MULTIBUS is a registered trademark of Intel Corporation.
samples the line at the falling edge of the clock. The registered
output 0'3 is clocked with the rising edge of the same clock,

4-33
 Do-D7 MPo-MP7

r-------------4"":"~--------------_i"""·".~--~_4MCS

~ ~------------~-------------+I
A·r-----------~--~====~---+I A.
M/iO Q

CLK Q CSL Q,
iAPX286 Am9568
AmPAL16R4
ALE Q2 ~---------I CLK
CS
CMDLY
CLK 1---+-----------+++1 CLK
82284
SRDY i+--i-''"''-()(
Ci3
iORC IOWC

ALEI_--~------------+--~I_----t_-----------.IALE

CMD~~----------------~

82288
IORC I_--------------------~~----t_-----------.I MRD

IOWCI_----------------------------~----------_.IMWR

02188A-43
Figure 4-3.10a iAPX286-Am9568 Interface

THE DCP CLOCK phase 2 cycles of the CPU. The CPU design guarantees that
The PAL device synchronizes the DCP clock to the Data there is always a phase 1 cycle between two phase 2 cycles.
Strobes IORC and IOWC (Figure 4-3.1 Ob). It also divides the Assuming a typical PAL device propagation delay of 25 ns,
16-MHz system clock (8-MHz CPU clock) down to the maxi- timing parameter TCDS (Time Clock Data Strobe) is 10.5 to
mum DCP clock rate of 4 MHz. At this clock rate, the Data 22.5 ns ( 3 + 32.5 - 25 ns to 15 + 32.5 - 25 ns). This satisfies
Strobe Delay to the DCP clock must be 0-30 ns. The Bus the 0 to 30 ns requirement.
Controller is specified to generate a Data Strobe timing of 3-15 The AmPAL 16R4 has active Low outputs. But one output, 02,
ns to the falling edge of CLK (16 MHz). Because of the higher should be active High. The equation for 02 was derived to be
propagation delay of a standard PAL device, the registered
outputs are toggled at the rising edge of CLK before the Data 02 = ALE' CS 01 • 02 0, . O2
Strobes become inactive. This gives additional 32.5 ns for the To compensate for the inversion in the PAL device, either de
DCP clock signal path. Morgan Theorem or Karnaugh-Veitch diagrams can be used to
01 to 03 are three outputs of the PAL device state machine. convert it to the form shown in PAL device Design Specifica-
The registered output are clocked with the rising edge of the tion.
16-MHz 82284 clock. Whenever ALE and CS are active, 01 to
03 are set to the initial state. 01 to 03 are outputs of a 3-bit IMPROVEMENTS
down counter, with 03 as the most significant bit. The DCP needs two Wait States only when the Control RegiS-
ters are read. Data Register read or writes and Control
03 is used to generate the SRDY signal for the 82284 as
Register reads can be executed with only one Wait State,
mentioned above.
which improves the Data Ciphering speed of this interface. The
02 is the DCP clock. This design must guarantee that the more sophisticated Wait control logic and the two external TTL
minimum DCP clock High or Low time is at least 115 ns or two gates can be integrated into one AmPAL22V10 device.
16-MHz clock cycles. This is done by toggling 02 only during

4-34
 (W) (W)
TS Tc Tc TC Ts 9 I
ClK

PClK

ALE

CMDlY

IORCIIOWC

CSl
-------'
D~A(R~~ ____________________________-{~~~~~~~~~~~~_________J~___________ _

DATA (WRITE) ____________________- J

ADDRESS
__________ -J~------------------

as /
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

02188A·44

Figure 4-3.10b Timin!l Diaaram

4·35
PAL16R4 PAL DESIGN SPECIFICATION
DCP043 JUERGEN STELBRINK 8-23-83
iAPX286 - Am9568 (DCP) INTERFACE DEVICE
ADVANCED MICRO DEVICES

CLK /CS CSL ALE /IORC /IOWC A1 A2 NC GND

JOE D1 D2 /Q1 Q2 /Q3 CMDLY AD1 AD2 VCC
Q1 := ALE*CS + /Q1
/Q2 .- Q1*/Q2*/ALE + Q1*/Q2*/CS + /Q1*Q2*/ALE + /Q1*Q2*/CS
Q3 := ALE*CS + Q1*Q2*Q3 + /Q1*Q2*Q3 + Q1*/Q2*Q3 + /Q1*/Q2*/Q3
/CMDLY .- /ALE+/CS
IF(CSL*IORC) /D1 /AD1
IF(CSL*IORC) /D2 /AD2
IF(CSL*/IORC) /AD1 /A1*ALE + /D1*/ALE
IF(CSL*/IORC) /AD2 /A2*ALE + /D2*/ALE

FUNCTION TABLE

CLK /CS CSL ALE /IORC A1 A2 D1 D2 AD1 AD2 /Q1 /Q2 /Q3 CMDLY

/ C
I M
C / C A a A A / / / D
L C S L R A A D D D D Q Q Q L
K S L E C 1 2 1 2 1 2 1 2 3 Y COMMENT
---------------------------------------------------------------
C L H H H L L Z Z L L L L L H 1 (lCS ACTIVE)
x L H H H L H Z Z L H L L L H
X L H H H H H Z Z H H L L L H
C L H L H H L L 'i L H H L L L 2 (WRITE CYCLE)
X H H L L L L L H L H H L L L (READ CYCLE)
C H H L L H L L H L H L H L L 3
C H H L L H L L L L L H H L L 4
C H H L L H L H H H H L L H L 5
C H H L H H L H H H H H L H L 6
C H H L H H L L L L L L H H L 7
C H H L H H L H L H L H H H L 8

C H L H H X X Z Z Z Z L L L L 1 (NO /CS)

4-36
DESCRIPTION:

INPUT SIGNALS:

CLK 16 MHZ SYSTEM CLOCK OF THE 82284 SYSTEM TIMING CONTROLLER.

THIS CLOCKS TRIGGERS THE D-FLIP-FLOPS OF FOUR PAL OUTPUTS

/CS ACTIVE LOW UNLATCHED CHIP SELECT OF THE ADDRESS DECODER

CSL ACTIVE HIGH LATCHED CHIP SELECT. IT HAS TO BE ACTIVE TO THE

RISING EDGE OF ALE OF THE NEXT CYCLE

ALE ADDRESS LATCH ENABLE OF THE 82288 BUS CONTROLLER

A1,A2 DEMULTIPLEXED ADDRESS INPUTS. THEY CARRY THE 2-BIT REGISTER

ADDRESS FOR THE DCP

/IORC INPUT/OUTPUT READ CONTROL OF THE 82288

/IOWC INPUT/OUTPUT WRITE CONTROL OF THE 82288

OUTPUT SIGNALS:

/Q1 INTERNAL STATE SIGNAL. IT IS DIVIDED BY TWO FROM CLK AND

SYNCHRONIZED TO ALE

/Q2 INTERNAL STATE SIGNAL. IT IS DIVIDED BY TWO FROM /Q1 AND

SYNCHRONIZED TO ALE. IT IS THE INVERTED DCP CLOCK (4MHZ).
THE RIGHT EDGE OF Q2 IS SYNCHRONOUS TO THE DATA STROBES
/IORC AND /IOWC, IF TWO WAIT STATES ARE INSERTED.

/Q3 INTERNAL STATE SIGNAL. IT IS DIVIDED BY TWO FROM /Q2 AND

SYNCHRONIZED TO ALE. IT IS USED TO GENERATE THE SYNCHRONOUS
READY (/SRDY) FOR THE 82284. EXTERNALLY IT HAS TO BE
LOGICALLY AND'ED WITH THE THE LATCHED CHIP SELECT (CSL).

CMDLY COMMAND DELAY GOES ACTIVE FOR ONE CLOCK WIDTH TO DELAY THE
DATA STROBES. THE AM9568 REQUIRES A DELAY BETWEEN ALE
INACTIVE AND DATA STROBE ACTIVE.

BIDIRECTIONAL SIGNALS:

D1,D2 DEMULTIPLEXED DATA BUS LINES TO 8086 CPU

AD1,AD2 MULTIPLEXED ADDRESS/DATA BUS LINES FOR THE DCP

4-37
5.0 INTERFACING TO THE 8088 5.3.1 8088 AND Am8052 CRT
CONTROLLER INTERFACE
5.1.0 8088 OVERVIEW The interface technique between the Am8052 CRT Controller
The 8088 CPU is an 8-bit processor designed around the 8086 and an 8-bit microprocessor also applies to the 8088 and
internal structure. Most functions of the 8088 are identical to AmB052 interface.
the equivalent 8086. The 8088 fetches and writes 16-bit words There are two fundamental issues associated with mixing
in two consecutive bus cycles. Both the 8086 and the 8088 devices that communicate over different-sized buses. The first
handle the external bus the same way but the 8088 handles problem is allowing the two devices to communicate on a
only 8-bits at a time; and both appear identical to the software "common" data bus. Consider, for example, a 16-bit system
engineer, with the exception of execution time. utilizing 8- and 16-bit peripherals. Overcoming the mismatched
The hardware interface of the 8088 contains the major differ- data paths requires some form of controlled multiplex-
ences between the two CPUs. The pin assignments are nearly ingldemultiplexing of the different data paths. In addition, extra
identical, however, with the following functional changes: control signals for partitioning the 16-bit word into 8-, and 16-bit
Aa-A15 These pins are only address outputs on the units may be required. Today, most of the 16-bit CPU based
8088. They are latched internally and remain systems that use 8-bit peripherals usually use just the lower
valid throughout a bus cycle in a manner half of the data bus to transfer data to and from the peripheral.
similar to the 8085 upper address lines. However, this scheme does not work when interfacing 16-bit
peripherals to 8-bit CPUs, especially when these peripherals
SSO Provides the SO status information in the mini- have bus master capability.
mum mode. This output occurs on pin 34 in
minimum mode only. DATA FUNNELLING
DT/R, 101M, and SSO provide the complete bus status in When a 16-bit peripheral attempts to transfer data over an 8-bit
minimum mode. bus (memory write cycle or slave read cycle), the 16-bit data
101M has been inverted to be compatible with the bus has to be broken down into two by1es and transferred
MCS-85 bus structure. sequentially. First, the lower 8-bits are transferred out on the
bus (Figure 5-3.1.1 a), and then in the next transfer cycle the
ALE is delayed by one clock cycle in the minimum mode when
upper 8-bits of the 16-bit word are sent out (Figure 5-3.1.1b).
entering HALT, to allow the status to be latched with ALE.
The generalized bus timing for such an operation is shown in
Figure 5-3.1 .1 c. Figures 5-3.1 .2a, 5-3.1.2b, and 5-3.1 .2c show
5.2.0 8088 AND Z8000 PERIPHERALS the opposite case; a bus read operation from an 8-bit bus to a
Most of the interface design between the 8088 and Z8000 pe- 16-bit peripheral. Here, the first by1e read from the system
ripherals are similar to that of the previous chapter. The user is must be latched. Once the second by1e has been fetched, the
referred back to Chapter 4 of this manual when the interface is 16-bit peripheral reads in the assembled 16-bit (2-by1e) word.
similar. Additionally, provisions may need to be made for the case
when the 16-bit peripheral accesses single by1es.
5.3.0 THE 8088 AND AMD Interruptions of the two cycle transfer must be analyzed very
PROPRIETARY PERIPHERALS carefully. Master transfers may not be interrupted by slave
The evolution of chip design has taken the 8-bit environment accesses while being in the middle of a two-cycle transaction.
into the 16-bit environment. While the new generation of pe- Similar, slave accesses may not be interrupted by master
ripheral devices are often 16 bits wide, the older, established transfers. While the interface funnels the data, the current bus
8-bit orientation of CPUs and peripherals are still significant. cycle needs to be stretched. When the peripheral is bus mas-
Interfacing a 16-bit peripheral with an 8-bit CPU often encoun- ter, as shown in Figures 5-3.1.1 a, 5-3.1.1 b, and 5-3.1.1 c, the
ters data path incompatibility and involves bus control 16-bit peripheral is holding its data available for what would
manipulation. This type of integration mainly involves separat- normally be two complete bus transfer cycles. This stretch can
ing the control and data paths from the new peripheral and the be achieved by delaying the transfer acknowledge signal to the
system. peripheral, causing it to wait (WAIT asserted).
The ability to mix different data path widths can improve sys- In slave mode, the 8-bit CPU would have to make two con-
tem functionality, performance, and cost. It is less expensive to secutive read operations to examine a 16-bit peripheral status
use an 8-bit bus in a new design because the memory require- register. The peripheral must not become bus master in-
ments are generally cheaper. A designer can use this data path between the first and second read operations since this in-
mixing to upgrade the existing system until a new system validates the results of the first read operation. This function
design is warranted, or the designer can simply improve on the can be handled in two different ways: if the CPU has a bus lock
existing design as new peripherals become available. AMD instruction (for example, like the iAPX family of CPUs), then the
makes a number of proprietary peripherals and the following programmer uses one of these before the CPU accesses the
sections show users with 8-bit systems how to incorporate peripheral. Alternately, the CPU can disable the arbitration
those AMD products into their designs. logic while it is perforrning the critical uninterruptible slave
transfer.

5-1
 8 BIT
SYSTEM

a) 16 BIT
DEVICE

8 BIT
SYSTEM

16 BIT
b) DEVICE

A'5-A,
ADDRESS --<_______________________________________ '----
~ ~r--

An ~'- _ _ _ _ _ ---II
c) 8-BIT
DATA BUS
----------{<::JD~<27~:O~>~)----_«=D~<~1~5~:8~>~>--
. . . .

WR,RD \ I \ r-
16-BIT--<
DATA BUS ~_ _ _ _ _ _~D~<~1~5:~O~>~_ _ _ _ _ _ .J}---
MEM/IO
Ar;C""KroN"'O"'Wii'iLE~D<iOG~E \......./ ~

02188A-45

Figure 5-3.1.1 Bus Master Write or Slave Read Operation

5-2
DEVELOPING THE CONTROL AND DATA word is loaded into the peripheral. Similarly, WAIT is asserted
TRANSFER INTERFACE until the second byte read cycle can be terminated.
Designing the control interface to allow mixing 8- and 16-bit The slave mode of operation works almost identically to the
peripherals requires an analysis of the data and control flow. peripheral bus master mode. The master read cycle is similar
The data flow automatically defines the data path design (see to the slave write cycle, and the master write cycle is similar to
Figures 5-3.1.1 & 5-3.1 .2). The bus master operation by the the slave read cycle. In general, if the peripheral puts data on
peripheral is relatively straightforward. During a write opera- the narrower system bus, the peripheral can keep the data
tion, the data is written out sequentially: the lower byte first and active in both sequential system bus cycles. On the other hand,
then the upper byte (or vice-versa). During a read operation, if data is loaded into the peripheral, the interface logic has to
the data is fetched sequentially. The byte fetched first is latch the data of the first fetch cycle, whereas the data of the
latched, to hold the data until the peripheral can read it. In the second cycle can be loaded directly into the peripheral (no
second byte read cycle, the remaining byte is fetched, the latching required).
16-bit word is assembled from the two bytes, and the 16-bit

8 BIT
SYSTEM

a) 16 BIT
DEVICE

8 BIT
SYSTEM

b) 16 BIT
DEVICE

ADDRESS
A,.-A,
--< >-
Ao \ r
8-BIT DATA
c) BUS ( D < 15:8 > ) ( D < 7:0 > )-
WR,RD \ I \ ,-
16-BIT DATA
BUS
( D < 15:0 >

MEMiiO
ACKNOWLEDGE

02188A-46
Figure 5-3.1.2 Bus Master Read or Slave Write Operation

5-3
When defining the interface, the designer must make a con- addition, the specific bus timing of the peripheral and the data
scious choice of which byte (upper or lower) to latch during bus must be examined to quantify the state control flow and
peripheral read operations (or conversely, slave peripheral provide information on data latching, read/write control
write operations), Once this decision has been made, the CPU strobes, and addressing to and from the peripheral. The state
must always access the latched data byte first (during a slave control flow is broken down into three parts bus master read,
write) and then access the non-latched byte to complete the slave read, and slave write operations.
transfer, This restriction is a minor one with no extra software The three control signals that must be generated by the 8/16-
overhead; yet it could affect the ease of the programmer's
a
bit control unit are: Address bit (Ao), peripheral hold (WA IT),
coding if not handled properly. For example, if the programmer and bus read (RD). The Ao line is generated by the control
uses a compiler to generate the software for the system, extra logic to indicate which byte is to be transferred in bus master
care may be necessary to ensure that the compiler generates modes only. Otherwise, the Ao generated by the system is
the correct addressing sequence. An alternative to this solution used to indicate which byte is being accessed. The WAIT line
would be to latch both the upper and lower data bytes. In that
holds up the peripheral during transfers. The RD line is re-
case, the cost of the interface would be increased, as would quired to indicate successive transfer cycles on the bus. The
the complexity, with no gain in performance. peripheral's control signals strobe active only once, because
The state diagram (Figure 5-3.1.3) illustrates the control se- the two-cycle transfer must be kept hidden from the peripheral.
quence implemented in the 8/16-bit bus control logic. It also The slave transfer flow is almost identical, except that the CPU
depicts how uninterrupted word transfers will occur and how is generating the bus signals and the transfer directions are
the addresses for upper and lower bytes are generated. In reversed, that is, a bus write goes into the peripheral.

9-
COMMENTS

SO 0 AS=1+
CS=1+
MROV=1
WAIT TILL PERIPHERAL TAKES BUS;
MAKE SURE MEMORV ACKNOWLEDGE IS
NOT ASSERTED.

AS=0'RW=1'MRDV=0

8:J MRDV =0
READ IN UPPER BVTE; Ao=1;
WAIT FOR MEMORV ACKNOWLEDGE;
ISSUE RD STROBE.

T MRDV=1

8:J MRDV =1
WAIT FOR MEMORV ACKNOWLEDGE
TO GO AWAV.

T MRDV=O

8:J MRDV =0
READ IN THE LOWER BVTE; Ao=O;
WAIT FOR MEMORV ACKNOWLEDGE;
ISSUE RD STROBE.

TMRDV=1

STROBE IN DATA TO PERIPHERAL;

DEASSERT WAIT;
WAIT FOR SUCCESSFUL READ.

021 88A-47

Figure 5-3.1.3 Bus Master Read State Flow-Control

5-4
The conceptual logic for the 16- to 8-bit data flow example is The state flow control requires logic capable of sequentially
shown in Figure 5-3.1.4. The data on the upper byte is latched moving from state to state, holding in a particular state, and
when data is being read (as a bus master) and read or written being reset or initialized back to a predefined state. This design
(as a bus slave). Although this interface must latch data com- integrates the state machine generator and the control signal
ing from the 8-bit data bus into the peripheral, it also needs to logic into the same Programmable Array Logic (PAL) device.
act as transceiver when the peripheral is sending data out to A considerable amount of logic is required to generate the
the system. The ideal part to accomplish such an interface data-path flow logic and the bus control signals. This is espe-
would be one that has a three-stated output, with an 8-bit wide cially true if the peripherals and CPUs have different signal
latch, in one direction and a three-stated driver in the other conventions (for example, AS, DS, and Rm versus ALE, RD,
direction. The Am2952 8-bit bidirectional 1/0 port combines the and WR). Conversion between different signal conventions,
upper data bus latch and upper data driver chips into one IC. It signal polarity changes, and extra functions (such as generat-
provides two 8-bit clocked 1/0 ports, each with three-state out- ing Ao) requires quite a bit of logic and design effort. If the
put controls and individual clocks and clock enables. An peripheral has bus master capability, additional information,
Am2949 bidirectional bus transceiver completes the logic re- such as bus arbitration controls, must be fed into the next state
quired to buffer the data path. determination logic to decide what control sequence to follow.

STATE
, ......; . - - - - - - - - CS
MACHINE

os .. .. BUS • ... Ao

Riw .. .. CONTROL
TRANSLATION .. ... RD
LOGIC
& • WR
WAIT FUNNEL LOGIC
CONTROL .. MEM ACK

CONTROL
LINES

8
DATA
PERIPHERAL CPU
FUNNEL
SIDE SIDE
LOGIC

021BBA-4B

Figure 5-3.1.4 Conceptual 16/S-Bit Conversion Logie

5-5
Figure 5-3.1.5 shows a typical 8/1S-bit control interface which The slave accesses by the CPU are either pointer writes (to
combines all the individual components discussed above. The select the desired control/status register) or lS-bit data
state machine and the bus and latch controls have to be tightly read/write operations. The pointer write operation is really an
coupled in order to transfer data between the 8-bit and lS-bit 8-bit operation because only the lower 8 bits of the data form
buses. The generalized machine is designed under the as- the register address. The three different transfer timings are
sumption that the peripheral has bus master capability. If this is shown in Figures 5-3.1.S, 5-3.1.7, and 5-3.1.8.
not the case, the design can be greatly simplified. Two special conditions have been incorporated into the state
Since the CRTC does not modify system memory, no provision flow diagrams whenever a transfer is first initiated. Before a
for a bus master write operation is required. This is important new transfer cycle is attempted (that is, while the state ma-
because it eliminates the need to generate a system write chine is waiting in SO), the memory acknowledge must be
control signal (WR). In addition, the control and display infor- inactive. This prevents any interference from the last transfer.
mation will always be aligned on word boundaries. This The second special condition occurs when the Am8052
relieves the 8/1S-bit control logic from worrying about funneling asserts the RiW line to indicate a write operation. Whenever
the bytes and performing odd/even byte transfers. It also saves the Am8052 updates the upper 8 bits of the 24-bit address
control inputs from the Am8052 because all transfers are latch, the RiW line indicates a write operation (in conjunction
words; there is no need for upper and lower data strobes or with AS). The Am8052 is not actually performing a system data
byte high enable inputs/outputs. write, only an address latch update. Hence, the state flow
reflects this fact by not starting a sequence if the RiW line is
active Low from the Am8052.

IA~2--l
ClK

ClKEN -------+--'. II
OE ---------t--.,
I
0< 15:8 >

OE - - - - - - I
8

TEN --------------------------,
REN -----------------------,

0< 7:0 >

Am2949
02188A-49

Figure 5-3.1.5 Data Funnel Logic

5-S
 T, T, Tw Tw Tw Tw T3

ClK,

AS8052~

05 8052

UPPER BYTE
TRANSFER

lOWER BYTE
TRANSFER

MEMACK

WAIT
~ c

Ao

SYSTEM
DATA
< HIGH BYTE ) < lOW BYTE
>-
CPs

RD
I

02188A-50

Figure 5-3.1.6 Bus Master Read Timing Diagram

5-7

.~~-------
AS, RD, CSSYS

CS8052

R/wZlO ~~\\\\\\\\\\\\\\\\\\\\\\S\\\\

OE --------------~(~
BR ' 1
'..._ _ _ _ _ _ _ _.....

Sy~~~~----~(C:::JL~O~W~B~yT~E==::=~~~_____H_IG_H_B_y_TE____~}---

02188A·51

Figure 5-3.1.7 Slave Read Timing Diagram

5-8
 AS, WR, CS svs

Ao !llJ IIff!ll

CS a052

OS --------------,?~
. \~,____________~I

R/V{ \\\\\\\\\\\\\\\\\\\\\\\\\\Si~

CPs

SYS~~~ ------(~____H_I_GH__BY_T_E____~}____T'~(----~(C====~L~OW~B~Y~TE~====}-----

» ( LOW AND HIGH BYTE }-----

AD o - 15 «

02188A-52

Figure 5-3.1,8 Slave Write Timing Diagram

These simplifications make it possible to combine the Am8052 TRADE-OFFS AND LIMITATIONS
to an 8-bit CPU control interface in a single AmPAL22V10 In a design dramatically affecting the I/O of the system, a
device (Figure 5-3.1.9) which also converts the bus control number of trade-offs and limitations should be noted. The most
signals from AS, DS, and RiW to RD and WR. Figure 5-3.1.9 obvious limitation in using l6-bit peripherals on an 8-bit bus is
shows the assembled control and data transfer logic for this that the l6-bit peripheral will be under-utilized. The speed of all
interface. The minimum AmB052 and bus control signals that I/O operations will be cut by 50%. Consequently, the bus
have to be generated are RD, Ao, DS, RiW. Although DS and utilization percentage will go up if the l6-bit peripheral
RiW are used as inputs during a bus master operation by the represents a significant factor of the bus usage. A CRT control-
Am8052, the AmPAL22V1 0 must convert the CPU R D and W R ler like the Am8052 might use 5% to 10% of the bus bandwidth
signals to DS and RiW for slave I/O operations. The signals Ao for display information when using l6-bit I/O. Converting to
and R D are generated by the control logic when the Am8052 is 8-bit I/O would double bus usage to 10% or 20%.
performing a read access to the system. The WAIT (or not
READY) signal to the Am8052 also needs to be generated by
the control logic. Additionally, the four control signals of the
bidirectional port and transceiver are generated.

5-9
----.--.--~~--
 ciD .. A,

CS

BAI ..
+ !. •
BUSAK

RD
BRQ

BAO ... WR

... • AO

AmPAL
.. MEMACK ( READY)

22Vl0
CS
~

IF
RiYJ CE sCPs

os CE R
AmS052
WAIT OE BR

CPR

OE As
Am2952
~
/

~
/
ADs - 15 / A BK DATA BUS
Is V 'I
A /8

"""
~ T

OREN If

ADo-7
r 'I /8
/ ...
V
) A
Am2949
B
/~

'I

021SSA·53

Figure 5-3.1.9 Am8052 8-Bit Interface

Another factor that might affect the bus usage is the efficiency 5.3.2 8088 AND AmZ8068 DATA
of the 8- to 16-bit conversion control logic. If the state machine
designed to perform the 8/16-bit conversion (or 16/32-bit) is
CIPHERING PROCESSOR INTERFACE
improperly designed, then extra transfer overhead may be in- Figure 5-3.2a shows the CPU-DMA interface. The CPU is op-
troduced. This could mean that a sequential transfer of two 8- erating in Maximum Mode. The bus arbitration handshake of
bit values takes longer than two single 16-bit transfers. The the DMA controller (HREQ and HACK) must be translated into
system designer must weight the cost of the extra overhead on the Bus Request/Grant handshake of the 8088 CPU.
a case-by-case basis. Most interfaces outside a system's im- If the CPU is programmed to operate in Minimum Mode, both
mediate family require some kind of extra interface logic devices have the same bus arbitration handshake. The HREQ
anyway. Therefore, by optimizing the control signals and incor- and HACK of the DMA controller can be connected directly to
porating them into programmable logic devices such as the the corresponding pins of the CPU (HREQ to HACK).
AmPAL22V10, the IC count can be dramatically reduced.

5-10
The central part of this interface is a PAL device, which has Master Port Read/Write is latched in the D Flip-Flop. It is
been programmed for the 8088 CPU timing. The PAL equation clocked in an output operation with CS3 active. One of the data
for this interface is shown at the end of this section. The Chip lines is latched in to define the status on the MR!W input. This
Select 2 (C S2) input of the PAL device must be stable during is necessary because the DCP requires a set-up time of 100 ns
the entire I/O transfer. This is guaranteed by decoding CS2 of MR/W to the Data Strobe. Generation of MR/W for each
from the latched address/data bus of the 8088 (Ao-A15 in Fig- cycle of a high-speed data transfer session of the DMA control-
ure 5-3.2a). ler would extend each cycle and slow down the maximum
throughput. This logic cannot be integrated into the PAL device
because of the flip-flop's asynchronous clock.

MRDC
~
MRWC
8288
r 10RC

10WC
AEN
~ ClK 8088 Am9517A-5
(5-8 MHz)
t (4 MHz)

8284
RQ/GT
-f:B 1)

~ L
HACK
HREQ

~ READY
ADa-AD,. :;.S\}3? {is)!
CS,
DECODER r. cs
r'l CSo cs.

ADo-AD7
J

~
it{{)
~

r
00-07
DACK DREG
...
~' ClK
Q
I
I
osc
4MHz
1
~
-
R/W MR/W MFlG
cs !- MPo-MP7

IOWC AmZ8068
IORC (4 MHz)
READY DACK MCS
ClK,
ClK2
ClK
MAS
;..J f ClK
MAS
MDS MDS
AmPAL16R4A MCS elK
NOTE 1: See Section 4-3 Figure 4-3.6 a and d
~ ~

02188A-54

Figure 5-3.2a 8088-Am9517-AmZ8068 Interface

5-11
Before executing an access to the DCP, the CPU must latch because the CPU must set up the DCP for data transfer before
the MRiW. The transfer itself is evaluated in a two-cycle opera- a DMA transfer session is started. The DCP is set up by putting
tion. out a OOH (data register address) to the 1/0 address mentioned
Master Port Address Strobe (MAS) is only generated if the above.
CPU executes an output instruction to a specific 1/0 address Figures 5-3.2c and 5-3.2d show data read and write cycles.
(CS2 active, Ao=Low) (Figure 53.2b) Address Latch Enable Figure 5-3.2e shows DMA data read and writes cycles.
of the CPU (ALE) cannot be used for the generation of MAS

ADDRESS ____ __ ~X~ V_Al_ID__~X~ ______________________________

: -~----+---C?~'+-_-_-_-_-_-_-_-_-_~_1_---,9==
DMAClK,
DCP ClK

R/W

Ao (lATCHED)
------------~-r------------~~----------~~-----
READY
(ASYNCHRONOUS TO CPU)

\ ......- ....../

02188A-55

Figure 5-3.2b Address Latch Cycle Timing (CPU-DCP)

5-12
ADDRESS _ _ --'X VALID X'-_________________

DMACLK,
DCPCLK

R/W

~
J I
Ao

READY
----' /

!/'A,-----,
----------~----~

02168A-56

Figure 5-3.2c Data Write Cycle Timing (CPU-DCP)

5-13
ADDRESS ______J)(~ ___V_A_Ll_D__~)(~________________________________________
ALE --.I

DMAClK,
DCP ClK

R/W

Ao

02188A-57

Figure 5-3.2d Data Read Cycle Timing

5-14
CPU ClK,
DCPClK

R/W

190ns

DATA
WRITE
CYCLE

DATA

R/W

DATA
READ
CYCLE

215ns

DATA

02188A-58

Figure 5-3.2e DMA-DCP Timing Diagram

5-15
PAL16R4 PAL DESIGN SPECIFICATION
DCP049 JUERGEN STELBRINK 8-12-83
8088- AM9517 (DMA)- AMZ8068 (DCP) INTERFACE DEVICE
ADVANCED MICRO DEVICES

CLK1 CLK2 jCS JIOR JIOW AO RW jDACK NC GND

JOE jMDS READY jQ1 jQ2 jQ3 jMAS NC CLK VCC
MAS := IOW*jIOR*CS*jAO*jQ3*jMAS ; ~~STER PORT ADDRESS STROBE

Q1 ,- CS*IOR*jIOW*RW*jQ2 +
CS*IOW*jIOR*jRW*jQ3 +
DACK*IOR*jIOW*RW*jQ2 +
DACK*IOW*jIOR*jRW*jQ3

Q2 := CS*IOR*jIOW*RW*Q1 +
CS*IOR*jIOW*RW*Q2 +
DACK*IOR*jIOW*RW*Q1 +
DACK*IOR*jIOW*RW*Q2
Q3 := CS*IOW*jIOR*jRW*Q1 +
CS*IOW*jIOR*jRW*Q2 +
DACK*IOW*jIOR*jRW*Q1 +
DACK*IOW*jIOR*jRW*Q2

MDS CS*AO*IOR*jIOW*RW + MASTER PORT READ

DACK*IOR*jIOW*RW +
Q2*AO +
CS*AO*IOW*jIOR*jRW*jQ3+ MASTER PORT WRITE
DACK*IOW*jIOR*jRW*jQ3

jREADY CS*jAO*IOW*jIOR*jRW*jQ3+ ADDRESS LATCH CYCLE

CS*AO*IOW*jIOR*jRW*jQ3 + DATA WRITE CYCLE
CS*AO*IOR*jIOW*RW*jQ2

jCLK CLI<'2 DCP CLOCK

FUNCTION TABLE

CLK1 CLK2 jCS JIOR JIOW jD~CK AO RW CLK jMAS jMDS READY jQl jQ2 jQ3

j R
C C j j D j j E
L L j I I A C M M A j j j
K K C 0 0 C A R L A D D Q Q Q
1 2 S R W K 0 W K S S Y 1 2 3 COMMENT
-------------------------------------------------------------
CLOCK GENERATION
X L X X X X X X H X X X X X X
X H X X X X X X L X X X X X X
ADDRESS LATCH
C X H H H H L L X H H H H H H CPU
X X L H L H L L X H H L H H H

5-16
 C X L H L H L L X L H L L H H
C X L H L H L L X H H H L H L
C X H H H H L L X H H H H H H
READ DATA
X X H H H H H H X H H H H H H CPU
X X L L H H H H X H L L H H H
C X L L H H H H X H L L L H H
C X L L H H H H X H L H L L H
C X L L H H H H X H L H H L H
C X H H H H H H X H H H H H H
X X H L H L X H X H L H H H H CYCLE S3 (DMA)
C X H L H L X H X H L H L H H
C X H L H L X H X H L H L L H CYCLE S4
C X H H H H X H X H H H H H H CYCLE S2
WRITE DATA
X X L H L H H L X H L L H H H CPU
C X L H L H H L X H L L L H H
C X L H L H H L X H H H L H L
C X H H H H H L X H H H H H H
X X H H L L H L X H L H H H H CYCLE S3 (DMA)
C X H H L L H L X H L H L H H
C X H H L L H L X H H H L H L CYCLE S4
C X H H H H H L X H H H H H H CYCLE S2
INVALID CYCLES
X X L L L H H H X H H H H H H
X X L L H H H L X H H H H H H
X X L H L H H H X H H H H H H
----------------------------------------------------------------
DESCRIPTION:

THIS PAL GENERATES ALL NECESSARY BUS CONTROL SIGNALS, TO

INTERFACE A 8088 CPU AND A AM9517 DMA CONTROLLER TO THE AMZ8068
DATA CIPHERING PROCESSOR. THE MAXIMUM SYSTEM CLOCK FOR THE DMA
CONTROLLER AND THE DCP IS 4 MHZ, THE SYSTEM CLOCK OF THE CPU CAN
BE UP TO 8 MHZ. THE DEVICES ARE WORKING ASYNCHRONOUSLY.

INPUT SIGNALS:

CLKl, DMA CLOCK

CLK2

/CS CHIP SELECT FOR THE DCP, GENERATED BY A DECODER LOGIC

/IOR INPUT/ OUTPUT READ

/IOW INPUT/ OUTPUT WRITE

AD LEAST SIGNIFICANT BIT OF THE Z80 ADDRESS BUS TO SELECT

THE TYPE OF OPERATION:
AO LOW SELECT DCP REGISTER FOR NEX'i' DATA CYCLES
(ADDRESS LATCH)
AD = HIGH READ OR WRITE INTERNAL REGISTER

5-17
 (DATA TRANSFER TO CONTROL, MODE, INPUT OR
OUTPUT REGISTER)
/DACK DMA ACKNOWLEDGE FROM DMA CONTROLLER, TREATED AS /CS=LOW
AND AO=HIGH

RW READ/ WRITE SIGNAL STORED IN A EXTERNAL LATCH, TO ALLOW

A DMA OPERATION WITHOUT WAIT STATES. THIS SOLVES THE
PROBLEM OF THE SETUP TIME OF MR/W OF THE MASTER PORT TO
MDS GOING ACTIVE. THE STATUS OF THIS SIGNAL MUST AGREE
WITH /IOR OR /IOW OR THE PAL GENERATES NO STROBES.

OUTPUT SIGNALS:

CLK INVERTED DMA CLOCK FOR THE DCP

/MAS MASTER PORT ADDRESS LATCH ENABLE, ACTIVE DURING ADDRESS

LATCH CYCLES TO LATCH THE REGISTER ADDRESS ON MPl AND MP2
(2 LINES OF THE MASTER PORT BUS) AND THE STATE OF /MCS
IN. THE DCP STORES INTERNALLY THE ADDRESS AND CHIP SELECT
TO THE NEXT ADDRESS LATCH CYCLE

/MDS MASTER PORT DATA STROBE, TO TIME DCP DATA TRANSFERS

/Ql, INTERNAL USED STATE SIGNALS (DO NOT CONNECT). Ql IS ACTIVE 2

/Q2, CLOCK CYCLES IN ALL CYCLES. IT IS USED TO GENERATE THE DELAYED
/Q3 Q2 AND Q3. Q2 IS ACTIVE IN A DATA READ CYCLE. IT ALLOWS /MDS
TO BE ACTIVE UNTIL /IOR HAS GONE INACTIVE. Q3 IS ACTIVE IN AN
ADDRESS LATCH OR DATA WRITE CYCLE. Q3 DISABLES READY AND /MDS
IN THE SECOND HALF OF THE CYCLE.

~8
5.3.3 8088 AND Am9513A SYSTEM In this design, certain simplifying constraints have been made.
Word operations are only allowed during command chaining
TIMING CONTROLLER
operations when the Am9516 is Bus Master. During Slave
This interface is very similar to the 8086 to Am9513A interface Write operations, the first byte output to the Am9516 must have
except that the Data bus is 8-bit wide instead of 16-bit wide. an odd address, and the following second' byte an even ad-
Figure 5-3.3a shows the block diagram for this interface. The dress. Conversely, during a Slave Read cycle, the first byte
dip-switch at the B-port of the Am29809 allows the designer to read from the Am9515 must be at an even address and the
decode any I/O address for the application. If a fixed address second at the next higher odd address. Furthermore, for both
decode is required, the B port lines can be selectively slave and master operations, the system must use the latched
grounded or left open, (as the part has internal pull-up). Note Ao (LAo) from the AmPAL22V10 as its sole Ao. That is, this
that Word Writes should not be used for this interface as they LAo must circumvent any address latching to memory and so
will violate Am9513A recovery time specification. is to be used directly.

5.3.4 8088 TO Am9516 UDC As can be seen from the figures, the AmPAL22V10 manip-
INTERFACE ulates the control signals to the transceivers and latches so
that bytes can be funneled into words during Am9516 Com-
Figure 5-3.4a shows the Data bus and Control Interface be-
mand Chaining operations and Slave Writes, and words can be
tween an 8088 microprocessor and an Am9516. This interface
funneled into bytes during Am9516 Slave Reads. Also, LAO is
is accomplished by using an AmPAL22V10, a 74LS161
alternately toggled in order to provide the dual address (16-
counter, an Am2952 bidirectional I/O port, and an Am2949
bits) during chaining operations.
bidirectional transceiver. Figures 5-3.4c and 5-3.4d show the
PAL device timing for both the Bus Master and the Bus Slave Figure 5-3.4e shows the PLPL equations and resulting sum-of-
cases. products equations for the design (PLPL is a higher level "C-
like" language for PAL devices). For those not familiar with "c"
or Pascal, the intermediate sum-of-products form shows the
equations in Boolean form.

AO-A15 ADDR
A3-A8 A1-Ae
+5V
6 e

YO-Y7 A Sa ,Sl
ALE AM2956 5
MN/MX G AM29809 CUT 1-5
B EO
8088
SRC 1-5
ID/M
AM9513A
A8-A15

ADO-AD7~ __________________________________-, DO-D7

roUT
~----------------------------------~~RD

~--------------------------------~~R
Xl X2

•See text, eo pF eo pF
~ ~
02188A-59
Figure 5-3.38

5-19
 Vee

OC

I l
MIIO HOLD BREQMIil)
HLDA BACK
ALE ALE

Rij ALE HLDA IBW

IRD BIW
8088 9516
WI! IWR IDS liS
~ READY AmPAL
RESET 22V10
IRW
IWAIT
RIW
WAIT
_8088_9516 CK
LAo CLOCK
RESET
>--t--t RESET Ao--t AD
ISELIl
CS ~
ADO-AD7 So 5, 52 IA IB IC /D ADo-AD15
,
/). J'.

C~
16
QA QB Qe

~,
L Q 74LS161
D CLOCK
CLEAR
i-"~8
1 Vee
P T LOAD

t--
,"" 8

7_
_"'Ii
V
1 LT ~49
2952
CEs OEIis ~
i!ER OEIiR
CDR-S
II
T

~
CLOCK
Y 8

":;"~"

02188A-60

Figure 5-3.4a The Am9516 UDC to 8088 CPU Data Bus and Control Interface

5-20
 r---------- -
-----------SLAVEWRITECYCLE-- 1--- - SLAVE AEAD CVCLE· - - - - - , - - ----j
'" -.lI nL-____nL-___----'n I

.
LATCHED

02188A-61
Figure 5-3.4c The Am9516 UDC to 8088 CPU Bus Slave Timing

Am9516
CLOCK

'" -.lI__________-----'nL..____-'nL-_____

xxx
L -_ _ _ --'r-IL..___-----'I
/

L-_-----'r--
L..I____---'r
LJ LJ

L __ _ _ _ _ _ _ _ _ _~L__ _ _ _ _ _ _ _ _ _ --'r__
02188A-62
Figure 5-3.4d The Am9516 UDC to 8088 CPU Bus Master Timing

5-21
DEVICE _8088_9516 (pa122VIO)

"This is a PLPL file to implement an interface between the 8-bit

8088 and the 16-bit Am9516. This design assumes that the Am9516
is programmed for byte operations and so only accesses 16-bit
words during chaining. -James Williamson"

PIN

CK 1 IRD 23
S[0:2J 2:4 IWR 22
AO 5 LAO 21
ISEL 6 IDS 20
ALE 7 IRW 19
HLDA 8 IWAIT 18
IBW 9 IA 17
READY 10 IB 16
RESET 11 Ic 15
ID 14;
BEGIN

IF (RESET) THEN ARESET();

II ============================================================== II

"This section defines the wiggles when the Am9516 is Bus Master"
II ============================================================== II

IF (HLDA) THEN ENABLE();

IF (/s[2J * HLDA) THEN BEGIN
IF (/S[lJ * Is[OJ) THEN
LAO ICK * BW + IBW * AO * ALE +
IBW * LAO * IALE
ELSE
LAO BW + IBW * AO * ALE +
IBW * LAO * IALE
END;
IF (HLDA) THEN
CASE (S[2:0J)
BEGIN
1) BEGIN
RD IRW * DS
A IBW * IRW * ICK
WR IBW * RW * DS
C IBW * RW
WAIT 1
END;
2) BEGIN
RD IRW * DS
B BW
A IBW * IRW
WR IBW * RW * DS
C IBW * RW
WAIT BW
END;

Figure 4-3.4e

5-22
 3) BEGIN
RD /RW * DS * B
B BW * CK
A /BW * RD
WR /BW * RW * DS
C /BW * RW
WAIT BW
END:

5) BEGIN
RD /RW * DS
A /BW * /CK
WAIT BW
END:

6) BEGIN
RD /RW * DS
A BW
END:
7) BEGIN
RD /RW * DS
A /RD
END:
END:
n=================!::=============================================11
"This section defines the wiggles when the 8088 is Bus Master"
11========::::========================================================11

BEGIN

LAO AO * ALE * SEL +

LAO * /ALE * SEL
B LAO * WR * SEL
A /LAO * WR * SEL
DS A +
/LAO * RD * SEL
C /LAO * RD * SEL
D LAO * RD * SEL
END:
END.
Figure 4-3.4e (continued)

mode operation is the need to convert HREQ and HACK into

5.3.5 8088 TO Am9517A INTERFACE the RQ/GT protocol. Figure 5-3.5c shows the PAL equation for
This interface assumes the Am9517A to be closely coupled to the PAL16R4 used in the Max. mode.
the 8088 (i.e. on the same board). Additional buffers may be
necessary for larger systems. The upper address latch is really Note that even if both the 8088 and Am9517 A are 5 MHz parts,
a page register, which the CPU loads. This provides the upper a common clock cannot be used since the 8088 clocks duty
address when the Am9517A is bus master. This page register cycle does not meet Am9517A requirements. Sometimes add-
is necessary since the Am9517A only supplies 16 bits of ad- ing another oscillator can be saved, as in the case of an 8 MHz
dress compared to the 8088's 20 bits. CPU. By dividing the clock by 2, the DMA can be operated at
4 MHz.
Diagrams in Figures 5-3.5a and 5-3.5b show the 8088 to
Am9517A interface in both Max. and Min. modes. When oper- 5.3.6 8088 AND Am9519A INTERRUPT
ating the 8088 in Max. mode, the 8288 can be used to produce
MRDC, MWTC, IORC, and IOWC without the addi-
CONTROLLER INTERFACE
tional logiC required in the Min. mode. A problem with Max. See Chapter 4

5-23
8284

CLOCK
......
V
READY~

READY
74lS03
O2
1,
ClK
HOLD I- HREQ ClK
I
rl....J
74lS03
At
RQ;GTo I A2 AmPAL 16R4
88/17.PAL

RQ;GT
11
6E
~
t CEN
lOB
CLK 8288_ _
AEN HlDA

ClK -'--
S2
-
S , _ S,
S2
MRDC
MWTC
MRDC
MWTC
10RC 10RC
So- S. 10WC 10WC

HACK

.l Am9S17A-S

ALE lE OE
ADDRESS
DECODER I- CS

~ AO

8088
SMHz
r-v 29846
'-~ A7

lE ADSTB
A
A,S f - - -
A8f--- I--- , 29846
i'r-
-
OE

t .A
..... ~ AEN
AD7 >---- I-- ' - - 07
ADO I--- DO

~S-
U
0 0 -07

J.
r lE

Oe
29846

""
AO-A7
7V Aa -A15 :r<
HACK
CS lOW
I
OE
A,. .1\, ~Al'
A,. --y 29846 V A,.

AlE- lE

02188A·63

Figure 5-3.5a

5-24
 CLK

,
8284A

READY PCLK ~

CLK READY _
RD B
Vee
Y,
1 lOR

>-- E4
>-- E3 lOW
- POL
Y.

WR A 2921

- E,
f- E.
Ys iiiiDC

>-- OE,
Y6 MWTC

WiD
""7 ADDRESS
DECODER
I cs
C 0E2
I
HLDA HACK

~h
HOLD IQ HREQ
Am9517A-5

ALE LE
OE eLK~ CLK

~ 29846 ,., Ao
I--
rY
8088
SMHz LE ADSTB

A,s
As
f--
f-- I-- r-

OE
29846

k-
I .A
..... I--- AEN

~
Atry I-- ~ try
ADo I-- Do

"" ~

riLE
0
7-
A 10E
29846

" 7'
Do-try
"
Ao-A7
7 "
As-A15 n
HACK--,
cs lOW
OE

'"
A,.
29846 A 19 -A16

ALE~
A'6 V
LE

021B8A-64

Figure 5-3.5b

5-25
Type Am9517 PAL
PAl16R4
8088 to Am9517A Interface
ClK IRQGT HOLD NC NC NC INC INC INC GND
IOE INC INC IHlDA ID2 IR2 IR1 INC INC Vee
R1: =HOlD
R2: =/R1
D2: =R1
IHlDA: =/R1 +/D2*/HlDA+/RQGT*/HlDA

Figure 5-3.5c

5·26
6.0 INTERFACING TO THE 68000 6.2.0 THE 68000 AND AmZ85XX
PERIPHERALS
6.1 68000 OVERVIEW The Am8500 series of peripherals, as well as others, require
The 68000 has an asynchronous, 16-bit, bidirectional, data C S to be valid before R D goes LOW. The timing of the 68000
bus. Data types supported by the 68000 are: bit data, integer does not guarantee this; therefore, it is necessary to delay the
data of 8, 16, or 32 bit, 32 bit addresses and binary coded falling edge of LDS to meet this requirement. We are using the
decimal data. It can transfer and accept data in either words or AmZ8530 here to illustrate the interface between the 68000
byles. The DTACK input indicates the completion of a data and an AmZ85XX device. The AmZ8530 Serial Communica-
transfer. When the processor recognizes DT ACK during a read tion Controller is an 1/0 device that offers user-programmable
cycle, the data is latched and the bus cycle terminates. When features for high end applications. It supports all advanced
DT ACK is recognized during a write cycle, the bus cycle also protocols: HDLC, SDLC, and IBM Bisync. It has a transmit rate
terminates. An active transition of DT ACK indicates the ter- of up to 1.5 Mbps. It has a programmable baud-rate generator
mination of a data transfer on the bus. All control and data lines which reduces chip count and cuts down on board real estate.
are sampled during the 68000's clock high time. The clock is Other features include built-in digital phase-lock-loop, auto
internally buffered, which results in some slight differences in echo, and local loopback.
the sampling and recognition of various signals. The 68000
The Am29809 Comparator and the Am29806 Com-
mask sets prior to CCI and allows DTACK to be recognized as
parator/Decoder provides high-speed address selection as
early as S2, and all devices allow BERR or DTACK to be
well as an open collector acknowledge driver. This allows
recognized in S4,S6, etc., which terminates the cycle. If the
memories and peripherals to be conveniently wire ORed to the
required setup time is met during S4, DT ACK will be
processor's DT ACK pin. This interface does not provide a
recognized during S5 and S6, and data will be captured during
hardware reset therefore, it is necessary to do a dummy read
S6. DTACK signal is internally synchronized to allow for valid
to the control port before issuing a software reset. This insures
operation in an asynchronous system. If an asysnchronous
the internal state machine is in the proper state to sequence
control signal does not meet the required setup time, it is possi-
through the Address Cycle and then the Data Cycle.
ble that it may not be recognized during that cycle. Because of
this, synchronous systems must not allow DTACK to precede
data by more than 40 to 240 nanoseconds, depending on the
6.2.1 THE 68000 AND AmZ8530
speed of the particular processor. 1/0 is memory-mapped, i.e., WITHOUT INTERRUPTS
there are no special 1/0 control signals, any peripheral is Implementation of an interface without interrupt is straightfor-
treated as a memory location. ward. INTACK must be tied High when not in use and the shift
register provides a means for inserting Wait States.
DMA: This Bus is requested by activating the BR input of the
68000. Bus Arbitration is started by the BG output going active. Figure 6-2.1 shows the interface between the 68000 and the
The Bus is available when AS becomes inactive. The request- AmZ8530. The AmZ8530 SCC is the fastest available serial
ing device must acknowledge bus mastership by activating the I/O in the market today. It supports all advanced protocols and
BGACK input to the CPU. has a number of user programmable features that provide
design flexibility.
The 23-bit address (At ... A23) is on a unidirectional, three-state
bus, and can address 8 M words (16 M byles) of memory or The data bus between the 68000 and AmZ8530 are directly
1/0. It provides the address for bus operation during all cycles, linked together. The Am29806 decodes the address and gen-
except the interrupt cycles. During interrupt cycles, address erates CS for the peripheral and produces AN Y E, which is
lines AI, A2 and A3 provide information about the level of used by the 74LS164, to generate Wait States. The 74LS164
interrupt being serviced. Instead of Ao and BYTEIWORD, controls the number of wait states by the '''(5"'' input which in
there are two separate data strobe lines for the two byles in a turn controls the DTACK signal to the CPU. This allows RD
word. A note of caution here, the 68000 treats the MSB of the and WR to obtain the required 400 ns width. At generates the
lower byle as an even byle, or word address. The same goes cill input to the AmZ8530 while the remaining address lines
with processors such as the Z8000. Processors such as the are connected to the Am29809 address comparator.
8086 treats the lower byte as the odd byle. The Am29809 Comparator and the Am29806 Com-
Interrupt is requested by activating any combination of the in- parator/Decoder provides high-speed address selection as
terrupt inputs to the 68000 (IPLO ... 2), indicating the encoded well as an open collector acknowledge driver. This allows
priority level of the interrupt requester (inputs at or below the memories and peripherals to be conveniently wire-ORed to the
current processor priority are ignored). The 68000 automati- processor's DT ACK pin. This interface does not provide a
cally saves the status register, switches to supervisor mode, hardware reset; therefore, it is necessary to do a dummy read
fetches a vector number from the interrupting device, and dis- to the control port before issuing a software reset.
plays the interrupt level on the address bus. For interfacing
with old 68000 peripherals, the 68000 issues an Enable signal
at one-tenth of the processor clock frequency. There are a
number of AMD proprietary third generation peripherals that
can be interfaced to the 68000 CPU, to improve system perfor-
mance. This chapter deals mainly with the interfacing of the
68000 and some of the AMD proprietary peripherals.

6-1
 74lS04
A••
......
Y
-!
A ..
An "- -.....
~ II I
V

I
,--- A Q. O. Oc OD

I e--
e--
8

CUi
74LSl64
CLK
--
c-
I-.
....

-
A,.
ANYE
A. Y 74LS04
68000 V AmZl530

DTACK .~ iiCK
Cs

A, Die

A. Alii
~
iili
~u-L
LOS

J. ~7'LS04
-- I
~
;J D

C l K _ CP
7.LSI.
0

'---
~
R/W

- '" Wii

02188A-65

Figure 6-2.1

6.2.2 THE 68000 AND AmZ8530 WITH The 74LS164 is added to generate the correct timing during an
Interrupt Acknowledge cycle. It allows 5 CPU clocks for the
INTERRUPTS
daisy-chain to settle before it generates R D to put the vector
This example addresses the problems of interfacing the 68000 onto the bus. The daisy-chain is implemented by using the lEI,
and AmZ8530 with interrupts. The circuit configuration is basi- lEO pins (not shown in the diagram) on the 8500 peripherals.
cally the same as the design without interrupts. The time allowed for the daisy-chain to settle is a function of
The 74LS148 and the two 74LS138s assume there are other the number of devices in the chain; thus, the allowance of 5
interrupting devices which are not compatible with the interrupt clocks used here is arbitrary. The 74LS164 also generates
daisy-chain of the 85XX Family. The 74LS148 and one of the DT ACK. A block diagram of this interface is shown in Figure
74LS138 can be eliminated if this is not the case. 6-2.2a. Timing diagram is followed in Figure 6-2.2b. It is more
The first 74LS138 acts as a status decoder; it is gated with AS straightforward to use the Am9519A Interrupt Controller in-
to de-glitch the outputs. The second 74LS138 decodes the stead of the on-Chip interrupt features. However, this approach
Interrupt Acknowledge priority level, allowing a two- does not allow the programmer to take advantage of some of
dimensional priority scheme. Daisy-chain can be used to the 85XX family's time-saving features.
resolve priority at any given priority level while the CPU
resolves priority between levels.

6-2
 SIP SWITCHES OR SOLDER

""'"
--
BRIDGES FOR SETTING
A"
74LS04 J ADDRESS

G
f--<> 0 -
Am29809 f--<>~
~o-
CONNECT FOR DESIRED
NUMBER OF WAIT STATES
8/ "- ':7

~
A"

~~
All I 74lS04
/ I' Ao .----A
'""
osc ~~
CLK CLKj2 f--<> 0-

~
fOUT 08 Oc DO

CLK
1 CLK_ CLK
-
14lS164

A
vccT G
f--<>
CLR B

~
alACK ACK
f--<> 1
~
Am29806
A.lO
.......
0/ ...
':S ~ ~74LS04
··>.·.····7i\·····<D :
As
A,
I Ao f--<>
f-o 0
M
5,
A, So CLK/2- PCLK

0 EOUT
ANYE
CS
It)
0
~
I
0 A,
~2
D/e

CO r=D-
74LS02

~W E
AD

CD LOS
~2

.t>.74LSO'
-<L

74lS32
CLK -
74LS74

CP
PRE
'--r---
c:c
--
~
R/IN
WR
.A 0C
74l;:0

IPL o I- Ao
EI

°H
1 iNT
I-
-}
A,

:=
IPl,
74LS148 2
OTHER
IPL 2 I- A, 3

F:
INTERRUPTS DE
4
74LS04 74LS164 Dd--

AS

r--
i
1
1~ t- ClR CLK

INTA

P-}
FC o A A,- A
FC, r-- B A2 - B 2

FC, ..--- C
74lS138

7
INTA A , _
C
I G2A
74LS138
,
4
P--
b-
INTA
FOR OTHER
INTERRUPTING
DEVICES
ClK-t:>o--
74LS04

02188A-66

Figure 6-2.2a Am8530 to 68000 Connection with Interrupts Using SSI and MSI

6-3
 T, TW TW TW TW T~

',-.., -----(

FCO-FC02

RD------__________________________________ ~

DATA IN ---c('-_--J),......--

02188A·67

Figure 6-2.2b Interrupt Acknowledge Timing

6-4
6.2_3 THE 68000 AND AmZ8530 WITH The timing during register programming is not shown. The PAL
device allows selection of one or two Wait States by making
INTERRUPTS VIA A PAL DEVICE Wo High or Low respectively. The table below shows the ap-
This example shows how a Programmable Array Logic (PAL) propriate number of Wait States as a function of CPU speed.
device simplifies the task of interrupt generation compared to
the MSI implementation. The block diagram for the interface Part CPU Speed Wait States
via a PAL device is shown in Figure 6-2.3a. The timing diagram
85XX 4 MHz 1
(Figure 6-2.3b) illustrates the Interrupt Acknowledge cycle. As
85XX 6 MHz 2
in the other designs, R D is generated during Interrupt Acknowl-
85XXA 8 MHz 2
edge to place the vector on the bus.
85XXA 10 MHz 2

PAL device equations are shown in Figure 6-2.3c.

74LS04
....
A"
...
JG

A" ".L J-,

"
....•..... .· · .• • •.• J .. / \ . i i i ... ; : Am29809

" "0
A011
/
four

"0 "L
1
/.~
A.S G
it.·. .·.· .·. .·.·.·.·. . ·. .·.· ·.· . . . . . . · .. . . . . . ..•..
's
A,
/ V AO
51 Am29806 0
So
M
-
A3 Eo CE

0 __
OOTACK
~VCC
Act( ANYE
CI_
Il)
0 IPL 2 .J
vcc
CO
IPL, J TVCC
N
r6 'P'-o !NT

E
CLOCK

LOS
2 CLOCK

LOS
CS
ACt< t - - -
-
RD
\VA
-
RD
\VA
c:(
R/W RW AmPAL 16R4
68K85XX
TVee
AS AS Wo
FC, FC, DE
FC, FC,
-
FCo FC o INTA INTA

A, DjC
0, A 0/ Do'

D~~ ...... ....

......•.. :1:......... ·.. L.!i2£:.
/
•...••..•••. :..:. 2::::........ > .. ii ... ............. ;) Do
V

02188A-68

Figure 6-2.3a 68000 to ArnZ8530 Connection Using a PAL

6-5
---- .. -~.-- .. ---_.
AS

DS

RD

PAL

02188A-69

Figure 6-2_3b

6-6
 PAL16R4 PAL DESIGN SPEC
PAT 002 JOE BRCICH 9 SEPT 83
68000 TO 8500 OR 9500 PERIPHERALS
ADVANCED MICRO DEVICES
CLOCK ICS RW I LOS IWO lAS FCO FCl FC2 GND
10E IINTA lACK IC IB IA 'IDLOS lRO IWR VCC
A :- A*/B + B *C + lAS

B :- A*/C + IA*C +
lAS
C :- IA*/B*AS + B*C*AS
DLOS :- LOS
RD - LOS*DLOS*RW*/INTA + A*C*INTA*AS + A*/B*INTA*AS
WR - LOS * IRW

INTA - FCO*FC1*FC2*AS
ACK - /INTA*/A*/B*/C*/WO + /INTA*/A*/B*C*WO +
INTA*/B*A + ACK * LOS
DESCRIPTION
THIS PAL DEVICE INTERFACES 85XX TYPE PERIPHERALS TO THE
68000 MICRO PROCESSOR. IT INSERTS 1 OR 2 WAIT STATES AS
SELECTED BY IWO-O IS ONE AND IWO-l IS TWO WAIT STATES. FOUR
WAIT STATES ARE INSERTED DURING INTERRUPT ACKNOWLEDGE CYCLES.
ALSO THE RD OUTPUT GENERATED DURING INTA IS A FUNCTION OF THE
INTERNAL STATE MACHINE AND NOT A FUNCTION OF LOS. OE CAN BE
LEFT OPEN SINCE THE FLIP FLOP OUTPUTS ARE NOT USED DIRECTLY.
THE FALLING EDGE OF RO IS DELAYED IN ORDER TO GUARENTEE
THE CS TO RD SETUP TIME REQUIREMENTS.

Figure 6-2.3c

6.3.0 68000 AND AMD PROPRIETARY The Am29809 Comparator and the Am29806 Com-
parator/Decoder provide high-speed address selection as well
PERIPHERALS INTERFACE as an open collector acknowledge driver. This allows
AMD manufactures a large number of microprocessor periph- memories and peripherals to be conveniently wire ORed to the
erals, and they can be interfaced with a number of CPU types, processor's DTACK pin.
the user is advised to verify that the interface specification is
met. Two of the important parameters are set-up and hold
6.3.1 68000 AND Am7990 LANCE
times to insure that peripherals will work with both fast and
slow CPU's. In some cases the insertion of a Wait State is all
INTERFACE
that is required. In the following sections, the interface between The design of the LANCE has made it easier for the user to
a number of the AMD proprietary peripheral products with the interface the device with demultiplexed buses. The example
68000 are discussed. shown here is an interface to be compatible with an 8 MHz or
faster 68000 (Figure 6-3.1 a). The two flip-flops are needed to
adapt the LANCE bus request handshake to the 68000.

6-7
 ADDRESS BUS DATA BUS
,. . vee
lr lr ~
~

29827
II 29827 I 29863 ; ~
---<

A23-A16
l' A23-A16
II "- ADR
A1S-A1
...
{} I
29809
I 29843

OE LE
IA
~
AD1S-ADo

DAi:O
D1S-Do
... I tt DALi
rveel
CS
DTACK READY
AS ALE
'--- DTACK FROM
S~M
BR Q D HACK

68000
CP 51 LANCE
Au lAS ICSIRBITB

--
Am7990
-T- ...--- BR
ICLR2 IHOLD HOLD
BGACK IBGACK

~ IDAS DAS

,fT PR

CP Q -
AmPAL16L8
68K90.PAL

ICLR

iG IBG

UDS IUDS
LoS !LDS
R/W

1PLo --- I BYTE RW

IPL1

1PL2
=
74LS

=142

Tvee
READ
BYTE

-
_--0

TO SYSTEM
FCo iNTR
74LS
F~l 138 --
INTA
FC2

VPA -11
02188A-70
Figure 6-3.1 a

6-8
Autovectoring is used since the Am7990 does not return a CPU overhead. The diagram for the 68000 and Am8052 inter-
vector during interrupt acknowledge cycles. The BYTE and face is shown in Figure 6-3.2a. Both Bus Masters support a
DAS signals of LANCE are used to generate the UDS and LDS 16-bit-wide data bus and a 24-bit linear addressing space (if
when LANCE is in Bus Master mode; the UDS and LDS is used the Linear/Segmented bit in the Am8052 Mode Register 1 is
to generate the DAS when LANCE is in Bus Slave mode. It set to "1 "). The control bus signals of the Am8052, however,
takes two latches to demultiplex the LANCE address/data lines differ from that of the 68000's and need to be translated
to adapt to the 68000 address bus. The flip-flops can be bidirectionally. An easier approach (not shown here) is to con-
replaced by an Am22V10 to minimize parts count. Equations vert the 68000 signals to Am8052 signals. Since the 68000 is
for the AmPAL16L8 are shown in Figure 6-3.1b. never a slave, the logic is simple. This approach is feasible
only if most are not 68000 peripherals.
The Am8052 provides two basic slave modes: the latched
6.3.2. 68000 AND Am8052 CRT mode for systems with multiplexed address/data buses and the
CONTROLLER INTERFACE unlatched mode for systems with demultiplexed address/data
One of the deSigner's most challenging tasks is to interface two buses. In this interface application, the Am8052 operates in the
generically different Bus Masters. An example would be the unlatched mode because the address and data buses of the
68000 microprocessor and the Am8052 CRT Controller. The 68000 are demultiplexed. In the unlatched slave mode, Ad-
Am8052 CRT Controller is a general purpose interface device dress Strobe (AS) is kept asserted throughout the entire bus
for raster scan CRT displays. The CRTC provides efficient cycle, making the internal latches for Chip Select (CS) and
manipulation of complex character formats and screen Control/Da ta (Cm) transparent. AS is driven Low by an open
structures to allow sophisticated text display without undue collector inverter connected to BAI. This forces AS to go Low
whenever the Am8052 is not in control of the bus.

PAL16L8 JOE BRCICH

PAT002 2 FEB 84
68000 TO LANCE INTERFACE
ADVANCED MICRO DEVICES
lAS RW BYTE IHOLD NC IBG AO NC IBGACK GND
ICS ITB IUDS IDAS ICLRl BR ICLR2 ILDS IRB VCC
IF (lBGACK) RB - CS*RW*UDS + CS*RW*LDS
IF (lBGACK) TB - CS*/RW
IF (BGACK) UDS
- DAS*/AO*BYTE + IBYTE*DAS
IF (BGACK) LDS
IF (lBGACK) CAS - UDS*LDS
- DAS*AO*BYTE + IBYTE*DAS

CLRl
-
CLR2 - BGACK
IAS*BG
,DELAY
IBR - IHOLD
DESCRIP'l'ION
THE GOAL OF THIS INTERFACE WAS TO BE COMPATIBLE
WITH 8 MHZ AND FASTER 68000'S WHILE MINIMIZING PARTS COUNT.
THE AM22V10 COULD BE USED TO ELIMINATE THE TWO FLIP-FLOPS
SHOWN. AUTOVECTORING IS USED SINCE THE 7990 DOES NOT RETURN
A VECTOR DURING INTERRUP'l' ACKNOWLEDGE CYCLES.
NOTE PROGRAM BSWP, BCON TO 1 ,AND ACON TO 0 IN CSR3 REG.

Figure 6-3.1 b

6-9
- - - - - - - _ ... - - - - - - - - - - - -
 ADDRESS BUS
DATA BUS

~ 8
o
/ 16
A,
f_----~I ciD

Am29823

AD'5
ADo

f-~---~IAS

D'5-Do~'r _ _ _ _ _ _ _ _ _ _ _- .______r -_ _ _ _~_~__~

~ ~OC
BGACK ...--------------~r_--~~--------~--~--~~----------~--~~.BAI

Vee Q ~ 0W A f Vee Am8052

68000

:~:
d '~r ;,:" ~
Vee FF1R CP 1---+--1-t----------+-------o<C""~
1

.
L---------_+--------~----------t_----..

+-----..-.
BREQ
CS

R/W

AS I--_ _~R .---)-rJ----CCl----<~-+--~. OS

BG I >0---1
......
LDS~~--~------------------~------t_~~~~
UDS 1---------------------~~_--~----__jL..."'" I Vee
R/W~--------------------~f__1--_.------7-4L-S-3-2------------~ t
IPL21 ..-----;:::::::;------~~~--_t------------------~~~----~--~--IN=T=R-Q
FC2 ~-_~I C WAIT
FC, B 74LS138 IO--------+---+---t------------+-------------- INTACK
FCo A Lee

DTACK.~--------------------~~._,--_+----------__i
J () ~
DTACK

02188A·71

Figure 6-3.2a 6S000-AmS052 Interface

6-10
The Am8052 in slave mode can only be accessed as a 16-bit this requirements, BGACK and BAI stay asserted until the
peripheral (word transfers only), This means that both Data Am8052 terminates its OMA burst and releases BREQ, At that
Strobes of the 68000 (LOS and UOS) must be active simulta- time FF2 is asynchronously set and BGACK and BA I are deac-
neously, It is only then that the OR gate asserts OS for the tivated, and the 68000 resumes operation,
Am8052, The driver is enabled when the 68000 is Bus Master The bus arbitration mechanism does not yet support OMA
(BAI High), In Master Mode, both data strobes are driven by preemption, However, Am8052 OMA preemption by external
the Am8052 since the Am8052 does only word transfers, devices can simply be supported by setting FF2 when preemp-
After the Am8052 is initialized and the display is enabled, the tion is desired, The preempting OMA can get the bus after the
Am8052 asserts Bus Request (BREQ) to request the system Am8052 has released the bus, This is indicated when the
bus, To avoid bus contention at the end of Bus Master read Am8052 deactivates BREQ, In this case, BAI being Low is no
cycle, the data bus transceiver (not shown) must be turned off longer sufficient to flag that the Arn8052 has been granted the
before the Am8052 starts driving the address for the next system bus, For proper OMA preemption support, the data
cycle, Timing Parameter 11 allows a turn-off time of 25 ns strobe drivers and the open collector driver for AS must be
which is sufficient for the Am29863 transceiver, controlled by a signal which flags that the Am8052 is on the
The 68000 CPU supports a three-wire bus arbitration mecha- bus, (Note: For the time between preernption (BAI High) and
nism, A peripheral requesting bus mastership asserts a Bus bus release (BREQ High), the Am8052 is still in control of the
Request (BR), see Figure 6-3,2b, The CPU, in response, system bus, The Arn8052 supports vectored interrupts if the
asserts a Bus Grant (BG), At the end of the current bus cycle, No Vector bit in Mode Register 2 is disabled (NV=O), The
the requesting peripheral goes on the bus, The end of the vector is put out in Interrupt Acknowledge cycles (INTACK
current CPU bus cycle is signaled by the Address Strobe going Low, lEI High, and OS Low),
inactive, The combination of Bus Grant active and Address All transactions to the Am8052 must be in words, All transac-
Strobe inactive asynchronously resets FF2 (see Figure 6- tions between the Am8052 and mernory are word operations;
3,2a), thereby asserting BAI for the Am8052 and Bus Grant thus, the Am8052 does not have a Bm line and will always
Acknowledge (BGACK), Resetting FF2 also resets FF1 produce both an LOS anci UOS, Since the design goal of the
asynchronously, which deactivates BA. In response to BR Am8052 restricted the package to 68 pins, an external latch is
becoming inactive, the 68000 deactivates BG, Note that BR required to get a full 24 bits of address, This latch is updated
must be Low for at least 20 ns after BGACK to prevent rear- whenever a 64K boundary is crossed by a special write cycle,
bitration, The inverters and the delay through FF1 must meet

BRO
aos2 =tr-(l---,---r--l?,:l====~-:_/-+--
BR68000 ~(
) ________________- J I .
__
/
BG"aooo
)\
((
\'--_-oJ1
?~\
!
AS68000 I
) -;

PROCESSOR_I ...._-------Ama052 --------,... I-PROCESSOR

02188A-72

Figure 6-3,2b Bus Exchange Timing

6-11
6.3.3 68000 TO AmZ8068 DATA - Clock Synchronization with two Low Cycles after the Data
CIPHERING PROCESSOR INTERFACE Strobes
Figures 6-3.3a and 6-3.3b show the 68000-DCP interface and - About 500 kbyte/sec Ciphering speed
the interface timing. This interface provides a two-chip solution Data transfers between the CPU and the DCP are accom-
to add high speed data ciphering to a 68000 based system. plished by a two-cycle operation. First the address of an inter-
About 500 kbyte/sec are possible in a CPU controlled transfer. nal register is latched in, then the data is transferred. This
The ciphering rate can be increased with a sophisticated DMA causes a small overhead in the initialization phase, but im-
controller, or with several DCPs operating in parallel. The CPU proves the Ciphering rate in a high-speed data Ciphering ses-
operates at 8 MHz and the DCP operates synchronously at sion. The rate of 500 kbyte/sec can be reached only if a
4 MHz. The Interface Controller, a PAL device, generates the high-speed peripheral device is connected to the Slave Port
Address and Data Strobes for the DCP and the Data Acknowl- and the DCP is programmed for dual port configuration.
edge for the CPU. It also divides the CPU clock by two and
The PAL device is programmed to allow only DCP transfers to
synchronizes it to the Data Strobes.
the DCP. The PAL device equations are shown in Figure 6-
The main features of this interface are: 3.3e. Ao must be odd to make the CPU transfer the data on the
- Multiplexed Control Mode Low byte of the data bus. A "0" on A1 indicates an Address
Latch Cycle, whereas a "1" on A1 indicates a Data Transfer
- Demultiplexed address and data bus
Cycle. Ao must be "1" in both cycles.
- Two-Cycle Operation

D7 MP7
0 A L8 .1- 0
0
0

Do
~
,
f ~
r
0
0

MPo
9 28
R/W MR/W

!6
R/W

A23 PROM,
0 ~ 2 14 14
COMPARATOR,
0
CS DCP ClK ClK
0 OR OTHER
A2
r DECODER

68000 AmPAL16R4 AmZ8068

29 7 12 27
A1 MAS AS

AS
6 3
A1

AS
7 4
UDS UDS
8 5 13 26
LDS LDS MDS MDS
-r- Vcc

10 19

P
DTACK DTACK2 CLK1
(OC)
NC "!!.. DTACK1 CLK2
15 8 11 13
CLK CLK OE C/K
1
OSC
8MHz
f MCS

021BBA-73

Figure 6-3.3a ArnZ8068 to 68000 Connection Using a PAL

6-12
 02188A-74
Figure 6-3.3b 68000-AmZ8068 Address Latch Cycle (A1 = Low)

An address decoder generates the Chip Select for the DCP. DATA WRITE CYCLE: (FIGURE 6-3.3d)
The Address Strobe indicates a valid address. The PAL device A Data Write Cycle is performed when Ao is High, AS, CS and
is only activated if the Lower Data Strobe becomes active while LDS are Low. The minimum pulse width of LDS is not sufficient
the Upper Data Strobe stays inactive. This means that data is for the DCP which requires at least 125 ns. One Wait state or a
transferred in MOVE.B instructions with an odd peripheral slower system clock will satisfy this parameter. In this interface,
address. one Wait state is inserted by activating DTACK at the end
The PAL device provides two Data Acknowledge outputs. of S4.
DTACK , is an active Low TTL output. DTACK 2 has the same The DCP clock is synchronized in Data Read or Write Cycles
timing as DTACK , , but is an Open Collector output. (The by forcing it Low when DTACK becomes active. This guaran-
Open Collector output is realized by a three-state output which tees that the DCP clock has a falling edge just before LDS
has only two states. Low or Floating.) (MDS) rises. The delay of the DCP clock to CLK is typically 8
ns for a normal speed PAL device. The delay of LDS to MDS is
ADDRESS LATCH CYCLE typically 12 ns. The delay of LDS to the system clock is 0-70 ns
In this cycle only a Master Port Address Strobe (MAS) is for the 8 MHz version. This results in a delay of 4-74 ns of MDS
generated. Master Port Chip Select (MCS) is tied to Low. LDS to the DCP clock. The DCP requires 0-50 ns when operating at
is sent to the MAS output. The minimum pulse width of LDS is the maximum clock rate.
115 ns; 80 ns are required for the AmZ8068.
This problem is solved by stretching the clock for one cycle.
DTACK is activated with the falling edge of the CPU clock after The DCP clock stays Low for two cycle in the end of a transfer
cycle S2. The CPU inserts no Wait states. DT ACK is deac- cycle. This is done automatically by the PAL device (see
tivated with the first edge of CLK after AS becomes inactive. Timing Diagram).

DATA READ CYCLE: (FIGURE 6-3.3c) A SAMPLE DATA CIPHERING SESSION

The generation of MDS in a Data Read Cycle is similar to the The interface was built on a Motorola 68000 evaluation board.
Data Write Cycle. Because the CPU activates LDS one cycle The instructions are shown below. These instructions were
earlier, there is no need for a Wait State. The minimum pulse executed with the "MACSBUG 1.32" evaluation board monitor.
width of LDS is 240 ns; the DCP requires 200 ns for a Status
Address Register:
Register read. DTACK is activated using the same logical con-
Ao ................. Address Latch Address (A1 =O,Ao= 1)
dition as in the Data Write cycle. Because of the earlier activa-
A1 .................. Data Transfer Address (A1 = 1,Ao= 1)
tion of LDS, DT ACK becomes active earlier and the CPU
inserts no Wait states.

6-13
 So
ClK

R/W

DCPClK

DTACK1,2 ________________- J

02l88A-75

Figure 6-3.3c 68000-AmZ8068 Data Read Cycle (Al = High)

ClK

R/W

DCPClK

DTACK1,2
________________________- J

02188A-76

Figure 6-3.3d 68000-AmZ8068 Data Write Cycle (Al = High)

6-14
PAL16R4 PAL DESIGN SPECIFICATION
DCP044 JUERGEN STELBRINK 8-24-83
68000 - ArnZ8068 (DCP) INTERFACE DEVICE
ADVANCED MICRO DEVICES
CLK2 ICS lAS IUDS ILDS RW Al CLK NC GND
IOE lMAS IMDS DCPCLK NC NC IDTACKl CLKl IDTACK2 VCC
ICLKl CLK INVERT CLOCK TO TRIGGER THE REGISTERED
OUTPUTS WITH THE FALLING EDGE OF CLK
MAS AS*LDS*/UDS*/RW*/A1*CS
MDS AS*LDS*/UDS*Al*CS
IDCPCLK .- DCPCLK + DIVIDE BY TWO
IDTACK1*CS*AS*LDS*/UDS +
DTACK1*/AS*/LDS*/UDS TWO CLOCKS LOW IN
THE END OF A DATA CYCLE

DTACKl := AS*LDS*/UDS*Al*CS + DATA TRANSFER CYCLE

AS*/RW*/A1*CS ADDRESS LATCH CYCLE
IF (DTACK1*AS*CS) DTACK2 DTACKl

FUNCTION TABLE
CLK2 CLK CLKl ICS lAS ILDS IUDS RW Al
DCPCLK lMAS IMDS IDTACKl IDTACK2

I I
D D D
C T T
C C I I P I I A A
L C L I I L U C M M C C
K L K C A D D R A L A D K K
2 K 1 S S S S W 1 K S S 1 2 COMMENT

CLOCK INVERT
X L H X X X X X X X X X X X
X H L X X X X X X X X X X X
DATA WRITE CYCLE
C X X L H H H H H X H H H Z SO
C X X L L H H L H X H H H Z S2
C X X L L L H L H L H L L L S4
C X X L L L H L H H H L L L SW (1 WAIT STATE)
C X X L L L H L H L H L L L S6
X X X L H H H L H L H H L Z S7
C X X H H H H L X L H H H Z SO
C X X H L X H X X H H H H Z S2
DATA READ CYCLE
C X X H H H H H H X H H H Z SO
C X X L L L H H H L H L L L S2

Figure 6-3.3e

6-15
 C x X L L L H H H H H L L L S4
C X X L L L H H H L H L L L S6
X X X L H H H H H L H H L Z S7
C X X L H H H H H L H H H Z SO
C x x X H H H H H H H H H Z S2
ADDRESS LATCH CYCLE
C X X L L H H L L X H H L L S2
C X X L L L H L L X L H L L S4
C X X L L L H L L X L H L L S6
X X X L H H H L L X H H L Z S7
C X X X H H H L L X H H H Z SO

-------------------------------------------------------------------
DESCRIPTION:
INPUT SIGNALS:
CLK2 CLOCK FOR THE REGISTERED OUTPUTS OF THE PAL. IT IS
CONNECTED TO CLKl
CLK 8 MHZ 68000 SYSTEM CLOCK
JCS CHIP SELECT FOR DCP (A2-A23 ARE RELEVANT)
JAS ADDRESS STROBE
jLDS LOWER DATA STROBE USED TO TIME THE MASTER PORT DATA STROBE
JUDS UPPER DATA STROBE HAS TO BE INACTIVE DURING ALL TRANSFERS
Al ADDRESS BIT 1 DISTINGUISHES BETWEEN ADDRESS LATCH AND
DATA TRANSFER CYCLES

Al=LOW ADDRESS LATCH

Al=HIGH DATA TRANSFER

RW READj WRITE CONTROL

OUTPUT SIGNALS:
jMAS MASTER PORT ADDRESS STROBE
jMDS MASTER PORT DATA STROBE
CLKl INVERTED CLOCK CLK
jDTACKl LOW ACTIVE DATA ACKNOWLEDGE FOR 68000
ONE WAIT STATE IS INSERTED IN A DATA WRITE CYCLE
jDTACK2 LOW ACTIVE DATA ACKNOWLEDGE FOR 68000 (OPEN COLLECTOR)
DCPCLK 4 MHZ DCP CLOCK, IT IS SYNCHRONIZED TO THE MASTER PORT
DATA STROBE. IN A DATA TRANSFER CYCLE DCPCLK STAYS TWO
CLK CYCLES LOW TO DELAY THE FIRST RISING EDGE OF THE

Figure 6-3.3e (continued)

6-16
6.3.4 68000 AND Am9513A SYSTEM Figure 6-3.4a shows the block diagram of the 68000-Am9513A
TIMING CONTROLLER INTERFACE interface. This interface was contributed by Carlos Manamer
The Am9513A System Timing Controller is an LSI circuit de- from Wang. The trick here is that CS is tied low and RD and
signed to service many types of counting, sequencing and W R is gated through only when the proper address is selected.
timing applications. It provides the capability for programmable This design inserts one Wait State for write and none for read.
frequency synthesis, high resolution programmable duty cycle This design assumes the CPU to be an 8 MHz device. It should
waveforms, retriggerable digital one-shots, time-of-day clock- also work with 10 MHz and 12 MHz CPU's as well. The key
ing, coincidence alarms, complex pulse generation, high thing to observe, when interfacing the Am9513A to the 68000,
resolution baud rate generation, frequency shift keying, stop- is C S setup time with respect to the falling edge of RD.
watching timing, event count accumulation, waveform analysis Without tying CS low, the falling edge of R D would have to be
and many more. A variety of programmable operating modes delayed to meet this requirement. This technique is shown in
and control features allow the Am9513A to be personalized for the second interface (Figure 6-3.4b). The flip-flop does the
particular applications as well as dynamically reconfigured un- delay while the OR gate prevents the rising edge from being
der program control. delayed, as this may cause bus contention with other devices.
Note that this second technique requires more Wait States
than the first.

WAIJ SlATES

Ao. .....
... .....,
CLOCK

,_,
R(~O

,
0
~RIT~
0

I 0

Ii
Am29101
A:a 1" ... "!'
I
A;. I -V A,

0 Tvee
EOtJI

I ,..
CW)

8 OlACK
A!o
,I .....
AU

...: -
G
C
-
a
14lS1.
D In
en
ex) ,
A'
A. '-
f
... -,
So >----
CP] E
CO A, s, fOUT

A,
fROII=:
C/O <C
LOS
- ~
AD

~~ .r cs

RIW -- WA

02188A-77

Figure 6-3.4a Am9513 to 68000 Connection Using SSI/MSI

6-17
 ....
All
....
I
A.II

A~I I
I
I I t-
) ...
-
A,
G
CLOCK
- -
IMHz
IOUH,
WAIT STAfES

READ

•,
WRITE

•,

T
fOUl

Vee I
0
0iiCi
A,.
7
I
-,
ACK

As
G

E~ ,..
CW)
A,
"

I -y Ao II)
0 A.
A,
5,
50
.........
Eo CO
0)
0
m A, C/O
E
«
~
Ali

i:DS
-- ClK-- c.
4)-
Alii

0 ..

0;.
--
~

I
,. ..
iiR

~15

... 08"
I
"
02188A·78

Figure 6·3.4b Am9513 to 68000 Connection Using SSI/MSI

6.3.5 68000 AND A SINGLE Am9516 actually a small penalty to pay, because most of the registers
are being loaded by the UDC itself by means of a linked-list
DMA CONTROLLER INTERFACE control structure. This results in very few writes being done
The Am9516 Universal DMA Controller (UDC) is a high perfor· directly to the UDC.
mance peripheral interface circuit for 8086 and 68000 CPUs,
Another interface problem to be addressed is the bus ex-
The UDC was designed to interface with non-multiplexed ad-
change protocol. The BREQ and BACK handshake of the UDC
dress and data bus systems, However, because it is basically a
is converted to the three-wire handshake of the 68000 by the
modified 8016, several incompatabilities remain, ALE is more
PA.L device and a 7403 package (open collector NAND Gate).
like the 8086 than the 68000. Although the timing of ALE
This IS done by a state machine internal to the PAL device. The
closely matches the AS of the 68000, it does not tristate when
state aSSignment was done to minimize external logic. This is
the 9516 is not the bus master. The major obstacle in this
very different from the discrete deSign in the Am9516 data
design was generating the proper Data Hold time for a slave
sheet because the PAL doesn't have preset and clear on its
write; the 8 MHz and 10 MHz CPU provides 30 ns and 20 ns,
flip-flops.
respectively, while the 9516 requires 40 ns. The newer, 8 and
10 MHz versions only require 10 ns Hold time, thus simplifying The UDC can support the bus error function by means of its
the design. EOP pin. If a bus error occurs during a DMA transfe[ an EOP
will cause the DMA operation to stop and interrupt 'the CPU.
The interface design shown here (Figure 6-3.5a) uses an AM-
The CPU can read status, address, word count, or anything
PAL16R4 to insert a Wait State and truncate DS to the 9516
else It may need to take corrective action. The UDC may then
early. PAL device equations are shown in Figure 6-3.5b. In this
be restarted or reprogrammed appropriately.
case the shqrtened DS strobes data into the 9516 while the
CPU holds data valid for almost 1 clock cycle afterwards. This The control signals LDS and UDS are generated by the PAL
Wait State is inserted only during slave write. This Wait State is device when the UDC is the bus master. This is a straightfor-
ward combination of DS, AO, and Bm.

6-18
 FC, r-+ C
FC, r-+ B 74LS138 IRmlf
FCo r-+ A
T
0,

IPLz lIlT

A • ':3
<... ;--:~.,
A;,
ADDRESS CONNECTED TO ANY ADDRESS LINE
'- PID

A23 23
BUS
TO SYSTEM 8 1 EO C"S

.
..lo.
As-AG. 51. So
A,
Vee ,. Am29806
II lICK (!
1iIIYE
Ao A,···A15
TWO l ALE
IJI[1 r----
Am29843 J
TPr;; r---- ,. ,.
Dr AC15

Do Vee vee . ADo

-
,
R
II
TWO
Am29863 T T m'I
--1
88000 Am9516
OSC CLOCK
--

T Dft
TOIFROM SYSTEM
f.:J
74LS74
D'mR

III
IIlIlllR'
III
Ao ITB
IBR
Ie IRB/es

AmPAL16R4
BACK
IBG
aREQ

IDS'
DSO
- 1
D 0
Vee
WAlT

BREa

~
;Q
lIS
lAS 68K9516M
ClK ClK IBW BIW

~
Vee
IUDS flDS IRW
BOR
10 MHz

oc <l- BACK

a CP
74LS74 Vee
D
ClR

mm
RIW
0111
~D
74LS74
0
OC
0-- EIIP

RIW

[III

Q_Q -
Ai UDS lDS RIW
TO SYSTEM
02188A-79

Figure 6-3.5a The Am9516 UDC to 68000 CPU Interface

Note that the address latch and data transceiver, along with the For those wary of or unfamiliar with PAL devices, these in-
address decode logic, are present in any case. The 68450 and terfaces can be built with standard gates and flip-flops. The
68440 also multiplex address and data, thus the PAL device is PAL device is simply a convenient means to collapse many 881
the only extra component required to make the 9516 a low cost packages into one and conserve board space.
alternative. Additionally, the 6 MHz 9516 has the same data
throughput as the 8 MHz 68450.

6-19
PAL16R4 PAL DESIGN SPECIFICATION
PAT006 JOE BRCICH 9/01/83
68000 TO Am9516 INTERFACE WITH DATA HOLD CORRECTION
ADVANCED MICRO DEVICES

CLK RW AO BREQ IBG IDSI lAS IBW Ics GND

10E ILDS IUDS DSO Ic BACK IBR ITB IRB VCC
IF (/BACK) RB Ics * RW * UDS +
Ics * RW * LOS
IF(/BACK) TB Ics * IRW
IF(BACK) UDS DSI * lAO * IBW +
BW * DSI
IF(BACK) LOS = DSI * AO * IBw +
BW * DSI

BR := BREQ * BG * BR * AS +
BREQ * IBG * IBACK

I BACK := IBREQ +
IBREQ * IBG +
IBREQ * AS +
IBREQ * IBACK +
IBG * IBACK +
AS * IBACK

C := UDS * IBAcK +
LOS * IBAcK

IDSO := BACK +
IBACK * IRW * C

DESCRIPTION
IF BREQ*BACK IS TRUE THE Am9516 HAS THE BUS, OTHERWISE THE 68000
HAS THE BUS. THIS PAL CONNECTS THE Am9516 TO THE 68000 WITH ONE
WAIT STATE DURING WRITES WHILE SHORTENING IDS TO ACHIEVE PROPER
DATA HOLD TIME. IT ALSO CONVERTS THE BUS EXCHANGE PROTOCOL INTO
68000 FORMAT. THIS DESIGN ASSUMES NO OTHER BUS MASTERS IN THE
SYSTEM. IRB AND ITB CONTROL THE TRANSCEIVERS WHEN CPU IS BUS
MASTER. Ics MUST BE A FUNCTION OF ALL DEVICES CONNECTED TO THE
CPU BUS NOT JUST THE Am9516 Ics AS SHOWN HERE.

The Ics
to IDS se~~~ time of 30 ns is met in the following ways:
--- -rr DurIng a-reaa
cycle-rhe-onIy-efIect~rom-not meeting-this
set-up time is that the data valid access time from the Am9516
will be delayed by a proportional amount. Since the minimum IDS
Low width from the 10-MHz 68000 (during a read) is 193 ns and the
minimum IDS Low width to the Am9516 is 150 ns, we have 43 ns
margin not counting gate delays which will further increase this
margin.
2) During a write cycle this is not an issue since the IDS
comes later and is stretched longer due to the Wait state.

Figure 6-3.5b

6-20
6.3.6 68000 AND DUAL Am9516 DMA prioritizes the request, and converts the control signals appro-
CONTROLLERS INTERFACE priately. Equations for the PAL device are shown in Figure
6-3.6b.
There has been interest shown in connecting two Am9516
DMA Controllers to obtain four channels. The example here The key parameters are: 1) data hold with respect to the rising
shows that such a system can be built by incorporating one edge of DS during a write, and 2) DTACK set-up time. Control
PAL device, AMD's new 22V10 (Figure 6-3.6a). Address and for a data bus transceiver is shown because it will be required
data buses are not shown as they are straightforward and in most systems. The PAL device provides these signals when
require no explanation. The PAL device, designated 68K16D2, the CPU is bus master; the Am9516 generates these control
converts the two DREQs into the 68000 three-wire handshake, signals directly when it is bus master.

DTACK

I ;---
0 Q ~ WAif

I
1(
C l K _ CP
-
29863 V'F V'F
TR~SCE~VER
T R ClK

~
80R
10 MHz RBEN
ClK,.
TBEN
Am9516
ClK -[::>0- ClK ITB IRB
ALE,
v~
ALE V'F

EOP -
OS
IBW BIW PID +--A,
BREQ, BREQ

~~
BACK, BACK
r - - RIW
ACK -
ICS ~
68000 AmPAL22V10 v~
68K16D2
TO Am29806
SYtEM
IC C-

csW
AS ~ lAS Ao + - -
BIW
BG IBGI ALE, ALE

BR
<t- BR
BREQ,
BACK,
IDS
'--+
BREQ
BACK
OS
WAif
ClK +--ClK,.

PIll +--A,
IBGACK IlOS RW IUDS
AllOWS
OTHER BUS v~
MASTERS Am9516
UDS
RIW RIW
lOS
EOP ~
RBEN
'fiiEN
oc
.-0<::]---- BACK,
BACK'p
BGACK BACK, BGO
OC
--0' BACK, i!Gi

02188A-80

Figure 6-3.6a Dual Am9516 UDCs to 68000 CPU Interface

6-21
 PAL 22V10 JOE BRCICH
PAT 001 5 APRIL 83
68000 TO DUAL 9516 INTERFACE
ADVANCED MICRO DEVICE~
CLK RW AO BREQl BREQ2 /BG NC ALE 1 /BW ALE 2 /BGACK GND
/CS /LDS IUDS /DS /C /AS /BR BACK2 BACKl /TB /RB VCC
BR - BREQ1*/BGACK + BREQ1*BG +
BREQ2*/BGACK + BREQ2*BG
BACK! BREQ1*BG*/AS + /BG*BGACK

IF (lBGACK) RB
BACK2
- BREQ2*/BREQ1*BG*/AS + /BG*BGACK
CS*RW*UDS + CS*RW*LDS
IF (I BGAS K) TB
- CS*/RW
IF (/BGACK*AS) OS :- AS*/C*/RW + AS*RW
IF (BGACK) AS ALEl + ALE2
IF (BGACK) UDS
IF (BGACK) LOS
-- DS*/AO*/BW + BW*DS
DS*AO*/BW + BW*DS
IF (AS) C :- UDS*BGACK + LDS* BGACK

DESCRIPTION
THE GOAL IN THIS DESIGN WAS TO BE COMPATIBLE WITH
8 MHZ AND FASTER 68000'S. BECAUSE THE EQUATIONS FOR OS AND
C WOULD EXTEND INTO THE NEXT CYCLE, THE OUTPUTS WERE TRI-
STATED TO TERMINATE THESE SIGNALS EARLIER. THIS REQUIRES THAT
PULL UP RESISTORS BE PLACED ON THESE OUTPUTS. THE INVERTED
CLOCK WAS USED TO PROVIDE MORE SETUP TIME FOR DTACK IN THESE
HIGH SPEED SYSTEMS. AT 8MHZ THE EQUATIONS CAN BE MODIFIED AND
THE PULL UP RESISTORS ELIMINATED. THIS EXAMPLE IMPLEMENTS
FIXED PRIORITY WHERE BREQl IS HIGHEST. NOTE THAT /AS SHOULD
NOT BE INCLUDED IN THE ADDRESS DECODER.
Figure 6-3.6b

The Am9516s are shown with independent clocks. The clocks If a bus error occurs, EOP will stop the current transfer and
may be divided from the CPU clock or may be generated inde- interrupt the CPU. The Interrupt Service routine can read the
pendently of the CPU. Because WAIT must meet the set-up status to determine if EOP caused the interrupt or if termina-
and hold times, DTACK may need synchronization by the use tion was normal. If EOP caused the interrupt, the Address
of a flip-flop, as shown. This flip-flop may be eliminated in Register can be read to determine where the bus error oc-
synchronous systems. curred. After the problem is corrected, the CPU can program
The clock is inverted to the PAL device to meet DT ACK set-up the Am9516 to complete the transfer or do an alternate trans-
time in systems of 10 MHz or faster. This inverter may be fer, as appropriate.
deleted in slower systems, if appropriate changes to the PAL When operating the DMA in interleave mode, an external EOP
device equations are made. This PAL device implements fixed should be gated with DACK to prevent affecting the wrong
priority between the Am9516s. BREQ1 is the highest priority. channel. This is unnecessary if interleave is not used, since the
Rotating priority can be implemented by adding another PAL UDC releases the bus.
device. This arbiter design supports both serial and parallel expansion
EOP s are pulled up separately, but could be tied together techniques and is therefore compatible with VME bus protocol.
since they affect a channel only if it is active. The bus error Bus grant out was implemented with an external gate due to a
function can be supported by connecting BERR and EOP shortage of pins. The VME/BCLR function was not imple-
mented because the Am9516 does not support preemption.

6-22
6.3.7 68000 AND Am9519A separated from the memory address space. This will prevent
spurious glitches on Chip Select and meet the Am9519J1:s re-
INTERRUPT CONTROLLER INTERFACE quirement that Chip Select be High for at least 100 ns prior to
Figure 6-3.7 shows the 68000 to Am9519A interface. This in- an Interrupt Acknowledge cycle. If there are no other interrupt-
terface for the Am9519A will work for the 4 MHz and 6 MHz ing devices in the system, GINT can be connected directly to
68000s. It will also work with faster CPUs, if Wait States are one of the TPL pins, as shown.
inserted during programming. RIP will automatically insert the
appropriate number of Wait States during the Interrupt Ac- AS is used to de-glitch the 74LS138's output, giving a clean
knowledge cycle. Further decoding the upper Address bits will INTA . Note that the Am9519A must be connected to the lower
reduce the address space occupied by this part. Appropriate Data Bus and AS must not be used to de-glitch CS.
decoding of the address bits should generate an I/O space One last thing to consider is the recovery time. Do not use the
MOVEP instruction to program the Am9519A.

LOS

RjW
--
..<iI
~2
WR

r74LS~
~ jjjj
~;ru;2

LAo WR
A23 A YO es
A22
At;
B

<C
en
C 25lS2548
AS E,

0
u;
Ao E2

0
0
A3
A2
E3

E4 ACK l Tvee
A

en
Am25LS2548 Tvee

CO DTACK
DC"
RIP

CD AS
J,
74LS07

E
FC2

Fe,

FCo
C

A
G2B

B 138

Y7 lACK
c:c
74LS138
~ Vee

IPL, --1
1PL1 I------' 7~
IPLo
.........t GINT

'7 A /8 • D!37

Do 0.80
'1 / V

02188A-81

Figure 6-3.7 68000 to Am9519A Interface

6-23
 SECTION C
8-BIT PROCESSORS·

7.0 INTERFACING TO THE zao to be used with non-BOBO/ZBO systems, and the other compati-
ble with the BOBO system. The CPU services interrupts by sam-
7.1.0 OVERVIEW OF THE Z80 pling NMI and INT signals at the rising edge of the last clock
of an instruction. Further interrupt service processing depends
The ZBO is an B-bit microprocessor which is software-
upon the type of interrupt that was detected.
compatible with the BOBO. In addition, it has some additional
instructions and registers which improve its processing capa-
bility. The dual-register set of the lBO CPU allows high-speed
7.1.1 Z80 TO Am9511A ARITHMETIC
context switching and efficient interrupt processing. In particu- PROCESSOR INTERFACE
lar, the Z-BO provides a refresh signal to interface with dynamic Figure 7-1.1 illustrates a programmed 110 interface technique
memory devices. The four traditional functions of a microcom- for Am9511A with a ZBO CPU.
puter system (parallel 110, serial 110, counting/timing, and The Chip Select (CS) signal is a decode of ZBO address lines
direct memory access) are easily implemented by the ZBO A1-A7. This assigns the Am9511A to two consecutive ad-
CPU. dresses, an even (Data) address, and the next higher odd
The ZBO and the associated family of peripheral controllers are (Command) address. Selection between the Data (even) and
linked by a vectored interrupt system. This system may be thE1 Command/Status (odd) ports is by the least significant ad-
daisy-chained to allow implementation of a priority interrupt dress bit A0.
scheme. Little, if any, additional logic is required for daisy-
chaining. Two other modes of interrupt are programmable; one

A7 G1

A6 G2A

A5 G2B
Am25LS138
A3 C
A2 B
-
Al A V CS

AO c/o
ZBO
A "-
D().D7 DBO·DB7
V -V
CLK
q, Am9S11A
+5V
RESET
G V3 0
REID lORD
V2 WR
,--c iNT
AD B Am25LS139
V1 AD 4.7K
r-< WAIT 10K
WR A
VO P +5V EACK

rr f>----
END
CLK

..... 74LS04
RESET
PAUSE p-
..... .....
.....

02188A-82

Figure 7-1.1 zao to Am9511A Interface

7-1
The 10RO (InpuVOutput Request) from the Z80 is an enable 7.1.2 zao TO Am9S12 ARITHMETIC
input to the 74LS139 decoder. The WR and RD from the Z80
are the two inputs to the decoder. The outputs Y1 and Y2 are
PROCESSOR INTERFACE
Block diagram for this interface is shown in Figure 7-1.2. The
tied to WR and RD of the the Am9511A. The PAUSE output of
Am9512 interface to Z80 requires two more gates than the
the Am9511 A is connected to the WA IT line of Z80. The
Am9511 A interface to Z80. An inverter is added to the interrupt
Am9511A outputs a LOW on PAUSE 150 ns (MAX) after RD
request line because the sense of the END/ERR signals are
or WR has become active. The PAUSE remains LOW for 3.5
different. The 74LS32 is added in the WAIT line because the
TCY + 50 ns (MIN) for data read and is LOW for 1.5 TCY + 50
Am9512 PAUSE will go LOW whenever chip select on the
ns (MIN) for status read from Am9511A where TCY is the clock
Am9512 goes Law. In Figure 7-1.2 the chip-select input can
period at which Am9511A is running. Therefore, the Z80 will
go LOW during second or third cycles of an instruction when
insert one to two extra WAIT states. The Am9511A PAUSE
the memory address matches the Am9512 1/0 address. If the
output responds to a data read, data write, or command write
74LS32 OR-gate is omitted, the WA IT input on the Z80 will to
request received while the Am9511A is still busy (executing a
LOW and the system will be deadlocked. Strobing the chip-
previous command) by pulling the PAUSE output Law. Since
select decoder will not work because this would cause a nega-
PAUSE and WAIT are tied together, as soon as the Z80 tries to
tive chip select to RD or WR time on the Am9512.
interfere with APU execution, Z80 enters the WAIT state.
The chip select decoder in this example is strobed with M1.
This accomplishes a dual purpose. It not only guarantees a
chip select transition on every 1/0 cycle, it also prevents the
chip select from going LOW during an interrupt acknowledge
cycle. This is vital because 10RO is also LOW during that
cycle. Without the M1 strobe, CS might go LOW and cause
PAUSE to go LOW which will again cause the system to dead-
lock.

iii G1
A7 G2A
AS G2B

Am25lS138
A3 C
A2 B
A1 A Y CS

AO C/D
~
;
~
ZBO
00-07 DBO·DB7
ClK
1> ~
RESET
RESET lORa G Y3 P--- Am9S12

Y2 WR
r----C iNT AD B Am2SLS139

r
Y1 AD
WR YO
END f--
WAIT A 0-- RESET

r--- ClK
PAUSE fr-
74~ EACK

'- +5V'"'
10K
?
A 74LS04
~
r-.... 74LS04
-V
74LS04
-1'

02188A-83

Figure 7-1.2 zao to Zm9512 Interface

7-2
7.1.3 zao AND Am9513A SYSTEM Since CS and RD orWR are actually ANDed inside the device,
the specification must be interpreted with some common
TIMING CONTROLLER sense. T pw only describes the shortest R D or WR pulse. There
Interfacing the Z80 and the Am9513A requires careful ex- is nothing wrong with it starting earlier (Figure 7-1.3d). There is
amination of timing parameters of both devices. The Am9513A also nothing wrong with RD or WR lasting longer (Figure 7-
data sheet specifies the timing requirements for CS, cm, R D, 1.3e). The Write Data Hold time is then related to the end of CS
WR, and DATA signals. Figure 7-1.3a shows timing relation- and its value is increased by T s.
ship requirements for the Am9513A during a Read cycle. The
There are many possible combinations to accomplish the
CS to RD setup time is 20 ns. This timing specification will not
desired effect. Figure 7-1 .3f shows a model that ascertains the
be met, with the Z80, because the CPU generates R D signal at
legal operating conditions. The delay box represents the setup
a maximum of 10 ns after lORa; lORa is the "enable" for the
time of C S with respect to R D or W R. It also should be clear
Am29806, Figure 7-1.3g, which produces the CS signal for the
that this time needs to be added to the Data Hold time since the
Am9513A. During the Write cycle (Figure 7-1.3b), WR to CS
internal W R will be delayed by this amount. This time must also
Hold time is 20 ns. This again will not be compatible for both
be added to the Read Access time because the internal R D is
devices because the Z80 specifies lORa will go inactive at the
also delayed by the same amount.
same time WR goes inactive. Generally, violation of these
timing parameters is not a serious problem. In most data Figure 7-1 .3g shows the interface between the Z80 and the
sheets, C Sand R D or W R are specified as in Figure 7-1 .3c. Am9513A System Timing Controller, along with the
Designers often have difficulties meeting these requirements. comparator-decoder Am29806 and a dip-switch.

cs

RD

DATA

Figure 7-1.3a 02188A-84

cs

'w'R

DATA

02188A-85

Figure 7-1.3b

7-3
CS

RD DR 'WR
Ts ~T pw ~ Th /
~ ....

02188A-86

Figure 7-1_3c

CS

RD DR 'WR
~Ts+Tpw~ Th ~

02188A-87

Figure 7-1_3d

CS
L_
T pw .... Th + T5 ~
-....
--
RD DR 'WR /
I
\ 'WRITE DATA r-
02188A-88

Figure 7-1_3e

7-4
 --1
r ')
CS DELAY
Interno.l RD or IJR

RD .". IJR

02188A·89

Figure 7-1.3f

ADDR A1-A2 AO

2
0 pF
A SO' Sl
G AM29806 Xl X2
A15 B EO
C/D 5
AO
OUT
1-5
IDRQ CS

GATE
Z 80 1-5

AM9513A
D7
5
SOURCE
DO DO
1-5
RD RD
FOUT
IJR IJR

• See text

02188A·90

Figure 7-1.3g

7-5
7.1.4 zao AND Am9517A DMA Since the Am9517A can be cascaded to provide multiple con-
trollers in a system, Figure 7-1.4b shows some possibilities of
CONTROLLER latch hookups for both single and double controller configura-
The circuit diagram in Figure 7-1.4a shows the interface involv- tions. Figure 7-1.4c shows the general expansion scheme of
ing the Am9517A with the Z8D microprocessor. The high order the Am9517A and Figure 7-1.4d shows the interconnections
A8-A15 memory address is latched by an 8-bit Am74LS373 for interfacing a single DMA controller to a microprocessor.
latch, while the lOR, lOW, MEMR and MEMW signals are
decoded from appropriate Z8D outputs.

L'6
~ / AD-A'

/
A8-A15 AO-A7

'---- r---- /I / "- 00-0

Am74LS373 /
r--- t---
I~ /8 V

DE
2.45MHz
I----
vv. '" vv.
CLOCK

j
0
;'
~~
vy.
ADSTB eLK
1
-L r--- ~
00-07
l"r -L V
00-07
/8 1 AEN
L ~ L ~
AO-A15
/ f .L- V
AO-A?

/,6
l I 8
CS
BUSRO
.A HREO
""4
BUSAK
.... HACK

zao MREQ ...- .... MEMR

Am9517A·1

Ali r:::' ~
Jo..
+5V
- ~
iOR

iNA - ....
~
lOW

1i)
- j... --
MEMW
RESET ICRO r--- ~

± S-
AST Aoy I-

02188A-91

Figure 7-1.4a Z80 to Am9S17A Interface

7-6
 AOSTB CP
Am9517A Am25lS373
AEN DE

AOSTB~--------~~~
Am9517A
AEN

CP
Am25LS373
DE
AOSTB I----+---.J
Am9517A
AEN

AOSTB 1-----1 >0--------1 CP Am25lS374

OR
Am9517A
AEN DE Am25lS2520

AOSTB
Am9517A
AEN

CP Am25lS374
OR
DE Am25lS2520
ADSTB
Am9517A
AEN

AOSTB~----------------------~STB
Am9517A AmB212
AEN~----------------------~OS2
MO OS1

AOSTB~--------~~~
Am9517A
AEN

AOSTB I----l---.J
Am9517A
AEN

02188A-92

Figure 7-1.4b

7-7
 Am9517

Am9517

DREQ
CLK
DACK

DREQ

HREO DACK
CPU
HACK OREQ

DACK

DREQ

DACK
Am9517

~~------i-~CLK DREQ 1-----1 HREQ

DACK HACK

L---______________ ~CLK

Note: All Am9517A devices must use common clock in Cascade mode.

02188A-93

Figure 7-1.4c Cascade Configuration

7-8
 ADDRESS BUS AO-A15

.( '),. .( '),.

AB-A15
t--- .J'-. - -
OE
Am74LS373
CP

V 1 B~BIT LATCH

~.('),.
AO-A15 AEN AO-A3 A4-A7 CS ADSTB
BUSEN·

HLDA HACK Am9517A

M
I
M
I
DBO- ~
>- 8w 0 DB7
l"'r vi
I~ I~ Ie '<t"
w OJ
HLORO HREO
'"-' '"a:w
OJ I~ a:
0 0
CPU

CLOCK
RESET f 41 41
MEMR
MEMW

lOR

lOW
I""""'
BUS

DBO-QB7

SYSTEM DATA BUS

V

02188A-94
Figure 7-1.4d Basic DMA Configuration

7.1.5 Z80 AND Am9568 DATA The multiplexed addressldata bus of the DCP is simulated in a
CIPHERING PROCESSOR WITH THE two-cycle operation. For output operation to an even address,
the PAL interface timing controller generates a Master Port
Am9517 DMA CONTROLLER Address Strobe (MAS) to select one of the internal registers.
This application design shows how to operate the ciphering Subsequent liD operations to an odd address (Ao=HIGH)
throughput up to 890 Kbyte/s by using the advanced 8-bit DMA transfer data to or frorn the preselected DCP register. During
Controller Am9517A-5 (also called the 8237-5). The host CPU liD operations to an odd address, the PAL device generates
is a Z80A. (Figure 7-1 .5a) Master Port Data Strobes (MRD or MWR). Before the DMA
The CPU sets up a data block in memory and programs the block transfer starts, the CPU rnust preselect the DCP data
DMA controller to transfer this data block to the DCP via the register. The register address of the data register is DOH.
Master Port. The DCP encrypts the data. A high-speed periph- The DMA controller operates in "flyby" mode. Data is trans-
eral device can read out the ciphered data from the Slave Port. ferred on the system data bus one byte at a time from rnemory
This dual-port configuration allows data input and output simul- to the DCP, or vice versa, without going through a DMA regis-
taneously and increases the throughput, compared to a single- ter. An liD Read (lOR) and Memory Write (MEMW) or liD
port configuration, by a factor of two. In the single-port Write (lOW) and Memory Read (MEMR) are active at the
configuration, only the Master Port is used for data transfer; it same time. The DCP is selected by DMA Acknowledge
handles both the clear and ciphered data. (DACK). The PAL device treats DACK as CS active and
Ao=HIGH. In this design the DMA controller can only execute
data transfer cycles; it is not able to change the internal register
address of the DCP.

7-9
 --
MREO MEMRD ~

ViR
rT2 ] )-
iIlEMW
~

74LS244

AD J)- lORD

IORO =r->- IOWR

,.•
A
00-07
,
Z80A
f* ~LS373 ~
OE
-V
....LJ 10.
As-A15
.~

Ao-A7

r--
,
ClK
Vee

RESET

~~
BUSRQ BUSAK

~
II ~r DECODER I
I
HREO HACK OSC
RESET f---
ClK
AEN
MEMR
MEMW
SPo-
SP, ¢:> PERIPHE RAl
lOR DEVICE
lOW
10.
MPo-
00-07 MP,
r
Am9517
~ II MCS
Am9568

~
Ao-A7
ADSTB .'
CS
,.....

-
f---+
DACK DACK ClK ClK
CLK1
4 ClK, AmPAL 16R:
i-+
AlE
MALE"
SCS

EOP cr Ao
lOR
lOW
MRD I--

MWR I--
MRO

MWR SDS ~

DREO MFlG
elK

~
02188A-95

Figure 7-1.5a Z80 and Am9568 DCP Interface

7-10
The DMA controller is set up for Demand Transfer Mode. It The DMA controller must be initialized for "extended" I/O write
releases the bus when the data request input goes inactive. in order to have a similar I/O bus timing to the Z80A CPU. A
The Master Port Flag (MFLG) is wired to the data request "late" I/O write delays the Master Port Write Strobe (MWR) to
input. The flag output goes active when the DCP is ready to the DCP by one clock cycle. If a late write is used, the data bus
accept data, or the output data is ready to be read out. After will not be valid at the time data is latched.
transferring one block of data (8 bytes), this flag goes inactive
To execute a DCP-to-memory transfer, the DMA does an I/O
until a new block can be put in or read out. The inactive time
read and memory write. The DMA controller can be
depends on the response time of the peripheral logic at the
programmed for an "extended" or "late" write, depending on
Slave Port. This flag is inactive for a minimum of five clocks.
the memory design.
SPEED In "flyby" mode the DMA controller generates no I/O address,
The DMA controller needs three clock cycles to transfer one so the CPU has to preselect the data Input or Output Register.
byte. After each block transfer (8 bytes), the DMA controller A DMA Acknowledge (DACK) enables MRD or MWR to con-
releases the bus and requests it back if M FLG goes active trol the data transfer.
again. This time is assumed to be 12 clocks. The ciphering of Figure 7-1.5b shows the DMA-DCP data transfer timing. When
one block is done concurrently with the input of the next block; the DMA Controller has transferred one block of data, the data
the internal operation is pipelined. The maximum throughput transfer has to be stopped until the DCP is ready for the next
can be calculated as: block transfer. The DCP makes the DMA Controller stop the
T = 8/ (8 • 3 + 12) • 4 MHz = 0.89 Mbyte/s transfer by deactivating MFLG. If MFLG is LOW, data may be
transferred; if MFLG is HIGH, the DCP does not accept data
The Compressed Transfer mode of the DMA controller cannot
transferred. The timing of the M FLG to DREQ path is the most
be used, because the PAL synchronization logic needs normal
critical in this application. If MFLG is deactivated too late, the
timing to synchronize the Data Strobes to the DCP clock.
DMA Controller will issue another data transfer which will be
disregarded by the DCP. The critical signal path will be
INITIALIZATION analyzed below.
The Multiplexed Control Mode C/K =LOW) of the DCP is To prevent the DMA from issuing another cycle the Data Re-
selected to enable access to the internal registers. The CPU quest input has to go inactive by the falling edge of the DMA
first programs the Mode Register to reset the DCP and to set clock at the end of cycle S3. The DMA controller samples the
up the port configuration and ciphering mode. After that, the input at this time and instigates another cycle if the request is
keys and initial vectors can be loaded. To initialize the DCP for still active. The setup time of DREQ is 0 ns. The Master Port
DMA transfer, the CPU executes one Address Latch Cycle, to Flag which is connected to the DREQ input goes inactive in the
pre-select the data register. eighth cycle with a maximum delay time of 150 ns after the
The DMA controller must be programmed such that DREQ and Data Strobes. The Data Strobe itself has a maximum delay
DACK are active LOW. time of 190 ns (Am9517A-5) after the rising edge of the clock in
cycle S2. That gives a time window of 375 ns of which 340 ns
TIMING are already used for the two delays (190 ns + 150 ns). The
The PAL device simulates the multiplexed address/data bus of propagation delay of a fast PAL device is 25 ns. This leaves
the DCP assuming a two-cycle operation mode. In the first 10 ns for other delays in the signal path.
cycle the CPU latches the address of the internal register into The PAL design assumes that the system memory needs no
the DCP; subsequent cycles transfer data to or from the se- Wait States.
lected register. Address Ao distinguishes the two cycles The peripheral logic at the Slave Port can use the Slave Port
(Figure 7-1.5b). An I/O instruction with Ao= LOW generates an Flag (SFLG) to time the transfer. If SFLG is active LOW, data
address latch cycle; an I/O instruction with Ao= HIGH gener- can be written to or read from the data register.
ates a data transfer cycle.

7-11
7-12
PALl6R4 PAL DESIGN SPECIFICATION
DCP048 JUERGEN STELBRINK 8-9-83
Z80A- AM95l7(DMA)- AM9568(DCP) INTERFACE DEVICE
ADVANCED MICRO DEVICES

CLKl CLK2 ICS JIOR JIOW AO jMFLG jDACK NC GND

JOE jMWR jMRD jQl jQ2 jQ3 MALE NC CLK VCC

jMALE := jIOW+IOR+jCS+AO+MALE ; MASTER PORT ADDRESS STROBE

Ql := CS*AO*IOR*jIOW*jQ2 +
CS*AO*IOW*jIOR*jQ3 +
DACK*IOR*jIOW*jQ2 +
DACK*IOW*jIOR*jQ3

Q2 := CS*AO*IOR*jIOW*Ql +
CS*AO*IOR*jIOW*Q2 +
DACK*IOR*jIOW*Ql +
DACK*IOR*jIOW*Q2
Q3 := CS*AO*IOW*jIOR*Ql +
CS*AO*IOW*jIOR*Q2 +
DACK*IOW*jIOR*Ql +
DACK*IOW*jIOR*Q2

MRD CS*AO*IOR*jIOW + MASTER PORT READ

DACK*IOR*jIOW +
Q2
MWR CS*AO*IOW*jIOR*jQ3 + MASTER PORT WRITE
DACK*IOW*jIOR*jQ3

jCLK CLK2 DCP CLOCK

FUNCTION TABLE

CLKl CLK2 JCS JIOR JIOW jDACK AO CLK MALE jMRD jMWR jQl jQ2 jQ3

j
C C j j 0 M j j
L L j I I A C A M M j j j
K K C 0 0 C A L L R W Q Q Q
1 2 S R W K 0 K E 0 R 1 2 3 COMMENT
---------------------------------------------------------
CLOCK GENERATION
X L X X X X X H X X X X X X
X H X X X X X L X X X X X X
ADDRESS LATCH
C X H H H H L X L H H H H H CYCLE T2 (CPU)
C X L H L H L X H H H H H H CYCLE TW
C X L H L H L X L H H H H H CYCLE T3
C X H H H H L X L H H H H H CYCLE Tl
READ DATA
X X H H H H H X L H H H H H CYCLE TW (CPU)
X X L L H H H X L L H H H H
C X L L H H H X L L H L H H
C X L L H H H X L L H L L H CYCLE TW (EXTRA WAIT STATE)
C X L L H H H X L L H H L H CYCLE T3
C X H H H H H X L H H H H H CYCLE Tl
X X H L H L X X L L H H H H CYCLE S3 (DMA)
C X H L H L X X L L H L H H
C X H L H L X X L L H L L H CYCLE S4
C X H H H H X X L H H H H H CYCLE S2

7-13
 WRITE DATA
X X L H L H H X L H L H H H CYCLE TW (CPU)
C X L H L H H X L H L L H H
C X L H L H H X L H H L H L CYCLE T3
C X H H H H H X L H H H H H CYCLE Tl
X X H H L L H X L H L H H H CYCLE S3 (DMA)
C X H H L L H X L H L L H H
C X H H L L H X L H H L H L CYCLE S4
C X H H H H H X L H H H H H CYCLE S2

----------------------------------------------------------------
DESCRIPTION:

THIS PAL GENERATES ALL NECESSARY BUS CONTROL SIGNALS, TO

INTERFACE A Z80A CPU AND A AM9517 DMA CONTROLLER TO THE AM9568
DATA CIPHERING PROCESSOR. THE MAXIMUM SYSTEM CLOCK FOR ALL PARTS
IS 4 MHZ.

1 INPUT AND 3 INPUT/ OUTPUT PINS ARE NOT USED.

INPUT SIGNALS:

CLK1, Z80 SYSTEM CLOCK

CLK2

/CS CHIP SELECT FOR THE DCP, GENERATED BY A DECODER LOGIC

/IOR INPUT/OUTPUT READ

/IOW INPUT/OUTPUT WRJTE

AO LEAST SIGNIFICANT BIT OF THE Z80 ADDRESS BUS TO SELECT

THE TYPE OF OPERATION:
AO LOW SELECT DCP REGISTER FOR NEXT DATA CYCLES
(ADDRESS LATCH)
AO = HIGH READ OR WRITE INTERNAL REGISTER
(DATA TRANSFER TO CONTROL, MODE, INPUT OR
OUTPUT REGISTER)

/OACK DMA ACKNOWLEDGE FROM DMA CONTROLLER, TREATED AS /CS=LOW

AND AO=HIGH

OUTPUT SIGNALS:

CLK INVERTED SYSTEM CLOCK FOR THE DCP

MALE MASTER PORT ADDRESS LATCH ENABLE, ACTIVE DURING ADDRESS

LATCH CYCLES TO LATCH THE REGISTER ADDRESS ON MPl AND MP2
(2 LINES OF THE MASTER PORT BUS) AND THE STATE OF /MCS
IN. THE DCP STORES INTERNALLY THE ADDRESS AND CHIP SELECT
TO THE NEXT ADDRESS LATCH CYCLE

/MRD MASTER PORT READ, TO ENABLE REGISTER READ OPERATIONS

/~R MASTER PORT WRITE, TO ENABLE REGISTER WRITE OPERATIONS

/Ql, INTERNAL USED STATE SIGNALS (DO NOT CONNECT). Ql IS ACTIVE 2

/Q2, CLOCK CYCLES IN EACH DATA TRANSFER OR DMA ACKNOWLEDGE CYCLE.
/Q3 IT IS USED TO GENERATE THE DELAYED Q2 AND Q3. Q2 IS USED TO
HOLD /MRD ACTIVE UNTIL /IOR IS GONE INACTIVE. Q3 MASKS /~R
OFF.

M4
7.1.6 Z80 TO Am9518/Am9568 DCP 1/0 addresses: XXXX XXX0 - Address Latch Cycle
This chapter shows, in two examples, how the Data Ciphering XXXX XXXI - Data Transfer Cycle
Processor (DCP) can be interfaced to a Z80 (Z80A, Z80S) X - User definable
CPU (Figure 7-1.6a). All interface control signals are The AmPAL 16R4 device controls the interface timing. It gener-
generated by one PAL device. ates the synchronized strobe signals for the DCP and the Wait
In CPU transfer mode,ciphering speed can reach up to 280 for the CPU to extend the cycles.
Kbyte/s. A Z80A DMA controller can double this value, and a The PAL device is programmed to allow two operation modes.
zaO-DMA-DCP hookup can increase the speed to 1.1 Mbyte/s. In Mode A the DCP works with the same clock rate as the CPU.
The multiplexed address/data bus of the DCP is simulated Mode S increases the ciphering speed by allowing higher than
using a two-cycle operation mode. An output instruction to an 4-MHz system clock rates for the CPU. In this mode, the PAL
even address (Ao=LOW) selects one of the internal registers device provides half the system clock rate for the DCP.
of the DCP. In all subsequent 1/0 operations with Ao=HIGH, A system with a Z80S at 6 MHz and an AmZ8068 at 3 MHz
the CPU can transfer data to or from DCP registers. The regis- increases the ciphering speed compared to a system where
ter address stays latched in the chip until the next Address both the CPU and the DCP clock are 4 MHz; the limiting factor
Strobe latches in a new address. The Address Latch Cycle is the data transfer capability of the CPU.
does not represent significant overhead in an encryption or
The key requirement in interfacing the DCP to a zao CPU is to
decryption session because, once the DCP is initialized and
meet the timing relationship between the Master Port Data
the data register is selected, no further Address Latch Cycle is
Strobe (MDS) and the DCP clock. The rising edge of MDS
needed.
must be synchronous to the falling edge of the clock.

ClK
l OSC

1
J
-.l

Ao-A7 AODR

Vcc
',.'L>I DECODER r ClK1
cs
...

AmPAL16R4 MCS
~
ClK2
ClK r-+
r---+
ClK

MCS
T
1
MAS
r---+ MAS

ZSO
WAIT WAIT
IORQ
MDS
r---+ MDS

ZSOA
IORQ Am95181
Ao Ao
ClKB I- AmZ8068
ZSOB Q t-
WR
OE AlB

WR
V NO~E1 MR/W

A ~
MPo-MP7
Do-D7
., ,. C/K

Note 1: AlB = HIGH:

-
AlB = lOW:
Z80·9518/Z80A·8068
Z80B·8068
(MODE AI
(MODE BI
~

02188A-97

Figure 7-1.6a Z80-0CP Interface

7-15
THE OPERATION MODES DATA READ CYCLE: (FIGURES 7-1_Sb AND
Mode A: 80th the l80 CPU and the DCP are operating 7-1.Sc)
synchronously at the same frequency. The DCP A Data Read Cycle reads the register whose address was
clock is inverted. This mode can be used with system
latched in the previous Address Latch Cycle. MCS and MAS
clocks up to 4 MHz. No extra Wait States are are inactive the whole cycle. MOS is active during the last two
inserted. clock cycles, T wand T3. In both A and 8 Modes, no Wait State
Mode 8: To get higher ciphering throughput, the data transfer is inserted. WR and Ao must be HIGH. In Mode 8 the DCP
speed of the l80 bus should be increased by using a clock is set HIGH in the beginning of T3 using an internal signal
higher system clock rate. In Mode 8 the PAL device Q to synchronize the falling edge of the DCP clock to the rising
divides the system clock by two to generate the OCP edge of MDS. Q is only active in Mode 8 during Wait State Tw.
clock. The DCP clock is synchronized to the M OS by This interface meets the data hold time of the l80, because the
delaying the clock one half cycle if they are not in data is stable to the beginning of T 1 of the next machine cycle.
phase (Figures 7-1.6d and 7-1.6e). During a Data
Write Cycle, one extra Wait State is inserted. An DATA WRITE CYCLE
Aml8068 must be used in this mode, even at a OCP
In this cycle, the CPU can write one byte into the addressed
clock rate of 3 MHz, because of its faster register
register. MCS and MAS are inactive. WR is active and Ao is
access time.
HIGH.
Figure 7-1.6a shows the interface. The Ais input of the PAL
Mode A (Figure 7-1.6a)
device is wired HIGH to select Mode A or LOW to select
Mode 8. MOS is strobed LOW for Tw. The OCP reads the data in at the
beginning of T3. No Wait State is inserted.
THE INTERFACE TIMING Mode 8 (Figure 7-1 .6d)
MDS is strobed LOW for the Wait cycle Tw and the additional
ADDRESS LATCH CYCLE: (FIGURES 7-1.Sb
Wait cycle T w to meet the minimum data strobe active time
AND 7-1.Sc) (parameter 44) of the DCP. The DCP reads the data in at the
Master Port Chip Select (MCS) is active when lORa and CS begin of T3'
are active LOW and Ao=LOW (even address). Master Port
Address Strobe (MAS) is strobed LOW for one system clock DATA CIPHERING SPEED
cycle during the l80's automatically inserted Wait cycle Tw to
The byte transfer capability of the l80 system bus limits the
meet the hold time requirement of MAS HIGH to MCS HIGH
data ciphering throughput of the DCP. A l80 DMA controller
(parameter 35).
doubles the maximum throughput compared to a CPU-
controlled transfer as indicated in the following table:

System Clk DCP Clk CPU DCP Mode N T

6 MHz 3 MHz l808 Aml8068 8 168/176 0.28/0.27
4 MHz 4 MHz Z80A Aml8068 A 168 0.19
2.5 MHz 2.5 MHz l80 Am9518 A 168 0.14

N - Number of OCP clock cycles to transfer and cipher 8 The formula for calculating the throughput is:
bytes of data. In CPU-controlled modes the use of the T = (8 * f) I (N + m) Mbytels
l80 block transfer commands like INIR, INDR, OTIR or
OTDR is assumed. f - DCP clock in MHz

T - Throughput in Mbytels 8 - 8 bytes per block

m - Number of extra DCP clock cycles to get a minimum
delay time of five clocks between transferring the last
byte of one block and the first byte of the next block. In
CPU controlled transfers m=O can be assumed, be-
cause the CPU has to evaluate instruction fetches and
memory data transfers between two 1/0 accesses.
M FLG indicates if the DCP accepts data transfer.

7-16
 \ . . . ._______1
WRITE
DATA
CYCLE

READ
Ao DATA
CYCLE

DCP ClK

* AUTOMATICAllY INSERTED BY THE zao CPU,

(NO MORE WAIT'S ARE AllOWED)

02188A·98

Figure 7-1.6b Z8D-Am95181Z80A-AmZ8068 Timing Diagram (Mode A)

7-17
 Ao

DCP CLK (1)

OR DCP CLK(1)

DCP CLK (2) OR

DCP CLK(2)

* AUTOMATICALLY INSERTED WAIT STATE

02188A-99

02188A-100

Figure 7-1_6c Address Latch Cycle (Mode B)

(No Clock Synchronization)

Figure 7-1_6d Data Read Cycle (Mode B)

7-18
 Tw Tw
T2 (NOTE 1) (NOTE 2) T3

CPU CLK

Ao

WAIT ------~
(NOTE 3)

DCPCLK(1)

OR

DCP CLK(2)

NOTE: 1. AUTOMATICALLY INSERTED WAIT STATE

2. EXTRA WAIT STATE
3. OPEN COLLECTOR OUTPUT

02188A-101

Figure 7-1.6e Data Write Cycle (Mode B)

MODE A MODEB

CLK1,CLK2~

sr------
AB

CLK: _ _ _ _ _ _' I_. . ~~_-_....J

. _ _-..:

CLK --.JLSL1 ...._----'

CLK~-l

02188A-102

Figure 7-1.6f Clock Timing Diagram (Mode A and B)

7-19
PALl6R4 PAL DESIGN SPECIFICATION
DCP046 JUERGEN STELBRINK 5/2/83
Z80- AM95l8/AMZ8068 INTERFACE CONTROLLER
ADVANCED MICRO DEVICES

CLKl CLK2 /CS /IORQ AO /WR AB NC NC GND

IOE NC /WAIT /CLKB /Q /MDS /MAS IMCS CLK VCC
MCS IORQ*CS*/AO MASTER PORT CHIP SELECT

MAS := IORQ*CS*/AO*WR*/MAS MASTER PORT ADDRESS STROBE

MDS := IORQ*CS*WR*/MDS*AO*AB + WRITE DATA STROBE (MODE A)

IORQ*CS*WR*AO*/MDS*/Q*/AB + WRITE DATA STROBE (MODE B)
IORQ*CS*WR*AO*MDS*Q*/AB + ; WRITE DATA STROBE (MODE B)
IORQ*CS*/WR*AO READ DATA STROBE (MODE A+B)

CLKB := /CLKB*/Q*/AB CLOCK FOR MODE B

ICLK CLK2*AB + (MODE A)

CLKB (MODE B)
Q := IORQ*CS*/MDS*/Q*AO*/AB USED TO GENERATE MDS AND WAIT
IF (Q*WR) WAIT Q*WR WAIT TO Z80
FUNCTION TABLE
CLKl CLK2 AB /CS /IORQ AO /WR CLK /MCS /MAS /MDS /WAIT IQ /CLKB

/ /
C C I / IW / C
L L / 0 / C M M M A L
K K A C R A W L C A D I / K
1 2 B S Q 0 R K S S S T Q B COMMENT
--------------------------------------------------------------------------
MODE A: Z80- AM95l8 OR Z80A- AMZ8068 INTERFACE
(DCP CLOCK = CPU CLOCK)
CLOCK GENERATION

X L H X X X X H X X X Z H H
X H H X X X X L X X X Z H H

ADDRESS LATCH

H X H H H X H X H H H Z H H MACHINE CYCLE Tl
L X H L H L H X H H H Z H H
C X H L H L H X H H H Z H H
H X H L L L L X L H H Z H H CYCLE T2
C X H L L L L X L L H Z H H
C X H L L L L X L H H Z H H CYCLE TW
H X H L H L H X H H H Z H H CYCLE T3

7·20
 C X H L H L H X H H H Z H H
WRITE DATA OPERATION

C X H L H H H X H H H Z H H CYCLE Tl
C X H L L H L X H H L Z H H CYCLE T2
C X H L L H L X H H H Z H H CYCLE TW
C X H L H H H X H H H Z H H CYCLE T3

READ DATA OPERATION

C X H L H H H X H H H Z H H CYCLE Tl
C X H L L H H X H H L Z H H CYCLE T2
C X H L L H H X H H L Z H H CYCLE TW
C X H L H H H X H H H Z H H CYCLE T3

INVALID OPERATION (READ IN ADDRESS LATCH)

C X H L L L H X L H H Z H H NO /MAS

/ /
C C I / / W / C
L L / 0 / C M M M A L
K K A C R A W L C A D I / K
1 2 B S Q 0 R K S S S T Q B COMMENT
;-------------------------------------------------------------------------
MODE B: Z80B- AMZ8068 INTERFACE
(DCP CLOCK = CPU CLOCK/2)
WRITE DATA OPERATION
C X L H H H H L H H H Z H L CYCLE Tl
C X L H H H H H H H H Z H H CYCLE T2
C X L L L H L L H H L L L L FIRST WAIT CYCLE (CLK=L)
C X L L L H L H H H L Z H H SECOND WAIT CYCLE
C X L L L H L L H H H Z H L CYCLE T3

C X L L L H L H H H L L L H FIRST WAIT CYCLE (CLK=H)

C X L L L H L H H H L Z H H SECOND WAIT CYCLE (SYNC ! )
C X L L L H L L H H H Z H L CYCLE T3

READ DATA OPERATION

C X L H H H H H H H H Z H H CYCLE Tl
C X L H H H H L H H H Z H L CYCLE T2
C X L L L H H H H H L Z L H WAIT CYCLE
C X L L L H H H H H L Z H H CYCLE T3 (SYNC! )
C X L L H H H L H H H Z H L NEXT CYCLE

--------------------------------------------------------------------------

7-21
DESCRIPTION:

THIS PAL GENERATES ALL NECESSARY BUS CONTROL SIGNALS, TO INTERFACE

THE AM95l8 OR AMZ8068 TO THE Z80 CPU WITH A SYSTEM CLOCK UP TO 6 MHZ.

2 INPUT AND 1 INPUT/ OUTPUT PINS ARE NOT USED, SO THAT FOR EXAMPLE
A DATA BUS TRANSCEIVER CONTROL LOGIC CAN BE ADDED.

IN SYSTEMS WITH A CLOCK UP TO 4 MHZ, THE DCP RUNS DIRECTLY AT THIS

FREQUENCY (MODE A, INPUT AB = HIGH) .
IF THE FREQUENCY IS HIGHER, THE DCP IS DIVIDED BY TWO FROM THE
SYSTEM CLOCK (MODE B, AB = LOW).

INPUT PINS:

CLKl, CLKl IS THE CLOCK INPUT FOR THE FOUR INTERNAL D-FLIP-FLOPS.
CLK2 THEY ARE CLOCKED BY THE RISING EDGE OF CLKl. THE DCP DATA
STROBE MUST BE SYNCHRONOUS TO THE FALLING EDGE OF THE CLOCK;
THE INVERTED CLK2 IS THEREFORE SENT TO THE OUTPUT CLK.
IN MODE B CLK2 IS SYNCHRONIZED BEFORE IT APPEARS ON THE CLK
OUTPUT. BOTH INPUTS ARE CONNECTED TO THE Z80 SYSTEM CLOCK.

/CS CHIP SELECT GENERATED BY AN ADDRESS DECODER LOGIC

(ACTIVE LOW). IF /CS IS ONLY ACTIVE IN I/O CYCLES,
THE /IORQ INPUT CAN BE WIRED LOW.

/IORQ INPUT/ OUTPUT REQUEST OF THE Z80 (LOW ACTIVE)

AD LEAST SIGNIFICANT BIT OF THE Z80 ADDRESS BUS

TO SELECT TYPE OF OPERATION:
AO= LOW SELECT REGISTER FOR NEXT DATA CYCLES
(ADDRESS LATCH)
AO= HIGH READ OR WRITE INTERNAL REGISTER
(DATA TRANSFER TO CONTROL, MODE, INPUT
OR OUTPUT REGISTER)

/WR WRITE SIGNAL OF THE Z80, DEFINES DATA TRANSFER DIRECTION

AB AB= HIGH MODE A

AB= LOW MODE B

OUTPUT SIGNALS:

/WAIT ACTIVE LOW DURING FIRST WAIT CYCLE IN WRITE DATA

OPERATION IN MODE B, TO GENERATE AN EXTRA WAIT STATE.
THE OTHER TIME /WAIT IS IN THREE STATE.

jMCS MASTER PORT CHIP SELECT, ONLY ACTIVE IN ADDRESS LATCH

CYCLES

/MAS MASTER PORT ADDRESS STROBE, ACTIVE IN ADDRESS CYCLES

TO LATCH THE REGISTER ADDRESS AND /MCS IN. THE DCP
STORES INTERNALLY THE ADDRESS AND THE CHIP SELECT

TO THE NEXT ADDRESS LATCH CYCLE

/MDS MASTER PORT DATA STROBE TO ENABLE DATA TRANSFER TO THE
INTERNAL REGISTERS OF THE DCP

CLK DCP CLOCK, IN MODE B SYNCHRONIZED TO THE MASTER PORT DATA

STROBE (/MDS)

JCLKB DCP CLOCK OUTPUT INTERNALLY USED FOR MODE B (NOT CONNECT)

/Q INTERNAL STATUS SIGNAL (NOT CONNECT)

7-22
7.1.7 THE zao AND Am9519A When the Am9519A is part of a daisy-chain, it must be the
lowest priority device because the Am9519A activates its
INTERRUPT CONTROLLER Enable Out (EO) output after receipt of the interrupt acknowl-
The Am9519A is an Universal Interrupt Controller, a processor edge signal (lORa, MT) from the microprocessor, while the
support device designed to enhance the interrupt handling ca- lilog parts require their lEI (Interrupt Enable In) signal to setup
pability of a wide variety of processors. A single Am9519A can at least 200 nsec (2.5 MHz l80) prior to the Interrupt Acknowl-
manage the masking, priority resolution and vectoring of up to edge going active. Earlier design examples decoded lORa
eight interrupts, and it may be easily expanded by the addition and M1 to determine an interrupt acknowledge cycle. Such an
of other Am9519A chips to handle a nearly unlimited set of approach has the disadvantage of making the lACK to occur
interrupt inputs. It offers many programmable operating op- late in the cycles. The new approach decodes M REO and M 1
tions to improve both the efficiency and versatility of the host instead. The flip-flop ensures glitches that result from a false
system operations. The diagram in figure 7-1.7a shows the decoding, during other cycles, do not affect the 9519A. This
interface between the l80 and the Am9519A. allows the 9519A sufficient time to assert PAUSE and, in most
The Am9519A can be configured as the sole interrupting cases, additional Wait States may not be necessary.
device to the l80 or in conjunction with other devices (such as
the DIO,CIO,CTC, etc.) in a daisy chain interrupt scheme.

AO-A15

;>-

..r-'
1 ::u- I
INT A1
A2
A
B
I AO
C/O
GINT

RiP r---
A3
C

74LS138
4.7K

AO-A1S
t----
G1
----l

zao
00-07 ~
J= G2B YO

...l'\
cs

DBO-DB?
Am9519A
EI t---- FROM lEO OUTPUT
OF ZILOG PERIPHERAL

'"" V
AD AD
~
WR
r------L-/ WR
IREQO-IREQ7
r4- INTERRUPT
INPUTS

WAIT
10RO

1>
Mi'
Ii ---
I lACK

PAUSE

4.7K
-0 +5V

~ 0 01 0 02

CLOCK
C
I C QQ
~
\)
-
02188A-103

Figure 7·1.7a

7-23
8.0 INTERFACING TO THE 8085 The 8085A-2 is a faster version of the 8085A. The 8085AH is a
3 MHz CPU with 10% supply tolerances and lower power con-
8.1 OVERVIEW OF THE 8085 sumption.

The 8085A is a complete 8-bit parallel central processing unit 8.1.1 THE 8085 AND Am9511A
(CPU). Its instruction set is 100% software compatible with the
8080A microprocessor. The 8085A reduces the parts count of
INTERFACE
8080A system while increasing the speed. Essentially, it inte- The system clock rate is 3 MHz in a typical8085A system. The
grates the 8080A, the 8224, and the 8228 into a single Chip. floating point processor to be used in this kind of interface
should be the Am9511-1 because of its 3 MHz maximum clock
The 8085A uses a multiplexed Data Bus. The address is split
rate. The Am8085A has an earlier Ready setup window
between the 8-bit Address Bus and the 8-bit Data Bus. Only 8
compared with the Am9080A. If the PAUSE signal is con-
bits of address is used for liD operations. The on-chip address
nected directly 0 the READY input of the Am8085A, the ready
latches of 8155/8355 memory products allow a direct interface
line will be pulled down too late for the Am8085A to go into the
with 8085A. 8085A components, including various timing com-
WAIT state. The 74LS74 is used for forcing one WAIT state
patible support chips, allow system speed optimization.
when the Am9511-1 is accessed. After the first WAIT state, the
The 8080/8085 processors duplicate the liD address on the 74LS74 Q output is reset to HIGH and the PAUSE of the
upper 8 bits as well as the lower 8 bits of the Address Bus. The Am9511-1 controls any additional wait states if necessary. The
upper address bus is used in the following examples because chip-select decoder is gated with 101M signal to prevent the
they are latched. Am9511-1 from responding to memory accesses when bits 9
to 15 of the memory address coinCides with Am9511-1 liD
address. Figure 8-1.1 shows the Am80B5A to 9511-1 interface .

.A
74l~

-
101M G1
RST5.5 A15
A14

All
G2A
G2B
C Am25LS138
T 4.7K

A10 B

X1
A9 A Y CS

&:
'T.-
Am8085A AS

A 1\
C/O END p-
X2
ADO-AD7 080-087
V

RD
" RD
Am9511A·l

\VA \VA
RESET OUT RESET
eLK OUT ClK
READY ALE

+5V f1K
1
PS
l
PS
+5V L 10K
EACK
PAUSE

0 Q 0
74LS02
74LS74 74lS74

CK '-- CK a ~ '17 74lS04

CR CR

~ 1
I
~
-
021 BBA-1 04

Figure 8-1.1 Am8085A to Am9511A-1 Intenace

8-1
8.1.2 Am8085A TO Am9512-1 The ERR output and END output are connected to separate
interrupt inputs so that the CPU can identify the source of
INTERFACE
interrupt without reading t~e status register of the ~m9512-1.
The Am9512 is designed specifically to interface to the
Since the Chip Select decoder is gated by the 101M Signal, a
Am8085A. The interface is straightforward and no additional
transition is guaranteed with each 1/0 operation without the
logic is required. The Am9512-1 is used here, instead of the
concem of insufficient address decode. The diagram in Figure
Am9512, because the typical Am8085A system runs at 3 MHz.
8-1.2 shows the Am8085A to Am9512-1 interface.

IO/M Gl
A15 G2A
A14 G2B
All C Am25lS138
Al0 B
A9 A Y cs
Xl

6MH z~ Am8085A
A8

;11 ~
C/O

L X2
ADO-AD7

" ./
DBG-DB7

Am9512-1
AD AD
WR WR

RST6.5 ClKOUT ClK ERR

RST5.5 RESET OUT RESET END

- READY +5V ""

10K
EACK PAUSE
~

02188A-105

Figure 8·1.2 Am8085A to Am9512·1 Interface

8-2
8.1.3 THE 8085 AND Am9513A interface between the Am9513A and an Am8085A CPU. The
SYSTEM TIMING CONTROLLER Am9513A is configured to appear in the CPU's 1/0 space;
connecting the 101M output of the CPU to the G2A input of the
The Am9513A is designed to interface easily to both the 8-bit
decoder and tying G1 high will memory-map the Am9513A.
and the 16-bit family of CPUs. Master Mode register bit MM13
The Am9513A operates with an 8-bit data bus. Master Mode
allows the user to program the Am9513A data bus for either an
register bit MM13 should be 0 and data bus pins OB13-0B15
8-bit or 16-bit width, allowing the Am9513A's data bus to be
should be tied high.
tailored to match that of the host CPU. Figure 8-1.3 shows an

RD 1m
WR WR

101M Gl Cs
0--
G2A 0--
G2Ei 0--
d- Am25LS138 0--
TO OTHER
I/O DEVICES
Am9513A/
Am8085A A 0-- Am9513
B 0--
VCC
-
---
C 0--
015
A9 AID All 014
AII-AI5 ~ 013
~ A8
C/15

Vi I
ADD-AD7
~ ) 00-07

V
ADDRESS-DATA BUS
TO OTHER DEVICES

02188A·l06

Figure 8-1.3

8-3
B.1.4 THE BOB5A AND Am9517A isolates the 8085A processor when DMA operations are in
process. The address for the first transfer operation comes out
INTERFACE
of the DMA controller in two bytes, the least-significant eight
This interface incorporates the Am9517A DMA into the 8085 bits on the eight address outputs and the most significant eight
microprocessor system. The multimode DMA controller issues bits on the data bus. The contents of the data bus are con-
a Hold Request whenever there is at least one valid DMA veniently latched into the Am25LS373 register to complete the
Request from a peripheral device. When the processor replies full 16 bits of the address bus. After the initial transfer takes
with a Hold Acknowledge signal, the Am9517A takes control of place, the register is updated only after a carry or borrow is
the address, data, and control buses. The 25LS2539 dual one- generated in the least-significant address byte. Figure 8-1.4
of-four decoder with three-state outputs easily decodes the I/O shows the block diagram for this particular interface.
and MEM space control lines from the processor, and also

A12 A13 .,4 A15

6
•
f J
r"8-A15 AD-A7

1 i'- 4.7kll :>'A7.A:

n,
TO SERVICE
QO-Q7 G'. DEVICES
r- G ..... e V3
Am25LS373
•
P.ft~
'---
r- Ill!
'---- A 25LS138
00-07
7'
'" ... ----I
Gl QO-Q7
Me CS AD·A3 M·A7 Ems ~

C u
.."
c
c c
ADST. G 25LS373

AI-AU
..ll.. l Ill! Oo-D7

0l[
u
c
HLDA JD eLR
HACK
AmaS17A c C
AEN
Jo, J "- i'-
t; Al'"
II Ii I~
74lS74 .1'>
~
~
HREQ
ep
d DBO-DB7

t J
n
HOLD
ALE r-- '---

r- ,.
10E 20E
AmB085A
CPU
1Y1 r----
101M lA

Rii 11'
1YO
-
r- ,.
Am25LS2539

'A
,'i'l
- Il5W

WR IE
1POL 'POL
2YO
r----
vee
3.
1 J CLOCK·-
RESET
OUT , I' .1'>
A
A~AD7 00.07
~ V

02188A-107

Figure 8·1.4 Am9517A to Am8085A Interface

8-4
 ------~-------- -- -- - - - -

8.1.5 8085 TO Am9518 DATA The minimum High time must be at least 150 nsfor an Am9518
CIPHERING PROCESSOR INTERFACE and 115 ns for an AmZ8068. resulting in a maximum clock rate
of 2.2 MHz and 2.5 MHz respectively.
Figure 8-1.5 shows the interface diagram between the 8085
microprocessor and the Am9518 Data Encryption device. The Minimum Low time: 0.5· T - 4 ns
DCP and the CPU operate synchronously at a maximum clock The minimum Low time is 190 ns at 2.2 MHz.
rate of 2.2 MHz. considerably simplifying the interface require-
The DCP requires that the MDS is synchronous to the clock.
ments. The 8-bit address/data bus of the CPU is directly con-
The range is 0 - TWL - 100 ns for the Am9518. TWL is the real
nected to the Master Port of the DCP. The Master Port Data
Low time of the clock.
Strobe is driven by RD or WR. The MRIW input of the DCP is
connected to the status line S1 of the 8085. This line is High Since the 8085 timing specification does not specify a timing
whenever the CPU executes a read instruction. The Master relationship between the clock and R D or W R. it is up to the
Port Address Strobe (MAS) is the inverted Address Latch designer to do the verification.
Enable (ALE). A decoded address and M/I 0= Low produces an A more sophisticated interface can avoid missing the timing
active Low Master Port Chip Select. It is latched by MAS. The specification and allows interfacing to a faster CPU. Ideas can
DCP can operate with the inverted CPU clock. if the clock is be found in the iSBX Bus Interface or 68000 Interface. The first
slowed down to satisfy the minimum High time requirement of shows a totally asynchronous operation of the DCP and the
the DCP. The 8085A data sheet gives a formula to determine CPU; the second shows how to delay the rising edge of the
the minimum clock High and Low times for slower clocks. clock following MDS.
Minimum High time: 0.5. T - 8 ns (T=clock cycle width)

ADo-AD7 ~IIIIIiJl MPo-MP7

Aa-A16

MCS
Am9518,
8085 RD AmZ8068
WR MDS

SI MR/W

ALE
MAS

ClK
Xl X2 ClK

~20PF

02188A-108

Figure S-1.5 SOS5-DCP Interface

8-5
----~-----.---.--- ._---
8.1.6 THE 8085 AND Am9519A Am8085A samples a READY (WAIT) signal on the rising edge
INTERRUPT CONTROLLER INTERFACE of ClK OUT during T2, and READY requires a 100 ns mini-
mum set up time prior to the rising edge of T2. The 3-input
The Am9519A is a Universal Interrupt Controller, a processor
NAND gate decodes an early I NT ~active signal using the two
support device designed to enhance the interrupt handling ca-
status outputs (SO,S1) and the 101M pin. This is required since
pability of a wide variety of processors. A single Am9519A can
the I NT A output from the Am8085A becomes valid too late to
manage the masking, priority resolution and vectoring of up to
meet the 100 ns setup time of READY. The Am9519A's
eight interrupts, and it may be easily expanded by the addition
PAUSE output takes over control of the READY line following
of other Am9519A chips to handle a nearly unlimited set of
T2. Insertion of a Wait State during the read and write opera-
interrupt inputs. It offers many programmable operating op-
tion to the Am9519A with CS is required only when the 5MHz
tions to improve both the efficiency and versatility of the host
Am8085A-2 part is used. The Wait State is needed because
system operations. The diagram in Figure 8-1.6 shows the
the minimum R 0 and W R pulse width of the Am8085A-2 is 230
interface between the Am8085 and the Am9519A. The two
ns, while the Am9519A-1, as example, requires 250 ns mini-
D-type flip-flops in conjunction with SO, S1 and 101M insert a
mum and the Am9519A, 300 ns minimum.
Wait State to the Am8085A whenever the microprocessor ac-
knowledges an interrupt. The circuitry is required since the

, A8-A15

II
A8·A15
.. ..'"
~ ~
L- A
ADO·AD7

;:..
~I
C/O
+5 v

'-- B

lo/iii
- C
G1
74LS138
RIP -
4.7K

rr
G2B
G2A YO CS

ADO·AD7 Vt
"-
"-
DBO·DB7
~ -V
Am8085A-2
Am9519A

INTR GINT

iNTA lACK

Rjj Rjj

WR WR
.- PAUSE
READY

iNTA
U-
SO 1 4.7K
.....J
lV-
r
Sl }5V
CLKOUT ALE
+5V
(

'REQUIRED ONLY WITH

5MHz Am8085A-2
"-- 0 Q~ 0

C .-- C Q ~ ~
CLR

L
02188A-109

Figure 8-1_68085 to Am9519A Interface

8-6
 an even address selects the data port and an odd address
9.0 INTERFACING TO THE selects the command or status port. The Am9511 A requires a
MC6809 60 ns Hold Time for CS or cin after WR goes High (inactive);
this is accomplished by using the Am25lS2519. The RiW out-
9-1 OVERVIEW OF THE MC6809 put of the MC6809 is decoded by the complementary latch
This 8-bit microprocessor, with five internal 16-bit registers, is outputs and the RD and WR pulses are generated by gating
compatible with all 6800 bus-oriented supplementary circuits these complementary outputs with the MC6809 timing signal
and peripherals. It is upward compatible with existing 6800 E. The Am2956 octal latch is necessary to meet the Data Hold
software and can work with a number of peripherals to en- Time requirement during writes to the Am9511 A. An external
hance system designs. The MC6809E uses external clocking timing source is connected to the Am9511 A ClK input since
to provide the flexibility required in a mUlti-processor system. this clock input can be asynchronous to the R D and W R con-
Three of the AMD peripherals are introduced here to interface trol signals from the MC6809.
with this microprocessor.
9-1.2 MC6809 TO Am9512 FLOATING
9-1.1 THE MC6809 AND Am9511A POINT PROCESSOR
FLOATING POINT PROCESSOR The Am9512 Floating Point Processor can be added to a
Figure 9-1.1 a shows the interface between the MC6809 and MC6809 based system to give throughput increase of an order
the Am9511A. The MC6809 uses memory mapped 110, of magnitude. Due to the peculiar timing characteristics of the
therefore, the Chip Select input of the Am9511 A needs to be MC6809 some additional interface circuitry is necessary. Fig-
derived from decoding address lines Al to A15. The cin input ure 9-1.2a shows a circuit implementing this interface. Figure
of the Am9511 A is generated from the address line Ao so that 9-1.2b is a timing diagram of the signals involved.

fIRQ END
"---
.....
MRDY --- PAUSE
+5V ----,
POL "-
C/D
YO

~ RD
AO D1
Yl
R/'J
APl25LS2519 74LSOO

"'1 ~ 'w'R
~
EOUT De '--""

Al-A15
-y
" 2X APl25LS252
_ _Y2
CP DE E
...,-
... CS

MC6809
E
EIN

II A1"I9511A
Q
I
97~
74LS04

,It

I~ ~ G
DE ~
DO-D7 ~DO-D7 YO-Y7
...- RESET
74LS04
AI'I2956
n r
r-V DBO-DB7
INPUT
RESET ClK
cJ
02l88A-ll0

Figure 9-1.1a MC6809 and Am9511A Interface

9-1
 RESET RESET
HRDY PAUSE
E ClK

AO DO YO c/D
R/iJ DI
YI
F=C:P- RD

~
25lS2519 loll ~ '" IoIR
AO

~ DECDDE D2 POLf-+v_ CS

~~~ Q
AI5
CP
MC6809 AM9512
Q 1
DO DE G DBO
AM25lS373
DB7

~
D7
1
r- VSS

IRQ ~

~ END
~
f1RQ ~ ERR

02188A-111
Figure 9-1.2a MC6809 to Am9512 Interface

E ~ / \ /
MC6809
Q
/ \ / '--
R/\/ ~ /
\ /
AM9512
\ /
1-7
>~ < >----1
DE~o LS373 \ /
Note! Dotted line Is dCltCl froM HC6809 without help froM LS373
02188A-112

Figure 9-1.2b MC6809 to Am9512 Write Cycle Timing Diagram

9-2
- WR and RD pulses are generated from RIW status line disabled. After the data is valid the latched outputs are ,en-
gated with timing signal E. RIW is decoded by the comple- abled, thereby holding the written data after the CPU releases
mentary latch outputs. the data bus. On Read cycles, the 25LS373 is bypassed and
- The 25LS2519 is necessary to hold CS, cil) (and WR to disabled.
LS373) after WR (at least 60 ns required).
9-1.3 THE MC6809 AND Am9517A
(Care should be taken to ensure CS decode meets setup
time requirements)
DMA CONTROLLER
This interface illustrates the connection of the 9517A DMA
- The 25LS373 is necessary to meet Data Hold Time require-
controller to the MC6809 processor, Figure 9-1.3a. Many
ments during writes to the 9512.
designs do not use multiplexers because they generate
At the start of a Write cycle, data is available immediately to the glitches when select changes. This particular design is an ex-
Am9512 because the latch is bypassed and the latch outputs ception; no glitches can occur because E is always low when
RIW switches. If a 68A09 or 68809 is used, a 9517A-4 should
also be used.

Ao
A7
~ Ao
A7

A AEN
......
1OE LE
I
AOSTB

Ao
A,.
25LS373

K-
Dr .l'\ Dr
DO Do
" "
Am9517A

LA
6809
Qt--- Q
6809
CLOCK
GENERATOR MRDY
t L-...y'
25LS2548

ACK
~~
WR
CS

Et--- E
E

r-- A
B lORe

~A
MRDe
B
LS257
A
,OWC
~B

A MWTC
~B S OE
V- I
R/Vi
SA
ss
....... I HACK

HALT
--:::;
,...,. HREQ

02188A-113

Figure 9-1.3a

9-3
When the 9517A is a slave, it ignores MRDC and MWTC ,and stretched in integral multiples of quarter (1/4) bus cycles, in
it does not matter that this circuit generates IORC AND M RDC order to allow interfacing to slower memories.
simultaneously, Because the MC6809 1/0 is memory-mapped,
The clock design illustrated in Figure 9-1.3b makes MRDY an
some interesting results can be achieved, For example, one
active low signal, and is sampled at one 4x clock before the
block of memory may be connected to 10RC and 10WC while end of E. This allows various devices to be wire-OR'ed to
another block is connected to MRDC and MWTC . With some control MRDY and, by making MRDY a "don't care" during
external hardware, this allows flyby transfers from memory-to- other parts of the cycle, makes generating M RDY easier. Fig-
memory, while peripheral-to-memory and memory-to-
ure 9-1 .3c illustrates the timing relationships between E, Q and
peripheral are still possible.
MRDY.
The input control signal, M RDY, shown in the MC6809 data
In many systems, MRDY will be generated from the system
sheet, allows stretching of E and Q to extend data access time.
clock; otherwise, a synchronizing flip-flop is added to prevent
E and Q operate normally while M RDY is high. And M RDY
metastable states.
must always be high, except when E is high. E and Q may be

r--------------..,----------t--- ETOSYSTEM

LS04

r---~I'>O-"""~r--- ETO PROCESSOR

QTOSYSTEM
.----ID Qo t--+--t_- AND PROCESSOR

CP Co

4.
OSC

02188A-114
Figure 9-1.3b

I7T \\ IIJ
Figure 9-1.3c 02188A-115

9-4
9-1.4 THE MC6809 AND Am9519A of other Am9519A chips to handle a nearly unlimited set of
INTERRUPT CONTROLLER interrupt inputs. It offers many programmable operating op-
tions to improve both the efficiency and versatility of the host
The Am9519A is an Universal Interrupt Controller, a processor
system operations. Figure 9-1.4a shows the interface between
support device designed to enhance the interrupt handling ca-
the MC6809 and the Am9519A; Figure 9-1.4b shows the timing
pability of a wide variety of processors. A single Am9519A can
relationships. Figure 9-1.4c shows how to generate MRDY. 03
manage the masking, priority resolution and vectoring of up to
Insures MRDY remains High during the second lACK pulse.
eight interrupts, and it may be easily expanded by the addition

3.3k

(FIRQ) IRQ G1NT

~
3.3k
A 15
A7
r--V Am29809

+5V
RIP

I ~ EI

As
A1
-----"'
-V
- Am29806
Am9519A-1

CS

6809

--
Ao C/O

E WR

I r-Ll
CLOCK
Q
CIRCUIT

1. ~
1 ROY

R/W
--
I RO

BS
h iAcK
~
BA

02188A-116
Figure 9-1.4a

9-5
 CLOCK MUST BE
STRETCHED TO MEET
Am9519A REQUIREMENTS
E

----------7~--------~
BA

120 MIN
REQUIRED BY Am9S19A

~ ~I

200~\------J1~
5OO{'--J VECTOR
HIGH
VECTOR
LOW

MRDY

4xCLK

Q,

Note: Time in nanosecods.

02188A-117

Figure 9-1.4b

9-6
 D Q3
HRDY
LS74
CP Q
PRE

D Q1 D Qe
lACK
LS74 LS74
CP Q CP Q
ClR

RESET

4 X ClK

02188A-118

Figure 9-1_4c

9-7
10.0 INTERFACING TO THE 8051 Figure 10-1.1a shows the 8051-DCP interface. The 8051 must
be programmed so that Port 0 provides a multiplexed ad-
10.1 OVERVIEW OF THE 8051 dress/data bus. Port 0 is connected to the Master Port of the
DCP.
The 8051 is an 8-bit microcomputer with an internal 4K x 8
ROM; 128 x 8 RAM; 32 I/O lines; two 16-bit timer/counters; a RD and WR are logically ORed to generate the Master Port
five-source, two-priority-Ievel, nested interrupt structure; a Data Strobe. Port 1.X controls the Master Port Read/Write
serial I/O port for either multiprocessor communications, I/O input (MRiW). This satisfies the set-up time requirement of
expansion, or full duplex UART; and on-chip oscillator and MRiW to MOS.
clock circuits. The 8051 can be expanded using standard TTL Master Port Chip Select can be tied Low if it is guaranteed that
compatible memories and the byte oriented 8080 and 8085 RD or WR only become active in a DCP access cycle. Other-
peripherals. The 8051 is efficient both as a controller and as a wise, it must be generated by an address decoder.
Boolean processor; it has extensive facilities for binary and
The 9568 can be used instead of the 9518/8068. The Am9568
BCD arithmetic and excels in bit-handling capabilities. The eliminates the need of Port 1.X to control Master Port
generic term "8051" is used to refer collectively to the 8051,
Read/Write. R 0 and W R can directly be connected to the cor-
8751, 9761, i8052, and 8031. The 8031 differs in that it lacks responding inputs of the DCP (MRD and MWR). ALE does not
program memory. The 8751 has an EPROM while the 9761
have to be inverted when connected to MALE.
and the i8052 have double the memory.
CLOCK DIVIDER
10.1.1 8051 TO Am9518 DCP The DCP clock divider logic as shown in Figure 10-1.1 a divides
INTERFACE the CPU clock by four or six, depending on the type of instruc-
tion the CPU executes (See the timing diagram in Figure 10-
8051 - Am9518/AmZ8068 1.1 b). If the CPU generates an ALE every sixth clock, the CPU
The 8031/805118751 Single-Component 8-Bit Microcomputer clock is divided by six. This is the normal case, and the speed
family can easily be interfaced to the DCP. Both devices, to- calculation of the DCP should be done for this clock rate. If the
gether with TTL logic, can form a stand-alone data ciphering
system for low to medium-speed data communication net-
works. Clear and ciphered data is handled serially with a pro-
grammable handshake protocol.

I I OSC
(12 MHz)

~ ....
Q1
I- D Qt-~ D

ClK ClK
Qr.;...~ MCS

XTAl1 J Q2

ClK

ALE MAS
8051 Am95181
RD
AmZ8068
SERIAL I MDS
--+ IN
WR
- ~

SERIAL
... SERIAL
OUT
PORT1.X
PORT1.Y
PORT1Z

.t ADDRESS/DATA BUS ~
MRlW
MFlG
SFLG

,;,
COMMUNICATIO NS r MPo-MP7
INTERFACE PORTO
~ C/K

V
02188A-119
Figure 10-1.1a 8051-DCP Interface

10-1
CPU is to execute "MOVX" instructions, every second ALE is 00 - Data Input or Output Regster
left out and the divide factor is four. For both cases the mini- 02 - Command or Status Register
mum DCP clock High or Low width is two CPU clock periods,
which guarantees that even a CPU clock of 12 MHz satisfies 06 - Mode Register
the minimum clock requirement for the Am9518 as well as the The Flags can be monitored by two input pins of the CPU, Port
AmZ8068. 1.Y and 1.Z. One Flag corresponds to the status of the Input
The AmZ8068 gives a wider range for the Data Strobe to R 0 or Register, the other one to the status of the Output Register.
WR delay. The typical value for the 8051 at room temperature They become active Low if the CPU can perform a data trans-
with a full load at these outputs is 50 ns. At a CPU clock rate of fer. In high-speed data ciphering applications, it might be too
10 MHz, this timing requirement is 0-100 ns (two clocks minus time consuming to toggle Port 1.x (MR/W). The toggling can
100 ns) for the Am9518 and 0-135 ns (two clocks minus 65 ns) be avoided by choosing the dual port configuration of the DCP.
for the AmZ8068. Both the Master and Slave Port are connected to Port 0 of the
CPU. During data Ciphering session, one port operates as the
PROGRAMMING data input port, the other port operates as the data output port.
This means that during the whole session, the data flow direc-
Port 1.X must be High for a Read access and Low for a Write
tion does not have to be turned around; MR/W can stay Low or
access. Data is transferred using a "MOVX Ri,.A:' or "MOVX
High for the whole session. MCS and SCS select the appropri-
A,Ri" instruction. Ri is register Ro or R1. Only this instruction
ate port.
generates the interface timing needed for the DCP. The inter-
nal register address is loaded into Rn before executing this
instruction.

!Is S1 112
Pt , P2 I Pt P2 I Pt ,

I
XTAL,

ALE

0,
s-r'-----------1
---I~I-.-------I ~------II ~ASE
02 IL-__---li

2.
} CASE

\~------------~I
PORTo = = = X A D D R E S S V A L I D _ DATA VALID X'-_ _ _ _ __

\~--------------~I
PORTo ===XADDRESS VALlDX'-_ _ _ _ _ _ _ _ _ _D_A_rA_"'_A.:L.:ID_ _ _ _ _ _ _ _ _ _ ..IXIo..______

02188A-120
Figure 10-1.1b 8051-DCP Timing Diagram

10-2
11.0 INTERFACING TO THE ZSOOO 11.1.2 THE Z8000 AND AmZ8068
DATA CIPHERING PROCESSOR
11.1.0 ZS001/S002 OVERVIEW INTERFACE
This CPU has a 16-bit data multiplexed address/data bus (the
The DCP is one of the state-of-the-art peripheral devices that
Z8001 has 7 additional non-multiplexed address outputs, works hand in hand with most of the popular microprocec;sors
called segment bits, extending its memory address range to 8 on the market. At the heart of the DCP is the Data Encryption
Mbyte). Standard (DES) algorithm unit that encrypts blocks of clear text
Z8001/8002 addresses are specified as bytes. In a 16-bit word into corresponding blocks of cipher text using a 56-bit key. The
the least significant byte has the higher address, the most DCP can hold three keys simultaneously: a Master Key to
significant byte has the lower address. This differs from the generate session keys, an Encryption Key, and a Decryption
8080, 8085, 8086, and Z80. Moreover, 16-bit and 32-bit words Key. The DCP's Input and Output registers can each transfer
must be aligned with an even address. data to and from the Master or Slave Port, on the 8-bit in-
The 8-bit peripherals should be connected to the lower half of put/output buses. The dual ports, with separate internal buses
the Z8001/2 data bus and must be addressed with odd ad- and separate input and output registers, compose a highly
dresses (non-contiguous addressing). pipelined data path that maximizes the throughput by allowing
simultaneous input, ciphering, and output operations.
The data bus is "asynchronous", i.e. the CPU machine cycle
can be stretched without clock manipulation by inserting Wait Figure 11-1.2 shows an interface between a 4-MHz Z8001/2
States between T2 and T3 of a read or write cycle to accom- microprocessor and the AmZ8068. The CPU and the DCP can
modate slower memory or peripherals. operate synchronously at a clock rate up to 3.5 MHz. All control
and strobe signals can be connected directly to the DCP.
Separate address space for I/O (64 kbytes) defined by Status
Code 0010 on the four Status outputs and by the RiW output The clock rate is reduced to 3.5 MHz to satisfy timing parame-
from the Z8001/2. Addresses are guaranteed valid before the ter (Clock lOW to MDS HIGH). The delay time from clock
rising edge of AS. falling to Data Strobe (DS) rising is specified at 0 to 70 ns for
the Z8000; the DCP requires 0 to 50 ns at 4 MHz. By reducing
Data from I/O must be valid before the rising edge of DS. Data the clock rate, this parameter becomes 0 to 70 ns at 3.5 MHz.
to I/O is valid during DS.
The system can operate at 4 MHz, if a 10-MHz Z8001/2 is
DMA: The bus is requested by activating the BUSRQ input to used. This faster version is specified for 0 to 45 ns.
the Z8001/2.
Bus Grant is confirmed by the BUS AK output from the A sample program for testing the DCP is shown in Figure
za001l2. 11-1.2b. The program is written in Z8000 (nonsegmented) as-
Interrupt is requested by activating either the NMI (non- sembly language. The DCP must be initialized for multiplexed
maskable), NVI (non-vectored interrupt), VI (vectored inter- Control Mode and "Master Port only" configuration. The cipher-
rupt), or SEGT (segment trap from the memory management ing mode can be ECB or CBC. The mode is defined by the
unit). varible "MODE". A one-cycle operation of the interface is
Interrupt is acknowledged by the STATUS code output from the assumed. For a two-cycle operation interface, instructions to
za001/2. During the Interrupt Acknowledge Cycle the Z8001/2 latch the register address must be added.
reads a 16-bit word containing an 8-bit jump vector for vectored
interrupt. 11.1.3 AmZ8002 TO Am9S11 A
FLOATING POINT PROCESSOR
11.1.1 Z8001 TO Am7990 LANCE INTERFACE
INTERFACE The Am9511 A can be interfaced to a 16-bit microprocessor
za001 interface to the LANCE is easily accomplished since the such as the AmZ8002. Since the data bus of the Am9511 A is
Z8000 also has a multiplexed bus and most of the control only 8 bits wide, the operations performed must be byte-
signals can directly be connected (Figure 11-1.1). This design oriented.
also uses the PAL (Am PAL 16l8) to reduce parts count. I NTR
The R D and W R inputs to the Am9511 A can obtained by
pin of the LANCE is connected to NVI pin of the Z8001, since
demultiplexing the data strobe (DS) output of the AmZ8002.
LANCE does not return a vector during the interrupt acknowl-
The data bus of the Am9511 A can be connected to either the
edge cycle. The PAL uses the status lines ST3-ST0 (when
upper 8 bits or the lower 8 bits of the AmZ8002 data bus. If the
Z8000 is the bus master), or HlDA from LANCE (when
Am9511A data bus is connected to the upper 8 bits, (Figure
LANCE is in bus master mode), to generate M, the memory
11-1.3a) the 110 address of the Am9511 A is always even. If the
request signal. The user should program the ACON, BCON,
Am9511A data bus is connected to the low 8 bits, the I/O
and BSWP to 1, prior to initializing the LANCE. When the
address is always odd. The chip select is derived from a
LANCE is the bus master, DALI and DAl0 control the
decode of A2 to A15' AI is used to select between data/status
transceiver. When the CPU is the bus master, T and Rare
during READ and data/command during WRITE.
generated from RiW and DS to control the transceiver.

11-1
 ADDRESS
BUS DATA BUS

/' 0
Vee r-
.
I Am29841
LE
Am29841
LE
I ~

~
~

~;Am29863
~

ADR
"- DAL1S-DALo
AD1S-ADo

SNo-SN6 A22-A16

0 TO SYSTEM DALI

I ~
i5Ai])
29806
CS

lAS AS
IDS CAS
R/'W READ
Vee
Z8001 ICE LE 1M lAS IDS READ IT IR
WAIT /WAIT IREADY REAiiY

ST3
ST2 -'"
ST3
ST2 AmPAL16L8
t
REAiiYFROM
LANCE
Z8K90.PAL SYSTEM
ST 1 ST 1 Am7990
STo STo Vee Vee
IHLDA
r-

NVi iiiffif
BUSRQ HOCfj"
BUSAK HiJ)A
Bm BYTE

Vee

RESET RESET
~

02188A-121

Figure 11-1.1

11-2
 AIIPAL 16L8 RASOUL 11. OSKOUY
PATOOl 11ARCH 13. 1984
File: Z8K90.PAL
Z8001 TO LANCE INTERFACE
ADVANCED MICRO DEVICES

lAS IHLDA READ ICS IDS IREADY ST3 ST2 STl GND

STO IT IN IriAIT LE IR IIC tiC NC VCC

IF I(HLDA) T = IREAD*/CS
IF (lllLDA) R = READ*DS*/CS

M = IHLDA*ST]*/ST2*/ST1*/STO +

IHLDA*/ST2*/ST1*STO +

IHLDA*ST3*ST2*/STl +

HLDA

wAIT IREADY

ILE = AS
Figure 11-1.1 b

siw G

STATUS
DECODER
~
STo-ST3
.,
l
ArnZ8000
LG ArnZ8068
~
1/0
ADa-AD15 ADDRESS MCS

AD3-AD7
r DECODER

ADo-AD7
Wr-j
~
~

r
MPo-MP7

AS MAS
DS MDS
R/W MR/W
ClK ClK
J CIK

~
OSCillATOR
(3.5 MHz)

02188A-122

Figure 11-1.2a Z8000-AmZ8068 Interface

11-3
--- ----~---~-~--~
MACR08000: Version 2.0 9/19/80 Page 1
0000 i**********************************·«**********************.*.* •• * •• **
0000 %* JS 3/12/84 *
0000 %* ENCRYPTION EXAMPLE FOR Z8000 *
0000 %* *
0000 %*************************************************************.*******
0000
0000 PROGRAM DCP SHOW;
0000 ORIGIN /flOOO;
1000
1000 DCP OUT: BYTE (32) ; % DCP OUTPUT STORAGE AREA
1020 DCP-I N: BYTE 32 ) ;
BYTE ~
% DCP INPUT STORAGE AREA
1040
1048
Clvr:
CE KEY: BYTE 8 .
8l; % CLEAR IV STORAGE FOR CBC/CFB ENCRYPTION
% CLEAR ENCRYPTION KEY
1050 MODE: BYTE ( 1 ) ; % MODE VALUE
1051 00
1052 DATAREG: WORD ( 1 ) ; % DATA REGISTER ADDRESS (MASTER PORT)
1054 CSR EG : WORD ( 1 ) ; % COMMAND/STATUS REGISTER ADDRESS
1056 MODEREG: WORD (1) ; % MODE REGISTER ADDRESS
1058
1058 DCP SHOW:
1058 6103 1052 - LD R3.DATAREG; % LOAD DATA REGISTER ADDRESS
105C 6101 1054 LD R1.CSREG; % LOAD COMMAND/STATUS REGISTER ADDRESS
1060 6102 1056 LD R2.MODEREG; % LOAD MODE REGISTER ADDRESS
1064 600F 1050 LOB RL7.MODE; % LOAD MODE VALUE
1068 3E2F OUTB R2.RL7; % SET MODE (INCLUDES SOFTWARE RESET)
106A
106A % LOAD IVE REGISTER
106A CFA5 LOB RL7.#A5; %IVE LOAD COMMAND
106C 3E1F OUTB R1.RL7;
106E 2108 0008 LD R8.#8; % BYTE COUNTER
1072 2109 1040 LD R9. CIVE; % ADDRESS OF CLEAR IVE FIELD
1076 3A92 0830 OTIRB R3.R9 .R8; % STROBE 8 BYTE IV IN
107A
107A % LOAD E KEY REGISTER
107A CFll LOB RL7.#1l; % LOAD E KEY COMMAND
10lC 3ElF OUTB R1.RL7;
107E 2108 0008 LD R8. #8; % BYTE COUNTER
1082 2109 1048 LD R9. CE KEY; % ADDRESS OF CLEAR E KEY FIELD
1086 3A92 0830 OTIRB R3,R9 -;-R8; % STROBE 8 BYTES KEY IN
108A
108A % ENCRYPTION SESSION
108A CF41 LOB RL7,#41; % START ENCRYPTION COMMAND
10BC 3ElF OUTB R1,RL7;
108E 2108 0008 LD R8,#8; % BY TE COUNTER
1092 2109 1020 LD R9, DCP IN; % DATA INPUT fiELD
1096 3A92 0830 OTIRB R3,R9 ,R8; % TRANSFER FIRST BLOCK
109A 2108 0008 LD R8,#8; % BYTE COUNTER
109E 3A92 0830 OTIRB R3,R9 .R8; % TRANSFER SECONO BLOCK
10A2 2108 0008 LD R8,#8; % BYTE COUNTER
10A6 210A 1000 LD R10, DCP OUT; % DATA OUTPUT FIELD
10AA 3A30 08AO I NIRB R10 ,R3,R8; % READ FIRST CIPHERED BLOCK BACK
10AE 2108 0008 LD R8,#8; % BYTE COUNTER
10B2 3A92 0830 OTIRB R3.R9 .R8; % TRANSFER THIRD BLOCK
10B6 2108 0008 LD R8.#8; % BYTE COUNTER
10BA 3A30 08AO INIRB R10 .R3.R8; % READ SECDND CIPHERED BLOCK BACK
lOBE 2108 0008 LD R8.#8; % BYTE COUNTER
10C2 3A92 0830 OTIRB R3.R9 .R8; % TRANSFER FOURTH BLOCK
10C6 2108 0008 LD R8.#8; % BYTE COUNTER
10CA 3A30 08AO IN IRB R10 ,R3.R8; % READ THIRD CIPHERED BLOCK BACK
10CE 2108 0008 LD R8,#8; % BYTE COUNTER
10D2 3A30 08AO IN IR B R10 .R3.R8; % READ FOURTH CIPHERED BLOCK BACK
10D6
10D6 % TERMINATE CIPHERING SESSION
1006 CFEO LDB RL7,#EO; % LOAD STOP COMMAND
10D8 3E1F OUTB R1,RL7; % ISSUE STOP COMMAND
10DA
10DA END.

Figure 11-1.2b

11-4
 Am25LS130

r B

Vi lID
R/W A Yo WR
G
ADo-15

OS t
AD 3 _1 5

A00-15 ~ / ) 080-7
['.r- 8 V

AmZ8173 AmZ8121 Am9511A

AmZ8002
(2X) A2-A15 (2X)
------J-. J\.,
0 y
/ EOUT CS
V ADDRESS
lATCH
14 -V CHIP
SELECT
AS
""" E DECODE ,Y

:l
(
EIN

A1
CI.D 4.7K:

r--<J NVI ST3 G RESET END p----.

ST2 C
0,
j<l WAIT ST1
B Am25lS138
NIO
ClK PAUSE p-
STO A Y2
RESET ClK EACK
74lS04
RESET Y .....
I"""
+5V~
10K
1
1K
+5Y

l
PS
1I I
A B C 0
- 0 Q L-c CR QD r--
74LS74 Am25LS195A

ClK CK at-- '---- SIL

CR J K ClK

I 1 j
1
~

02188A-123

Figure 11-1.3a AmZ8002 to Am9511A Interface

Due to the long READ access time of the Am9511A, the
AmZ8002 must be put in a WAIT state for each READ access
11.1.4 AmZ8002 TO Am9S12
to the Am9511 A. If the PA USE output of the Am9511 A is FLOATING POINT PROCESSOR
connected directly to the WAIT input of the AmZ8002, the INTERFACE
PAUSE output will arrive too late to put the AmZ8002 into the The AmZ8002 to Am9512 interface is similar to the AmZ8002
WAIT state. The Am25LS195A 4-bit shift register is used to to Am9511A interface, except the PAUSE output of the
solve this problem. During each address strobe, the aD output Am9512 can be connected directly to the WAIT input of the
will be forced LOW if chip select to the Am9511 A is present. AmZ8002. This is because the PAUSE output of the Am9512
The aD will remain LOW for two clock periods. If PAUSE is follows the chip select instead of R D and W R and the
LOW during this period, the WA IT line will remain LOW be- AmZ8002 has sufficient time to go into the WAIT state. Figure
cause the Am25LS195A is held at the reset state. After the 11-1 .4 shows the interface block diagram.
PAUSE returns to HIGH, the aD output will go HIGH after two
clocks and the AmZ8002 can proceed with the current opera-
tion.

+
B

Am25LS139 Y1 iID
R/W A YO WR
G ADO-AD15

OS 1
16
/8~
~
ADO-A015
L DBO-DB?
'v- -V
~o
ADO-'AD7

AmZ8002
AmZB173
(2X)
y
=t:; 114 V
AmZ8121
(2X)
Am9512

CHIP EOUT CS
ADDRESS
SELECT
LATCH
AS .J"o.. r-- DECODE

7~
- E

EIN

A1
C/O END 10---
,--< NY! ST3 G RESET
ST2 C
Am25LS138 ClK
PAUSE p-
,-c WAIT ST1 B
EACK
STO A Y2
RESET

1
ClK

...r-, 74LS04
+5V
10K
J
RESET
....
+5V 0
1K
6
PS
'-- D ot-- t--
Am74LS74

ClK CK at--
CR

'r'
74LS04 A
~

02188A·124

Figure 11-1.4 AmZ8002 to Am9512 Interface

11-6
11.1.5 THE Z8000 AND Am9513A CPU's OS and RiW lines. For maximum data bandwidth be-
tween the CPU and the Am9513A, Master Mode register bit
SYSTEM TIMING CONTROLLER MM13 should be set to 1 to configure the Am9513A for a 16-bit
INTERFACE data bus width. This can be accomplished by writing command
In this interface the Am9513A is connected with an AmZ8001 opcode FFEF(hex) to the Am9513A following each reset and
or AmZ8002 CPU (Figure 11-1.5a). The Am9513A appears in power up.
both Regular and Special I/O space, by virtue of the decoding Figures 11-1.5b, c, and d show various ways to drive the X1
of status lines ST1-ST3. Status line ST0 should be decoded and X2 inputs. Figure 11-1.5d shows the Am9513A internal
also if it is necessary to separate the Regular and Special I/O oscillator being driven by an external signal. The Am9513A
spaces. The Am25LS2536 is a latched decoder which stores Electrical Specification should be consulted for the voltage
the address information on the rising edge of AS, providing the levels required on the X2 input to guarantee proper oscillator
Am9513A with a stable CS for the duration of the transfer. The operation in this configuration.
Am74LS158 multiplexer generates RD and WR from the

AmZ8001/2 Am9513
OS R/W WR RD
L L L H
L H H L
H L H H
H H H H
RESET

Al r---<
IT
A2

B2
74LS158
Bl r-
os G VI AD
RIW S V2 WR

RESET

1
CLR
AS CP Y7 CS

p- Am9513A
r-- r:::f"')---c Gi p-
-
ST3
AmzaOOl ST2
OR
AmZaOO2 25LS2536 ~
ST1
AD13
G2 p- TO OTHER
I/O DEVICES

AD14
A
~
~
B p-
r- C _ _ VO p- ,-- 0 Qr- C/O
POL CE OE Am74LS74

~ J ADI
ADo-AD1S ~ "- DO-DIS

'"
~ -V

02188A-125

Figure 11-1.5a AmZS001/S002-Am9513 Interface

11-7
b c d (NO
CONNECTION)

X1 X1 Am9513 I-------c
X1
. - - _......_-/r
I gTAt"
Am9513A
.-----c +5V
Am9513

''";~1 p~----,
R Rint
X2 l.SlI" X2
r
~ ~

I "18PF
CERAMIC
I-= C

02188A-126

"Note: The Am9513A oscillator was changed from the Am9513. The capacitor
values in previous designs should be changed to the values shown.

Figure 11-1.5b, c, d Driving the X1 and X2 Inputs

line is grounded. This is an alternative solution to the discrete

11.1.6 THE Z8002 AND Am9519A
gate implementation. The Am9519A makes a vectored inter-
INTERFACE rupt request to the CPU using the Group Interrupt line (GINT )
The Am9519A Interrupt Controller is used in a system to which should be a LOW active output from the AM9519A.
relieve the CPU from the task of determining the sources of GINT is reset by the CPU vectored Interrupt Acknowledge
interrupts. It also serves to prioritize multiple interrupts. The (VIACK). The latter is decoded from the status lines and
interface block diagram is shown in Figure 11-1 .6a. The strobed into a flip-flop on the trailing edge of AS. The inclusion
Am2956 latches and Am8304 bidirectional buffers are used to of the flip-flop ensures that no spurious pulses from the status
generate separate add;·ess and data buses from the CPU ad- decode may erroneously cause an interrupt acknowledge.
dress/data bus. The latched address is checked by two
The Am9519A should be programmed to respond to a single
25LS2521 8-bit comparators which generate a Chip Select
interrupt acknowledge which in turn results in the transfer of 1
(CS) for the Am9519A. The addresses used here are 0021 H or
by1e of interrupt status to the CPU. This is sufficient since the
0023H in normal I/O space. Latched address bit LADDR1 is
vectored interrupt mechanism in the CPU requires only 1 by1e
not included in the comparison, but drives the c/o input to the
of status to form the vector. Since the Am9519A returns unique
Am9519A. This defines address 0021H as being the address
vectors for each of the 8 possible interrupts it receives from the
for data transactions and address 0023H as being the address
devices, the interrupt acknowledge cycle enables the CPU to
for command/status transaction. Note the I/O addresses are
determine the source of the interrupt without any further over-
odd, since the 9519A is on the lower data bus.
head. The interrupt inputs to the Am9519A from the devices
The lower half of the buffered data bus drives the bidirectional may be levels or pulses. If levels are employed, some form of
data bus of the Am9519A. The read and write commands re- request reset will have to be included. In the block diagram,
quired by the Am9519A are generated with half o~ 74LS139 pulsed interrupt requests are assumed and should be con-
decoder. DS is applied to the enable input and RIW is applied nected to the IREO inputs of the Am9519A, which should be
to the least significant select line. The most significant select programmed for Low Active interrupt requests.

11-8
 END
Vee Vee
AM9')IIA

EACK

iRma
00 - Dr
AMZBOOZ " OBo-Oll r iHfOi f~JO

TO SYSTEM AM9519A
ADORE 55 BU!> UNIV[ n!,Al
AM')SIIA
INTEnnUPT
CONTHOLLER
OHP EA(K
A"ln295C 5ELECT
DEeOOE EO - - - - - - t o o - j 0.
D Y] 25LS25Z1

(, Or .,
.,~I-
'~ril _ _------1
(10
j"j'\'(K Gi"m~
Y
AM9SIIA

50
NfO
510

51 I
VIA(K DS
"I:t Vee
WAif Vi 5Tl 10K
10K>
;;

02188A-127

Figure 11-1.6a AmZ8000 to Am9519A Interface

11-9
 SECTION D
BUS INTERFACING

12.0 MISCELLANEOUS The second PAL device in this interface designated 9516MBC,
converts the Am9516 signals into MULTIBUS' control signals.
12.1 MULTIBUS '" TO Am9516 It also generates R D and W R for the 8530 so that flyby trans-
fers can be done. When not doing flyby, this part of the PAL
INTERFACE device should be changed. There are several considerations
This interface shows the Am9516 connected to the when using the SCC with DMA not addressed here. These are
MULTIBUS' (Figure 12-1a). This is accomplished by two PAL covered in a separate application. This example will work for
device designs. The equations for the PAL devices are shown moderate serial data serial data rates. To operate the SCC at
in Figures 12-1b and 12-1c. The first designated Am9516MBC maximum speed, a local RAM should be used as bus arbitra-
does the MULTIBUS' arbitration as defined by the MULTIBUS' tion overhead could cause problems. The main purpose here
specification. Common bus request (CBRQ) was not imple- was to illustrate the versatility of PAL devices and how
mented in this design. Additionally this design holds the bus as easy it is to interface apparently incompatible devices to the
long as BREQ is active. If the user wishes to release the bus MULTIBUS '.
after each transaction the Am9516 should be programmed for The two PAL device shown are similar in function to the 8289
CPU interleave.
and 8288 shown with the 8086 CPU. A similar design could be
done for processors such as the 68000 or other bus masters
such as the 8052 CRT controller which has its own DMA.
• MULTIBUS is a registered trademark of Intel Corporation

12-1
 Am8284
RESET REseT

~
ROY, READY READY MNjMX

AEN,
AEH, ~
eLK
Am8086
CPU
WR
-
T CLOCK AO o -AD15
A
AODRESS·OATA BUS
lOCK
SO S; S, "
'"
SYSTEM MEMORY

II
~ _"""'M,'~7
~
7'
~~ ~'eLK LOCK So S, s, elK ALE 'A
G
D iiD'-

I
Am8289
AEH ""....
AEN DEN CD B De
25LS533
Y Ao-A23 °0-°15 READY

~
rg
~
I~ I~ II Ii II Ig Ii I~ I~ Ii I~
MULTIBUS
~>
<,
'"
MULT1BUS
I I"~ I~ Ii
;'lit

tI ~
< .; <
Ig11~II~V~I~ I~ l~
Ig
[ Ii Ii
,;;
,
8
I\l
I :h
l~:-"i
r(, r- ISSY
I
A,B,e,G
DECODER Am2948
B _ AmPAL16R4
R
Y, Yo A oe~~ (9516MBA)

" - IBUSY
LJ
D/e A/B
°0-°7
A I Aol { D r AD,-AD15

ADDRESS-DATA BUS
"I"" 1
" I" I 1
~
8
CH-A
I
L
I ':':. _m,"_!"o:.~
~ CH-B
AmZ8530
sec

REa
'll B/W
CREa
ALE P/D CS

Am9516
UDe
WAIT

SREa
Q 0
ose

ICEN ~

f------O=
R/W
CE AmPAL16L8
OACK
WR iiD os (9516MBC)

I I r I I

Figure 12-1a Am9516 to 8086 in a MULTIBUS® Environment 02188A-12S

PAL16L8 PAL DESIGN SPECIFICATION
PAT 002 JOE BRCICH 9 SEPT 82
MULTIBUS CONTROL FOR 9516
ADVANCE MICRO DEVICES
BACK MIO NC NC /DACK NC NC NC /CEN GND
NC /RD /IORC /DS /MWTC /MRDC /IOWC /RW /WR VCC
IF (BACK) IORC = /MIO*DS*/RW*CEN
IF (BACK) IOWC = /MIO*DS*RW*CEN
IF (BACK) MRDC .. MIO*DS*/RW*CEN
IF (BACK) MWTC .. MIO*DS*RW*CEN
RD - DACK*RW*BACK + IORC*/BACK
WR" DACK*, ~W*BACK + IOWC */BACK
IF (jBACK) OS = IORC + IOWC
IF (jBACK) RW - IOWC

DESCRIPTION
THIS PAL CONVERTS MULTI BUS SIGNALS INTO 9516 COMPATIBLE SIGNALS AND
VICE VERSA. IT ALSO SUPPORTS THE 8530 IN FLYBY MODE.

Figure 12-1b

12-3
PAL16R4 PAL DESIGN SPECIFICATION
PAT 004 JOE BRCICH 30 JULY 84
MULTIBUS ARBITER FOR 9516
ADVANCE MICRO DEVICES
/BCLK /XACK BRQ /BSY /BPRN /DS NC /IORC /CS GND
JOE /RBEN /TBEN BACK /CEN /BREQ /BUSY /BPRO /WAIT VCC
IF (/BACK) TBEN - IORC * CS
IF (/BACK) RBEN = /IORC * CS
WAIT - /XACK * BACK
BREQ :- BRQ
BPRO - /BRQ * BPRN
/BACK : - /BUSY
BUSY:- BREQ * BPRN * /BSY * /BUSY +
BREQ * BUSY * BPRN + DS * BUSY
CEN :- BACK
.DESCRIPTION
/CEN DELAYS THE COMMANDS TO MEET THE MULTI BUS REQUIREMENT THAT ADDRESS
AND DATA BE VALID AT LEAST 50 NS PRIOR TO CONTROL ACTIVE. IF WE DO
NOT ALLOW PREEMPTION; REMOVE BPRN FROM THE SECOND EXPRESSION IN THE
BUSY EQUEATION AND ELIMINATE THE THIRD EXPRESSION.

Figure 12-1c

12-4
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