IN74HC595A

8-BIT SERIAL-INPUT/SERIAL OR
PARALLEL-OUTPUT SHIFT REGISTER
WITH LATCHED 3-STATE OUTPUTS
High-Performance Silicon-Gate CMOS

The IN74HC595A is identical in pinout to the LS/ALS595. The

device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC595A consists of an 8-bit shift register and an 8-bit
D-type latch with three-state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register
also provides parallel data to the 8-bit latch. The shift register and
latch have independent clock inputs. This device also has an
asynchronous reset for the shift register.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA ORDERING INFORMATION
IN74HC595AN Plastic
• High Noise Immunity Characteristic of CMOS Devices
IN74HC595AD SOIC
TA = -55° to 125° C for all
packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 16 =VCC
PIN 8 = GND

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 IN74HC595A

MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PD Power Dissipation in Still Air, Plastic DIP+ 750 mW
SOIC Package+ 500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 260 °C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to 0 VCC V
GND)
TA Operating Temperature, All Package Types -55 +125 °C
t r, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V 0 1000 ns
VCC =4.5 V 0 500
VCC =6.0 V 0 400

This device contains protection circuitry to guard against damage due to high static voltages or
electric fields. However, precautions must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be
constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.

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 IN74HC595A

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C ≤85 ≤125 Unit
to °C °C
-55°C
VIH Minimum High- VOUT=0.1 V or VCC-0.1 V 2.0 1.5 1.5 1.5 V
Level Input IOUT≤ 20 µA 4.5 3.15 3.15 3.15
Voltage 6.0 4.2 4.2 4.2
VIL Maximum Low - VOUT=0.1 V or VCC-0.1 V 2.0 0.5 0.5 0.5 V
Level Input IOUT ≤ 20 µA 4.5 1.35 1.35 1.35
Voltage 6.0 1.8 1.8 1.8
VOH Minimum High- VIN=VIH or VIL 2.0 1.9 1.9 1.9 V
Level Output IOUT ≤ 20 µA 4.5 4.4 4.4 4.4
Voltage, QA-QH 6.0 5.9 5.9 5.9
VIN=VIH or VIL
IOUT ≤ 6.0 mA 4.5 3.98 3.84 3.7
IOUT ≤ 7.8 mA 6.0 5.48 5.34 5.2
VOL Maximum Low- VIN=VIH or VIL 2.0 0.1 0.1 0.1 V
Level Output IOUT ≤ 20 µA 4.5 0.1 0.1 0.1
Voltage, QA-QH 6.0 0.1 0.1 0.1
VIN=VIH or VIL
IOUT ≤ 6.0 mA 4.5 0.26 0.33 0.4
IOUT ≤ 7.8 mA 6.0 0.26 0.33 0.4
VOH Minimum High- VIN=VIH or VIL 2.0 1.9 1.9 1.9 V
Level Output IOUT ≤ 20 µA 4.5 4.4 4.4 4.4
Voltage, SQH 6.0 5.9 5.9 5.9
VIN=VIH or VIL
IOUT ≤ 4.0 mA 4.5 3.98 3.84 3.7
IOUT ≤ 5.2 mA 6.0 5.48 5.34 5.2
VOL Maximum Low- VIN=VIH or VIL 2.0 0.1 0.1 0.1 V
Level Output IOUT ≤ 20 µA 4.5 0.1 0.1 0.1
Voltage, SQH 6.0 0.1 0.1 0.1
VIN=VIH or VIL
IOUT ≤ 4.0 mA 4.5 0.26 0.33 0.4
IOUT ≤ 5.2 mA 6.0 0.26 0.33 0.4
IIN Maximum Input VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
Leakage Current
IOZ Maximum Three- Output in High- 6.0 ±0.5 ±5.0 ±10 µA
State Leakage Impedance State
Current, QA-QH VIN= VIL or VIH
VIN=VCC or GND
ICC Maximum VIN=VCC or GND 6.0 4.0 40 160 µA
Quiescent Supply IOUT=0µA
Current
(per Package)

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 IN74HC595A

AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)

VCC Guaranteed Limit
Symbol Parameter V 25 °C ≤85 ≤125 Unit
to °C °C
-55°C
fmax Minimum Clock Frequency (50% Duty 2.0 6.0 4.8 4.0 MHz
Cycle) (Figures 1and 7) 4.5 30 24 20
6.0 35 28 24
tPLH, Maximum Propagation Delay, Shift Clock 2.0 140 175 210 ns
tPHL to SQH (Figures 1and 7) 4.5 28 35 42
6.0 24 30 36
tPHL Maximum Propagation Delay , Reset to 2.0 145 180 220 ns
SQH (Figures 2 and 7) 4.5 29 36 44
6.0 25 31 38
tPLH, Maximum Propagation Delay , Latch 2.0 140 175 210 ns
tPHL Clock to QA-QH (Figures 3 and 7) 4.5 28 35 42
6.0 24 30 36
tPLZ, Maximum Propagation Delay , Output 2.0 150 190 225 ns
tPHZ Enable to QA-QH (Figures 4 and 8) 4.5 30 38 45
6.0 26 33 38
tPZL, Maximum Propagation Delay , Output 2.0 135 170 205 ns
tPZH Enable to QA-QH (Figures 4 and 8) 4.5 27 34 41
6.0 23 29 35
tTLH, tTHL Maximum Output Transition Time, QA-QH 2.0 60 75 90 ns
(Figures 3 and 7) 4.5 12 15 18
6.0 10 13 15
tTLH, tTHL Maximum Output Transition Time, SQH 2.0 75 95 110 ns
(Figures 1 and 7) 4.5 15 19 22
6.0 13 16 19
CIN Maximum Input Capacitance - 10 10 10 pF
COUT Maximum Three-State Output - 15 15 15 pF
Capacitance (Output in High-Impedance
State), QA-QH

Power Dissipation Capacitance (Per Typical @25°C,VCC=5.0 V

Package)
CPD Used to determine the no-load dynamic 300 pF
power consumption:
PD=CPDVCC2f+ICCVCC

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 IN74HC595A

TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)

VCC Guaranteed Limit
Symbol Parameter V 25 °C to ≤85°C ≤125 Unit
-55°C °C
tsu Minimum Setup Time,Serial 2.0 50 65 75 ns
Data Input A to Shift Clock 4.5 10 13 15
(Figure 5) 6.0 9 11 13
tsu Minimum Setup Time, Shift 2.0 75 95 110 ns
Clock to Latch Clock (Figure 6) 4.5 15 19 22
6.0 13 16 19
th Minimum Hold Time, Shift 2.0 5 5 5 ns
Clock to Serial Data Input A 4.5 5 5 5
(Figure 5) 6.0 5 5 5
trec Minimum Recovery Time, 2.0 50 65 75 ns
Reset Inactive to Shift Clock 4.5 10 13 15
(Figure 2) 6.0 9 11 13
tw Minimum Pulse Width, Reset 2.0 60 75 90 ns
(Figure 2) 4.5 12 15 18
6.0 10 13 15
tw Minimum Pulse Width, Shift 2.0 50 65 75 ns
Clock (Figure 1) 4.5 10 13 15
6.0 9 11 13
tw Minimum Pulse Width, Latch 2.0 50 65 75 ns
Clock (Figure 6) 4.5 10 13 15
6.0 9 11 13
t r, tf Maximum Input Rise and Fall 2.0 1000 1000 1000 ns
Times (Figure 1) 4.5 500 500 500
6.0 400 400 400

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 IN74HC595A

FUNCTION TABLE
Inputs Resulting Function
Operation Res Seria Shift Latc Output Shift Latch Serial Parallel
et l Cloc h Enable Register Register Output Output
Input k Cloc Contents Content SQH s QA-
A k s QH
Reset shift L X X L,H, L L U L U
register
Shift data into shift H D L,H, L D SRA U SRG SRH U
register SRN SRN+1
Shift register H X L,H, L,H, L U U U U
remains
unchanged
Transfer shift H X L,H, L U SRN LRN U SRN
register contents
to latch register
Latch register X X X L,H, L * U * U
remains
unchanged
Enable parallel X X X X L * ** * Enable
outputs d
Force outputs into X X X X H * ** * Z
high-impedance
state
SR = shift register contents X = don’t care
LR = latch register contents Z = high impedance
D = data (L,H) logic level * = depends on Reset and Shift Clock inputs
U = remains unchanged ** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTS:
A - Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register.
CONTROL INPUTS:
Shift Clock - Shift Register Clock Input. A low-to-high transition on this input causes the data at the
Serial Input pin to be shifted into the 8-bit shift register.
Reset - Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift
register portion of this device only. The 8-bit latch is not affected.
Latch Clock - Storage Latch Clock Input. A low-to-high transition on this input latches the shift
register data.
Output Enable - Active-Low Output Enable. A low on this input allows the data from the latches to
bepresented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance
state. The serial output is not affected by this control unit.
OUTPUTS:
QA-QH - Noninverted, 3-state, latch outputs.
SQH - Voninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register.
This output does not have three-state capability.

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 IN74HC595A

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

Figure 3. Switching Waveforms Figure 4. Switching Waveforms

Figure 5. Switching Waveforms Figure 6. Switching Waveforms

Figure 7. Test Circuit Figure 8. Test Circuit

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IN74HC595A

TIMING DIAGRAM

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 IN74HC595A

EXPANDED LOGIC DIAGRAM