Digital design and implementation of an overcurrent

relay on FPGA
Praveen Kumar Vishal Kumar Rajendra Pratap
Electrical engineering Electrical engineering Electrical engineering
Department Department Department
IIT Roorkee IIT Roorkee IIT Roorkee
Roorkee, India Roorkee, India Roorkee, India
[email protected] [email protected] [email protected]

Abstract—Protection relays are an important component of a dominant features, FPGA is currently used to perform various
power system, which are used to minimize the disturbances caused high-speed computation task of the power system such as power
by the internal and external faults of the system to ensure the monitoring, control, identification of the fault and protection of
continuous power supply. Overcurrent relay (OCR) is the most the distribution systems [8-13]. Coordinate rotation digital
economical and widely used component in the power system computing (CORDIC) processor based digital relay is suggested
protection. The OCR operates by tripping the circuit breaker in [8]. Relaying algorithms is implemented using CORDIC
when the fault current increases above the threshold value. This processor. Pipeline architecture of the OCR is suggested in the
paper presents the design and implementation of an inverse reference [10].
definite minimum time (IDMT) OCR on the reconfigurable
Close loop testing of the OCR with inverse characteristics
hardware i.e. field programmable gate array (FPGA). Two types
has not been done in the literature. In this paper a high speed
of inverse characteristics (i.e. Very and Extremely inverse) are
considered in the paper. An efficient moving window, root mean
moving window technique for RMS estimation is proposed and
square estimation module is proposed in this design which reduces the proposed algorithm of the OCR is also tested in close loop
the hardware requirement of the chip. Finally, the accuracy of the environment.
design is verified for different values of peak-up current and time The article is organized as follows: Section II describes the
dial settings. The relay is implemented on Xilinx Virtex ML-505 inverse definite minimum time characteristics of OCR. Section
FPGA Board. The proposed relay meet the characteristics of the III introduces the functional architecture of the prosed OCR.
IEEE standard C37.112-1996 for overcurrent relays. Digital design of the proposed algorithm is discussed in Section
IV. The algorithm is simulated on ISE simulator, obtained result
Keywords— FPGA, overcurrent relay, root mean square , peak- is discussed in Section V. Experimental set-up is explained in
up current Section VI and in Section VII experimental results are discussed.
Finally, the conclusion is provided in Section VI.
I. INTRODUCTION
Over-current relays are widely used as the main protection II. IDMT OCR
devices for medium-voltage distribution system [1-3]. The OCRs are used to control the excess current flowing through
evolution of the OCR, which begin from sluggish and costly the network caused by the abnormal behavior of the power
electromagnetic relays to relatively cheaper and efficient solid system component or external fault. There are three different
state relays and finally to advanced digital relays which are types of OCR suggested in the literature i.e. instantaneous,
economical, intelligent, fast and robust. define time, and IDMT [14]. Instantaneous OCR generates the
Many works has been suggested for the implementation of trip signal at the instant of fault occurrence. A fixed delay block
the OCR in the literature. A microprocessor (μP) based OCRs is is used by the definite time OCR to produce the trip signal.
presented in [4-6]. Whereas [7] presents the design of the OCR Whereas, the operating time of the IDMT characteristics based
on the programmable microcontroller (μC). μP and μC based OCR is inversely proportional to the current flowing into the
relay have a specific property of re-programmability due to OCR. Hence, the greater the fault current, the shorter will be
which multiple functions can be realized on a single chip.
However, the protection algorithm of these relay is processed
sequentially, resulting in increased computational time and the
overall performance of the relay is adversely affected. These
relays have also suffered from many limitations such as
computational burden, memory requirement, limited speed and
high cost.
The FPGA is a high-speed computation device and used for
the implementation of the intelligent electronic devices. The
advantage of the FPGA based IDMT relays over μC and μP
based relays are high computational performance, low latencies,
re-programmability and parallel processing. Due to these Fig. 1. Block diagram of the OCR module

978-1-5386-4318-1/17/$31.00 ©2017 IEEE

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 TABLE I. CONSTANTS FOR DIFFERENT TYPES OF STANDARD
INVERSE CHARACTERISTICOF

Relay
A B p tr
characteristics

MI 0.0515 0.1140 0.020 00 4.85

EI 28.2 0.1217 2.0000 29.1

VI 19.61 0.491 2.0000 21.6

relay operating time. Most of the OCRs are adopting the IEEE Fig. 2. Block diagram for the MAF
standard C37.112-1996 [15]. Different types of inverse
characteristics, such as standard inverse, very inverse and maximizes the conversion range of the ADC. The gain of the
extremely inverse, have been suggested in [15]. Fig.1 shows the amplifier is adjusted to (-)1 to allow the wide range of voltage
functional block diagram of the proposed OCR. In this block that can be sampled. The offset of the input signal is set to
diagram A, B, p, and Tr are the constants of the relay 1.65V and the amplitude of the signals is varied from (+)1.25 V
characteristics. Data_In, Clk, Reset, TDS and Ip are the inputs to (–)1.25V. The digital output of the ADC is obtained from the
and trip is the outputs of the proposed design. Different types of
equation (1) which is in the 14 bit 2’s complement data format.
characteristics of the OCR is selected by the variable parameter
constants given in Table I. Operating time of the relay is
emulated by the equations (1-2). ሺܸ௜௡ െ ͳǤ͸ͷሻ
‫ܦ‬ሾͳ͵ǣ Ͳሿ ൌ ͺͳͻʹ ൈ ‫ ܰܫܣܩ‬ൈ (3)
For 0 < M < 1 ͳǤʹͷ

‫ܣ‬
‫ݐ‬ሺ‫ܫ‬ሻ ൌ ܶ‫ ܵܦ‬൬ ൅ ‫ܤ‬൰ ሺͳሻ B. Low Pass Filter Module
‫ܯ‬௣െͳ
MAF is one of the simplest finite impulse response (FIR)
For M>1 filter has been used in the proposed design. A general equation
of Mth order MAF is given by (3).
‫ݐ‬௥
‫ݐ‬ሺ‫ܫ‬ሻ ൌ ܶ‫ ܵܦ‬൬ ൰ ሺʹሻ ெିଵ
‫ܯ‬ଶ െͳ ͳ
ூೝ೘ೞ ܻሾ݉ሿ ൌ ෍ ‫ݔ‬ሾ݊ െ ݉ሿ (4)
where, ‫ ܯ‬ൌ . ‫ܯ‬
ூ೛ ௠ୀ଴

III. FUNCTIONAL MODULE OF THE OCR MAF normalizes the higher order harmonics of the discrete
In this section, various sub-modules of the proposed OCR signal by replacing the present samples available with the mean
i.e. Analog to digital (ADC) converter, moving average filter of the (M-1)th samples present in the window. In the proposed
(MAF), root mean square estimation (RMS) and relay emulating OCR the value of M has been taken as 4 and applied to each
module have been discussed. sample obtained from the ADC module. Fig. 2 shows the block
diagram of the MAF. X[n] and Y[n] are the input and output data
A. Analog to digital converter of the MAF. T is the unit delay block which is used to store the
An onboard LTC1407A-1 dual ADC consisting of a data of 2nd, 3rd and 4th sample. The 2-bit logical left shift
programmable scaling pre-amplifier LTC6912-1 of Spartan®-3E operation is performed for the estimation of the average of the
development board [16] has been used in this design. The incoming data.
amplifier is used to scale the incoming voltage, so that it

Fig. 3. Data path for RMS module

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C. Calculation of Root Mean Square Value
The RMS of the filtered data Xm obtained from MAF is
computed by (4).
ெିଵ
ͳ
ܻሾ݉ሿ ൌ ෍ ‫ݔ‬ሾ݊ െ ݉ሿ (5)
‫ܯ‬
௠ୀ଴

where xm=x(m.¨T), ¨T is the sampling interval and N is the

number of samples of a fundamental power frequency cycle
(f=50 Hz). The sampling frequency is considered as 0.8 kHz to
accommodate 16 samples in a single cycle, which reduces the
memory requirement in terms of the number of registers along
with the hardware complexity of the RMS module. Fig. 3 shows
the complete data path of the RMS module in which 15 adders,
16 multipliers, 15 general purpose registers and one special shift
register for the division are used for calculation of the real time
average of the discrete signal coming from the MAF. Later the
Xilinx LogiCORE IP coordinate rotational digital computer
(CORDIC) v4.0 core [17] is used for the computation of the
square root of the sampled signal and provide 16-bits digital
data.
D. Relay emulating module
In this module inverse characteristics of the OCR are
emulated by the equations (6-8). The REM module initializes by
the sensing of the incoming signals i.e. Irms, rst, clk, Zr, and Zs.
REM operates on the positive-edge of the 800 Hz input clock Fig. 4. Flow chart of the OCR
signal. The condition of ȈZi is updated at every sample and
compared with the NT. At every clock edge of 800 Hz clock
signal, the sum (ȈZi) is computed and compared with NT. These
signals are processed by the REM, which takes the necessary ்ܰ οܶ
ܼ௦ ൌ  ሺ͸ሻ
decision as per the inputs, and OCR characteristic for the ‫ݐ‬ሺ‫ܫ‬ሻ
generation of the trip signal.
For 0<M ” 1
For M ” 1, Zi = Zr, and for M > 1, Zi = Zs.
௄ െ்ܰ οܶ
ܼ௥ ൌ  ሺͺሻ
෍ ܼ௜ ൐ ்ܰ  ሺ͸ሻ ‫ݐ‬ሺ‫ܫ‬ሻ
௜ୀଵ
For M > 1

Fig. 5. Simulation Result

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 In the above equations, t(I) is the relay set and reset time of data is monitored at a clock of 800 Hz which differentiate the
the proposed relay, that is evaluated by the equations (1-2). Zs current flowing through the network wheatear it is faulty current
and Zr are the registers which store the information of the or normal. At the arrival of the rms values of current, summation
contribution to the accumulator ™Zi, NT is the threshold value ȈZi is increased by the amount Zs when irms > Ip or decreased
[4] used to emulate the inverse characteristics of the relay. When by Zr when Irms < Ip. Updated value of ȈZi is compared with
™Zi > NT, the trip signal is generated sent to the CB. NT at every positive edge of 800 Hz clock. The trip signal is
generated when ȈZi is greater than NT.
IV. RELAY ALGORITHM
Fig.4 shows the flow chart of the proposed algorithm. The V. SIMULATION RESULTS
parameter of the characteristics curve A, B, p and tr are selected. The proposed design is verified on the ML-505 FPGA
development board [18]. Verilog ISE12.4 design tool has been
used for the development of the design. Simulation results of the
design have been verified using ISE simulator. Fig.5 shows the
simulation results for VI characteristics of the OCR, TDS=1 and
M= 10. In this plot, Pink colored signal shows the status of the
trip signal which is generated at t= 467.77ms. The tripping time
of the relay is compared with the IEEE standard relay
characteristics suggested in [15]. The trip time of the proposed
design is 407.289 ms whereas the trip time of the IEEE standard
relay is 406.548 ms calculated by the equation (1). 0.18 % is the
observed error of the proposed design with respect to the
Fig. 6. Hardware for the verification of the propose relay standard relay which shows the performance of the proposed
design is at par with the standard relay.
Ip of the proposed relay is also fixed to limit the current flowing VI. EXPERIMENTAL SETUP
through the power system network. The current sensed by the
CT is send to the analog to digital converter where the incoming The hardware of the proposed design is targeted to the Xilinx
analog signal is converted to the 16-bit digital data. The obtained Virtex-ML-505-XC5VLX50T-1FFG1136 FPGA using Xilinx
data is passed to the RMS estimation module. The RMS of the ISE 12.4 design suit. Fig.6 shows the complete hardware setup

Fig. 7. Close loop verification of the proposed relay

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