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Gateway Ref2

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0% found this document useful (0 votes)
25 views18 pages

Gateway Ref2

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gufran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Gateway Integration Tutorial

Silvaco, Inc.
2811 Mission College Blvd, Floor 6 June 1, 2020
Santa Clara, CA 95054
Phone: (408) 567-1000
Web: www.silvaco.com
Notice

The information contained in this document is subject to change without notice.


Silvaco, Inc. MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY
OF FITNESS FOR A PARTICULAR PURPOSE.
Silvaco, Inc. shall not be held liable for errors contained herein or for incidental or
consequential damages in connection with the furnishing, performance, or use of this
material.
This document contains proprietary information, which is protected by copyright laws of the
United States. All rights are reserved. No part of this document may be photocopied,
reproduced, or translated into another language without the prior written consent of Silvaco
Inc.
AccuCell, AccuCore, Athena, Athena 1D, Atlas, Blaze, C-Interpreter, Catalyst AD, Catalyst
DA, Clarity RLC, Clever, Clever Interconnect, Custom IC CAD, DeckBuild, DevEdit,
DevEdit 3D, Device 3D, DRC Assist, Elite, Exact, Expert, Expert C++, Expert 200,
ExpertViews, Ferro, Gateway, Gateway 200, Giga, Giga 3D, Guardian, Guardian DRC,
Guardian LVS, Guardian NET, Harmony, Hipex, Hipex C, Hipex NET, Hipex RC,
HyperFault, Interconnect Modeling, IWorkBench, Laser, LED, LED 3D, Lisa, Luminous,
Luminous 3D, Magnetic, Magnetic 3D, MaskViews, MC Etch & Depo, MC Device, MC
Implant, Mercury, MixedMode, MixedMode XL, MultiCore, Noise, OLED, Optolith,
Organic Display, Organic Solar, OTFT, Quantum, Quantum 3D, Quest, RealTime DRC, REM
2D, REM 3D, SEdit, SMovie, S-Pisces, SSuprem 3, SSuprem 4, SDDL, SFLM, SIPC, SiC,
Silvaco, Silvaco Management Console, SMAN, Silvaco Relational Database, Silos,
Simulation Standard, SmartSpice, SmartSpice 200, SmartSpice API, SmartSpice Debugger,
SmartSpice Embedded, SmartSpice Interpreter, SmartSpice Optimizer, SmartSpice RadHard,
SmartSpice Reliability, SmartSpice Rubberband, SmartSpice RF, SmartView, SolverLib,
Spayn, SpiceServer, Spider, Stellar, TCAD Driven CAD, TCAD Omni, TCAD Omni Utility,
TCAD & EDA Omni Utility, TFT, TFT 3D, Thermal 3D, TonyPlot, TonyPlot 3D, TurboLint,
Universal Token, Universal Utility Token, Utmost III, Utmost III Bipolar, Utmost III Diode,
Utmost III GaAs, Utmost III HBT, Utmost III JFET, Utmost III MOS, Utmost III MultiCore,
Utmost III SOI, Utmost III TFT, Utmost III VBIC, Utmost IV, Utmost IV Acquisition
Module, Utmost IV Model Check Module, Utmost IV Optimization Module, Utmost IV
Script Module, VCSEL, Verilog-A, Victory, Victory Cell, Victory Device, Victory Device
Single Event Effects, Victory Process, Victory Process Advanced Diffusion & Oxidation,
Victory Process Monte Carlo Implant, Victory Process Physical Etch & Deposit, Victory
Stress, Virtual Wafer Fab, VWF, VWF Automation Tools, VWF Interactive Tools, and Vyper
are trademarks of Silvaco, Inc.
All other trademarks mentioned in this manual are the property of their respective owners.
Copyright © 1984 - 2020, Silvaco, Inc.

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How to Read this Manual

Style Conventions

Font Style/Convention Description Example

Courier This represents the commands, ENTER


parameters, and variables syntax.
Courier Bold This represents keywords. FUNCTION

Times Roman Bold This represents the menu options File


and buttons in the GUI.
New Century Schoolbook This represents the variables of x+y=1
Italics equations.

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4 SILVACO, Inc.
Table of Contents

Chapter 1 
Gateway Link to Guardian LVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2 
TCAD Atlas MixedMode Netlisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Creating the Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Creating a Atlas device symbol in Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Edit the Atlas Control File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Generate the Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Extra Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Using the MixedMode Netlist in Atlas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3 
Gateway to Silos Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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Table of Contents

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Chapter 1
Gateway Link to Guardian LVS
After LVS has been run through the Silvaco Guardian LVS application, you can link the
Gateway schematics to the Expert layout application.
To do this, run the applications in this order:
1. Run Expert.
2. Run Guardian LVS from Expert (select VerificationLaunch LVS in Expert).
3. Run Gateway from Guardian LVS (selecting ActionLaunch Gateway in Guardian
LVS)
You can only cross probe between Gateway and Expert after an LVS comparison run in the
Guardian LVS Navigator tool.
To launch LVS Navigator, either:
• Select ActionLVS Navigator.
• Double click in a Match, Unmatch, Parameter Error or Parameter Match report on a
device or net name.
To use the first method, click the Restart button in LVS Navigator dialog. The checkboxes
Schematic and Layout should be checked on to highlight the devices/nets in Gateway and
Expert.
To use the second method:
1. Double click on a device/net name in a report. Unmatch report is most important because
it contains the discrepancies and potential matches. The Action upon Double click dialog
will appear.
2. Click LVS Navigator radio button and press OK to launch LVS Navigator tool.
The selected device/net will be highlighted in Gateway and Expert. You can press Next and
Previous buttons to highlight other devices or nets in a category.
For a full description of cross probing between applications, see Section “4.1.2.4: LVS
Navigator” of the Guardian LVS User’s Manual.

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Chapter 2
TCAD Atlas MixedMode
Netlisting
Creating the Netlist

2.1 Creating the Netlist


Gateway now allows circuit schematics to be saved as an Atlas MixedMode netlist to be run
using the Atlas device simulator.
To create a MixedMode netlist through Gateway, perform the following steps:
1. Create a new symbol for the Atlas device in Gateway
2. Create a schematic using the new symbol along with other SPICE symbols.
3. Edit the Atlas Control File.
4. Generate the netlist.

2.1.1 Creating a Atlas device symbol in Gateway


To create a new symbol for the Atlas device in Gateway, do the following (see Figure 2-1):
1. Open Gateway and the workspace.
2. Select FileNew Symbol.
3. Add graphics, pins, and attributes to the symbol.
4. Create an Atlas template string in the format:
@PREFIX@PATH %$B %$C %$E $INFILE $WIDTH
5. Save the symbol to a library in the workspace (e.g., spicelib).
Create a schematic using the new symbol along with other SPICE symbols.

Figure 2-1 Atlas Symbol Creation

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Creating the Netlist

To create a new schematic in Gateway, do the following (see Figure 2-2):


1. Open Gateway and the workspace.
2. Select FileNew Schematic.
3. Place the symbol created in the previous section along with other symbols from the
workspace to create a schematic.
4. Save the schematic.

Figure 2-2 ECL Inverter Circuit Schematic

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Creating the Netlist

2.1.2 Edit the Atlas Control File


This Atlas control file contains any extra information that is required for Atlas, such as model
definitions, SPICE control statements, and information to save.
To edit the Atlas control file, do the following:
1. Set the simulator to Atlas .
2. Select SimulationEdit Control File.
3. Add the control file information.
A sample Atlas control file will look like Figure 2-3.

Figure 2-3 An example of an Atlas Control File

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Creating the Netlist

2.1.3 Generate the Netlist


Once the schematic is created to generate the netlist, select SimulationCreate Netlist.
The netlist created will look like in Figure 2-4.

Figure 2-4 An example of an Atlas netlist

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Extra Options

2.2 Extra Options


There are a couple of preferences that apply to the MixedMode netlist, these are:
• 3D Mode - This option when checked adds .begin 3d at the top of the netlist to place
Atlas in 3D mode.
• Include ATLAS control file in netlist - This option when checked will include the Atlas
control file in the netlist. The control file will be appended to the netlist. If you enter a
.end statement in their Atlas control file, then Gateway will not add one. If Gateway
detects that a .end is missing, it will add one to the end of the netlist.

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Using the MixedMode Netlist in Atlas

2.3 Using the MixedMode Netlist in Atlas


After generating the netlist in Gateway and saving the file, you can load the netlist into
DeckBuild and simulate it using Atlas. You can also run the simulation directly from Gateway
using the Simulation menu.
Once the simulation is complete, you can view the output file created by Atlas (if an output
file has been chosen to be produced) by selecting PostprocessView .OUT File.
The resulting nodal voltages and current can be plotted using TonyPlot (see Figure 2-5),
which can be accessed directly through the Run Tonyplot option.

Figure 2-5 Nodal Voltages vs. Transient Time


MixedMode Netlisting from Gateway allows you to create complex circuits in a simply and
easy manner. It then passes the resulting netlist to Atlas for simulation.

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Using the MixedMode Netlist in Atlas

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Chapter 3
Gateway to Silos Link
To aid in debugging digital circuits, a link between the design browsers in Silos and Gateway
has been implemented.
To enable this link, follow these steps:
1. Generate the Silos project file through Gateway (SimulationView Input Deck)
2. Run Silos interactively and load the generated project file.
3. Compile or run the project file.
4. Select ExplorerLink Explorer to Gateway.
Figure 3-1 shows the link between Gateway and Silos for a digital design. When the link is
active any module instance in the Silos Design Browser will be reflected in the Gateway
design browser. The scope fields above the corresponding design browsers will be updated to
show the correct scope of the design on each application.

Figure 3-1 Gateway to Silos Link

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