Mipi C-PHY Specification v1-0

Specification for
SM
C-PHY
Version 1.0 – 05 August 2014

MIPI Board Adopted 07 October 2014
* NOTE TO IMPLEMENTERS *
This document is a Specification. MIPI member companies’ rights and obligations apply to this Specification as defined
in the MIPI Membership Agreement and MIPI Bylaws.
Copyright © 2013-2014 MIPI Alliance, Inc.

All rights reserved.
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Confidential
Specification for
SM
C-PHY
Version 1.0
05 August 2014
MIPI Board Adopted 07 October 2014
Further technical changes to this document are expected as work continues in the C-PHY Subgroup of
the PHY Working Group.

Confidential
Specification for C-PHY Version 1.0
05-Aug-2014
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Version 1.0 Specification for C-PHY
05-Aug-2014
Contents
1 Introduction .................................................................................................................1
1.1 Scope ............................................................................................................................... 1
1.2 Purpose ............................................................................................................................ 2
2 Terminology .................................................................................................................3
2.1 Use of Special Terms ....................................................................................................... 3
2.2 Definitions ....................................................................................................................... 3
2.3 Abbreviations................................................................................................................... 4
2.4 Acronyms ......................................................................................................................... 4
3 References ....................................................................................................................6
4 C-PHY Overview .........................................................................................................7
4.1 Summary of PHY Functionality ...................................................................................... 7
4.1.1 Summary of Lane Signaling States .............................................................................. 7
4.1.2 Representation of Symbols in High-Speed Mode ........................................................ 9
4.1.3 Representation of High-Speed Signaling States ......................................................... 10
4.2 Mandatory Functionality ............................................................................................... 10
5 Architecture ............................................................................................................... 11
5.1 Lane Modules ................................................................................................................ 11
5.2 Master and Slave............................................................................................................ 12
5.3 High Frequency Clock Generation ................................................................................ 12
5.4 Lanes and the PHY-Protocol Interface........................................................................... 12
5.5 Selectable Lane Options ................................................................................................ 13
5.6 Lane Module Types ....................................................................................................... 15
5.6.1 Unidirectional Lane .................................................................................................... 16
5.6.2 Bi-directional Lanes ................................................................................................... 16
5.7 Configurations ............................................................................................................... 16
5.7.1 Unidirectional Configurations .................................................................................... 17
5.7.2 Bi-Directional Half-Duplex Configurations ............................................................... 19
6 Global Operation .......................................................................................................21
6.1 Transmission Data Structure .......................................................................................... 21
6.1.1 Data Units ................................................................................................................... 21
6.1.2 Bit order, Serialization, and De-Serialization ............................................................. 21
6.1.3 Encoding, Decoding, Mapping and De-Mapping ....................................................... 21
6.1.4 Data Buffering ............................................................................................................ 32
6.2 Lane States and Line Levels .......................................................................................... 33
6.3 Operating Modes: Control, High-Speed, and Escape .................................................... 34
6.4 High-Speed Data Transmission ..................................................................................... 34
6.4.1 Burst Payload Data ..................................................................................................... 34
6.4.2 Start-of-Transmission ................................................................................................. 34
6.4.3 End-of-Transmission .................................................................................................. 35
6.4.4 HS Data Transmission Burst....................................................................................... 35
6.5 Bi-directional Lane Turnaround..................................................................................... 41
6.6 Escape Mode.................................................................................................................. 43
6.6.1 Remote Triggers ......................................................................................................... 44
6.6.2 Low-Power Data Transmission .................................................................................. 45
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6.6.3 Ultra-Low Power State ............................................................................................... 45

6.6.4 Escape Mode State Machine ...................................................................................... 45
6.7 (Not Used) ..................................................................................................................... 47
6.8 (Not Used) ..................................................................................................................... 47
6.9 Global Operation Timing Parameters ............................................................................ 47
6.10 System Power States ...................................................................................................... 49
6.11 Initialization ................................................................................................................... 49
6.12 Calibration ..................................................................................................................... 49
6.13 Global Operation Flow Diagram ................................................................................... 49
6.14 Data Rate Dependent Parameters (informative) ............................................................ 50
6.14.1 Parameters Containing Only UI Values .................................................................. 50
6.14.2 Parameters Containing Time and UI values ........................................................... 51
6.14.3 Parameters Containing Only Time Values .............................................................. 51
6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent ..... 51
7 Fault Detection ..........................................................................................................52
7.1 Contention Detection ..................................................................................................... 52
7.2 Sequence Error Detection .............................................................................................. 52
7.2.1 SoT Error .................................................................................................................... 53
7.2.2 SoT Sync Error ........................................................................................................... 53
7.2.3 EoT Sync Error ........................................................................................................... 53
7.2.4 Escape Mode Entry Command Error.......................................................................... 53
7.2.5 LP Transmission Sync Error ....................................................................................... 53
7.2.6 False Control Error ..................................................................................................... 53
7.3 Protocol Watchdog Timers (informative) ...................................................................... 53
7.3.1 HS RX Timeout .......................................................................................................... 53
7.3.2 HS TX Timeout .......................................................................................................... 53
7.3.3 Escape Mode Timeout ................................................................................................ 53
7.3.4 Escape Mode Silence Timeout ................................................................................... 53
7.3.5 Turnaround Errors ...................................................................................................... 54
8 Interconnect and Lane Configuration .....................................................................55
8.1 Lane configuration ......................................................................................................... 55
8.2 Boundary Conditions ..................................................................................................... 55
8.3 Definitions ..................................................................................................................... 55
8.4 S-parameter Specifications ............................................................................................ 56
8.5 Characterization Conditions .......................................................................................... 56
8.6 Interconnect Specifications ............................................................................................ 56
8.6.1 Differential Characteristics ......................................................................................... 57
8.6.2 Common-mode Characteristics .................................................................................. 57
8.6.3 Intra-Lane Cross-Coupling ......................................................................................... 57
8.6.4 Mode-Conversion Limits............................................................................................ 58
8.6.5 Inter-Lane Static Skew ............................................................................................... 58
8.7 Driver and Receiver Characteristics .............................................................................. 58
8.7.1 Differential Characteristics ......................................................................................... 58
8.7.2 Common-Mode Characteristics .................................................................................. 59
8.7.3 Mode-Conversion Limits............................................................................................ 59
9 Electrical Characteristics .........................................................................................60
9.1 Driver Characteristics .................................................................................................... 61
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9.1.1 High-Speed Transmitter.............................................................................................. 61

9.1.2 Low-Power Transmitter .............................................................................................. 66
9.2 Receiver Characteristics ................................................................................................ 71
9.2.1 High-Speed Receiver .................................................................................................. 71
9.2.2 Low-Power Receiver .................................................................................................. 73
9.3 Line Contention Detection............................................................................................. 74
9.4 Input Characteristics ...................................................................................................... 74
10 High-Speed Signal Timing .....................................................................................76
10.1 High-Speed UI Timing .................................................................................................. 76
10.2 High-Speed Data Eye Pattern and Transmission Timing............................................... 77
10.3 Timing Specifications .................................................................................................... 79
10.3.1 Tx Timing Specifications ....................................................................................... 80
10.3.2 Rx Timing Specifications ....................................................................................... 80
10.4 Reverse High-Speed Data Transmission Timing ........................................................... 81
11 Regulatory Requirements ......................................................................................82
12 Built-In Test Circuitry (Informative) ...................................................................83
12.1 Introduction.................................................................................................................... 83
12.2 Register Concept............................................................................................................ 83
12.2.1 Allocation of Register Addresses ........................................................................... 83
12.2.2 Example of Register Access via CCI ...................................................................... 84
12.2.3 Register Definitions ................................................................................................ 86
12.3 Tx Lane Test Circuitry ................................................................................................... 86
12.3.1 TLRn_Lane_Configuration .................................................................................... 87
12.3.2 TLRn_Test_Patterns_Select ................................................................................... 87
12.3.3 TLRn_PRBS_Seed_0 ............................................................................................. 89
12.3.4 TLRn_PRBS_Seed_1 ............................................................................................. 89
12.3.5 TLRn_PRBS_Seed_2 ............................................................................................. 89
12.3.6 Tx Lane PRBS Register Operation......................................................................... 89
12.4 Rx Lane Test Circuitry ................................................................................................... 90
12.4.1 RLRn_Lane_Configuration .................................................................................... 92
12.4.2 RLRn_Test_Pattern_Select..................................................................................... 92
12.4.3 RLRn_Rx_Lane_Status .......................................................................................... 92
12.4.4 RLRn_PRBS_Seed_0 ............................................................................................. 93
12.4.5 RLRn_PRBS_Seed_1 ............................................................................................. 93
12.4.6 RLRn_PRBS_Seed_2 ............................................................................................. 93
12.4.7 Rx Lane PRBS Register Operation ........................................................................ 93
12.4.8 Rx Lane Word Error Count and Word Count Functionality ................................... 94
12.4.9 RLRn_Word_Error_Count ..................................................................................... 95
12.4.10 RLRn_Word_Count_0 ............................................................................................ 95
12.4.11 RLRn_Word_Count_1 ............................................................................................ 95
12.4.12 RLRn_Word_Count_2 ............................................................................................ 95
12.4.13 RLRn_Word_Count_3 ............................................................................................ 95
12.4.14 RLRn_Word_Count_4 ............................................................................................ 96
12.4.15 RLRn_Word_Count_5 ............................................................................................ 96
12.4.16 Symbol Error Count and Symbol Error Location Functionality ............................ 96
12.4.17 RLRn_Sym_Error_Count ....................................................................................... 96
12.4.18 RLRn_1st_Sym_Err_Loc_0 ................................................................................... 96
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12.5 Tx Global Configuration and Status Registers .............................................................. 97
12.5.1 TGR_Global_Configuration ................................................................................... 97
12.5.2 Burst Enable/Disable Functionality ........................................................................ 97
12.5.3 TGR_Preamble_Length .......................................................................................... 98
12.5.4 TGR_Post_Length .................................................................................................. 99
12.5.5 TGR_Preamble_Prog_Sequence_0,1 ..................................................................... 99
12.5.8 TGR_Preamble_Prog_Sequence_6,7 ................................................................... 100
12.5.9 TGR_Preamble_Prog_Sequence_8,9 ................................................................... 100
12.5.10 TGR_Preamble_Prog_Sequence_10,11 ............................................................... 100
12.5.11 TGR_Preamble_Prog_Sequence_12,13 ............................................................... 100
12.6 Rx Global Configuration and Status Registers ............................................................ 101
Annex A Logical PHY-Protocol Interface Description (informative) .................102
A.1 Signal Description ....................................................................................................... 102
A.2 High-Speed Transmit from the Master Side ................................................................ 109
A.3 High-Speed Receive at the Slave Side......................................................................... 109
A.4 (Not Used) ................................................................................................................... 110
A.5 (Not Used) ................................................................................................................... 110
A.6 Low-Power Data Transmission.................................................................................... 110
A.7 Low-Power Data Reception ......................................................................................... 111
A.8 Turn-around ................................................................................................................. 111
Annex B Interconnect Design Guidelines (informative) ...................................... 113
B.1 Practical Distances ....................................................................................................... 113
B.2 RF Frequency Bands: Interference .............................................................................. 113
B.2.1 Specific Recommendations Regarding EMI and EMC ........................................ 113
B.3 Transmission Line Design ........................................................................................... 117
B.4 Reference Layer ........................................................................................................... 117
B.5 Printed-Circuit Board................................................................................................... 117
B.6 Flex Circuits................................................................................................................. 117
B.7 Series Resistance ......................................................................................................... 117
B.8 Connectors ................................................................................................................... 117
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Figures
Figure 1 Six Physical Layer Wire States of C-PHY Encoding, Nominal Values Shown ................. 8
Figure 2 State Diagram Showing All Six Wire States, and All Possible Transitions ....................... 9
Figure 3 End-to-End Transmission of Data, 16-bit Word Conversion to Channel States .............. 10
Figure 4 Universal Lane Module Functions ................................................................................... 11
Figure 5 Three Lane PHY Configuration ....................................................................................... 13
Figure 6 Option Selection Flow Graph .......................................................................................... 14
Figure 7 Universal Lane Module Architecture ............................................................................... 15
Figure 8 Lane Symbol Macros and Symbols Legend..................................................................... 17
Figure 9 All Possible Lane Types ................................................................................................... 17
Figure 10 Unidirectional Single Lane Configuration ..................................................................... 18
Figure 11 Unidirectional Multiple Lane Configuration without LPDT ......................................... 18
Figure 12 Two Directions Using Two Independent Unidirectional PHYs without LPDT ............. 19
Figure 13 Bidirectional Single Lane Configuration ....................................................................... 19
Figure 14 Bi-directional Multiple Lane Configuration .................................................................. 20
Figure 15 Encoder and Transmitter Example ................................................................................. 23
Figure 16 Receiver and Symbol Decoder Example........................................................................ 25
Figure 17 Data Mapping Between Seven Symbols and a 16-Bit Word.......................................... 26
Figure 18 Example, Mapping Circuit Converts 16-bit Word to Seven Symbols............................ 27
Figure 19 Example, Detailed Logic Diagram of 16-bit word to 7-Symbol Mapping Circuit ........ 28
Figure 20 Example, De-Mapping Circuit Converts Seven Symbols to a 16-Bit Word .................. 30
Figure 21 Detailed Logic Diagram Example of a 7-Symbol to 16-bit Word De-Mapper .............. 31
Figure 22 Line Levels..................................................................................................................... 33
Figure 23 High-Speed Data Transmission in Burst ........................................................................ 37
Figure 24 TX and RX State Machines for High-Speed Data Transmission ................................... 38
Figure 25 Link Error and Sync Word Detection Examples ............................................................ 40
Figure 26 Turnaround Procedure .................................................................................................... 41
Figure 27 Turnaround State Machine ............................................................................................. 42
Figure 28 Trigger-Reset Command in Escape Mode ..................................................................... 44
Figure 29 Two Data Byte Low-Power Data Transmission Example .............................................. 45
Figure 30 Escape Mode State Machine .......................................................................................... 46
Figure 31 Lane Module State Diagram .......................................................................................... 50
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Figure 32 Point-to-point Interconnect ............................................................................................ 55

Figure 33 Set-up for S-parameter Characterization of RX, TX and TLIS ..................................... 56
Figure 34 Template for Differential Insertion Losses..................................................................... 57
Figure 35 Differential Reflection Template for Lane Module Receivers ....................................... 58
Figure 36 Differential Reflection Template for Lane Module Transmitters ................................... 59
Figure 37 Template for RX Common-Mode Return Loss .............................................................. 59
Figure 38 Electrical Functions of a Fully Featured C-PHY Transceiver ........................................ 60
Figure 39 C-PHY Signaling Levels ................................................................................................ 61
Figure 40 Example High-Speed Transmitter .................................................................................. 62
Figure 41 Ideal Single-ended and Resulting Differential High Speed Signals............................... 64
Figure 42 Possible VCPTX and ΔVOD Distortions of the Single-ended HS Signals.......................... 64
Figure 43 Example Circuit for VOD and VCPTX Measurements ....................................................... 65
Figure 44 Example LP Transmitter ................................................................................................ 67
Figure 45 V-I Characteristic for LP Transmitter Driving Logic High ............................................ 67
Figure 46 V-I Characteristic for LP Transmitter Driving Logic Low ............................................. 68
Figure 47 LP Transmitter V-I Characteristic Measurement Setup.................................................. 68
Figure 48 Slew Rate vs. CLOAD (Falling Edge) ........................................................................... 70
Figure 49 Slew Rate vs. CLOAD (Rising Edge) ............................................................................ 70
Figure 50 HS Receiver Implementation Example .......................................................................... 71
Figure 51 Input Glitch Rejection of Low-Power Receivers ........................................................... 73
Figure 52 Signaling and Contention Voltage Levels ...................................................................... 74
Figure 53 Pin Leakage Measurement Example Circuit .................................................................. 75
Figure 54 Conceptual C-PHY Lane Timing Compliance Measurement Planes ............................. 76
Figure 55 Example of Wire State Transitions at Symbol (UI) Boundaries .................................... 76
Figure 56 Illustration of all Possible Transitions from the +x State ............................................... 78
Figure 57 Eye Pattern Example, “Conventional” Trigger .............................................................. 78
Figure 58 C-PHY Eye Pattern Example, Triggered Eye ................................................................ 79
Figure 59 C-PHY Receiver Eye Diagram ...................................................................................... 80
Figure 60 Configuration and Status Register mapping .................................................................. 84
Figure 61 Use of CCI for Normal Operation and Test ................................................................... 85
Figure 62 High-Level Tx and Rx, Global and Lane Functions ...................................................... 86
Figure 63 Transmit (Master) Lane Block Diagram with Test Circuitry ......................................... 87
Figure 64 Repeating 14-Symbol Debug Pattern in High Speed Data ............................................ 88
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Figure 65 Tx Lane PRBS Register Function and Seed Value Initialization ................................... 90
Figure 66 Receive (Slave) Lane Block Diagram with Test Circuitry ............................................. 91
Figure 67 Rx Lane PRBS Register Function and Seed Value Initialization ................................... 94
Figure 68 Example Showing Cause/Effect of TGR burst enable/disable ....................................... 98
Figure 69 Preamble Programmable Sequence, Showing Bit Order, and Enabled/Disabled......... 101
Figure 70 Example High-Speed Transmission from the Master Side .......................................... 109
Figure 71 Example High-Speed Receive at the Slave Side .......................................................... 110
Figure 72 Low-Power Data Transmission .................................................................................... 111
Figure 73 Example Low-Power Data Reception .......................................................................... 111
Figure 74 Example Turn-around Actions Transmit-to-Receive and Back to Transmit ................ 112
Figure 75 Radio Interference from Serial Interface Connections................................................. 113
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Tables
Table 1 Signal Voltage and Differential Voltage for the Six C-PHY Wire States ............................. 9
Table 2 Lane Type Descriptors ....................................................................................................... 16
Table 3 Definition of Wire States ................................................................................................... 22
Table 4 Five possible transitions from previous state to present state ............................................ 23
Table 5 Transmit Pre-Driver Control Logic ................................................................................... 23
Table 6 Receive Transition Mapping .............................................................................................. 24
Table 7 Truth Table of the “Tx Mux Control Logic” in Figure 19 ................................................. 29
Table 8 Truth Table of the “Rx Mux Control Logic” in Figure 21 ................................................. 32
Table 9 Lane State Descriptions ..................................................................................................... 33
Table 10 Start-of-Transmission Sequence ...................................................................................... 34
Table 11 End-of-Transmission Sequence ....................................................................................... 35
Table 12 High-Speed Data Transmission State Machine Description ............................................ 38
Table 13 High-Speed Data Reception State Machine Description ................................................. 39
Table 14 Link Turnaround Sequence .............................................................................................. 41
Table 15 Turnaround State Machine Description ........................................................................... 42
Table 16 Escape Entry Codes ......................................................................................................... 44
Table 17 Escape Mode State Machine Description ........................................................................ 46
Table 18 Global Operation Timing Parameters .............................................................................. 48
Table 19 Initialization States .......................................................................................................... 49
Table 20 C-PHY High-Speed Wire States ...................................................................................... 62
Table 21 Strong Zero and Strong One State for Each Wire Pair .................................................... 63
Table 22 HS Transmitter DC Specifications................................................................................... 65
Table 23 HS Transmitter AC Specifications ................................................................................... 66
Table 24 LP Transmitter DC Specifications ................................................................................... 68
Table 25 LP Transmitter AC Specifications ................................................................................... 69
Table 26 HS Receiver DC Specifications ....................................................................................... 72
Table 27 HS Receiver AC Specifications ....................................................................................... 72
Table 28 LP Receiver DC specifications ........................................................................................ 73
Table 29 LP Receiver AC Specifications........................................................................................ 73
Table 30 Contention Detector (LP-CD) DC Specifications ........................................................... 74
Table 31 Pin Characteristic Specifications ..................................................................................... 75
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Table 32 Unit Interval (UI) Specification ....................................................................................... 77

Table 33 Transmit Timing Requirements, TLIS and Receive are Informative ............................... 80
Table 34 Receiver Timing Specifications ....................................................................................... 80
Table 35 PPI Signals..................................................................................................................... 102
Table 36 Cellular Bands Used by Mobile Devices ....................................................................... 114
Table 37 GNSS and Connectivity Bands Used by Mobile Devices ............................................. 116
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Release History
Date Version Description
2014-Oct-07 V1.0 Initial Board Approved Release.
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1 Introduction
2 This document describes a high-speed serial interface called C-PHY, which provides high throughput
3 performance over bandwidth limited channels for connecting to peripherals, including displays and cameras.
4 (This includes display Chip-on-Glass receiver channels and image sensor transmitters that exhibit bandwidth
5 limitations.)
6 The C-PHY is based on 3-Phase symbol encoding technology delivering 2.28 bits per symbol over three-wire
7 trios, and is targeting 2.5Gsymbols/s. C-PHY has many characteristics in-common with D-PHY [MIPI01];
8 many parts of C-PHY were adapted from D-PHY. C-PHY was designed to be able to coexist on the same IC
9 pins as D-PHY so that dual-mode devices can be developed.
1.1 Scope
10 The scope of this document is to describe the lowest layers of the high-speed interfaces to be applied by MIPI
11 Alliance application or protocol level specifications. This includes the physical interface, electrical interface,
12 low-level timing and the PHY-level protocol. The goal has been to define a C-PHY high-speed interface that
13 can coexist on the same pins as the MIPI D-PHY interface. These functional areas taken together are known
14 as C-PHY.
15 The C-PHY specification shall always be used in combination with a higher layer MIPI specification that
16 references this specification. Any other use of the C-PHY specification is strictly prohibited, unless approved
17 in advance by the MIPI Board of Directors.
18 The following topics are outside the scope of this document:
19 • Explicit specification of signals of the clock generator unit. The C-PHY specification does
20 implicitly require a minimum performance of the internal clock signals in order to meet the
21 defined specifications of the external signals. Intentionally, only the behavior on the interface pins
22 is constrained. Therefore, the clock generation unit is excluded from this specification, and will be
23 a separate functional unit that provides the required clock signals to the C-PHY in order to meet
24 the specification. This allows many implementation trade-offs as long as these do not violate this
25 specification.
26 • Procedure to resolve contention situations. The C-PHY contains several mechanisms to detect
27 Link contention. However, certain contention situations can only be detected at higher levels and
28 are therefore not included in this specification.
29 • Ensure proper operation of a connection between different Lane Module types. There are
30 several different Lane Module types to optimally support the different functional requirements of
31 several applications. This means that next to some base-functionality there are optional features
32 which can be included or excluded. This specification only ensures correct operation for a
33 connection between matched Lane Modules types, which means: Modules that support the same
34 features and have complementary functionality. In case the two sides of the Lane are not the same
35 type, and these are supposed to work correctly, it shall be ensured by the manufacturer(s) of the
36 Lane Module(s) that the provided additional functionality does not corrupt operation. This can be
37 most easily accomplished if the additional functionality can be disabled by other means
38 independent of the MIPI C-PHY interface, such that the Lane Modules behave as if they were the
39 same type.
40 • ESD protection level of the IO. The required level of ESD protection will depend on a particular
41 application environment and product type.
42 • Exact symbol error rate value. The actual value of the achieved symbol error rate depends on the
43 total system integration and the hostility of the environment. Therefore, it is impossible to specify
44 a symbol error rate for individual parts of the Link. This specification allows for implementations
45 with a symbol error rate less than 10-12.
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46 • Specification of the PHY-Protocol Interface. The C-PHY specification includes a PHY-Protocol

47 Interface (PPI) annex that provides one possible solution for this interface. This annex is limited to
48 the essential signals for normal operation in order to clarify the kind of signals needed at this
49 interface. For power reasons this interface will be internal for most applications. Practical
50 implementations may be different without being inconsistent with the C-PHY specification.
51 • Implementations. This specification is intended to restrict the implementation as little as possible.
52 Various sections of this specification use block diagrams or example circuits to illustrate the
53 concept and are not in any way claimed to be the preferred or required implementation. Only the
54 behavior on the C-PHY interface pins is normative. Regulatory compliance methods are not within
55 the scope of this document. It is the responsibility of product manufacturers to ensure that their
56 designs comply with all applicable regulatory requirements.
57 Items that are outside of the scope of this document are generally the same as those described in the D-PHY
58 specification, except for a detailed description of built-in test circuitry and test patterns. The built-in test
59 circuit description is included as an informative chapter to be followed at the option of the system or device
60 implementer. This document deviates from the norm and defines the behaviors of the test circuitry because
61 the general functionality of C-PHY is different from most other PHY implementations. It is useful to provide
62 a common test circuit description that can be followed by device implementers and test equipment providers
63 so there will be compatibility between devices implementing C-PHY and test equipment.
64 Coexistence with D-PHY on the same IC pins is possible, and likely in many applications; the means of doing
65 so is beyond the scope of this standard.
66 Regulatory compliance methods are not within the scope of this document. It is the responsibility of product
67 manufacturers to ensure that their designs comply with all applicable regulatory requirements.
1.2 Purpose
68 The C-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance interface
69 specifications for mobile devices such as, but not limited to, camera, display and unified protocol interfaces.
70 Implementing this specification reduces the time-to-market and design cost of mobile devices by
71 standardizing the interface between products from different manufacturers. In addition, richer feature sets
72 requiring high data rates can be realized by implementing this specification. Finally, adding new features to
73 mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications.
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2 Terminology
2.1 Use of Special Terms

74 The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the
75 words “shall”, “should”, “may”, and “can” in the development of documentation, as follows:
76 The word shall is used to indicate mandatory requirements strictly to be followed in order
77 to conform to the Specification and from which no deviation is permitted (shall equals is
78 required to).
79 The use of the word must is deprecated and shall not be used when stating mandatory
80 requirements; must is used only to describe unavoidable situations.
81 The use of the word will is deprecated and shall not be used when stating mandatory
82 requirements; will is only used in statements of fact.
83 The word should is used to indicate that among several possibilities one is recommended
84 as particularly suitable, without mentioning or excluding others; or that a certain course of
85 action is preferred but not necessarily required; or that (in the negative form) a certain
86 course of action is deprecated but not prohibited (should equals is recommended that).
87 The word may is used to indicate a course of action permissible within the limits of the
88 Specification (may equals is permitted to).
89 The word can is used for statements of possibility and capability, whether material,
90 physical, or causal (can equals is able to).
91 All sections are normative, unless they are explicitly indicated to be informative.
2.2 Definitions
92 Bi-directional: A single Lane that supports communication in both the forward and reverse directions.
93 C-PHY: The PHY defined in this document. C-PHYs may be used in channel-limited applications, hence the
94 use of the character “C.”
95 Escape Mode: An optional mode of operation for lanes that allows low bit-rate commands and data to be
96 transferred at very low power.
97 Forward Direction: The signal direction is defined relative to the direction of the high-speed data. The main
98 direction of data communication, from source to sink, is denoted as the forward direction.
99 Lane: Consists of two complementary lane modules communicating via three-line, point-to-point lane
100 Interconnects. The term “lane” is often used to denote interconnect only.
101 Lane Interconnect: Three-line, point-to-point interconnect used for both differential high-speed signaling
102 and low-power, single-ended signaling.
103 Lane Module: Module at each side of the lane for driving and/or receiving signals on the lane.
104 Line: An interconnect wire used to connect a driver to a receiver. Three lines are required to create a lane
105 interconnect.
106 Link: A connection between two devices containing at least one lane. A link consists of at least two PHYs
107 and one lane interconnect.
108 Master: The master side of a link is defined as the side that transmits the high-speed data. The master side
109 transmits data in the forward direction.
110 PHY: A functional block that implements the features necessary to communicate over the lane interconnect.
111 A PHY consists of one or more lane modules and a PHY adapter layer.

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112 PHY Adapter: A protocol layer that converts symbols from an APPI to the signals used by a specific PHY
113 PPI.
114 PHY Configuration: A set of lanes that represent a possible link. A PHY configuration consists of a one or
115 more lanes.
116 Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for forward
117 direction.
118 Slave: The slave side of a link is defined as the side that receives high-speed data from the master. The slave
119 side may transmit data in low-power mode in the reverse direction.
120 Turnaround: Reversing the direction of communication on a lane.
121 Unidirectional: A single lane that supports communication in the forward direction only.
122 Wire State: the combination of signal levels driven on the three lines of a lane.
2.3 Abbreviations
123 e.g. For example (Latin: exempli gratia)
124 i.e. That is (Latin: id est)
2.4 Acronyms
125 APPI Abstracted PHY-Protocol Interface
126 BER Bit Error Rate
127 CIL Control and Interface Logic
128 DDR Double Data Rate
129 EMI Electro Magnetic Interference
130 EoT End of Transmission
131 HS High-Speed; identifier for operation mode
132 HS-RX High-Speed Receiver (Low-Swing Differential)
133 HS-TX High-Speed Transmitter (Low-Swing Differential)
134 IEEE Institute of Electrical and Electronics Engineers
135 IO Input-Output
136 ISTO Industry Standards and Technology Organization
137 LP Low-Power: identifier for operation mode
138 LP-CD Low-Power Contention Detector
139 LPDT Low-Power Data Transmission
140 LP-RX Low-Power Receiver (Large-Swing Single-Ended)
141 LP-TX Low-Power Transmitter (Large-Swing Single-Ended)
142 LPS Low-Power State(s)
143 LSB Least Significant Bit
144 Mbps Megabits per second
145 MSB Most Significant Bit

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146 PHY Physical Layer

147 PICS Protocol Implementation Conformance Statement
148 PLL Phase-Locked Loop
149 PPI PHY-Protocol Interface
150 PWB Printed Wiring Board
151 PRBS Pseudorandom Binary Sequence
152 RF Radio Frequency
153 RX Receiver
154 SE Single-Ended
155 SoT Start of Transmission
156 TLIS Transmission-Line Interconnect Structure: physical interconnect realization between Master
157 and Slave
158 TX Transmitter
159 UI Unit Interval, equal to the duration of any HS state
160 ULPS Ultra-Low Power State

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3 References
161 [MIPI01] MIPI Alliance Specification for D-PHY, version 1.2, MIPI Alliance, Inc., 10 September 2014.
162 [PET01] Peterson, W. Wesley; Weldon, E. J. Jr., Error-Correcting Codes, Second Edition, Massachusetts
163 Institute of Technology, 1972.

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For Evaluation Only.
05-Aug-2014
4 C-PHY Overview
164 C-PHY describes a high-speed, rate-efficient PHY, especially suited for mobile applications where channel
165 rate limitations are a factor. The needs of rate limited channels are accomplished through the use of 3-Phase
166 symbol encoding technology delivering approximately 2.28 bits per symbol over a three-wire group of
167 conductors. This C-PHY specification has been written primarily for the connection of cameras and displays
168 to a host processor. Nevertheless, it can be applied to many other applications.
169 C-PHY has re-used many parts of the D-PHY standard. C-PHY was designed to coexist on the same IC pins
170 as D-PHY so that dual-mode devices can be developed. C-PHY high-speed data coding differs substantially
171 from the D-PHY clock-forwarding system, although the high-speed signal levels and terminations bear some
172 similarity. The low-power mode of D-PHY is reused almost completely, and the transitions to and from the
173 high-speed and low-power modes is very similar to the D-PHY standard.
174 Key characteristics of C-PHY coding are:
175 • Uses a group of three conductors rather than conventional pairs. The group of three wires is called
176 a lane, and the individual lines of the lane are called: A, B and C. C-PHY does not have a separate
177 clock lane.
178 • Within a three-wire lane, two of the three wires are driven to opposite levels; the third wire is
179 terminated to a mid-level (at either one end or both ends), and the voltages at which the wires are
180 driven changes at every symbol.
181 • Multiple bits are encoded into each symbol epoch, the data rate is ~2.28x the symbol rate. There is
182 no additional overhead for line coding, such as 8b10b, which is not needed.
183 • Clock timing is encoded into each symbol. This is accomplished by requiring that the combination
184 of voltages driven onto the wires must change at every symbol boundary. This simplifies clock
185 recovery.
186 • The signal is received using a group of three differential receivers.
187 • The C-PHY interface can co-exist on the same pins/pads as the D-PHY interface signals.
4.1 Summary of PHY Functionality

188 The C-PHY provides a synchronous connection between master and slave. A practical PHY configuration
189 consists of one or more three-wire lanes. The link includes a high-speed signaling mode for fast-data traffic
190 and a low-power signaling mode for control purposes. Optionally, a low-power escape mode can be used for
191 low speed asynchronous data communication. High-speed data communication appears in bursts with an
192 arbitrary number of payload data bytes. The low-power mode and escape mode remain the same as defined
193 in the D-PHY specification.
194 The PHY uses three wires per lane, so three wires are required for the minimum PHY configuration. In high-
195 speed mode each lane is terminated on both sides and driven by a low-swing, 3-Phase signal. In low-power
196 mode all wires are operated single-ended and non-terminated. To minimize EMI, the drivers for this mode
197 shall be slew-rate controlled and current limited.
198 The maximum achievable bit rate in high-speed mode is determined by the performance of transmitter,
199 receiver and interconnect implementations. This specification is primarily intended to define a solution for a
200 symbol rate range of 80 to 2500 Msps per lane, which is the equivalent of about 182.8 to 5714 Mbps per lane.
201 Although PHY configurations are not limited to this range, practical constraints make it the most suitable
202 range for the intended applications. For a fixed clock frequency, the available data capacity of a PHY
203 configuration can be increased by using more lanes. Effective data throughput can be reduced by employing
204 burst mode communication. The maximum data rate in low-power mode is 10 Mbps.
4.1.1 Summary of Lane Signaling States

205 Figure 1 shows the current flow through the lane for all six wire states. The circuit examples below are
206 simplified for the data encoding example; they are intended to illustrate the basic signaling states on the three-

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207 wire link. Figure 1 shows the positive-polarity wire states on the left and negative-polarity wire states on the
208 right. The three rotation states (x, y and z) are shown from top to bottom. The six driven states (called wire
209 states) on a C-PHY lane are called: +x, -x, +y, -y, +z, and -z. The positive polarity wire states have the same
210 wires driven as the corresponding negative polarity states, but the polarity is opposite on the driven pair of
211 wires. For example: the +x wire state is defined as A being driven high and B driven low, while the -x wire
212 state is B driven high and A driven low. The “undriven” conductor can be undriven when operating at lower
213 symbol rates, or is actually driven by a termination at a voltage half way between the highest and lowest
214 driven levels if operating at higher symbol rates.
Positive Polarity States Negative Polarity States

Master side “A” to “B” (+x state) Master side “B” to “A” (-x state)
+V Slave side +V Slave side
PU_A 50 “A” Z0=50 ZID/2=50 PU_A 50 “A” Z0=50 ZID/2=50
+ +
PD_A 50 Rx_AB PD_A 50 Rx_AB
+V/2 “1” -V/2 “0”
+V - +V -
PU_B 50 “B” Z0=50 ZID/2=50 PU_B 50 “B” Z0=50 ZID/2=50
+ +
PD_B 50 Rx_BC PD_B 50 Rx_BC
-V/4 “0” +V/4 “1”
+V - +V -
PU_TC 100 “C” Z0=50 ZID/2=50 PU_TC 100 “C” Z0=50 ZID/2=50
+ +
PD_TC 100 Rx_CA PD_TC 100 Rx_CA
-V/4 “0” +V/4 “1”
- -
Master side “B” to “C” (+y state) Master side “C” to “B” (-y state)
PU_TA 100 “A” Z0=50 ZID/2=50 PU_TA 100 “A” Z0=50 ZID/2=50
+ +
PD_TA 100 Rx_AB PD_TA 100 Rx_AB
-V/4 “0” +V/4 “1”
+V - +V -
PU_B 50 “B” Z0=50 ZID/2=50 PU_B 50 “B” Z0=50 ZID/2=50
+ +
PD_B 50 Rx_BC PD_B 50 Rx_BC
+V/2 “1” -V/2 “0”
+V - +V -
PU_C 50 “C” Z0=50 ZID/2=50 PU_C 50 “C” Z0=50 ZID/2=50
+ +
PD_C 50 Rx_CA PD_C 50 Rx_CA
-V/4 “0” +V/4 “1”
- -
Master side “C” to “A” (+z state) Master side “A” to “C” (-z state)
PU_A 50 “A” Z0=50 ZID/2=50 PU_A 50 “A” Z0=50 ZID/2=50
+ +
PD_A 50 Rx_AB PD_A 50 Rx_AB
-V/4 “0” +V/4 “1”
+V - +V -
PU_TB 100“B” Z0=50 ZID/2=50 PU_TB 100“B” Z0=50 ZID/2=50
+ +
PD_TB 100 Rx_BC PD_TB 100 Rx_BC
-V/4 “0” +V/4 “1”
+V - +V -
PU_C 50 “C” Z0=50 ZID/2=50 PU_C 50 “C” Z0=50 ZID/2=50
+ +
PD_C 50 Rx_CA PD_C 50 Rx_CA
+V/2 “1” -V/2 “0”
- -
215
Figure 1 Six Physical Layer Wire States of C-PHY Encoding, Nominal Values Shown

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216 Table 1 Signal Voltage and Differential Voltage for the Six C-PHY Wire States
Wire Wire Amplitude Receiver diff input voltage Receiver digital output
State A B C A–B B–C C–A Rx_AB Rx_BC Rx_CA
+x ¾V ¼V ½V +½ V -¼ V -¼ V 1 0 0
-x ¼V ¾V ½V -½ V +¼ V +¼ V 0 1 1
+y ½V ¾V ¼V -¼ V +½ V -¼ V 0 1 0
-y ½V ¼V ¾V +¼ V -½ V +¼ V 1 0 1
+z ¼V ½V ¾V -¼ V -¼ V +½ V 0 0 1
-z ¾V ½V ¼V +¼ V +¼ V -½ V 1 1 0
4.1.2 Representation of Symbols in High-Speed Mode

217 One of the symbol to wire state encoding rules is that a state-transition exists at every symbol boundary. The
218 reason for this rule is that it encodes the clock timing within the symbol, which has a number of advantages.
219 With six possible wire states (as shown in Figure 1 and Table 1) there are always 5 possible transitions to the
220 next wire state from any present wire state. The possible state transitions are illustrated in the state diagram
221 in Figure 2. The symbol value is defined by the change in wire state values from one unit interval to the next.
222 Note that more than two bits of information (actually log2(5) = 2.3219 bits) can be encoded into each symbol.
223 Seven consecutive symbols are used to transmit 16 bits of information. (Note that 57 = 78,125 permutations
224 in seven consecutive symbols, with five possible wire state transitions that define each symbol. The
225 information encoded in seven symbols is more than sufficient to represent a 16-bit binary value, 216 = 65,536.)
-y
C to B
W
CW
CC
+y
B to C
Positive
Polarity
+x +z
A to B C to A
-x -z
A to C
B to A
Negative Polarity
226
Figure 2 State Diagram Showing All Six Wire States, and All Possible Transitions

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4.1.3 Representation of High-Speed Signaling States

227 Figure 3 shows all processes involved in the transmission of 16-bit data from the transmitter in the master to
228 the reception of 16-bit words in the receiver at the slave device. 16-bit words at the transmitter are converted
229 to seven channel symbols by a Mapper. Then the seven symbols are serialized and sent one symbol at a time
230 to a Symbol Encoder and 3-wire driver which drives the three signals of the lane (A, B and C lines) at the
231 transmitting end. At the receiving end, there are three differential receivers that receive A minus B, B minus
232 C, and C minus A. The digital outputs of the differential receivers connect to a Symbol Decoder and clock
233 recovery circuit. The output of the Symbol Decoder is fed to a serial-to-parallel converter, and every group
234 of 7 symbols output by the Symbol Decoder is presented to the De-Mapper where they are converted back to
235 a 16-bit word. The functional details of the Mapper, Symbol Encoder, Symbol Decoder and De-Mapper are
236 described in section 6.1.3.
Take in 16 bits, generate 7 symbols Receive 7 symbols, output 16 bits

Seven 3-phase-encoded wire
states for each 16-bit word
16-bit word, output

Rx_Data[15:0]
Tx_Data[15:0]
16-bit word, input
Parallel-to-Serial
Serial-to-Parallel
Symbol A A 3-Wire 7-symbol
16-bit to
(16) 7-symbol (21) (3)
Encoder, B t0 t1 t2 t3 t4 t5 t6 B Receiver,
(3) (21)
to 16-bit
(16)
3-Wire C ws0 ws1 ws2 ws3 ws4 ws5 ws6 C Symbol De-
Mapper
Driver Decoder Mapper
Each Wire State has
6 possible states.
21 = 7 symbols,
Tx_Flip, The change on ABC from one Unit Interval Rx_Flip,
3 bits each.
Tx_Rotation, to the next defines the symbol value. Rx_Rotation,
3 bits define one
Tx_Polarity Symboln = f(wsn, wsn-1) Rx_Polarity
237 of 5 state transitions
238
Figure 3 End-to-End Transmission of Data, 16-bit Word Conversion to Channel States
4.2 Mandatory Functionality

239 All functionality that is specified in this document shall be implemented for all C-PHY configurations, unless
240 it is specifically stated as informative or specified as optional in Section 5.5.

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5 Architecture
241 This section describes the internal structure of the PHY including its functions at the behavioral level.
242 Furthermore, several possible PHY configurations are given. Each configuration can be considered as a
243 suitable combination from a set of basic modules.
5.1 Lane Modules

244 A PHY configuration consists of one or more lane modules. Each of these PHY lane modules communicates
245 via three lines to a complementary part at the other side of the lane interconnect.
PPI
(appendix) LP-TX
A
B
TX C
HS-TX
Clock
Lane
Control
Data HS-RX RT
and
Interface
RX
Ctrl
Logic LP-RX
LP-CD
Protocol
Side CD Line Side
246
Figure 4 Universal Lane Module Functions
247 Each lane module consists of one or more high-speed functions utilizing three interconnect wires
248 simultaneously, one or more single-ended low-power functions operating on each of the interconnect wires
249 individually, and control & interface logic. An overview of all functions is shown in Figure 4. High-speed
250 signals have a low voltage swing, e.g. 250 mV, while low-power signals have a large swing, e.g. 1.2V. High-
251 speed functions are used for high-speed data transmission. The low-power functions are mainly used for
252 control, but have other, optional, use cases. The I/O functions are controlled by a Lane Control and Interface
253 Logic block. This block interfaces with the higher layer protocol unit and determines the global operation of
254 the lane module.
255 High-speed functions include a differential transmitter (HS-TX) and a differential receiver (HS-RX).

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256 A lane module may contain either a HS-TX or a HS-RX, but not both. An enabled high-speed function shall
257 terminate the lane on its side of the lane interconnect as defined in Section 9.1.1 and Section 9.2.1. If a high-
258 speed function in the lane module is not enabled then the function shall be put into a high impedance state.
259 Low-power functions include single-ended transmitters (LP-TX), receivers (LP-RX) and low-power
260 Contention-Detectors (LP-CD). Low-power functions are always associated with a lane as these are single-
261 ended functions operating on all three of the interconnect wires individually.
262 Presence of high-speed and low-power functions is correlated. That is, if a lane module contains a HS-TX it
263 shall also contain a LP-TX. A similar constraint holds for HS-RX and LP-RX.
264 If a lane module containing a LP-RX is powered, that LP-RX shall always be active and continuously monitor
265 line levels. A LP-TX shall be enabled only when driving low-power states. The LP-CD function is required
266 only for bi-directional operation. If present, the LP-CD function is enabled to detect contention situations
267 while the LP-TX is driving low-power states. The LP-CD checks for contention before driving a new state
268 on the line except in ULPS.
269 The activities of LP-TX, HS-TX, and HS-RX in a single lane module are mutually exclusive, except for some
270 short crossover periods. For detailed specification of the line-side signals, and the HS-TX, HS-RX, LP-TX,
271 LP-RX and LP-CD functions, refer to Chapter 9 and Chapter 10.
272 For proper operation, the set of functions in the lane modules on both sides of the lane interconnect has to be
273 matched. This means for each HS and LP transmit or receive function on one side of the lane interconnect, a
274 complementary HS or LP receive or transmit function must be present on the other side. In addition, a
275 contention detector is needed in any lane module that combines TX and RX functions.
5.2 Master and Slave

276 Each link has a master and a slave side. The master provides the high-speed data signals to each lane and is
277 the main data source. The slave receives the data signals at the lanes and is the main data sink. The main
278 direction of data communication, from source to sink, is denoted as the forward direction. Data
279 communication in the opposite direction is called reverse transmission. Only bi-directional lanes can transmit
280 in LP mode in the reverse direction. High speed reverse data is not supported in any configuration.
5.3 High Frequency Clock Generation

281 In many cases a PLL Clock Multiplier is needed for the high frequency clock generation at the master side.
282 The C-PHY specification uses an architectural model where a separate Clock Multiplier Unit outside the
283 PHY generates the required high frequency clock signals for the PHY. Whether this Clock Multiplier Unit in
284 practice is integrated inside the PHY is left to the implementer.
5.4 Lanes and the PHY-Protocol Interface

285 A complete link contains, beside lane modules, a PHY Adapter Layer that ties all lanes, the Clock Multiplier
286 Unit, and the PHY-Protocol Interface together. Figure 5 shows a PHY configuration example for a link with
287 three lanes plus a separate Clock Multiplier Unit. The PHY Adapter Layer, though a component of a PHY, is
288 not within the scope of this specification.
289 The logical PHY-Protocol interface (PPI) for each individual lane includes a set of signals to cover the
290 functionality of that lane. As shown in Figure 5, Clock signals may be shared for all lanes. The reference
291 clock and control signals for the Clock Multiplier Unit are not within the scope of this specification.

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Clock
Multiplier
Unit APPI = Abstracted PHY-Protocol Interface (complete PHY, all Lanes
Ref Clk PPI = PHY Protocol Interface (per Lane, some signals can be shared with multiple Lanes)
Controls
PPI C-PHY C-PHY PPI

Master Lane Module Slave Lane Module
APPI PPI C-PHY C-PHY PPI APPI

Master Lane Module Slave Lane Module
PHY
PPI C-PHY C-PHY PPI
PHY
Adapter Adapter
Layer Master Lane Module Slave Lane Module Layer
PHY PHY
292 Master Side Slave Side
Figure 5 Three Lane PHY Configuration
5.5 Selectable Lane Options

293 A PHY configuration consists of one or more lanes. All lanes shall support high-speed transmission and
294 escape mode in the forward direction.
295 There are two main types of lanes:
296 • Bi-directional (featuring turnaround and some reverse communication functionality)
297 • Unidirectional (without turnaround or any kind of reverse communication functionality)
298 Bi-directional lanes shall include the following reverse communication option:
299 • Low-power reverse escape mode (including or excluding LPDT). Note that high-speed reverse
300 data communication is not supported.
301 All lanes shall include escape mode support for ULPS and Triggers in the forward direction. Other escape
302 mode functionality is optional; all possible escape mode features are described in Section 6.6. Applications
303 shall define what additional escape mode functionality is required and, for bi-directional lanes, shall select
304 escape mode functionality for each direction individually.
305 This results in many options for complete PHY configurations. The degrees of freedom are:
306 • Single or multiple lanes
307 • Bi-directional and/or unidirectional lane (per lane)
308 • Supported types of reverse communication (per lane)
309 • Functionality supported by escape mode (for each direction per lane)
310 Figure 6 is a flow graph of the option selection process. Practical configuration examples can be found in
311 Section 5.7.

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START
What is max HS bit rate per lane

given IC technology at both ends
and the interconnect?
Determine max momentary bandwidth and concurrency

requirement in each direction (RBWab>=RBWba) and
decide how this can be mapped on half-duplex lanes,
(dual-) simplex lanes, or a combination of these. Take
into account start-of-transmission and end-of-
transmission delays and for half-duplex lanes
turnaround delay.
Iterate
For all
Lanes
Decide on using LPDT

in Forward direction
Is half-
duplex operation Yes
required?
Max required
No momentary reverse
No Yes
direction lane bandwidth
>10Mb/s
If traffic can
be scheduled properly
No
using reverse Esc LPDT
use LPDT?
No
Yes
Full Escape mode support

in Reverse direction
Functionality
decided for all
Lanes?
Yes
PHY Configuration PHY Configuration
known not known
312
Figure 6 Option Selection Flow Graph

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5.6 Lane Module Types

313 The required functions in a lane module depend on the lane type and which side of the lane interconnect the
314 lane module is located. There are two main lane types: unidirectional lane and bi-directional lane. Several
315 PHY configurations can be constructed with these lane types. See Figure 6 for more information on selecting
316 lane options. Figure 7 shows a universal lane module diagram with a global overview of internal functionality
317 of the CIL function. This Universal Module can be used for all lane types. The requirements for the ‘Control
318 and Interface Logic’ (CIL) function depend on the lane type and lane side. Section 6 and Annex A implicitly
319 specify the contents of the CIL function. The actual realization is left to the implementer.
PPI
(appendix)
LP-TX
TX Ctrl Logic
A
Data In Data Esc Encoder B
IF TX C
Data Out logic Mapper HS-Serialize
Encoder HS-TX
Sequences
Clocks-in De- HS- Data

Mapper Deserialize
Decoder
Sampler
HS-RX RT
Clocks-out
RX
LP-RX
Esc Decoder
Ctrl Decoder
Data In Ctrl
IF
Data Out logic State Machine
(incl Enables, Selects LP-CD
and System ctrl)
Protocol Error detect

Side CD Line Side
320
Figure 7 Universal Lane Module Architecture
321 Of course, stripped-down versions of the universal lane module that just support the required functionality
322 for a particular lane type are possible. These stripped-down versions are identified by the acronyms in Table
323 2. For simplification reasons, any of the four identification characters can be replaced by an X, which means
324 that this can be any of the available options. For example, a CIL-MFEN is therefore a stripped-down CIL
325 function for the master side of a unidirectional lane with escape mode functionality only in the forward
326 direction. Note that a CIL-XFXN implies a unidirectional link, while either a CIL-XFXE or CIL-XFAA block
327 implies a bidirectional link.

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328 Table 2 Lane Type Descriptors

Prefix Lane High-Speed Forward Direction Reverse Direction
Interconnect Capabilities Escape Mode Escape Mode
Side Features Supported Features Supported
CIL- M – Master F – Forward Only A – All (including LPDT) A – All (including LPDT)
S – Slave E – events – E – events –
X – Don’t Care Triggers and ULPS Only Triggers and ULPS Only
X – Don’t Care N – None
Y – Any (A, E or A and E)
X – Don’t Care
Note:
“Any” is any combination of one or more functions.
329 The recommended PHY-Protocol Interface contains Data-in and Data-out in word format, Input and/or output
330 Clock signals and Control signals. Control signals include requests, handshakes, test settings, and
331 initialization. A proposal for a logical internal interface is described in Annex A. Although not a requirement
332 it may be very useful to use the proposed PPI as a guide. For external use on IC’s an implementation may
333 multiplex many signals on the same pins. However, for power efficiency reasons, the PPI is normally within
334 an IC.
5.6.1 Unidirectional Lane

335 For a unidirectional lane the master module shall contain at least a HS-TX, a LP-TX, and a CIL-MFXN
336 function. The slave side shall contain at least a HS-RX, a LP-RX and a CIL-SFXN.
5.6.2 Bi-directional Lanes

337 A bi-directional lane Module includes some form of reverse communication; either reverse escape mode, or
338 reverse escape with LPDT. The functions required depend on what methods of reverse communication are
339 included in the lane module.
5.6.2.1 Bi-directional Lane Modes

340 A bi-directional lane module shall include a low-power reverse escape mode (including or excluding LPDT).
341 The master-side lane module includes a HS-TX, LP-TX, LP-RX, LP-CD, and CIL-MFXY. The slave-side
342 consists of a HS-RX, LP-RX, LP-TX, LP-CD and a CIL-SFXY.
5.7 Configurations
343 This section outlines several common PHY configurations but should not be considered an exhaustive list of
344 all possible arrangements. Any other configuration that does not violate the requirements of this document is
345 also allowed.
346 In order to create an abstraction level, the lane modules are represented in this section by lane module
347 Symbols. Figure 8 shows the syntax and meaning of symbols.

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This Other Options Meaning
Supported Directions for High-Speed Data

Transmission (Forward only)
Supported Directions for Escape mode excluding LPDT

(Bi-directional or Forward Only)
Supported Directions for Escape mode including LPDT

(Bi-directional, Forward Only or Reverse Only)
PPI PPI: PHY-Protocol Interface
348
Figure 8 Lane Symbol Macros and Symbols Legend
349 For multiple lanes a large variety of configurations is possible. Figure 9 shows an overview of symbolic
350 representations for different lane types. The acronyms mentioned for each lane type represent the
351 functionality of each module in a short way. This also sets the requirements for the CIL function inside each
352 Module.
• Forward High-speed Only MFAA

C-PHY C-PHY
PPI PPI • Bi-directional Escape Mode &
Lane Module Lane Module • Bi-directional LPDT SFAA
• Forward High-speed Only MFAE

C-PHY C-PHY
Lane Module Lane Module • Forward LPDT Only SFAE
• Forward High-speed Only MFEA

C-PHY C-PHY
Lane Module Lane Module • Reverse LPDT Only SFEA
• Forward High-speed Only MFAN

C-PHY C-PHY
PPI PPI • Forward Escape Mode Only &
Lane Module Lane Module • Forward LPDT Only SFAN
• Forward High-speed Only MFEE

C-PHY C-PHY
Lane Module Lane Module • No LPDT SFEE
• Forward High-speed Only MFEN

C-PHY C-PHY
PPI PPI • Forward Escape Mode Only &
Lane Module Lane Module • No LPDT SFEN
353
Figure 9 All Possible Lane Types
5.7.1 Unidirectional Configurations

354 All unidirectional configurations are constructed with one or more unidirectional lanes. Two basic
355 configurations can be distinguished: single-lane and multiple-lanes. For completeness a dual-simplex
356 configuration is also shown. At the PHY level there is no difference between a dual-simplex configuration
357 and two independent unidirectional configurations.

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5.7.1.1 PHY Configuration with a Single Lane

358 This configuration includes one unidirectional lane from master to slave. Communication is therefore only
359 possible in the forward direction. Figure 10 shows an example configuration without LPDT. This
360 configuration requires three interconnect signal wires.
Master Slave
C-PHY C-PHY
PPI PPI
Lane Module Lane Module
361
Figure 10 Unidirectional Single Lane Configuration
5.7.1.2 PHY Configuration with Multiple Lanes

362 This configuration includes multiple unidirectional lanes from master to slave. Bandwidth is extended, but
363 communication is only possible in the forward direction. The PHY specification does not require all lanes to
364 be active simultaneously. In fact, the protocol layer controls all lanes individually. Figure 11 shows an
365 example of this configuration for three lanes. If N is the number of lanes, this configuration requires 3  N
366 interconnect wires.
Master Slave
C-PHY C-PHY
PPI PPI
C-PHY C-PHY
PPI PPI
C-PHY C-PHY
PPI PPI
367
Figure 11 Unidirectional Multiple Lane Configuration without LPDT
5.7.1.3 Dual-Simplex (Two Directions with Unidirectional Lanes)

368 This case is the same as two independent (dual), unidirectional (simplex) links: one for each direction. Each
369 direction may contain either a single, or multiple, lanes. Please note that the master and slave side for the two
370 different directions are opposite. The PHY configuration for each direction shall comply with the C-PHY
371 specifications. As both directions are conceptually independent, the bit rates for each direction do not have
372 to match. However, for practical implementations, it is attractive to match rates and share some internal
373 signals as long as both links fulfill all specifications externally. Figure 12 shows an example of this dual PHY
374 configuration.

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Master Slave
C-PHY C-PHY
PHY-1 PPI PPI
Slave Master
C-PHY C-PHY
PHY-2 PPI PPI
375
Figure 12 Two Directions Using Two Independent Unidirectional PHYs without LPDT
5.7.2 Bi-Directional Half-Duplex Configurations

376 Bi-directional configurations consist of one or more bi-directional lanes. Half-duplex operation enables bi-
377 directional traffic across shared interconnect wires. This configuration saves wires compared to the dual-
378 simplex configuration. However, time on the link is shared between forward and reverse traffic and link
379 turnaround. LPDT can have similar rates in the forward and reverse directions. This configuration is
380 especially useful for cases with asymmetrical data traffic.
5.7.2.1 PHY Configurations with a Bi-Directional Single Lane

381 This configuration includes one of any kind of bi-directional lane. This allows time-multiplexed data traffic
382 in both forward and reverse directions. Figure 13 shows this configuration with a lane that supports both
383 high-speed and escape (without LPDT) communication in both directions. Other possibilities are that only
384 one type of reverse communication is supported or LPDT is also included in one or both directions. All these
385 configurations require three interconnect wires.
Master Slave
C-PHY C-PHY
PPI PPI
386
Figure 13 Bidirectional Single Lane Configuration
5.7.2.2 PHY Configurations with Multiple Lanes

387 This configuration includes multiple bi-directional lanes. Communication is possible in both the forward and
388 reverse direction for each individual lane. The maximum available bandwidth scales with the number of lanes
389 for each direction. The PHY specification does not require all lanes to be active simultaneously or even to be
390 operating in the same direction. In fact, the protocol layer controls all lanes individually. Figure 14 shows
391 an example configuration with two lanes. If N is the number of lanes, this configuration requires 3  N
392 interconnect wires.

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Master Slave
C-PHY C-PHY
PPI PPI
C-PHY C-PHY
PPI PPI
393
Figure 14 Bi-directional Multiple Lane Configuration

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6 Global Operation
394 This section specifies operation of C-PHY including signaling types, communication mechanisms, operating
395 modes and coding schemes. Detailed specifications of the required electrical functions can be found in
396 Section 9.
6.1 Transmission Data Structure

397 During high-speed, or low-power, transmission, the link transports payload data provided by the protocol
398 layer to the other side of the link. This section specifies the restrictions for the transmitted and received
399 payload data.
6.1.1 Data Units

400 The minimum payload data unit for the high-speed mode of transmission shall be one 16-bit word. Data
401 provided to a TX and taken from a RX on any lane operating in high-speed mode shall be an integer number
402 of 16-bit words.
403 The minimum payload data unit for the low-power mode of transmission shall be one byte. Data provided to
404 a TX and taken from a RX on any lane operating in low-power mode shall be an integer number of bytes.
6.1.2 Bit order, Serialization, and De-Serialization

405 For serial transmission, the data shall be serialized in the transmitting PHY and de-serialized in the receiving
406 PHY. For high-speed data transmission the PHY maps 16-bit words into groups of seven symbols as described
407 in section 6.1.3.3. Symbol s6 is defined as the most significant symbol of the seven symbol group and symbol
408 s0 is defined as the least significant symbol. The group of seven symbols shall be transmitted in the sequence
409 of: s0, s1, s2, s3, s4, s5, s6, where s0 shall be transmitted first. Symbol s1 shall be transmitted in the UI
410 immediately following symbol s0, s2 shall be transmitted in the UI immediately following s1, and so on, and
411 s6 shall be transmitted in the UI immediately following s5. Symbol s0 of the next group of seven symbols
412 shall be transmitted in the UI immediately following s6 of the present group.
6.1.3 Encoding, Decoding, Mapping and De-Mapping

413 C-PHY shall use two layers of coding with serialization and deserialization in between, as illustrated in Figure
414 3:
415 1. Mapping and De-Mapping – A Mapper converts a 16-bit data unit to be transmitted into a group
416 of seven transmitted symbols. A De-Mapper converts a group of 7 received symbols into a 16-bit
417 data unit.
418 2. Serialization and Deserialization – A parallel to serial converter accepts a group of 7 symbols
419 from the Mapper and presents one symbol at a time to the Symbol Encoder. A serial to parallel
420 converter accepts one symbol at a time from the Symbol Decoder and presents a group of 7
421 symbols to the De-Mapper.
422 3. Encoding and Decoding – A Symbol Encoder converts one symbol into a wire state to be sent
423 over the lane based on the present 3-bit symbol value and the wire state that was transmitted in the
424 previous UI. A Symbol Decoder computes a received symbol value based on the wire state
425 received in the present UI and the wire state received in the previous UI.
6.1.3.1 Wire States

426 One of six possible high-speed wire states shall be driven onto a lane during a high-speed unit interval (UI).
427 Each of the lines of a lane shall be driven to one of three signal levels: low, middle or high. In some
428 implementations the middle signal level can be the result of the transmitter not driving the signal. Each of
429 the three lines in a lane shall be at a different signal level than the other two lines. The six wire states consist
430 of the six possible permutations of driving the three lines of a lane with a different signal level on each line.

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431 The six wire states shall be called +x, -x, +y, -y, +z and –z are defined as described in Table 3. Examples of
432 the wire states are shown in Figure 1 and Table 1.
433 The wire states defined as having a positive polarity are: +x, +y and +z. The wire states defined as having a
434 negative polarity are: -x, -y and -z.
435 Table 3 Definition of Wire States

Wire State Name High-Speed State Code Name Line Signal Levels
A B C
+x HS_+X High Low Middle
-x HS_-X Low High Middle
+y HS_+Y Middle High Low
-y HS_-Y Middle Low High
+z HS_+Z Low Middle High
-z HS_-Z High Middle Low
6.1.3.2 Symbol Encoding and Decoding

436 Each symbol shall be represented using a 3-bit number having one of five values: 000, 001, 010, 011 and
437 100. The symbol values are based on the specific transitions between the wire states as shown in Figure 2.
438 These transitions are derived from the 3-bit symbol value where each bit defines a particular wire state change
439 parameter: flip, rotate, and polarity. The flip, rotate and polarity bits affect the wire state as follows:
440 • The least significant bit of the 3-bit symbol value is Polarity, which indicates whether the polarity
441 changes state from the previous symbol. When Polarity is “one” then the wire state transmitted
442 during symbol interval N has a polarity that is opposite that of the wire state transmitted during
443 symbol interval N-1 (i.e. from positive: +x, +y, +z to negative: -x, -y, -z; or negative to positive);
444 else if Polarity is “zero” then the polarity of the wire state transmitted during symbol interval N
445 remains the same as the wire state transmitted during symbol interval N-1.
446 • The next least significant bit of the 3-bit value is Rotation, which indicates the direction of rotation
447 from the wire state transmitted during symbol interval N-1 compared to the wire state transmitted
448 during symbol interval N. When Rotation is one, then the direction of rotation is clockwise; else,
449 when Rotation is zero then the direction of rotation is counterclockwise.
450 • The most significant bit of the 3-bit symbol value is Flip, which indicates there is only a polarity
451 change in the next symbol but the wire state will not rotate to a different phase. A Flip causes a
452 transition between states +x and -x, between +y and -y, or between +z and -z. The flip transitions
453 are represented by the blue arrows in Figure 2. When Flip is one then the phase is the same as the
454 previous symbol but the polarity is opposite of the polarity in the previous symbol. Also, when
455 Flip is one then the values of Rotation and Polarity for the same corresponding symbol are
456 ignored, and are both set to zero.
6.1.3.2.1 Encoding
457 The symbol encoding shall be performed as described in Table 4, which defines the symbol encoding
458 algorithm. The translation defined in Table 4 converts one 3-bit symbol value into a wire state to be sent over
459 the lane based on the present 3-bit symbol value and the wire state that was transmitted in the previous UI.
460 Every transition in the state diagram of Figure 2 is represented in Table 4. The present wire state is determined
461 by the previous wire state and the symbol input value. For example: if the 3-bit symbol value is 011 (no flip,
462 CW rotation, opposite polarity) and the previous wire state is +y, then the next wire state is -z.

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463 Table 4 Five possible transitions from previous state to present state
Symbol Previous Wire State, interval N-1 What Happens
Input
+x -x +y -y +z -z
Value
000 +z -z +x -x +y -y Rotate CCW, polarity is Same
001 -z +z -x +x -y +y Rotate CCW, polarity is Opposite
010 +y -y +z -z +x -x Rotate CW, polarity is Same
011 -y +y -z +z -x +x Rotate CW, polarity is Opposite
1xx -x +x -y +y -z +z Same phase, polarity is Opposite
Note:
1. Symbol Input value is: [Tx_Flip, Tx_Rotation, Tx_Polarity]
2. Values in the table show the Present Wire State transmitted during interval N, as a function of the
Previous Wire State transmitted during interval N-1, and 3-bit Symbol Value.
464 An example Transmit Encoder and driver circuit is shown in Figure 15. The 3-bit binary values that represent
465 the previous and present wire state in Figure 15 exist only to make the example easier to follow. This is to
466 break the process in the example into two steps: Transmit Symbol Encoding Logic and Transmit Pre-driver
467 Control Logic. The wire state binary values are internal to the Symbol Encoder and Transmitter circuit, so
468 the values that describe the wire states within these blocks are an implementation choice. For example: the
469 actual logic circuit could use the decoded 6-bit pre-driver value [PU_A, PD_A, PU_B, PD_B, PU_C, PD_C]
470 to define the present wire state value (using only 6 of the 64 possible values) instead of using the intermediate
471 3-bit wire state value.
Tx Wire State This is an

intermediate value. No +V
Tx_Flip specific binding of wire PU_A
Flip state to binary value is “A”
Tx_Rotation required. PD_A
Rotation +x,-x,+y,-y,+z or -z
Tx_Polarity Transmit PU_B
Polarity
Pre-Drivers
& Control
PD_B +V
Transmit Symbol Logic PU_C “B”
Encoding Logic
PD_C
Prev_St[2] Pres_St[2] D2 Q2
Prev_St[1] Pres_St[1] D1 Q1 +V
Prev_St[0] Pres_St[0] D0 Q0
“C”
472 Tx_symclk
Figure 15 Encoder and Transmitter Example
Table 5 Transmit Pre-Driver Control Logic
Wire Driver Driver Driver Driver Driver Driver
VA VB VC
State PU_A PD_A PU_B PD_B PU_C PD_C
+x ¾V ¼V ½V 1 0 0 1 0 0
-x ¼V ¾V ½V 0 1 1 0 0 0
+y ½V ¾V ¼V 0 0 1 0 0 1
-y ½V ¼V ¾V 0 0 0 1 1 0
+z ¼V ½V ¾V 0 1 0 0 1 0

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-z ¾V ½V ¼V 1 0 0 0 0 1
473 Note that the Transmit Pre-Driver Control Logic table is shown only to illustrate the logic function of the
474 translation of wire state to driver control signals. The actual implementation may require carefully designed
475 routing and signal gating to precisely control the skew between the A, B and C wires of the lane.
6.1.3.2.2 Decoding
476 The symbol decoding function shall be performed as described in Table 6. Every transition in the state
477 diagram of Figure 2 is represented in Table 6. Note that there are no transitions to the same state (because
478 there is always a wire state transition at each symbol boundary) so the table shows “n/a” to indicate that these
479 transitions are not applicable. The symbol value shall be determined based on the transition from the previous
480 wire state (interval N-1) to the present wire state (interval N). For example: if the previous wire state is +y
481 which results in “010” at the output of the receivers (prev_Rx_AB=0, prev_Rx_BC=1, prev_Rx_CA=0) and
482 the present wire state is -z which results in “110” at the output of the receivers (Rx_AB=1, Rx_BC=1,
483 Rx_CA=0), then the symbol value is 011 which represents: no flip, a CW rotation and polarity change. This
484 symbol value of 011 is located in Table 6 where the “+y” column and the “-z state” row intersect. (“y” toward
485 “z” is CW rotation and “+” to “-“ is a polarity change.)
486 Table 6 Receive Transition Mapping

Present Wire State Previous Wire State [prev_Rx_AB, prev_Rx_BC, prev_Rx_CA]
[Rx_AB, Rx_BC, Rx_CA] (wire state received during interval N-1)
(received during -z
+x [100] -x [011] +y [010] -y [101] +z [001]
interval N) [110]
+x state [100] n/a 1xx 000 001 010 011
-x state [011] 1xx n/a 001 000 011 010
+y state [010] 010 011 n/a 1xx 000 001
-y state [101] 011 010 1xx n/a 001 000
+z state [001] 000 001 010 011 n/a 1xx
-z state [110] 001 000 011 010 1xx n/a
symbol value above = [Rx_Flip, Rx_Rotation, Rx_Polarity]
487 An example receiver circuit with symbol decoding is shown below in Figure 16.

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A +
Rx_AB prev_Rx_AB Rx_Flip
D2 Q2 D2 Q2 prev_Rx_AB
Rx_BC prev_Rx_BC
- D1 Q1 D1 Q1 prev_Rx_BC Rx_Rotation
Rx_CA prev_Rx_CA
D0 Q0 D0 Q0 prev_Rx_CA
Rx_Polarity
B +
Receive
-
Symbol
Decoding
C +
Logic
3ph_Term_
Enable -
Rx_AB
Rx_BC
Rx_CA
Clock
symclk
Recovery
Circuit
Clock
Clk_in Gating Clk_out
Clean Clock
t3-SETTLE_expired Enable Cell
Window Gen.
488
Figure 16 Receiver and Symbol Decoder Example
6.1.3.3 16-to-7 Mapping and 7-to-16 De-Mapping Circuit Implementation

489 The Mapper and De-Mapper are the outer-most functions in the C-PHY digital coding system. The Mapper
490 is the first function that occurs on the transmit side, and the De-Mapper is the last function performed on the
491 receive side. This order of functions is shown in Figure 3. The Mapper converts a 16-bit word into a group
492 of seven symbols at the transmitting end. At the receiving end, a 7-to-16 De-Mapper converts groups of seven
493 symbols back to 16-bit words. The mapping process is described in 6.1.3.3.1, and the de-mapping process is
494 described in 6.1.3.3.2.
495 The 16-to-7 Mapper and 7-to-16 De-Mapper perform a mapping and inverse mapping function between 16-
496 bit input/output values and a group of 7 symbols. The Mapper and De-Mapper shall conform to the process
497 defined in Figure 17.
498 The group of seven symbols is comprised of seven 3-bit symbol values. Each symbol is comprised of a flip,
499 rotate and polarity bit, so for any particular symbol, n, sn = [Flip[n], Rotation[n], Polarity[n]].
500 A seven-symbol Mapper output value is defined for every possible 16-bit Mapper input value. However, not
501 all possible seven symbol sequences correspond to a 16-bit mapper input value. The output of the De-Mapper
502 is not defined when an invalid group of seven symbols is presented to the input of the De-Mapper. An invalid
503 group of seven symbols is defined as the collection of symbols having a value of “4” (the state of Flip[6:0])
504 that does not correspond to one of the 28 mapped regions defined in Figure 17. The De-Mapper output is not
505 specified for these invalid groups of seven symbols, so the De-Mapper output should be an implementation
506 choice when an invalid seven symbol group is presented to the De-Mapper.
507 Since the mapping and inverse mapping functions are completely feed-forward functions, pipeline registers
508 can be inserted between intermediate stages if necessary to lessen timing constraints in systems that operate
509 at a high symbol rate.

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[data15, data14, data13, data12, data11, data10, data9, data8, data7, data6, data5, data4, data3, data2, data1, data0]
Composition of 16-bit value, Tx_Data[15:0] or Rx_Data[15:0]
(1024) 6, 4 0xfc00 to 0xffff Flip[6:0]==0x50==[1,0,1,0,0,0,0] [1,1,1,1,1,1, ro5, po5, ro3, po3, ro2, po2, ro1, po1, ro0, po0]
(1024) 5, 4 0xf800 to 0xfbff Flip[6:0]==0x30==[0,1,1,0,0,0,0] [1,1,1,1,1,0, ro6, po6, ro3, po3, ro2, po2, ro1, po1, ro0, po0]
(1024) 6, 3 0xf400 to 0xf7ff Flip[6:0]==0x48==[1,0,0,1,0,0,0] [1,1,1,1,0,1, ro5, po5, ro4, po4, ro2, po2, ro1, po1, ro0, po0]
(1024) 5, 3 0xf000 to 0xf3ff Flip[6:0]==0x28==[0,1,0,1,0,0,0] [1,1,1,1,0,0, ro6, po6, ro4, po4, ro2, po2, ro1, po1, ro0, po0]
(1024) 4, 3 0xec00 to 0xefff Flip[6:0]==0x18==[0,0,1,1,0,0,0] [1,1,1,0,1,1, ro6, po6, ro5, po5, ro2, po2, ro1, po1, ro0, po0]
(1024) 6, 2 0xe800 to 0xebff Flip[6:0]==0x44==[1,0,0,0,1,0,0] [1,1,1,0,1,0, ro5, po5, ro4, po4, ro3, po3, ro1, po1, ro0, po0]
(1024) 5, 2 0xe400 to 0xe7ff Flip[6:0]==0x24==[0,1,0,0,1,0,0] [1,1,1,0,0,1, ro6, po6, ro4, po4, ro3, po3, ro1, po1, ro0, po0]
(1024) 4, 2 0xe000 to 0xe3ff Flip[6:0]==0x14==[0,0,1,0,1,0,0] [1,1,1,0,0,0, ro6, po6, ro5, po5, ro3, po3, ro1, po1, ro0, po0]
(1024) 3, 2 0xdc00 to 0xdfff Flip[6:0]==0x0c==[0,0,0,1,1,0,0] [1,1,0,1,1,1, ro6, po6, ro5, po5, ro4, po4, ro1, po1, ro0, po0]
(1024) 6, 1 0xd800 to 0xdbff Flip[6:0]==0x42==[1,0,0,0,0,1,0] [1,1,0,1,1,0, ro5, po5, ro4, po4, ro3, po3, ro2, po2, ro0, po0]
(1024) 5, 1 0xd400 to 0xd7ff Flip[6:0]==0x22==[0,1,0,0,0,1,0] [1,1,0,1,0,1, ro6, po6, ro4, po4, ro3, po3, ro2, po2, ro0, po0]
(1024) 4, 1 0xd000 to 0xd3ff Flip[6:0]==0x12==[0,0,1,0,0,1,0] [1,1,0,1,0,0, ro6, po6, ro5, po5, ro3, po3, ro2, po2, ro0, po0]
(1024) 3, 1 0xcc00 to 0xcfff Flip[6:0]==0x0a==[0,0,0,1,0,1,0] [1,1,0,0,1,1, ro6, po6, ro5, po5, ro4, po4, ro2, po2, ro0, po0]
(1024) 2, 1 0xc800 to 0xcbff Flip[6:0]==0x06==[0,0,0,0,1,1,0] [1,1,0,0,1,0, ro6, po6, ro5, po5, ro4, po4, ro3, po3, ro0, po0]
(1024) 6, 0 0xc400 to 0xc7ff Flip[6:0]==0x41==[1,0,0,0,0,0,1] [1,1,0,0,0,1, ro5, po5, ro4, po4, ro3, po3, ro2, po2, ro1, po1]
(1024) 5, 0 0xc000 to 0xc3ff Flip[6:0]==0x21==[0,1,0,0,0,0,1] [1,1,0,0,0,0, ro6, po6, ro4, po4, ro3, po3, ro2, po2, ro1, po1]
(1024) 4, 0 0xbc00 to 0xbfff Flip[6:0]==0x11==[0,0,1,0,0,0,1] [1,0,1,1,1,1, ro6, po6, ro5, po5, ro3, po3, ro2, po2, ro1, po1]
(1024) 3, 0 0xb800 to 0xbbff Flip[6:0]==0x09==[0,0,0,1,0,0,1] [1,0,1,1,1,0, ro6, po6, ro5, po5, ro4, po4, ro2, po2, ro1, po1]
(1024) 2, 0 0xb400 to 0xb7ff Flip[6:0]==0x05==[0,0,0,0,1,0,1] [1,0,1,1,0,1, ro6, po6, ro5, po5, ro4, po4, ro3, po3, ro1, po1]
(1024) 1, 0 0xb000 to 0xb3ff Flip[6:0]==0x03==[0,0,0,0,0,1,1] [1,0,1,1,0,0, ro6, po6, ro5, po5, ro4, po4, ro3, po3, ro2, po2]
0xafff
Flip[6:0]==0x40==[1,0,0,0,0,0,0]
(4096) 6 [1,0,1,0, ro5, po5, ro4, po4, ro3, po3, ro2, po2, ro1, po1, ro0, po0]
0xa000
0x9fff
Flip[6:0]==0x20==[0,1,0,0,0,0,0]
0x9000
0x8fff
Flip[6:0]==0x10==[0,0,1,0,0,0,0]
0x8000
0x7fff
Flip[6:0]==0x08==[0,0,0,1,0,0,0]
0x7000
0x6fff
Flip[6:0]==0x04==[0,0,0,0,1,0,0]
0x6000
0x5fff
Flip[6:0]==0x02==[0,0,0,0,0,1,0]
0x5000
0x4fff
Flip[6:0]==0x01==[0,0,0,0,0,0,1]
0x4000
0x3fff
Flip[6:0]==0x00==[0,0,0,0,0,0,0]
[0,0, ro6, po6, ro5, po5, ro4, po4, ro3, po3, ro2, po2, ro1, po1, ro0, po0]
Legend for abbreviated bit values above:

(0 – 6 are ro0 ⇒ Rotation[0] po0 ⇒ Polarity[0]
ro1 ⇒ Rotation[1] po1 ⇒ Polarity[1]
all zero) ro2 ⇒ Rotation[2] po2 ⇒ Polarity[2]
510 (16384) 0x0000
Figure 17 Data Mapping Between Seven Symbols and a 16-Bit Word
511 Figure 17 specifies the mapping of 16-bit words to groups of seven symbols. The value of the 16-bit word is
512 shown on the left, ranging from 0x0000 at the bottom to 0xffff at the top. The vectors enclosed in square
513 brackets to the right show the correspondence of Rotation and Polarity values to specific bits in the 16-bit
514 word. The seven Flip bits of the seven symbols define one of 28 different regions within the 16-bit range.
515 One region contains 16,384 values, 7 regions contain 4,096 values each, and 20 regions contain 1,024 values
516 each. The use of these varying sized regions simplifies the mapping function.
6.1.3.3.1 Tx 16-bit to 7-symbol Mapper

517 The Mapper shall perform a translation of a 16-bit value to a seven symbol group per the mapping function
518 defined in Figure 17.
519 A high-level diagram of an example of a 16-to-7 Mapper is shown in Figure 18, and a low-level
520 implementation of the Mapper example is shown in Figure 19.

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Tx_Rotation[0]
Tx_Data[0] Tx_Polarity[0]
Tx_Data[1] Tx_Rotation[1]
Tx_Data[3]
Tx_Rotation[2]
Tx_Data[4] Mux Encoder Tx_Polarity[2]
Tx_Data[5] converts
12 of the data bits to
7 Rotation and
Tx_Data[8] Polarity outputs Tx_Rotation[4]
Tx_Data[12]
Tx_Rotation[6]
Tx_Data[13]
Tx_Polarity[6]
Tx_Flip[0]
Mux Control Tx_Flip[1]
Logic Function Tx_Flip[2]
& generates Tx_Flip[3]
Tx_Data[14] Same Rotation Tx_Flip[4]
Tx_Data[15] outputs Tx_Flip[5]
Tx_Flip[6]
521
Figure 18 Example, Mapping Circuit Converts 16-bit Word to Seven Symbols

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mux0
sB
Tx_Data[0] in0[0] out[0] Tx_Polarity[0]
Tx_Data[1] in0[1] out[1] Tx_Rotation[0]
“0” in1[0]
“0” in1[1]
muxa1
muxb1
sB sA out[0] Tx_Polarity[1]
in0[0]
in0[1] out[1] Tx_Rotation[1]
Tx_Data[2] in1[0]
Tx_Data[3] in1[1]
“0” in2[0]
“0” in2[1]
muxa2
muxb2
sB sA
in0[0] out[0] Tx_Polarity[2]
in1[0]
in1[1]
Tx_Data[4] in2[0]
Tx_Data[5] in2[1]
“0” in3[0]
“0” in3[1]
muxa3
muxb3
sB sA
in1[0]
in1[1]
Tx_Data[6] in2[0]
Tx_Data[7] in2[1]
“0” in3[0]
“0” in3[1]
muxa4
muxb4
sB sA
in1[0]
in1[1]
in2[0]
in2[1]
“0” in3[0]
“0” in3[1]
muxa5
muxb5
sB sA
Tx_Data[8] in1[0]
Tx_Data[9] in1[1]
Tx_Data[10] in2[0]
Tx_Data[11] in2[1]
Tx_Data[12] “0” in3[0]
Tx_Data[13] “0” in3[1]
muxa6
Tx Mux mux0 muxb6
muxa1
Control muxb1 in0[0]
sB sA
out[0] Tx_Polarity[6]
Logic muxa2 in0[1] out[1] Tx_Rotation[6]
muxb2 in1[0]
muxa3 in1[1]
Tx_Data[10] muxb3
Tx_Data[11] muxa4 in2[0]
Tx_Data[12] muxb4 in2[1]
Tx_Data[13] muxa5 “0” in3[0]
Tx_Data[14] Tx_Data[14] muxb5 “0” in3[1]
Tx_Data[15] Tx_Data[15] muxa6
muxb6
Tx_Flip[0] Tx_Flip[0]
522
Figure 19 Example, Detailed Logic Diagram of 16-bit word to 7-Symbol Mapping Circuit

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523 Figure 19 shows the low-level circuit of the 16-to-7 Mapper example in the block diagram of Figure 18 that
524 performs the conversion of a 16-bit data word to be transmitted into seven consecutive symbols. The logic
525 function of the “Tx Mux Control Logic” in the Figure 19 example appears below in Table 7.
526 Table 7 Truth Table of the “Tx Mux Control Logic” in Figure 19
Flip[6:0]
Tx_Data
[15:10]
muxb6
muxb5
muxb4
muxb3
muxb2
muxb1
muxa6
muxa5
muxa4
muxa3
muxa2
muxa1
mux0
0x00 – 0x0f 1 0 1 0 1 0 1 0 1 0 0 1 0 0x00
0x10 – 0x13 0 1 0 1 0 1 0 1 0 1 0 0 1 0x01
0x14 – 0x17 0 1 0 1 0 1 0 1 0 1 1 0 0 0x02
0x18 – 0x1b 0 1 0 1 0 1 0 1 1 1 0 1 0 0x04
0x1c – 0x1f 0 1 0 1 0 1 1 1 1 0 0 1 0 0x08
0x20 – 0x23 0 1 0 1 1 1 1 0 1 0 0 1 0 0x10
0x24 – 0x27 0 1 1 1 1 0 1 0 1 0 0 1 0 0x20
0x28 – 0x2b 1 1 1 0 1 0 1 0 1 0 0 1 0 0x40
0x2c 0 0 0 0 0 0 0 0 0 0 1 0 1 0x03
0x2d 0 0 0 0 0 0 0 0 1 1 0 0 1 0x05
0x2e 0 0 0 0 0 0 1 1 0 1 0 0 1 0x09
0x2f 0 0 0 0 1 1 0 1 0 1 0 0 1 0x11
0x30 0 0 1 1 0 1 0 1 0 1 0 0 1 0x21
0x31 1 1 0 1 0 1 0 1 0 1 0 0 1 0x41
0x32 0 0 0 0 0 0 0 0 1 1 1 0 0 0x06
0x33 0 0 0 0 0 0 1 1 0 1 1 0 0 0x0a
0x34 0 0 0 0 1 1 0 1 0 1 1 0 0 0x12
0x35 0 0 1 1 0 1 0 1 0 1 1 0 0 0x22
0x36 1 1 0 1 0 1 0 1 0 1 1 0 0 0x42
0x37 0 0 0 0 0 0 1 1 1 1 0 1 0 0x0c
0x38 0 0 0 0 1 1 0 1 1 1 0 1 0 0x14
0x39 0 0 1 1 0 1 0 1 1 1 0 1 0 0x24
0x3a 1 1 0 1 0 1 0 1 1 1 0 1 0 0x44
0x3b 0 0 0 0 1 1 1 1 1 0 0 1 0 0x18
0x3c 0 0 1 1 0 1 1 1 1 0 0 1 0 0x28
0x3d 1 1 0 1 0 1 1 1 1 0 0 1 0 0x48
0x3e 0 0 1 1 1 1 1 0 1 0 0 1 0 0x30
0x3f 1 1 0 1 1 1 1 0 1 0 0 1 0 0x50
6.1.3.3.2 Rx 7-symbol to 16-bit De-Mapper

527 The De-Mapper shall perform a translation of a seven symbol group to a 16-bit value per the mapping
528 function defined in Figure 17.

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529 A high-level diagram of an example of a 7-to-16 De-Mapping circuit is shown in Figure 20, and a detailed
530 low-level implementation of the De-Mapper example is shown in Figure 21.
Rx_Rotation[0]
Rx_Polarity[0]
Rx_Rotation[1]
Rx_Polarity[1]
Rx_Rotation[2]
Rx_Polarity[2]
Mux Decoder converts
Rx_Rotation[3]
seven 2-bit inputs to Rx_Data[13:0]
Rx_Polarity[3]
one 14-bit output
Rx_Rotation[4]
Rx_Polarity[4]
Rx_Rotation[5]
Rx_Polarity[5]
Rx_Rotation[6]
Rx_Polarity[6]
Rx_Flip[0]
Rx_Flip[1]
Rx_Flip[2]
Mux Control
Rx_Flip[3] Rx_Data[15:14]
Logic function
Rx_Flip[4]
Rx_Flip[5]
Rx_Flip[6]
531
Figure 20 Example, De-Mapping Circuit Converts Seven Symbols to a 16-Bit Word

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muxa0
muxb0
sB sA
Rx_Polarity[0] in0[0]
Rx_Rotation[0] in0[1]
in1[0] out[0] Rx_Data[0]

in2[0]
in2[1]
muxa1
muxb1
sB sA

in2[0]
in2[1]
muxa2
muxb2
sB sA

in2[0]
in2[1]
muxa3
muxb3
sB sA

in2[0]
in2[1]
muxa4
muxb4
sB sA
Rx_Polarity[5] in1[0] out[0] Rx_Data[8]

Rx_Rotation[5] in1[1] out[1] Rx_Data[9]
muxa5
muxb5
sB sA
Rx Mux muxa0 in0[0]
muxb0 in0[1]
Control muxa1
Logic muxb1 in1[0] out[0] Rx_Data[10]
muxa2 in1[1] out[1] Rx_Data[11]
muxb2
Rx_Flip[0] Flip[0] muxa3 in2[0]
Rx_Flip[1] Flip[1] muxb3 in2[1]
Rx_Flip[2] Flip[2] muxa4
Rx_Flip[3] Flip[3] muxb4
Rx_Flip[4] Flip[4] muxa5 mux6
Rx_Flip[5] Flip[5] muxb5 S
Rx_Flip[6] Flip[6] mux6 in0[0]
in0[1]
table[10]
out[0] Rx_Data[12]
table[11] in1[0]
out[1] Rx_Data[13]
table[12] in1[1]
table[13]
table[14] Rx_Data[14]
table[15] Rx_Data[15]
532
Figure 21 Detailed Logic Diagram Example of a 7-Symbol to 16-bit Word De-Mapper
533 The logic function of the “Rx Mux Control Logic” in Figure 21 is shown below in Table 8.

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534 Table 8 Truth Table of the “Rx Mux Control Logic” in Figure 21
Rx_Flip[6:0]
table[15:14]
table[13:12]
table[11:10]
muxb5
muxb4
muxb3
muxb2
muxb1
muxb0
muxa6
muxa5
muxa4
muxa3
muxa2
muxa1
muxa0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x
0x01 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 x
0x02 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 x
0x04 1 0 1 0 1 0 1 0 1 0 0 0 0 1 2 x
0x08 1 0 1 0 1 0 1 0 0 0 0 0 0 1 3 x
0x10 1 0 1 0 1 0 0 0 0 0 0 0 0 2 0 x
0x20 1 0 1 0 0 0 0 0 0 0 0 0 0 2 1 x
0x40 1 0 0 0 0 0 0 0 0 0 0 0 0 2 2 x
0x03 1 1 0 1 0 1 0 1 0 1 0 1 0 2 3 0
0x05 1 1 0 1 0 1 0 1 0 1 0 0 1 2 3 1
0x09 1 1 0 1 0 1 0 1 0 0 1 0 1 2 3 2
0x11 1 1 0 1 0 1 0 0 1 0 1 0 1 2 3 3
0x21 1 1 0 1 0 0 1 0 1 0 1 0 1 3 0 0
0x41 1 1 0 0 1 0 1 0 1 0 1 0 1 3 0 1
0x06 1 1 0 1 0 1 0 1 0 1 0 0 0 3 0 2
0x0a 1 1 0 1 0 1 0 1 0 0 1 0 0 3 0 3
0x12 1 1 0 1 0 1 0 0 1 0 1 0 0 3 1 0
0x22 1 1 0 1 0 0 1 0 1 0 1 0 0 3 1 1
0x42 1 1 0 0 1 0 1 0 1 0 1 0 0 3 1 2
0x0c 1 1 0 1 0 1 0 1 0 0 0 0 0 3 1 3
0x14 1 1 0 1 0 1 0 0 1 0 0 0 0 3 2 0
0x24 1 1 0 1 0 0 1 0 1 0 0 0 0 3 2 1
0x44 1 1 0 0 1 0 1 0 1 0 0 0 0 3 2 2
0x18 1 1 0 1 0 1 0 0 0 0 0 0 0 3 2 3
0x28 1 1 0 1 0 0 1 0 0 0 0 0 0 3 3 0
0x48 1 1 0 0 1 0 1 0 0 0 0 0 0 3 3 1
0x30 1 1 0 1 0 0 0 0 0 0 0 0 0 3 3 2
0x50 1 1 0 0 1 0 0 0 0 0 0 0 0 3 3 3
6.1.4 Data Buffering

535 Data transmission takes place on protocol request. As soon as communication starts, the protocol layer at the
536 transmit side shall provide valid data as long as it does not stop its transmission request. For lanes that use
537 line coding, control symbols can also be inserted into the transmission. The protocol layer on the receive side
538 shall take the data as soon as delivered by the receiving PHY. The signaling concept, and therefore the PHY
539 protocol handshake, does not allow data throttling. Any data buffering for this purpose shall be inside the
540 protocol layer.

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6.2 Lane States and Line Levels

541 Transmitter functions determine the lane state by driving certain line levels. During normal operation either
542 a HS-TX or a LP-TX is driving a lane. A HS-TX always drives the lane differentially. The three LP-TX’s
543 drive the three lines of a lane independently and single-ended. This results in six possible high-speed lane
544 states and four possible low-power lane states: LP-000, LP-001, LP-100 and LP-111. The high-speed lane
545 states are: +x, -x, +y, -y, +z and –z. The interpretation of low-power lane states depends on the mode of
546 operation. The LP-Receivers shall always interpret any of the six high-speed states as LP-000.
Low-Power signaling level, VOH
Max LP-RX High
Minimum LP-RX Low threshold

HS diff. swing (e.g. 250mV)
HS common level
(e.g. 250mV)
547 Reference Ground

Figure 22 Line Levels
548 The Stop state has a very exclusive and central function. If the line levels show a Stop state for the minimum
549 required time, the PHY state machine shall return to the Stop state regardless of the previous state. This can
550 be in RX or TX mode depending on the most recent operating direction. Table 9 lists all the states that can
551 appear on a lane during normal operation. Detailed specifications of electrical levels can be found in section
552 9.
553 All LP state periods shall be at least tLPX in duration. State transitions shall be smooth and exclude glitch
554 effects. A clock signal can be reconstructed by exclusive-ORing the A and C lines. Ideally, the reconstructed
555 clock duration is at least 2  tLPX, but may have a duty cycle other than 50% due to signal slope and trip levels
556 effects.
557 Table 9 Lane State Descriptions

State Line Voltage Levels High-Speed Low-Power
Code A Line B Line C Line Burst Mode Control Mode Escape Mode
HS_+X HS High HS Low HS Mid +x state N/A, Note 1 N/A, Note 1
HS+-X HS Low HS High HS Mid -x state N/A, Note 1 N/A, Note 1
HS_+Y HS Mid HS High HS Low +y state N/A, Note 1 N/A, Note 1
HS_-Y HS Mid HS Low HS High -y state N/A, Note 1 N/A, Note 1
HS_+Z HS Low HS Mid HS High +z state N/A, Note 1 N/A, Note 1
HS_-Z HS High HS Mid HS Low -z state N/A, Note 1 N/A, Note 1
LP-000 LP Low LP Low LP Low N/A Bridge Space
LP-001 LP Low LP Low LP High N/A HS-Rqst Mark-0
LP-100 LP High LP Low LP Low N/A LP-Rqst Mark-1
LP-111 LP High LP High LP High N/A Stop N/A, Note 2
Note:
1. During high-speed transmission the low-power Receivers observe LP-000 on the lines.
2. If LP-111 occurs during escape mode the lane returns to Stop state (Control Mode LP-111).
3. Only 4 of the 8 possible low-power states are defined, because the C-PHY low-power states
correspond exactly to the D-PHY low-power states so that D-PHY low-power mode can be
duplicated.

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6.3 Operating Modes: Control, High-Speed, and Escape

558 During normal operation a lane will be either in Control or high-speed mode. High-speed data transmission
559 happens in bursts and starts from and ends at a Stop state (LP-111), which is by definition in Control mode.
560 The lane is only in high-speed mode during data bursts. The sequence to enter High- Speed mode is: LP-111,
561 LP-001, LP-000 at which point the lane remains in high-speed mode until a LP-111 is received. The escape
562 mode can only be entered via a request within Control mode. The lane shall always exit escape mode and
563 return to control mode after detection of a Stop state. If not in high-speed or escape mode the lane shall stay
564 in Control mode. The Stop state serves as a general standby state and may last for any period of time > tLPX.
565 Possible events starting from the Stop state are high-speed data transmission request (LP-111, LP-001, LP-
566 000), escape mode request (LP-111, LP-100, LP-000, LP-001, LP-000) or turnaround request (LP-111, LP-
567 100, LP-000, LP-100, LP-000).
6.4 High-Speed Data Transmission

568 High-speed data transmission occurs in bursts. To aid receiver synchronization, data bursts shall be extended
569 on the transmitter side with a Preamble and Post sequence. The effects of the high-speed transmitter shall be
570 eliminated on the receiver side by detecting certain events designed to be detected by the receiver so it can
571 ignore the ambiguous operating states during the mode transitions. These Preamble and Post sequences can
572 therefore only be observed on the transmission lines.
573 Transmission starts from, and ends with, a Stop state. During the intermediate time between bursts a lane
574 shall remain in the Stop state, unless a turnaround or escape request is presented on the lane. During a HS
575 Data Burst the lane shall be in high-speed mode and will be constantly toggling per the encoding rules, thus
576 providing high-speed data timing to the slave side.
6.4.1 Burst Payload Data

577 The payload data of a burst shall always represent an integer number of payload data words with a minimum
578 length of one word. Note that for short bursts the Start and End overhead consumes much more time than the
579 actual transfer of the payload data. There is no maximum number of words implied by the PHY. However, in
580 the PHY there is no autonomous way of error recovery during a HS data burst. The practical symbol error
581 rate is nearly zero. It is important to consider for every individual protocol what the best choice is for
582 maximum burst length.
6.4.2 Start-of-Transmission
583 After a Transmit request, a lane leaves the Stop state and prepares for high-speed mode by means of a Start-
584 of-Transmission (SoT) procedure. Table 10 describes the sequence of events on TX and RX side.
585 Table 10 Start-of-Transmission Sequence

Tx Side Rx Side
Drives Stop state (LP-111) Observes Stop state
Drives HS-Rqst state (LP-001) for time tLPX Observes transition from LP-111 to LP-001 on the
lines
Drives Bridge state (LP-000) for time t3-PREPARE Observes transition from LP-001 to LP-000 on the
lines, enables line termination after time t3-TERM-EN
Enables high-speed driver and disables low-power
drivers simultaneously.
Drives Preamble sequence for time t3-PREAMBLE Enables HS-RX and waits for timer t3-SETTLE to
expire in order to neglect transition effects
Starts looking for the Sync Word sequence
Inserts the Sync Word Sequence

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Synchronizes upon recognition of Sync Word

Sequence
Continues to transmit high-speed payload data
Receives payload data
6.4.3 End-of-Transmission
586 At the end of a Data Burst, a lane leaves high-speed Transmission mode and enters the Stop state by means
587 of an End-of-Transmission (EoT) procedure. Table 11 shows a possible sequence of events during the EoT
588 procedure. EoT processing may be performed by the protocol layer or by the C-PHY.
589 Table 11 End-of-Transmission Sequence

Tx Side Rx Side
Completes Transmission of payload data Receives payload data
Transmits the Post Sequence immediately after last Detect Post Sequence to determine last valid Data
payload data bit for time t3-POST word and skip the remainder of the Post sequence
Disables the HS-TX, enables the LP-TX, and drives Detects the lines leaving LP-000 state and entering
Stop state (LP-111) for time tHS-EXIT Stop state (LP-111) and disables Termination
6.4.4 HS Data Transmission Burst

590 Figure 23 shows the sequence of events during the transmission of a Data Burst. Transmission can be started
591 and ended independently for any lane by the protocol layer. However, for most applications the lanes will
592 start synchronously but may end at different times due to an unequal amount of transmitted bytes per lane.
593 The handshake with the protocol layer is described in Annex A.
594 Beginning from the Stop state, LP-111, the signals transition to LP-001 and then LP-000 to signal that high-
595 speed data transmission will begin soon. At the end of t3-PREPARE the low-power drivers are disabled and the
596 high-speed drivers are enabled simultaneously. The TX state machine should transmit the same wire state as
597 the first high-speed wire state at the beginning of t3-PREBEGIN for each Data Burst in order for the test equipment
598 to measure t3-PREBEGIN value consistently. This does not correspond to any particular symbol value because
599 there is no previous HS wire state before it. It is likely that the first few wire states of the t3-PREBEGIN interval
600 will not be seen at the high-speed receiver. This is because there will be some delay for the high-speed drivers
601 to reach their required signal levels at the beginning of t3-PREBEGIN, and also the high-speed receivers will be
602 enabled and at some point start producing outputs toward the end of t3-SETTLE. The receive circuitry shall be
603 enabled toward the end of t3-SETTLE when it is safe for it to reliably decode the “3” symbols during t3-PRE-BEGIN.
604 It is not guaranteed at exactly which symbol clock generation and symbol decoding will begin at the end of
605 t3-SETTLE. The t3-PREBEGIN field may often consist of multiple groups of seven “3” symbols to provide a
606 sufficient number of clocks to the upper layer protocol to initialize any pipeline stages prior to receiving data.
607 The length of t3-PREBEGIN is a programmable value set in the master.
608 The master may output a programmable sequence during t3-PROGSEQ of the preamble, if it is enabled using a
609 programmable sequence enable bit such as the MSB of the control register described in section 12.5.3. The
610 symbol values transmitted in the programmable sequence, or whether the programmable sequence is used at
611 all, is a choice of the system designer.
612 Figure 23 shows examples of the preamble with and without the programmable sequence. Seven symbols of
613 value “3” are sent during t3-PREEND just prior to sending the Sync Word.
614 The Sync Word precisely identifies the beginning of the Packet Data and also identifies the timing alignment
615 of word boundaries in the Packet Data. The Sync Word contains a sequence of five “4” symbols which does
616 not occur in any sequence of symbols generated by the Mapper. The Sync Word may also be transmitted later
617 in the burst to mark the beginning of redundant Packet Headers transmitted by the upper layer protocol.

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618 The end of Packet Data is identified by a unique sequence of “4” symbols in t3-POST. The receiver identifies
619 the end of Packet Data when it detects a sequence of seven consecutive “4” symbols. The Post field may
620 often consist of multiple groups of seven “4” symbols to provide a sufficient number of clocks to the upper
621 layer protocol to clear out any pipeline stages that may contain received data. The length of the Post field is
622 a programmable value set in the master, for example: the post length field of the register described in section
623 12.5.4.
624 At the end of t3-POST the high-speed drivers are disabled and the low-power drivers are enabled simultaneously,
625 and all three signals of the lane are driven high together to LP-111, the Stop state.

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Detail of Programmable Sequence

3 3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 3 3
A/B/C t3-PREAMBLE
tLPX t3-PREPARE
t3-PREBEGIN t3-PROGSEQ t3-PREEND t3-SYNC
VIH(min)
VIL(max)
VTERM-EN(max) 3 3 3 3 3 3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 3 3 3 3 3 3 3 3 4 4 4 4 4 3 4 4 4 4 4 4 4 4
tREOT
t3-TERM-EN Packet t3-POST tHS-EXIT
Preamble Sync Word
t3-SETTLE Data Post LP-111
LP-111 LP-001 LP-000 Preamble is composed of: 3,3,3,3,3,… Sync Word: Post is composed of
with mid-section consisting of a programmable sequence. 3,4,4,4,4,4,3 multiple of unused code
Reset initializes all to 3,3,3,3,3... (Least Significant word: 4,4,4,4,4,4,4
Symbol first)
A/B/C t3-PREAMBLE
tLPX t3-PREPARE
t3-PREBEGIN t3-PREEND t3-SYNC
VIH(min)
VIL(max)
VTERM-EN(max) 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 3 4 4 4 4 4 4 4 4
tREOT
t3-TERM-EN Packet t3-POST tHS-EXIT
Preamble Sync Word
t3-SETTLE Data Post LP-111
LP-111 LP-001 LP-000 Preamble is composed Sync Word: Post is composed of multiple
of: 3,3,3,3,3,… 3,4,4,4,4,4,3 of unused code word:
Prog. sequence in (Least Significant 4,4,4,4,4,4,4
626 mid-section is disabled. Symbol first)
Figure 23 High-Speed Data Transmission in Burst

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TX-Stop RX-Stop
TX-HS-Request RX-HS-Request
TX-HS-Prepare RX-HS-Prepare
TX-HS-Run RX-HS-Run
Sub-state Machine Sub-state Machine
TX-HS-Preamble RX-HS-Settle
TX-HS-Prog-Seq RX-HS-Preamble
TX-HS-Pre-End
TX-HS-Sync-Word RX-HS-Sync-Search
TX-HS-Send-Data RX-HS-Receive-Data
TX-HS-Post RX-HS-Post
627
Figure 24 TX and RX State Machines for High-Speed Data Transmission
628 Table 12 High-Speed Data Transmission State Machine Description

State Line Condition Exit State Exit Conditions
or Line State
TX-Stop Transmit LP-111 TX-HS-Request On request of Protocol
for High-Speed
Transmission
TX-HS-Request Transmit LP-001 TX-HS-Prepare End of timed interval
tLPX
TX-HS-Prepare Transmit LP-000 TX-HS-Preamble End of interval t3-PREPARE
TX-HS-Preamble Preamble TX-HS-Prog-Seq End of Preamble &
3,3,3,3… Prog-Seq selected
TX-HS-Pre-End End of Preamble &
Prog-Seq not selected
TX-HS-Preamble Preamble words
remaining count > 0
TX-HS-Prog-Seq Prog-Seq TX-HS-Pre-End End of Prog-Seq
TX-HS-Pre-End Pre-End TX-HS-Sync-Word End of Pre-End
TX-HS-Sync-Word Sync Word TX-HS-Send-Data End of Sync-Word
TX-HS-Send-Data Packet Data TX-HS-Post End of Packet Data
TX-HS-Send-Data Packet Data available to
send
TX-HS-Post Post TX-Stop Last word of Post sent

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or Line State
4,4,4,4… TX-HS-Post Post words remaining
count > 0
629 Table 13 High-Speed Data Reception State Machine Description

State Line Exit State Exit Conditions
Condition
or Line State
RX-Stop LP-111 RX-HS-Request Line transition to LP-001 detected
RX-HS-Request LP-001 RX-HS-Prepare Line transition to LP-000 detected
PX-HS-Prepare LP-000 RX-HS-Settle t3-TERM-EN expired
RX-HS-Settle LP-000 or RX-HS-Prog-Seq t3-SETTLE expired & Prog-Seq selected
Preamble RX-HS-Sync- t3-SETTLE expired & Prog-Seq not selected
3,3,3,3… Search
RX-HS-Settle t3-SETTLE time not expired
RX-HS-Preamble Any part of RX-HS-Sync- High-speed circuit initialization complete
Preamble Search
RX-HS-Preamble High-speed circuit initialization not
complete
RX-HS-Sync- Preamble or RX-HS-Receive- Sync Word detected
Search Sync Word Data
RX-HS-Receive- Packet Data RX-HS-Post First word of Post detected
Data
RX-HS-Receive- Post not yet detected
Data
RX-HS-Post Post RX-Stop Line transition to LP-111 detected
4,4,4,4… RX-HS-Post Receiving Post, waiting for LP-111
6.4.4.1 Sync Word for Packet Header Resynchronization

630 A given C-PHY wire state link error causes two symbol decoding errors. If the erroneous wire state also
631 matches the wire state immediately preceding and/or following it, then the C-PHY receiver’s clock and data
632 recovery circuit will miss one or two symbol clocks, thereby causing loss of 7-symbol word alignment. If left
633 uncorrected, this loss of word alignment will likely cause extensive de-mapping errors in the rest of the
634 received packet payload.
635 In order to facilitate restoration of the transmitted word alignment, this specification defines an unmapped,
636 7-symbol Sync Word which may be inserted by the C-PHY transmitter at a point directed by the protocol
637 layer via the PPI. The 7-symbol value of the Sync Word is [3444443], which is the same value used for the
638 Sync Word as described in Section 6.4.4.
639 The C-PHY transmitter directly encodes the Sync Word into a series of seven wire states, bypassing the
640 symbol mapping block which normally processes 16-bit packet payload words.
641 The C-PHY receiver recognizes a Sync Word by detecting any sequence of five consecutive {4} symbols
642 immediately followed a {3} symbol at the output of the symbol decoder; i.e. detection of the least significant
643 {3} symbol of the Sync Word is not required. Ignoring the latter symbol actually makes Sync Word detection
644 more robust because a wire state error occurring during the most significant symbol of the 7-symbol payload
645 word immediately preceding the Sync Word also causes corruption of the Sync Word’s least significant
646 symbol. See Figure 25 for examples of Sync Word detection.

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647 The C-PHY receiver detects the Sync Word directly at the output of the symbol decoder, prior to the symbol
648 de-mapping block. Any 16-bit word generated by the symbol de-mapping block in response to the Sync Word
649 shall be ignored and not passed to the receiver protocol layer.
650 Upon detecting the Sync Word, the C-PHY receiver resets 7-symbol word alignment to start with the first
651 symbol immediately following Sync Word detection (i.e. the first symbol immediately following the {3}
652 symbol). Word realignment points are shown in the Sync Word detection examples of Figure 25.
653 All C-PHY receivers shall support Sync Word detection and realignment. While this specification itself does
654 not require a C-PHY transmitter to support Sync Word insertion, it may instead be required by the protocol
655 layer specification used in conjunction with the transmitter.
Link Error Example (a): Loss of No Symbol Clocks

Symbol Interval
{ TX: Transmit Sync Word [s0:s6]
s0 s1 s2 s3 s4 s5 s6
Transmitted Symbols 2 1 3 2 1 3 0 3 4 4 4 4 4 3 2 4 3
Transmitted Wire States +z +x -z +x +y -x +y +x -y +y -y +y -y +y -z -x +x -y
Received Wire States +z +x -z +x +y -x +y +z -y +y -y +y -y +y -z -x +x -y

RX: Detect Sync Word [s1:s6]
Received Symbols 2 1 3 2 1 3 2 1 4 4 4 4 4 3 2 4 3
7 Received Symbols
Link Error Example (b): Loss of One Symbol Clock

Symbol Interval TX: Transmit Sync Word [s0:s6]
{
s0 s1 s2 s3 s4 s5 s6
Transmitted Wire States +z -y +z +y -z +z -y +y -z +z -z +z -z +z -x -z +x -z
Received Wire States +z -y +z +y -z +z -y -y -z +z -z +z -z +z -x +x -y -x

7 Received Symbols
Link Error Example (c): Loss of Two Symbol Clocks

Symbol Interval TX: Transmit Sync Word [s0:s6]
{
s0 s1 s2 s3 s4 s5 s6
Transmitted Wire States +z -z +x -z -x -z +y -x +y -y +y -y +y -y +z +y +z -z
Received Wire States +z -z +x -z -x -z +y +y +y -y +y -y +y -y +z +y +z -z

7 Received Symbols
Notes:
• Symbols are transmitted serially from left to right
• Wire state and symbol errors are highlighted in yellow
• : point at which symbol clock is lost
• : point at which symbol clock is restored
• : point of incorrect word alignment
656 • : point at which correct word alignment is restored
Figure 25 Link Error and Sync Word Detection Examples

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6.5 Bi-directional Lane Turnaround

657 The transmission direction of a bi-directional lane can be swapped by means of a link turnaround procedure.
658 This procedure enables information transfer in the opposite direction of the current direction. The procedure
659 is the same for either a change from forward-to-reverse direction or reverse-to-forward direction. Notice that
660 master and slave side shall not be changed by turnaround. Link turnaround shall be handled completely in
661 Control mode. Table 14 lists the sequence of events during turnaround.
662 Table 14 Link Turnaround Sequence

Initial TX Side = Final RX Side Initial RX Side = Final TX Side
Drives Stop state (LP-111) Observes Stop state
Drives LP-Rqst state (LP-100) for time tLPX Observes transition from LP-111 to LP-100 states
Drives Bridge state (LP-000) for time tLPX Observes transition from LP-100 to LP-000 states
Drives LP-100 for time tLPX Observes transition from LP-000 to LP-100 states
Drives Bridge state (LP-000) for time tTA-GO Observes the transition from LP-100 to Bridge
state and waits for time tTA-SURE. After correct
completion of this time-out this side knows it is in
control.
Drives Bridge state (LP-000) for a period tTA-GET
Stops driving the lines and observes the line states
with its LP-RX in order to see an
acknowledgement.
Drives LP-100 for a period tLPX
Observes LP-100 on the lines, interprets this as
acknowledge that the other side has indeed taken
control. Waits for Stop state to complete turnaround
procedure.
Drives Stop state (LP-111) for a period tLPX
Observes transition to Stop state (LP-111) on the
lines, interprets this as turnaround completion
acknowledgement, switches to normal LP receive
mode and waits for further actions from the other
side
663 Figure 26 shows the turnaround procedure graphically.
tLPX tLPX tLPX tTA-GO

drive
overlap
LP-111 LP-100 LP-000 LP-100 LP-000 LP-000 LP-000 LP-100 LP-111

tTA-SURE tTA-GET tLPX tLPX
664
Figure 26 Turnaround Procedure
665 The low-power clock timing for both sides of the link does not have to be the same, but may differ. However,
666 the ratio between the low-power state periods, tLPX, is constrained to ensure proper turnaround behavior. See
667 Table 18 for the ratio of tLPX(MASTER) to tLPX(SLAVE).

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668 The turnaround procedure can be interrupted if the lane is not yet driven into TX-LP-Yield by means of
669 driving a Stop state. Driving the Stop state shall abort the turnaround procedure and return the lane to the
670 Stop state. The PHY shall ensure against interruption of the procedure after the end of TX-TA-Rqst, RX-TA-
671 Rqst, or TX-TA-GO. Once the PHY drives TX-LP-Yield, it shall not abort the turnaround procedure. The
672 protocol layer may take appropriate action if it determines an error has occurred because the turnaround
673 procedure did not complete within a certain time. See Section 7.3.5 for more details. Figure 27 shows the
674 turnaround state machine that is described in Table 15.
TX-Stop RX-Stop
TX-LP-Rqst RX-LP-Rqst
TX-LP-Yield RX-LP-Yield
TX-TA-Rqst RX-TA-Rqst
TX-TA-Go RX-TA-Wait
TX-TA-Get
RX-TA-Look
RX-TA-Ack TX-TA-Ack
RX-Stop TX-Stop
Note: Horizontally aligned states

675 occur simultaneously
Figure 27 Turnaround State Machine
676 Table 15 Turnaround State Machine Description

or Line State
Any Rx state Any Received RX-Stop Observe LP-111 at lines
TX-Stop Transmit LP-111 TX-LP-Rqst On request of protocol for turnaround
TX-LP-Rqst Transmit LP-100 TX-LP-Yield End of timed interval tLPX
TX-LP-Yield Transmit LP-000 TX-TA-Rqst End of timed interval tLPX
TX-TA-Rqst Transmit LP-100 TX-TA-Go End of timed interval tLPX
TX-TA-Go Transmit LP-000 RX-TA-Look End of timed interval TTA-GO
RX-TA-Look Receive LP-000 RX-TA-Ack Line transition to LP-100

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or Line State
RX-TA-Ack Receive LP-100 RX-Stop Line transition to LP-111
RX-Stop Receive LP-111 RX-LP-Rqst Line transition to LP-100
RX-LP-Rqst Receive LP-100 RX-LP-Yield Line transition to LP-000
RX-LP-Yield Receive LP-000 RX-TA-Rqst Line transition to LP-100
RX-TA-Rqst Receive LP-100 RX-TA-Wait Line transition to LP-000
RX-TA-Wait Receive LP-000 TX-TA-Get End of timed interval tTA-SURE
TX-TA-Get Transmit LP-000 TX-TA-Ack End of timed interval tTA-GET
TX-TA-Ack Transmit LP-100 TX-Stop End of timed interval tLPX
Note:
During RX-TA-Look, the protocol layer may cause the PHY to transition to TX-Stop.
During high-speed data transmission, Stop states (TX-Stop, RX-Stop) have multiple valid exit states.
6.6 Escape Mode

677 Escape mode is a special mode of operation for lanes using Low-Power states. With this mode some
678 additional functionality becomes available. Escape mode operation shall be supported in the forward
679 direction and is optional in the reverse direction. If supported, escape mode does not have to include all
680 available features.
681 A lane shall enter escape mode via an escape mode entry procedure (LP-111, LP-100, LP-000, LP-001, LP-
682 000). As soon as the final Bridge state (LP-000) is observed on the lines the lane shall enter escape mode in
683 space state (LP-000). If an LP-111 is detected at any time before the final Bridge state (LP-000), the Escape
684 mode entry procedure shall be aborted and the receive side shall wait for, or return to, the Stop state.
685 Once escape mode is entered, the transmitter shall send an 8-bit entry command to indicate the requested
686 action. Table 16 lists all currently available escape mode commands and actions. All unassigned commands
687 are reserved for future expansion.
688 The Stop state shall be used to exit escape mode and cannot occur during escape mode operation because of
689 the spaced-one-hot encoding. The Stop state immediately returns the lane to Control mode. If the entry
690 command doesn’t match a supported command, that particular escape mode action shall be ignored and the
691 receive side waits until the transmit side returns to the Stop state.
692 The PHY in escape mode shall apply spaced-one-hot bit encoding for asynchronous communication.
693 Therefore, operation of a lane in this mode does not depend on a separate clock signal. The complete escape
694 mode action for a Trigger-Reset command is shown in Figure 28.

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LP-111à100à000à001à000à001à000à100à000à...
0 1 1 0 0 0 1 0
Escape Mode Entry Entry Command Mark-1 and

Stop State
LP CLK = EXOR(A, C)
695
Figure 28 Trigger-Reset Command in Escape Mode
696 Spaced-one-hot coding means that each mark state is interleaved with a space state. Each symbol consists
697 therefore of two parts: a one-hot phase (Mark-0 or Mark-1) and a space phase. The TX shall send Mark-0
698 followed by a space to transmit a ‘zero-bit’ and it shall send a Mark-1 followed by a space to transmit a ‘one-
699 bit’. A mark that is not followed by a space does not represent a bit. The last phase before exiting escape
700 mode with a Stop state shall be a Mark-1 state that is not part of the communicated bits, as it is not followed
701 by a space state. The Clock can be derived from the two line signals, A and C, by means of an exclusive-OR
702 function. The length of each individual LP state period shall be at least tLPX,MIN.
703 Table 16 Escape Entry Codes

Escape Mode Action Command Type Entry Command Pattern
(first bit transmitted to last bit transmitted)
Low-Power Data Transmission mode 11100001
Ultra-Low Power State mode 00011110
Undefined-1 mode 10011111
Undefined-2 mode 11011110
Reset-Trigger Trigger 01100010
[Remote Application]
Unknown-3 Trigger 01011101
6.6.1 Remote Triggers

704 Trigger signaling is the mechanism to send a flag to the protocol layer at the receiving side, on request of the
705 protocol layer on the transmitting side. This can be either in the forward or reverse direction depending on
706 the direction of operation and available escape mode functionality. Trigger signaling requires escape mode
707 capability and at least one matching Trigger Escape entry command on both sides of the interface.
708 Figure 28 shows an example of an escape mode Reset-Trigger action. The lane enters escape mode via the
709 escape mode entry procedure. If the entry command Pattern matches the Reset-Trigger Command a Trigger
710 is flagged to the protocol layer at the receive side via the logical PPI. Any bit received after a Trigger
711 Command but before the lines go to the Stop state shall be ignored. Therefore, dummy bytes can be
712 concatenated in order to provide Clock information to the receive side.

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713 Note that Trigger signaling including Reset-Trigger is a generic messaging system. The Trigger commands
714 do not impact the behavior of the PHY itself. Therefore, Triggers can be used for any purpose by the protocol
715 layer.
6.6.2 Low-Power Data Transmission

716 If the escape mode entry procedure is followed-up by the entry command for Low-Power Data Transmission
717 (LPDT), Data can be communicated by the protocol layer at low speed, while the lane remains in low-power
718 mode.
719 Data shall be encoded on the lines with the same spaced-one-hot code as used for the entry commands. The
720 data is self-clocked by the applied bit encoding and does not rely on a supplemental clock signal. The lane
721 can pause while using LPDT by maintaining a space state on the lines. A Stop state on the lines stops LPDT,
722 exits escape mode, and switches the lane to control mode. The last phase before Stop state shall be a Mark-1
723 state, which does not represent a data-bit. Figure 29 shows a two-byte transmission with a pause period
724 between the two bytes.
Escape LPDT First Data Byte Pause: Second Data Byte Exit
Mode Entry Command 01110101 Asynchronous 11010000 Escape
no transition
LP CLK = EXOR(A, C)
725
Figure 29 Two Data Byte Low-Power Data Transmission Example
726 Using LPDT, a low-power (bit) clock signal (fMOMENTARY < 20MHz) provided to the transmit side is used to
727 transmit data. Data reception is self-timed by the bit encoding. Therefore, a variable clock rate can be allowed.
728 At the end of LPDT the lane shall return to the Stop state.
6.6.3 Ultra-Low Power State

729 If the Ultra-Low Power State entry command is sent after an escape mode entry command, the lane shall
730 enter the Ultra-Low Power State (ULPS). This command shall be flagged to the receive side protocol. During
731 this state, the lines are in the space state (LP-000). Ultra-Low Power State is exited by means of a Mark-1
732 state with a length tWAKEUP followed by a Stop state. Annex A describes an example of an exit procedure and
733 a procedure to control the length of time spent in the Mark-1 state.
6.6.4 Escape Mode State Machine

734 The state machine for escape mode operation is shown in Figure 30 and described in Table 17.

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TX-Stop RX-Stop
TX-LP-Rqst RX-LP-Rqst
TX-LP-Yield RX-LP-Yield
TX-Esc-Rqst RX-Esc-Rqst
TX-Esc-Go RX-Esc-Go
TX-Esc-Cmd RX-Esc-Cmd
TX-Triggers
TX-Mark RX-Wait
TX-ULPS RX-ULPS
TX-LPDT RX-LPDT
Note: Horizontally aligned states

735 occur simultaneously
Figure 30 Escape Mode State Machine
736 Table 17 Escape Mode State Machine Description

or Line State
Any RX state Any Received RX-Stop Observe LP-111 at lines
TX-Stop Transmit LP-111 TX-LP-Rqst On request of protocol layer
for Esc mode (PPI)
TX-LP-Rqst Transmit LP-100 TX-LP-Yield After time tLPX
TX-LP-Yield Transmit LP-000 TX-Esc-Rqst After time tLPX
TX-Esc-Rqst Transmit LP-001 TX-Esc-Go After time tLPX
TX-Esc-Go Transmit LP-000 TX-Esc-Cmd After time tLPX
TX-Esc-Cmd Transmit sequence of TX-Triggers After a Trigger Command
8-bit (16-line-states)
TX-ULPS After Ultra-Low Power Command
spaced-one-hot
encoded entry TX-LPDT After Low-Power Data Transmission
command Command
TX-Triggers Space state or optional TX-Mark Exit of the Trigger State on request of the
dummy bytes for the protocol layer (via the PPI)
purpose of generating
clocks

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or Line State
TX-ULPS Transmit LP-000 TX-Mark End of ULP State on request of the protocol
layer (via the PPI)
TX-LPDT Transmit serialized, After last transmitted data bit
spaced-one-hot
encoded payload data
TX-Mark Mark-1 TX-Stop Next driven state after time tLPX, or tWAKEUP if
leaving ULP State
RX-Stop Receive LP-111 RX-LP-Rqst Line transition to LP-100
RX-LP-Rqst Receive LP-100 RX-LP-Yield Line transition to LP-000
RX-LP-Yield Receive LP-000 RX-Esc-Rqst Line transition to LP-001
RX-Esc-Rqst Receive LP-001 RX-Esc-Go Line transition to LP-000
RX-Esc-Go Receive LP-000 RX-Esc-Cmd Line transition out of LP-000
RX-Esc-Cmd Receive sequence of RX-Wait After Trigger and Unrecognized Commands
8-
RX-ULPS After Ultra-Low Power Command
bit (16-line-states)
spaced-one-hot RX-LPDT After Low-Power Data Transmission
encoded Command
entry Command
RX-ULPS Receive LP-000 RX-Wait Line transition to LP-100
RX-LPDT Receive serial, RX-Stop Line transition to LP-111 (Last state should be
Spaced- a Mark-1)
One-Hot encoded
payload data
RX-Wait Any, except LP-111 RX-Stop Line transition to LP-111
Note:
During high-speed data transmission, Stop states (TX-Stop, RX-Stop) have multiple valid exit states.
6.7 (Not Used)

737 Note:
738 This section is null for the C-PHY Specification. The section heading has been retained in order to
739 synchronize section numbering with the D-PHY Specification [MIPI01].
6.8 (Not Used)

740 Note:
6.9 Global Operation Timing Parameters

743 Table 18 lists the ranges for all timing parameters used in this section. The values in the table assume a UI
744 variation in the range defined by ΔUI (see Table 32).
745 Transmitters shall support all transmitter-specific timing parameters defined in Table 18.
746 Receivers shall support all Receiver-specific timing parameters in defined in Table 18.

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747 Also note that while corresponding receiver tolerances are not defined for every transmitter-specific
748 parameter, receivers shall also support reception of all allowed conformant values for all transmitter specific
749 timing parameters in Table 18 for all HS UI values up to, and including, the maximum supported HS symbol
750 rate specified in the receiver’s datasheet.
751 Table 18 Global Operation Timing Parameters

Parameter Description Min Max Unit Notes
t3-PREPARE Time that the transmitter drives the 3-wire LP-000 38 95 ns 2
line state immediately before the HS_+x line state
starting the HS transmission.
t3-TERM-EN Time for the slave to enable the HS line Note 38 ns 3
termination, starting from the time point when the 5
A, B and C wire cross VIL_MAX
t3-SETTLE Time interval during which the HS receiver should 95 300 ns 3,4
ignore any HS transitions on the lane, starting
from the beginning of t3-PREPARE
t3-HS-EXIT Time that the transmitter drives LP-111 following a 100 ns 2
HS burst.
tLPX Transmitted length of any low-power state period 50 ns 1, 2
tINIT See Section 6.11. 100 µs 2
Ratio tLPX Ratio of tLPX(MASTER)/tLPX(SLAVE) between master and 2/3 3/2
slave side
tTA-GET Time that the new transmitter drives the Bridge 5 tLPX 2
state (LP-000) after accepting control during a link
turnaround.
tTA-GO Time that the transmitter drives the Bridge state 4 tLPX 2
(LP-000) before releasing control during a link
turnaround.
tTA-SURE Time that the new transmitter waits after the LP- tLPX 2 tLPX ns 2
100 state before transmitting the Bridge state (LP-
000) during a link turnaround.
tWAKEUP Time that a transmitter drives a Mark-1 state prior 1 ms 2
to a Stop state in order to initiate an exit from
ULPS.
Note:
1. tLPX is an internal state machine timing reference. Externally measured values may differ slightly
from the specified values due to asymmetrical rise and fall times.
2. Transmitter-specific parameter.
3. Receiver-specific parameter.
4. The stated values are considered informative guidelines rather than normative requirements since
this parameter is untestable in typical applications.
5. As specified in Section 9.2.1, the receiver termination impedances shall not be enabled until the
single-ended voltages on all of A, B and C fall below VTERM-EN.
752 t3-SETTLE > t3-PREPARE t3-PROGSEQ = 14 UI or 0 UI
753 t3-SETTLE < t3-PREPARE + t3-PREAMBLE t3-PREEND = 7 UI
754 t3-PREAMBLE = t3-PREBEGIN + t3-PROGSEQ + t3-PREEND t3-SYNC = 7 UI
755 t3-PREBEGIN should be adjustable from 7 UI minimum to 448 UI maximum in increments of 7 UI. An
756 example method to specify the length of t3-PREBEGIN is provided in section 12.5.3. t3-POST should be
757 adjustable from 7 UI minimum to 224 UI maximum in increments of 7 UI. An example method to specify
758 the length of t3-POST is provided in section 12.5.4.

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6.10 System Power States

759 Each lane within a PHY configuration, that is powered and enabled, has potentially two different power
760 consumption levels: high-speed transmission mode and Ultra-Low Power State. For details on Ultra-Low
761 Power State see Section 6.6.3. The transition between these modes shall be handled by the PHY.
6.11 Initialization
762 After power-up, the slave side PHY shall be initialized when the master PHY drives a Stop state (LP-111) for
763 a period longer than tINIT. The first Stop state longer than the specified tINIT is called the initialization period.
764 The master PHY itself shall be initialized by a system or protocol layer input signal (PPI). The master side
765 shall ensure that a Stop state longer than tINIT does not occur on the lines before the master is initialized. The
766 slave side shall ignore all line states during an interval of unspecified length prior to the initialization period.
767 In multi-lane configurations, all lanes shall be initialized simultaneously.
768 Note that tINIT is considered a protocol-dependent parameter, and thus the exact requirements for tINIT,MASTER
769 and tINIT,SLAVE (transmitter and receiver initialization Stop state lengths, respectively,) are defined by the
770 protocol layer specification and are outside the scope of this document. However, the C-PHY specification
771 does place a minimum bound on the lengths of tINIT,MASTER and tINIT,SLAVE, which each shall be no less than
772 100 μs. A protocol layer specification using the C-PHY specification may specify any values greater than this
773 limit, for example, tINIT,MASTER ≥ 1 ms and tINIT,SLAVE = 500 to 800 μs.
774 Table 19 Initialization States

State Entry Conditions Exit State Exit Conditions Line Levels
Master Off Power-down Master Power-up Any LP level
Initialization except Stop states
for periods>100µs
Master Init Power-up or TX-stop A first Stop state Any LP signaling
protocol request for a period longer sequence that
than tINIT,MASTER as ends with a long
specified by the initialization Stop
protocol layer state
Slave Off Power-down Any LP state Power-up Any
Slave Init Power-up or RX-Stop Observe Stop Any LP signaling
protocol layer state at the inputs sequence which
request for a period ends with the first
tINIT,SLAVE as long initialization
specified by the stop period
protocol layer
6.12 Calibration
775 There is no explicit calibration required by the C-PHY specification. Any detail regarding calibration is
776 outside the scope of this specification.
6.13 Global Operation Flow Diagram

777 All previously described aspects of operation, either including or excluding optional parts, are contained in
778 lane modules. Figure 31 shows the operational flow diagram for a lane module. Within both TX and RX four
779 main processes can be distinguished: High-Speed Transmission, escape mode, turnaround, and initialization.

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TX Trigger Escape
Init ULP Mode
Mode
Master LPDT
HS-Prpr
HS HS
HS-Rqst Stop LP-Rqst
LP-000
LP-00 LP
-01
LP-001 LP-111
LP-11 LP-100
SoT
SoT HST EoT Turnaround
LP-000à100à000à100
RX Trigger Escape
Escape
ULP Mode
Mode
Init
Init Wait
Slave
Slave LPDT
HS-Prpr
HS
- HS-Rqst
HS Stop
Stop LP-Rqst
LP
LP-000
LP-00 LP-001
LP-01 LP-111
LP-11 LP-100
LP-10
SoT HST EoT Turnaround

Turnaround
LP-000à100à000à100
LP- 00>10>00>10
780
Figure 31 Lane Module State Diagram
6.14 Data Rate Dependent Parameters (informative)

781 The high-speed data transfer rate of the C-PHY may be programmable to values determined by a particular
782 implementation. Any individual data transfer between SoT and EoT sequences must take place at a given,
783 fixed rate. However, reprogramming the data rate of the C-PHY high-speed transfer is allowed at
784 initialization, before starting the exit from ULP state or in Stop state. The method of data rate reprogramming
785 is out of the scope of this document.
6.14.1 Parameters Containing Only UI Values

786 Certain parameters are specified as a number of UI intervals. Often this shall be a multiple of 7 UI which
787 simplifies the implementation of both the master and slave because decisions regarding the transmission of
788 fields can take place at a word clock interval. Parameters specified in units of UI are:
789 • t3-PREBEGIN – the length of the first part of the Preamble
790 • t3-PROGSEQ – the length of the programmable sequence section of the preamble
791 • t3-PREEND – the length of the end of the preamble
792 • t3-PREAMBLE – the length of the entire preamble including t3-BEGIN, t3-PROGSEQ and t3-PREEND
793 • t3-SYNC – the length of the Sync Word
794 • t3-POST – the length of the Post sequence at the end of the burst

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6.14.2 Parameters Containing Time and UI values

795 There are no parameters specified as the sum of an explicit time and a number of UI.
6.14.3 Parameters Containing Only Time Values

796 Several parameters are specified only as explicit time values. These explicit time values are typically derived
797 from the time needed to charge and discharge the interconnect and are, therefore, not data rate dependent. It
798 is conceivable to use an analog timer or counter clocked by the UI to ensure the implementation satisfies
799 these parameters. However, if these time values are implemented by counting UI only, then the count value
800 is a function of the data rate and, therefore, must be changed when the data rate is changed.
801 The following parameters are based on time values alone:
802 • t3-PREPARE
803 • t3-TERM-EN
804 • t3-SETTLE
805 • t3-HS-EXIT
6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent
806 The remaining parameters in Table 18 shall be complied with even when the high-speed clock is off. These
807 parameters include low-power and initialization state durations and LP signaling intervals. Though these
808 parameters are not HS data rate dependent, some implementations of D-PHY may need to adjust these values
809 when the data rate is changed.

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7 Fault Detection
810 There are three different mechanisms to detect malfunctioning of the link. Bus contention and error detection
811 functions are contained within the C-PHY. These functions should detect many typical faults. However, some
812 faults cannot be detected within the C-PHY and require a protocol-level solution. Therefore, the third
813 detection mechanism is a set of application specific watchdog timers.
7.1 Contention Detection

814 If a bi-directional lane module and a unidirectional module are combined in one lane, only unidirectional
815 functionality is available. Because in this case the additional functionality of one bi-directional PHY Module
816 cannot be reliably controlled from the limited functionality PHY side, the bi-directional features of the bi-
817 directional Module shall be safely disabled. Otherwise in some cases deadlock may occur which can only be
818 resolved with a system power-down and re-initialization procedure.
819 During normal operation one and only one side of a link shall drive a lane at any given time except for certain
820 transition periods. Due to errors or system malfunction a lane may end up in an undesirable state, where the
821 lane is driven from two sides or not driven at all. This condition eventually results in a state conflict and is
822 called Contention.
823 All lane modules with LP bi-directionality shall include contention detection functions to detect the following
824 contention conditions:
825 • Modules on both sides of the same line drive opposite LP levels against each other. In this case,
826 the line voltage will settle to some value between VOL,MIN and VOH,MAX. Because VIL is greater than
827 VIHCD, the settled value will always be either higher than VIHCD, lower than VIL, or both. Refer to
828 Section 9.3. This ensures that at least one side of the link, possibly both, will detect the fault
829 condition.
830 • The Module at one side drives LP-high while the other side drives HS-low on the same line. In
831 this case, the line voltage will settle to a value lower than VIL. The contention shall be detected at
832 the side that is transmitting the LP-high.
833 The first condition can be detected by the combination of LP-CD and LP-RX functions. The LP-RX function
834 should be able to detect the second contention condition. Details on the LP-CD and LP-RX electrical
835 specifications can be found in Section 9. Except when the previous state was TX-ULPS, contention shall be
836 checked before the transition to a new state. Contention detection in ULPS is not required because the bit
837 period is not defined and a clock might not be available.
838 After contention has been detected, the protocol layer shall take proper measures to resolve the situation.
7.2 Sequence Error Detection

839 If for any reason the lane signal is corrupted the receiving PHY may detect signal sequence errors. Errors
840 detected inside the PHY may be communicated to the protocol layer via the PPI. This kind of error detection
841 is optional, but strongly recommended as it enhances reliability. The following sequence errors can be
842 distinguished:
843 • SoT Error
844 • SoT Sync Error
845 • EoT Sync Error
846 • Escape Entry Command Error
847 • LP Transmission Sync Error
848 • False Control Error

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7.2.1 SoT Error

849 The Sync Word for Start of High-Speed Transmission is fault tolerant of errors in the least significant symbol,
850 as described in Section 6.4.4.1. Therefore, the Sync Word is usable to establish word boundary
851 synchronization and identification of the start of data, but confidence in the payload data is lower. If this
852 situation occurs, an SoT Error is indicated.
7.2.2 SoT Sync Error

853 If the Sync Word is corrupted in a way that proper synchronization cannot be expected, a SoT Sync Error is
854 indicated.
7.2.3 EoT Sync Error

855 The EoT Sync Error is not applicable to C-PHY. Redundant Post words follow the packet data, and an error
856 in the misalignment of data words is easily detected by the upper layer protocol.
7.2.4 Escape Mode Entry Command Error

857 If the receiving lane module does not recognize the received entry command for escape mode an escape mode
858 entry command error is indicated.
7.2.5 LP Transmission Sync Error

859 At the end of a low-power data transmission procedure, if data is not synchronized to a Byte boundary an
860 Escape Sync Error signal is indicated.
7.2.6 False Control Error

861 If a LP-Rqst (LP-100) is not followed by the remainder of a valid escape or turnaround sequence, a False
862 Control Error is indicated. This error is also indicated if a HS-Rqst (LP-001) is not correctly followed by a
863 Bridge State (LP-000).
7.3 Protocol Watchdog Timers (informative)

864 It is not possible for the PHY to detect all fault cases. Therefore, additional protocol-level time-out
865 mechanisms are necessary in order to limit the maximum duration of certain modes and states.
7.3.1 HS RX Timeout
866 In HS RX mode if no EoT is received within a certain period the protocol layer should time-out. The timeout
867 period can be protocol specific.
7.3.2 HS TX Timeout
868 The maximum transmission length in HS TX is bounded. The timeout period is protocol specific.
7.3.3 Escape Mode Timeout

869 A device may timeout during escape mode. The timeout should be greater than the escape mode Silence Limit
870 of the other device. The timeout period is protocol specific.
7.3.4 Escape Mode Silence Timeout

871 A device may have a bounded length for LP TX-000 during escape mode, after which the other device may
872 timeout. The timeout period is protocol specific. For example, a display module should have an escape mode
873 Silence Limit, after which the host processor can timeout.

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7.3.5 Turnaround Errors

874 A turnaround procedure always starts from a Stop state. The procedure begins with a sequence of Low- Power
875 States ending with a Bridge State (LP-000) during which drive sides are swapped. The procedure is finalized
876 by the response including a Turn State followed by a Stop state driven from the other side. If the actual
877 sequence of events violates the normal turnaround procedure a "False Control Error" may be flagged to the
878 protocol layer. See Section 7.2.6. The Turn State response serves as an acknowledgement for the correctly
879 completed turnaround procedure. If no acknowledgement is observed within a certain time period the
880 protocol layer should time-out and take appropriate action. This period should be larger than the maximum
881 possible turnaround time for a particular system. There is no time-out for this condition in the PHY.

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8 Interconnect and Lane Configuration

882 The interconnect between transmitter and receiver carries all signals used in C-PHY communication. This
883 includes both high-speed, low voltage signaling I/O technology and low speed, low power signaling for
884 control functions. For this reason, the physical connection should be implemented by means of point-to-point
885 transmission lines referenced to ground. The total interconnect may consist of several cascaded transmission
886 line segments, such as, printed circuit boards, flex-foils, and cable connections.
TX/RX TLIS RX/TX
887
Figure 32 Point-to-point Interconnect
8.1 Lane configuration

888 The complete physical connection of a lane consists of a transmitter (TX), and/or receiver (RX) at each side,
889 with some Transmission-Line-Interconnect-Structure (TLIS) in between. The overall lane performance is
890 therefore determined by the combination of these three elements. The split between these elements is defined
891 to be on the module (IC) pins. This section defines both the required performance of the Transmission-Line-
892 Interconnect-Structure for the signal routing as well as the I/O-cell Reflection properties of TX and RX. This
893 way the correct overall operation of the lane can be ensured.
894 With respect to physical dimensions, the Transmission-Line-Interconnect-Structure will typically be the
895 largest part. Besides printed circuit board and flex-foil traces, this may also include elements such as vias and
896 connectors.
8.2 Boundary Conditions

897 The reference characteristic impedance level is 100 Ohm differential, 50 Ohm single-ended per line, and 25
898 Ohm common-mode for any two lines together. The 50 Ohm impedance level for single-ended operation is
899 also convenient for test and characterization purposes.
900 This typical impedance level is required for all three parts of the lane: TX, TLIS, and RX. The tolerances for
901 characteristic impedances of the interconnect and the tolerance on line termination impedances for TX and
902 RX are specified by means of S-parameter templates over the whole operating frequency range.
903 The differential channel is also used for LP single-ended signaling. Therefore, it is strongly recommended to
904 apply only very loosely coupled differential transmission lines.
905 The flight time for signals across the interconnect should not exceed two nanoseconds.
8.3 Definitions
906 The frequency ‘fh’ is the highest fundamental frequency for data transmission and is equal to 1/(2*UIINST,MIN).
907 Implementers should specify a value UIINST,MIN that represents the minimum instantaneous UI possible within
908 a high-speed data transfer for a given implementation.
909 The frequency ‘fhMAX’ is a device specification and indicates the maximum supported fh for a particular
910 device.
911 The frequency ‘fLP,MAX’ is the maximum toggle frequency for low-power mode.
912 RF interference frequencies are denoted by ‘fINT’, where fINT,MIN defines the lower bound for the band of
913 relevant RF interferers. The frequency fMAX is defined by

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3 1
914 𝑓𝑓𝑀𝑀𝑀𝑀𝑀𝑀 = ∙
4 𝑈𝑈𝑈𝑈𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼,𝑀𝑀𝑀𝑀𝑀𝑀
8.4 S-parameter Specifications

915 The required performance of the physical connection is specified by means of S-parameter requirements for
916 TX, TLIS, and RX, for TLIS by mixed-mode, 4-port parameters, and for RX and TX by mixed-mode,
917 reflection (return loss) parameters. The S-parameter limits are defined over the whole operating frequency
918 range by means of templates.
919 The differential transmission properties are most relevant and therefore this specification uses mixed-mode
920 parameters. As the performance needs depend on the targeted bit rates, most S-parameter requirements are
921 specified on a normalized frequency axis with respect to bit rate. Only the parameters that are important for
922 the suppression of external (RF) interference are specified on an absolute frequency scale. This scale extends
923 up to fMAX. Beyond this frequency the circuitry itself should suppress the high-frequency interference signals
924 sufficiently.
925 Only the overall performance of the TLIS and the maximum reflection of RX and TX are specified. This
926 fully specifies the signal behavior at the RX/TX-module pins. The subdivision of losses, reflections and
927 mode-conversion budget to individual physical fractions of the TLIS is left to the system designer. Annex B
928 includes some rules of thumb for system design and signal routing guidelines.
8.5 Characterization Conditions

929 All S-parameter definitions are based on a 50 Ω impedance reference level. The characterization can be done
930 with a measurement system, as shown in Figure 33.
Z0 = 50Ω
Vc1 + Vd1/2 RX/TX
Measurement Vc1 - Vd1/2

Equipment Vc1
Z0 = 50Ω Z0 = 50Ω
Vc1 + Vd1/2 TLIS Vc1 + Vd1/2
Vc1 - Vd1/2
Vc1 - Vd1/2
Measurement Measurement
Equipment Vc1 Equipment
Vc1
931
Figure 33 Set-up for S-parameter Characterization of RX, TX and TLIS
8.6 Interconnect Specifications

932 The Transmission-Line Signal-Routing (TLSR) is specified by means of mixed-mode 4-port S-parameter
933 behavior templates over the frequency range. This includes the differential and common-mode, insertion and
934 return losses, and mode-conversion limitations.

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8.6.1 Differential Characteristics

935 The differential transfer behavior (insertion loss) of the TLIS should meet the Sdd21 and Sdd12 template
936 shown in Figure 34, where i ≠ j. This applies to all the three differential pairs AB, BC & CA.
-2.25dB+/-0.25dB
-3.15dB+/-0.25dB
Sddij -5.25dB+/-0.25dB
[dB]
0 0.75G fh 2fh
0.75G fh 2fh
937 Sddij, dB -2.25 +/-0.25dB -3.15+/-0.25dB -5.25 +/-0.25dB
Figure 34 Template for Differential Insertion Losses
938 The differential reflection for both ports of the TLIS is specified by Sdd11 and Sdd22, and should be less
939 than -12dB from 0 to 2fh. Not meeting the differential reflection coefficients might impact interoperability
940 and operation.
8.6.2 Common-mode Characteristics

941 The common-mode insertion loss is implicitly specified by means of the differential insertion loss and the
942 intra-lane cross coupling. The requirements for common-mode insertion loss are therefore equal to the
943 differential requirements.
944 The common-mode reflection coefficients Scc11 and Scc22 should both be below –12 dB at frequencies up
945 to 2fh. Not meeting the common-mode reflection coefficients might impact interoperability and operation.
8.6.3 Intra-Lane Cross-Coupling

946 The two lines applied as a differential pair during HS transmission are also used individually for single-ended
947 signaling during low-power mode. Therefore, the coupling between the two wires should be restricted in
948 order to limit single-ended cross coupling. The coupling between the two wires is defined as the difference
949 of the S-parameters Scc21 and Sdd21 or Scc12 and Sdd12. In either case, the difference should not exceed –
950 35 dB for frequencies up to 2fh.

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8.6.4 Mode-Conversion Limits

951 All mixed-mode, 4-port S-parameters for differential to common-mode conversion, and vice-versa, should
952 not exceed –29 dB for frequencies below fh. This includes Sdc12, Scd21, Scd12, Sdc21, Scd11, Sdc11,
953 Scd22, and Sdc22.
8.6.5 Inter-Lane Static Skew

954 The difference in signal delay between any two Lanes should be less than 160ps for all frequencies up to,
955 and including, fh.
8.7 Driver and Receiver Characteristics

956 Besides the TLIS the lane consists of two RX-TX modules, one at each side. This paragraph specifies the
957 reflection behavior (return loss) of these RX-TX modules in HS-mode. This applies to all the three differential
958 pairs AB, BC & CA. The signaling characteristics of all possible functional blocks inside the RX-TX modules
959 can be found in Section 9. The low-frequency impedance range for line terminations at Transmitter and
960 Receiver is 80-120Ohm.
961 The figures in this section apply to the speed ranges:
962 1. >1.5Gsps and CPAD_TX = 3pF
963 2. ≤1.5Gsps and CPAD=5pF
8.7.1 Differential Characteristics

964 The differential reflection of a lane module in high-speed RX mode should conform to the limits specified
965 by the template shown in Figure 35.
log f
0 fLP,MAX fh fMAX
0
-3 dB
-5 dB
SddRX
-18 dB
[dB]
Frequency
0 fLP,MAX fh fMAX
966 SddRX, dB -18 -18 -5 -3
Figure 35 Differential Reflection Template for Lane Module Receivers
967 The differential reflection of a lane module in high-speed TX mode should conform to the limits specified
968 by the template shown in Figure 36.

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log f
0 fLP,MAX fh fMAX
0
-3 dB
-5 dB
SddTX
-18 dB
[dB]
Frequency
fLP,MAX fh fMAX
969 SddTX, dB -18 -5 -3
Figure 36 Differential Reflection Template for Lane Module Transmitters
8.7.2 Common-Mode Characteristics

970 The common-mode return loss specification is different for a high-speed TX and RX mode, because the RX
971 is not DC terminated to ground. The common mode reflection of a lane module in high-speed TX mode
972 should be less than -3dB from fLP,MAX up to fMAX. The common mode reflection of a lane module in high-
973 speed RX mode should conform to the limits specified by the template shown in Figure 37. Assuming a high
974 DC common-mode impedance implies a sufficiently large capacitor at the termination center tap. The
975 minimum value allows integration. While the common-mode termination is especially important for reduced
976 influence of RF interferers the RX requirement limits reflection for the most relevant frequency band.
log f
0 ¼fINT,MIN fINT,MIN fMAX

0
-3 dB
SccRX
[dB] Frequency
0 ¼fINT,MIN fINT,MIN fMAX
SccRX, dB 0 0 -6 -3dB -6 dB
977
Figure 37 Template for RX Common-Mode Return Loss
8.7.3 Mode-Conversion Limits

978 The differential to common-mode conversion limits of TX and RX should be -26dB up to fMAX.

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9 Electrical Characteristics
979 A PHY may contain the following electrical functions: a high-speed Transmitter (HS-TX), a high-speed
980 Receiver (HS-RX), a low-power transmitter (LP-TX), a low-power receiver (LP-RX), and a low-power
981 contention detector (LP-CD). A PHY does not need to contain all electrical functions, only the functions that
982 are required for a particular PHY configuration. The required functions for each configuration are specified
983 in Section 5. All electrical functions included in any PHY shall meet the specifications in this section. Figure
984 38 shows the complete set of electrical functions required for a fully featured PHY transceiver.
LP-TX
A
B
TX C
HS-TX
HS-RX RT
RX
LP-RX
LP-CD
CD Line Side
985
Figure 38 Electrical Functions of a Fully Featured C-PHY Transceiver

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986 The HS transmitter and HS receiver are used for the transmission of the HS data signals. The HS transmitter
987 and receiver utilize low-voltage C-PHY signaling for signal transmission. The HS receiver contains a
988 switchable star termination.
989 The LP transmitter and LP receiver serve as a low power signaling mechanism. The LP transmitter is a push-
990 pull driver and the LP receiver is an un-terminated, single-ended receiver.
991 The signal levels are different for high-speed mode compared to single-ended low-power mode. Figure 39
992 shows both the high-speed and low-power signal levels on the left and right sides, respectively. The high-
993 speed signaling levels are below the low-power low-level input threshold such that low-power receiver
994 always detects logic low level when high-speed signals are present.
995 All absolute voltage levels are relative to the ground voltage at the transmit side.
VOH,MAX
LP VOH
LP VIH VOH,MIN
VIH
LP Threshold
Region
VIL
VOHHS
Max VOD
HS VOUT VCPTX,MAX
HS VCP LP VIL
Range
Range
VCPTX,MIN
Min VOD VGNDSH,MAX
VOLHS
LP VOL GND
996 VGNDSH,MIN
Figure 39 C-PHY Signaling Levels
997 A lane switches between low-power and high-speed mode during normal operation. Bidirectional lanes can
998 also switch communication direction. The change of operating mode or direction requires enabling and
999 disabling of certain electrical functions. These enable and disable events shall not cause glitches on the lines
1000 that would result in a detection of an incorrect signal level. Therefore, all mode and direction changes shall
1001 be smooth to always ensure a proper detection of the line signals.
9.1 Driver Characteristics
9.1.1 High-Speed Transmitter

1002 A high-speed C-PHY signal driven on the A, B and C pins is generated by a high-speed output driver. Table
1003 20 is a summary of the six possible high-speed wire states that can be driven on a C-PHY lane. Figure 40
1004 shows two example implementations of a high-speed transmitter. The “T2” Driver Type that presents a valid
1005 output impedance at the HS Mid level is the recommended implementation. At slow speeds the “T1” Driver
1006 Type may be used if the parametric requirements of Chapter 9 and Chapter 10 can be met.

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1007 Table 20 C-PHY High-Speed Wire States

State Line Voltage Levels
Code A Line B Line C Line
HS_+X HS High HS Low HS Mid
HS_-X HS Low HS High HS Mid
HS_+Y HS Mid HS High HS Low
HS_-Y HS Mid HS Low HS High
HS_+Z HS Low HS Mid HS High
HS_-Z HS High HS Mid HS Low
“T1” Driver Type “T2” Driver Type

+V PU_TA +V +V
50Ω
“A” PU_A 50Ω 100Ω
50Ω PD_A “A”
PU_A 50Ω 100Ω
PD_TA
PD_A +V
Transmit PU_B 50Ω PU_TB +V +V
Pre-Drivers
PD_B “B”
& Control Transmit PU_B
50Ω 50Ω 100Ω
Pre-Drivers
Circuitry PU_C PD_B “B”
& Control
50Ω 100Ω
PD_C +V
Circuitry PD_TB
50Ω
“C” PU_TC +V +V
50Ω
PU_C 50Ω 100Ω
PD_C “C”
50Ω 100Ω
PD_TC
1008
Figure 40 Example High-Speed Transmitter
1009 The single-ended output voltages are defined VA, VB and VC at the A, B and C pins, respectively. The
1010 differential output voltages VOD_AB, VOD_BC and VOD_CA are defined as the difference of the voltages: VA
1011 minus VB, VB minus VC, and VC minus VA, respectively.
1012 𝑉𝑉𝑂𝑂𝑂𝑂_𝐴𝐴𝐴𝐴 = 𝑉𝑉𝐴𝐴 − 𝑉𝑉𝐵𝐵 ; 𝑉𝑉𝑂𝑂𝑂𝑂_𝐵𝐵𝐵𝐵 = 𝑉𝑉𝐵𝐵 − 𝑉𝑉𝐶𝐶 ; 𝑉𝑉𝑂𝑂𝑂𝑂_𝐶𝐶𝐶𝐶 = 𝑉𝑉𝐶𝐶 − 𝑉𝑉𝐴𝐴 ;
1013 The output voltages VA, VB and VC at the A, B and C pins shall not exceed the high-speed output high voltage
1014 VOHHS. VOLHS is the high-speed output, low voltage on A, B and C, and is determined by VOD_AB, VOD_BC,
1015 VOD_CA and VCPTX. The high-speed VOUT is bounded by the minimum value of VOLHS and the maximum value
1016 of VOHHS.
1017 The common-point voltage VCPTX is defined as the arithmetic mean value of the voltages at the A, B and C
1018 pins:
𝑉𝑉𝐴𝐴 + 𝑉𝑉𝐵𝐵 + 𝑉𝑉𝐶𝐶

1019 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 =
3

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1020 VOD_AB, VOD_BC and VOD_CA and VCPTX are shown graphically in Figure 41 for ideal high-speed signals. Figure
1021 42 shows single-ended high-speed signals with the possible kinds of distortion of the differential output and
1022 common-point voltages. The strong one and zero levels of VOD_AB, VOD_BC and VOD_CA, and VCPTX may be
1023 slightly different for driving any of the six possible wire states on the lane. The strong one and strong zero
1024 states for a given wire pair occur only in certain states, and it is the strong levels that are considered to
1025 determine ∆VOD. Table 21 shows which high-speed states produce the strong levels for each wire pair.
1026 Table 21 Strong Zero and Strong One State for Each Wire Pair
Wire Pair Strong Zero Strong One State Weak Zero Weak One States
State States
AB HS_-X HS_+X HS_+Y, HS_+Z HS_-Y, HS_-Z
BC HS_-Y HS_+Y HS_+X, HS_+Z HS_-X, HS_-Z
CA HS_-Z HS_+Z HS_+X, HS_+Y HS_-X, HS_-Y
1027 The output differential voltage mismatch, ∆VOD, is defined as the difference of the maximum and minimum
1028 of: the absolute values of the differential strong one and strong zero output voltages of the three possible wire
1029 pairs. This is expressed by the following equations that consider the VOD for a particular wire pair in a specific
1030 state as described in Table 21:
1031 𝑉𝑉𝑂𝑂𝑂𝑂_𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑚𝑚𝑚𝑚𝑚𝑚�𝑉𝑉𝑂𝑂𝑂𝑂_𝐴𝐴𝐴𝐴_+𝑋𝑋 , �𝑉𝑉𝑂𝑂𝑂𝑂_𝐴𝐴𝐴𝐴_−𝑋𝑋 �, 𝑉𝑉𝑂𝑂𝑂𝑂_𝐵𝐵𝐵𝐵_+𝑌𝑌 , �𝑉𝑉𝑂𝑂𝑂𝑂_𝐵𝐵𝐵𝐵_−𝑌𝑌 �, 𝑉𝑉𝑂𝑂𝑂𝑂_𝐶𝐶𝐶𝐶_+𝑍𝑍 , �𝑉𝑉𝑂𝑂𝑂𝑂_𝐶𝐶𝐶𝐶_−𝑍𝑍 ��
1032 𝑉𝑉𝑂𝑂𝑂𝑂_𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑚𝑚𝑚𝑚𝑚𝑚�𝑉𝑉𝑂𝑂𝑂𝑂_𝐴𝐴𝐴𝐴_+𝑋𝑋 , �𝑉𝑉𝑂𝑂𝑂𝑂_𝐴𝐴𝐴𝐴_−𝑋𝑋 �, 𝑉𝑉𝑂𝑂𝑂𝑂_𝐵𝐵𝐵𝐵_+𝑌𝑌 , �𝑉𝑉𝑂𝑂𝑂𝑂_𝐵𝐵𝐵𝐵_−𝑌𝑌 �, 𝑉𝑉𝑂𝑂𝑂𝑂_𝐶𝐶𝐶𝐶_+𝑍𝑍 , �𝑉𝑉𝑂𝑂𝑂𝑂_𝐶𝐶𝐶𝐶_−𝑍𝑍 ��
1033 ∆𝑉𝑉𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂_𝑀𝑀𝑀𝑀𝑀𝑀 − 𝑉𝑉𝑂𝑂𝑂𝑂_𝑀𝑀𝑀𝑀𝑀𝑀
1034 If VCPTX(HS_+X), VCPTX(HS_-X), VCPTX(HS_+Y), VCPTX(HS_-Y), VCPTX(HS_+Z), and VCPTX(HS_-Z) are the common-point
1035 voltages for static HS_+X, HS_-X, HS_+Y, HS_-Y, HS_+Z and HS_-Z states, respectively, then the common-
1036 point reference voltage is defined as:
1037 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉,𝑅𝑅𝑅𝑅𝑅𝑅 =
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉(𝐻𝐻𝐻𝐻_+𝑋𝑋) + 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉(𝐻𝐻𝐻𝐻_−𝑋𝑋) + 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉(𝐻𝐻𝐻𝐻_+𝑌𝑌) + 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉(𝐻𝐻𝐻𝐻_−𝑌𝑌) + 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉(𝐻𝐻𝐻𝐻_+𝑍𝑍) + 𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉(𝐻𝐻𝐻𝐻_−𝑍𝑍)

1038
6
1039 The transient common-point voltage variation is defined by:
1040 ∆𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 (𝑡𝑡) = 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 (𝑡𝑡) − 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶,𝑅𝑅𝑅𝑅𝑅𝑅
1041 The static common-point voltage mismatch between the six high-speed states is defined as:
1042 𝑉𝑉𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑚𝑚𝑚𝑚𝑚𝑚�𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_+𝑋𝑋) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_−𝑋𝑋) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_+𝑌𝑌) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_−𝑌𝑌) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_+𝑍𝑍) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_−𝑍𝑍) �
1043 𝑉𝑉𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑚𝑚𝑚𝑚𝑚𝑚�𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_+𝑋𝑋) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_−𝑋𝑋) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_+𝑌𝑌) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_−𝑌𝑌) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_+𝑍𝑍) , 𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻_−𝑍𝑍) �

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𝑉𝑉𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀 − 𝑉𝑉𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀𝑀
1044 ∆𝑉𝑉𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶(𝐻𝐻𝐻𝐻) =
2
1045 The transmitter shall send data such that the high frequency and low frequency common-point voltage
1046 variations do not exceed ΔVCPTX(HF) and ΔVCPTX(LF), respectively. An example test circuit for the measurement
1047 of VOD and VCPTX is shown in Figure 43.
+x -y -z +z +y -x
V
VOHHS A
V
VCPTX C
VB
VOLHS
Strong 1
VA - V B Weak 1
zero
VB - V C crossing
VC - V A Weak 0
Strong 0
1048
Figure 41 Ideal Single-ended and Resulting Differential High Speed Signals
Large VA Amplitude (single-ended high-speed signals)

VA +x -y -z ∆VOD +z +y -x
VOHHS
VC
VCPTX
VOLHS
VB VOD_AB_+X VOD_BC_-Y VOD_CA_-Z VOD_CA_+Z VOD_BC_+Y VOD_AB_-X
Fixed Offset VA (single-ended high-speed signals)

VA ∆VOD/2 ∆VOD/2
VOHHS
VC
VCPTX
VOLHS
VB VOD_AB_+X VOD_BC_-Y VOD_CA_-Z VOD_CA_+Z VOD_BC_+Y VOD_AB_-X
∆VOD/2
Slow Rise/Fall VA (single-ended high-speed signals)
VOHHS
VA
V
VCPTX C
V
VB
OLHS
1049
Figure 42 Possible VCPTX and ΔVOD Distortions of the Single-ended HS Signals

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A RL
TX
VOD
_AB
B RL
VOD
_BC
C RL
2pF 2pF 2pF VOD 22pF

VCPTX
_CA
1050
Figure 43 Example Circuit for VOD and VCPTX Measurements
1051 The single-ended output impedance of the transmitter at the A, B and C pins is denoted by ZOS. ΔZOS is the
1052 mismatch of the single ended output impedances at the A, B and C pins, denoted by ZOS_A, ZOS_B and ZOS_C,
1053 respectively. This mismatch is defined as the ratio of the difference between the largest and smallest value of
1054 ZOS_A, ZOS_B and ZOS_C and the average of those impedances:
𝑚𝑚𝑚𝑚𝑚𝑚�𝑍𝑍𝑂𝑂𝑂𝑂_𝐴𝐴 , 𝑍𝑍𝑂𝑂𝑂𝑂_𝐵𝐵 , 𝑍𝑍𝑂𝑂𝑂𝑂_𝐶𝐶 � − 𝑚𝑚𝑚𝑚𝑚𝑚�𝑍𝑍𝑂𝑂𝑂𝑂_𝐴𝐴 , 𝑍𝑍𝑂𝑂𝑂𝑂_𝐵𝐵 , 𝑍𝑍𝑂𝑂𝑂𝑂_𝐶𝐶 �

1055 ∆𝑍𝑍𝑂𝑂𝑂𝑂 = 3 ∙
𝑍𝑍𝑂𝑂𝑂𝑂_𝐴𝐴 + 𝑍𝑍𝑂𝑂𝑆𝑆_𝐵𝐵 + 𝑍𝑍𝑂𝑂𝑂𝑂_𝐶𝐶
1056 The output impedance ZOS and the output impedance mismatch ΔZOS shall be compliant with Table 22 for all
1057 six possible high-speed wire states and for all allowed loading conditions. It is recommended that
1058 implementations keep the output impedance during state transitions as close as possible to the steady state
1059 value. The output impedance ZOS can be determined by injecting an AC current into the A, B and C pins and
1060 measuring the peak-to-peak voltage amplitude.
1061 The driver shall meet the tR and tF specifications as specified in Table 23. The specifications for TX common-
1062 mode return loss and the TX differential mode return loss can be found in Section 8.
1063 It is recommended that a high-speed transmitter that is directly terminated at its pins should not generate any
1064 overshoot in order to minimize EMI.
1065 Table 22 HS Transmitter DC Specifications

Parameter Description Min Nom Max Units Notes
VCPTX HS transmit static common-point voltage 175 225 to 310 mV 1, 3
250
|∆VCPTX(HS)| VCPTX mismatch when output is in any of the 9 mV 2
six high-speed states
|VOD| HS transmit differential voltage of the 300 mV 1
strong differential strong one and strong zero
specified in Table 21.

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|VOD| HS transmit differential voltage of the 97 mV 1

weak differential weak one and weak zero specified
in Table 21.
|∆VOD| VOD mismatch between the absolute values of 17 mV 2
the differential strong one and strong zero
output voltages in any of the six possible high-
speed states.
VOHHS HS output high voltage 425 mV 1
ZOS Single ended output impedance 40 50 60 Ω
∆ZOS Single ended output impedance mismatch 10 %
Note:
1. Value when driving into load impedance, ZID, equal to 100 ohms.
2. A transmitter should minimize ΔVOD and ΔVCPTX(HS) in order to minimize radiation, and optimize
signal integrity
3. Typical value of VCPTX should be in the specified range depending upon the supply voltage used for
each implementation.
1066 Table 23 HS Transmitter AC Specifications

∆VCPTX(HF) Common-level variations above 450 15 mVRMS
MHz
∆VCPTX(LF) Common-level variation between 50 25 mVPEAK
MHz and 450 MHz
0.285 UI 1, 2, 3, 5,
Rise time and fall time from -58 mV to 6
tR and tF
+58 mV 0.4 UI 1, 3, 4, 5,
(Note 4) 6
tRISE-FALL-MAX Rise time and fall time limit from -58 mV
360 ps ps 4, 5
to +58 mV
Note:
1. UI is equal to 1/(2*fh). Refer to Section 8.3 for the definition of fh.
2. Applicable for all HS symbol rates > 1.5 Gsps
3. To avoid excessive radiation, devices operating at symbol rates ≤ 1.5 Gsps should not use values
below 100 ps.
4. The maximum absolute time limit of rise and fall times, tRISE-FALL-MAX, establishes an upper time limit
that is not UI-based. This upper bound that constrains the rise and fall time is useful for
implementation of the clock recovery circuit. For rates ≤ 1.5Gsps the rise and fall time shall be ≤
min(0.4  UI, tRISE-FALL-MAX).
5. Value when driving into load impedance, ZID, equal to 100 ohms.
6. The rise time measurement applies only to the strong zero to weak one transition, and the fall time
measurement applies only to the strong one to weak zero transition.
9.1.2 Low-Power Transmitter

1067 The low-power transmitter shall be a slew-rate controlled push-pull driver. It is used for driving the lines in
1068 all low-power operating modes It is therefore important that the static power consumption of a LP transmitter
1069 be as low as possible. The slew-rate of signal transitions is bounded in order to keep EMI low. An example
1070 of a LP transmitter is shown in Figure 44.

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1.2V
Pre-driver
1071
Figure 44 Example LP Transmitter
1072 VOL is the Thevenin output, low-level voltage in the LP transmit mode. This is the voltage at an unloaded pad
1073 pin in the low-level state. VOH is the Thevenin output, high-level voltage in the high-level state, when the pad
1074 pin is not loaded. The LP transmitter shall not drive the pad pin potential statically beyond the maximum
1075 value of VOH. The pull-up and pull-down output impedances of LP transmitters shall be as described in Figure
1076 45 and Figure 46, respectively. The circuit for measuring VOL and VOH is shown in Figure 47.
I
VDD
110 ohm
~110 ohm
VDD – V2
110 ohm
V2 = 850mV V
1077
Figure 45 V-I Characteristic for LP Transmitter Driving Logic High

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350mV V
-3.2mA
~110 ohm
-11.8mA
-I
1078
Figure 46 V-I Characteristic for LP Transmitter Driving Logic Low
force input
“0” or “1” I
sweep
= V = output
voltage
1079
Figure 47 LP Transmitter V-I Characteristic Measurement Setup
1080 The impedance ZOLP is defined by:
𝑉𝑉𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 − 𝑉𝑉𝑃𝑃𝑃𝑃𝑃𝑃
1081 𝑍𝑍𝑂𝑂𝑂𝑂𝑂𝑂 = � �
𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂
1082 The times tRLP and tFLP are the 15%-85% rise and fall times, respectively, of the output signal voltage, when
1083 the LP transmitter is driving a capacitive load CLOAD. The 15%-85% levels are relative to the fully settled
1084 VOH and VOL voltages. The slew rate δV/δtSR is the derivative of the LP transmitter output signal voltage over
1085 time. The LP transmitter output signal transitions shall meet the maximum and minimum slew rate
1086 specifications as shown in Table 25, Figure 48 and Figure 49. The intention of specifying a maximum slew
1087 rate value is to limit EMI.
1088 Table 24 LP Transmitter DC Specifications

VOH Thevenin output high level 0.95 1.3 V

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VOL Thevenin output low level -50 50 mV

ZOLP Output impedance of LP transmitter 110 Ω 1, 2
Note:
1. See Figure 45 and Figure 46.
2. Though no maximum value for ZOLP is specified, the LP transmitter output impedance shall ensure the tRLP/tFLP
specification is met.
1089 Table 25 LP Transmitter AC Specifications

tRLP/tFLP 15% - 85% rise time and fall time 25 ns 1
tREOT 30% - 85% rise time and fall time 35 ns 5, 6
tLP-PULSE-TX Pulse width First LP 40 4
of the LP exclusive-OR
exclusive- clock pulse after
OR clock Stop state or last
pulse before stop
state
All other pulses 20 4
tLP-PER-TX Period of the LP exclusive-OR 90 ns
clock
δV/δtSR Slew rate @ CLOAD = 0pF 500 mV/ns 1, 3,
7, 8
Slew rate @ CLOAD = 5pF 300 mV/ns 1, 3,
7, 8
7, 8
7, 8
Slew rate @ CLOAD = 0 to 70pF 25 mV/ns 1, 2, 3
(Falling Edge Only)
Slew rate @ CLOAD = 0 to 70pF 25 mV/ns 1, 3,
(Rising Edge Only) 9
Slew rate @ CLOAD = 0 to 70pF 25 – mV/ns 1, 3,
(Rising Edge Only) 0.0625(VO,INST – 10, 11
550)
CLOAD Load capacitance 0 70 pF 1
Note:
1. CLOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX
and RX are assumed to always be <10pF. The distributed line capacitance can be up to 50pF for a
transmission line with 2ns delay.
2. When the output voltage is between 400 mV and 790 mV.
3. Measured as average across any 50 mV segment of the output signal transition.
4. This parameter value can be lower than tLPX due to differences in rise vs. fall signal slopes and trip
levels and mismatches between A, B and C LP transmitters. Any LP exclusive-OR pulse observed
during HS EoT (transition from HS level to LP-111) is glitch behavior as described in Section 9.2.2.
5. The rise-time of tREOT starts from the HS common-level at the moment the differential amplitude
drops below 70mV, due to stopping the differential drive.
6. With an additional load capacitance CCP between 0 and 90 pF on the termination center tap at RX
side of the lane
7. This value represents a corner point in a piecewise linear curve. See Figure 48 and Figure 49.
8. When the output voltage is in the range specified by VPIN(absmax).

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10. Where VO,INST is the instantaneous output voltage, A, B or C, in millivolts.
1090 There are minimum requirements on the duration of each LP state. To determine the duration of the LP state,
1091 the A, B and C signal lines are each compared to a common trip-level. The result of these comparisons of the
1092 A and C signals lines is then exclusive-ORed to produce a single pulse train. The output of this “exclusive-
1093 OR clock” can then be used to find the minimum pulse width output of an LP transmitter.
1094 Using a common trip-level in the range [VIL,MAX + VOL,MIN, VIH,MIN + VOL,MAX], the exclusive-OR clock shall
1095 not contain pulses shorter than tLP-PULSE-TX.
500
CLOAD, pF
0 5 20 70
400
δV/δtSR,MIN, mV/ns
δV/δtSR, mV/ns
25 25 25 25
δV/δtSR,MAX, mV/ns 500 300 250 150
300
200
Valid Slew Rate Range

100
0
0 10 20 30 40 50 60 70
1096
CLOAD, pF
Figure 48 Slew Rate vs. CLOAD (Falling Edge)
CLOAD, pF
500
0 5 20 70
δV/δtSR,MIN, mV/ns
(400 mV to 550 mV)
25 25 25 25
400 δV/δtSR,MIN, mV/ns
δV/δtSR, mV/ns
(550 mV to 790 mV)

See Table 19
δV/δtSR,MAX, mV/ns 500 300 250 150
300
200
Valid Slew Rate Range

100
0
0 10 20 30 40 50 60 70
1097 CLOAD, pF
Figure 49 Slew Rate vs. CLOAD (Rising Edge)

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9.2 Receiver Characteristics
9.2.1 High-Speed Receiver

1098 The HS receiver is a group of three differential line receivers. It contains three switchable parallel input
1099 terminations, ZID/2 between the three inputs: A, B and C. A simplified diagram of an example implementation
1100 is shown in Figure 50.
Rx Common Point
A +
Rx_AB
ZID/2
-
B +
Rx_BC
ZID/2
-
C +
Rx_CA
ZID/2
-
Termination
Enable CCP
1101
Figure 50 HS Receiver Implementation Example
1102 The differential input high and low threshold voltages of the high-speed receiver are denoted by VIDTH and
1103 VIDTL, respectively. VILHS and VIHHS are the single-ended, input low and input high voltages, respectively.
1104 VCPRX(DC) is the differential input common-point voltage. The high-speed receiver shall be able to detect
1105 differential signals at its A, B and C input signal pins when all three signal voltages, VA, VB and VC, are
1106 within the common-point voltage range and if the voltage differences between VA, VB and VC exceed either
1107 VIDTH or VIDTL. The high-speed receiver shall receive high-speed data correctly while rejecting common-
1108 point interference ΔVCPRX(HF) and ΔVCPRX(LF).
1109 During operation of the high-speed receiver, the three termination impedances ZID/2 are required between the
1110 A, B and C pins of the high-speed receiver. The three ZID/2 terminations shall be disabled when the module
1111 is not in the high-speed receive mode. When transitioning from low-power mode to high-speed receive mode
1112 the termination impedances shall not be enabled until the single-ended input voltages on all of A, B and C
1113 fall below VTERM-EN. To meet this requirement, a receiver does not need to sense the A, B and C lines to
1114 determine when to enable the line termination, rather the LP to HS transition timing can allow the line
1115 voltages to fall to the appropriate level before the line termination is enabled.
1116 The differential input impedances of the receiver for A-B, B-C and C-A pairs are denoted by ZID_AB, ZID_BC,
1117 and ZID_CA, respectively. ΔZID is the mismatch of the differential input impedances. This mismatch is defined
1118 as the ratio of the difference between the largest and smallest value of ZID_AB, ZID_BC and ZID_CA, and the
1119 average of those impedances:
𝑚𝑚𝑚𝑚𝑚𝑚�𝑍𝑍𝐼𝐼𝐼𝐼_𝐴𝐴𝐴𝐴 , 𝑍𝑍𝐼𝐼𝐼𝐼_𝐵𝐵𝐵𝐵 , 𝑍𝑍𝐼𝐼𝐼𝐼_𝐶𝐶𝐶𝐶 � − 𝑚𝑚𝑚𝑚𝑚𝑚�𝑍𝑍𝐼𝐼𝐼𝐼_𝐴𝐴𝐴𝐴 , 𝑍𝑍𝐼𝐼𝐼𝐼_𝐵𝐵𝐵𝐵 , 𝑍𝑍𝐼𝐼𝐼𝐼_𝐶𝐶𝐶𝐶 �

1120 ∆𝑍𝑍𝐼𝐼𝐼𝐼 = 3 ∙
𝑍𝑍𝐼𝐼𝐼𝐼_𝐴𝐴𝐴𝐴 + 𝑍𝑍𝐼𝐼𝐼𝐼_𝐵𝐵𝐵𝐵 + 𝑍𝑍𝐼𝐼𝐼𝐼_𝐶𝐶𝐶𝐶
1121 The differential input impedances ZID and the differential input impedance mismatch ΔZID shall be compliant
1122 with Table 26 for all six possible high-speed wire states and for all allowed loading conditions. It is

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1123 recommended that implementations keep the input impedance during state transitions as close as possible to
1124 the steady state value.
1125 The RX common-mode return loss and the RX differential mode return loss are specified in Chapter 8. CCP
1126 is the common-mode AC termination, which ensures a proper termination of the receiver at higher
1127 frequencies. For higher data rates, CCP is needed at the termination center tap in order to meet the common-
1128 mode reflection requirements.
1129 The differential input voltage signal VDIF_RX(t) is defined as the voltage difference of the receiver inputs for
1130 the A-B, B-C and C-A pairs, defined as:
1131 VDIF_RX_AB(t) = VA(t) - VB(t); VDIF_RX_BC(t) = VB(t) - VC(t); VDIF_RX_CA(t) = VC(t) - VA(t);
1132 VDIF_RX,MAX = VIHHS,MAX - VILHS,MIN
1133 Table 26 HS Receiver DC Specifications

VCPRX(DC) Common-Point voltage HS receive mode 95 390 mV 1, 2
VIDTH Differential input high threshold 40 mV
VIDTL Differential input low threshold -40 mV
VIHHS Single-ended input high voltage 535 mV 1
VILHS Single-ended input low voltage -40 mV 1
VTERM-EN Single-ended threshold for HS termination 450 mV
enable
ZID_AB Differential input impedance 80 100 120 Ω
ZID_BC
ZID_CA
∆ZID Differential input impedance mismatch 10 %
Note:
1. Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz.
2. This table value includes a ground difference of 50mV between the transmitter and the receiver,
the static common-point level tolerance and variations below 450MHz.
1134 Table 27 HS Receiver AC Specifications

∆VCPRX(HF) Common-point interference 50 mV 2
beyond 450 MHz
∆VCPRX(LF) Common-point interference -25 25 mV 1, 4
50MHz – 450MHz
CCP Common-point termination 90 pF 3
Note:
1. Excluding ‘static’ ground shift of 50mV.
2. ΔVCPRX(HF) is the peak amplitude of a sine wave superimposed on the receiver inputs.
3. For higher bit rates, a 22pF capacitor is needed to meet the common-mode return loss specification.
4. Voltage difference compared to the DC average common-point potential.

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9.2.2 Low-Power Receiver

1135 The low-power receiver is an un-terminated, single-ended receiver circuit. The low-power receiver is used
1136 to detect the low-power state on each pin. For high robustness, the LP receiver shall filter out noise pulses
1137 and RF interference. It is recommended the implementer optimize the LP receiver design for low power.
1138 The input low-level voltage, VIL, is the voltage at which the receiver is required to detect a low state in the
1139 input signal. A lower input voltage, VIL-ULPS, may be used when the receiver is in the Ultra-Low Power State.
1140 VIL is larger than the maximum single-ended line voltage during HS transmission. Therefore, a LP receiver
1141 shall detect low during HS signaling.
1142 The input high-level voltage, VIH, is the voltage at which the receiver is required to detect a high state in the
1143 input signal. In order to reduce noise sensitivity on the received signal, an LP receiver shall incorporate a
1144 hysteresis, The hysteresis voltage is defined as VHYST.
1145 The LP receiver shall reject any input signal smaller than eSPIKE. Signal pulses wider than TMIN-RX shall
1146 propagate through the LP receiver.
1147 Furthermore, the LP receivers shall be tolerant of super-positioned RF interference on top of the wanted line
1148 signals. This implies an input signal filter. The LP receiver shall meet all specifications for interference with
1149 peak amplitude VINT and frequency fINT. The interference shall not cause glitches or incorrect operation
1150 during signal transitions.
2*tLPX 2*tLPX
eSPIKE
VIH
Input
VIL
eSPIKE
tMIN-RX tMIN-RX
Output
1151
Figure 51 Input Glitch Rejection of Low-Power Receivers
1152 Table 28 LP Receiver DC specifications

VIH Logic 1 input voltage 740 mV
VIL Logic 0 input voltage, not in ULP State 550 mV
VIL-ULPS Logic 0 input voltage, ULP State 300 mV
VHYST Input hysteresis 25 mV
1153 Table 29 LP Receiver AC Specifications

eSPIKE Input pulse rejection 300 Vps 1, 2, 3
TMIN-RX Minimum pulse width response 20 ns 4
VINT Peak interference amplitude 200 mV
fINT Interference frequency 450 MHz
Note:
1. Time-voltage integration of a spike above VIL when being in LP-0 state or below VIH when being in
LP-1 state. eSpike generation will ensure the spike is crossing both VIL,MAX and VIH,MIN levels.

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2. An impulse less than this will not change the receiver state.
3. In addition to the required glitch rejection, implementers shall ensure rejection of known RF-
interferers.
4. An input pulse greater than this shall toggle the output.
9.3 Line Contention Detection

1154 The low-power receiver and a separate contention detector (LP-CD) shall be used in a bi-directional lane to
1155 monitor the line voltage on each low-power signal. This is required to detect line contention as described in
1156 Section 7.1. The low-power receiver shall be used to detect an LP high fault when the LP transmitter is driving
1157 high and the pin voltage is less than VIL. Refer to Table 28. The LP-CD shall be used to detect an LP low
1158 fault when the LP transmitter is driving low and the pin voltage is greater than VIHCD. Refer to Table 30. An
1159 LP low fault shall not be detected when the pin voltage is less than VILCD.
1160 The general operation of a contention detector shall be similar to that of an LP receiver with lower threshold
1161 voltages. Although the DC specifications differ, the AC specifications of the LP-CD are defined to match
1162 those of the LP receiver and the LP-CD shall meet the specifications listed in Table 29 except for TMIN-RX.
1163 The LP-CD shall sufficiently filter the input signal to avoid false triggering on short events.
1164 The LP-CD threshold voltages (VILCD, VIHCD) are shown along with the normal signaling voltages in Figure
1165 52.
VOH,MAX VOH,MAX
LP-TX
Output High LP-RX
VOH,MIN
Input High
VIH,MIN VIH,MIN
LP-CD
Input High LP-RX
Threshold
Region
VIL,MAX VIL,MAX
VIHHS
VIHCD,MIN
LP-CD HS-RX
LP-RX VCPRXDC,MAX
Threshold HS-RX Common
Region Input Low
Input Mode
VILCD,MAX
LP-CD Range Input
Range VCPRXDC,MIN
VOL,MAX Input Low
LP-TX
GND GND
Output Low VILHS
VOL,MIN
Low Power Low Power Low Power High Speed Receiver

1166 Transmitter Contention Detector Receiver
Figure 52 Signaling and Contention Voltage Levels
1167 Table 30 Contention Detector (LP-CD) DC Specifications

VIHCD Logic 1 contention threshold 450 mV
VILCD Logic 0 contention threshold 200 mV
9.4 Input Characteristics

1168 No structure within the PHY may be damaged when a DC signal that is within the signal voltage range VPIN
1169 is applied to a pad pin for an indefinite period of time. VPIN(absmax) is the maximum transient output voltage at
1170 the transmitter pin. The voltage on the transmitter’s output pin shall not exceed VPIN,MAX for a period greater
1171 than TVPIN(absmax). When the PHY is in the low-power receive mode the pad pin leakage current shall be ILEAK
1172 when the pad signal voltage is within the signal voltage range of VPIN. The specification of ILEAK assures

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1173 interoperability of any PHY in the LP mode by restricting the maximum load current of an LP transmitter.
1174 An example test circuit for leakage current measurement is shown in Figure 53.
1175 The ground supply voltages shifts between a master and a slave shall be less than VGNDSH.
A
Disable
B
LP_Rx_A C-PHY
LP_Rx_B C
LP_Rx_C
ILEAK ILEAK ILEAK
VA VB VC
1176
Figure 53 Pin Leakage Measurement Example Circuit
1177 Table 31 Pin Characteristic Specifications

VPIN Pin signal voltage range -50 1350 mV
ILEAK Pin leakage current -10 10 µA 1
VGNDSH Ground shift -50 50 mV
VPIN(absmax) Transient pin voltage level -0.15 1.45 V 3
tVPIN(absmax) Maximum transient time above VPIN(max) or 20 ns 2
below VPIN(min)
Note:
1. When the pad voltage is in the signal voltage range from VGNDSH,MIN to VOH + VGNDSH,MAX and the
lane module is in LP receive mode.
2. The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20ns window
after any LP-0 to LP-1 transition or vice versa. For all other situations it must stay within the VPIN
range.
3. This value includes ground shift.

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10 High-Speed Signal Timing

1178 This section specifies the required timing of the High-speed signaling interface independent of the electrical
1179 characteristics of the signal. C-PHY is based on 3-Phase symbol encoding technology where the symbol
1180 timing information is encoded in the data sent in each lane. There is at least one transition in the received
1181 signal at each UI boundary.
1182 Data transmission may occur at any rate greater than the minimum specified data bit rate.
1183 Figure 54 shows an example PHY configuration including the compliance measurement planes for the
1184 specified timing requirements. Note that the effect of signal degradation inside each package due to parasitic
1185 effects is included in the timing budget for the transmitter and receiver and is not included in the interconnect
1186 degradation budget. See Section 8 for details.
Symbols Received
Decoder Symbols
Encoder Interconnect
Reference & Clock
Recovered
Clock Recovery
Clock
Driver
Receiver
Master IC Slave IC
Transmit Timing Compliance Receive Timing Compliance

Measurement Plane = Transmitter IC Pins Measurement Plane = Receiver IC Pins
1187
Figure 54 Conceptual C-PHY Lane Timing Compliance Measurement Planes
10.1 High-Speed UI Timing

1188 The master sends high-speed data timing to the slave by encoding the symbol clock timing in the transmitted
1189 symbol stream. Symbol encoding to wire states ensures that a transition occurs in the high-speed data at every
1190 symbol boundary. The slave recovers the clock for data sampling using these guaranteed transitions in the
1191 symbol stream. An example of the single-ended VA, VB, and VC voltages that change at every UI interval, as
1192 well as the differential received voltages VA-VB, VB-VC, and VC-VA, is shown in Figure 55.
+x +z +y +z -z +x -z
VA ¾V
VB ½V
VC ¼V
UIINST UIINST UIINST UIINST UIINST
Strong 1
VA - VB Weak 1
zero
VB - V C crossing
VC - V A Weak 0
Strong 0
1193
Figure 55 Example of Wire State Transitions at Symbol (UI) Boundaries
1194 Slave circuitry that recovers clock and samples data should respond immediately to transitions in the received
1195 data stream. Therefore, implementations may use frequency spreading modulation on the clock to reduce
1196 EMI.

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1197 Table 32 Unit Interval (UI) Specification

UIINST UI instantaneous 12.5 ns 1, 2
-10% 10% UI 3
∆UI UI variation
-5% 5% UI 4
Note:
1. This value corresponds to a minimum 80 Msps data rate.
2. The minimum UI shall not be violated for any single bit period. The allowed instantaneous UI
variation can cause instantaneous data rate variations. Therefore, slave devices should be able to
accommodate these instantaneous variations of the UI interval .
3. When UI ≥ 1ns, within a single burst.
4. When UI < 1ns, within a single burst.
1198 The allowed instantaneous UI variation can cause large, instantaneous data rate variations. Therefore, it is
1199 recommended that devices accommodate these instantaneous variations using some method, such as with
1200 elastic storage or by designing the data sink to be tolerant of UI variations.
10.2 High-Speed Data Eye Pattern and Transmission Timing

1201 An eye pattern is a useful tool to specify the C-PHY timing characteristics. The C-PHY eye pattern described
1202 below is slightly different than a conventional eye pattern. Differences compared to conventional eye patterns
1203 are due to multiple levels seen at the receiving end, and due to specific behaviors of the clock recovery and
1204 data capture circuits that are likely to be implemented.
1205 One or more of the differential receiver outputs in the slave will change at each UI boundary due to the
1206 symbol encoding rules. When multiple receiver outputs change they are often staggered in time due to slight
1207 differences in rise and fall times between the three signals of the lane and due to slight differences in signal
1208 propagation times between the combinations of signal pairs received (e.g. A-B, B-C, and C-A). This concept
1209 is illustrated in detail in Figure 56, which shows the five types of transitions that can appear in the eye pattern.
1210 Figure 56 illustrates the concept that transitions of all three pair combinations can occur at slightly different
1211 times near each UI boundary due to the noted characteristics of the C-PHY drivers and receivers; and that
1212 there can be one, two or three zero-crossings at each UI boundary. Time t∆J in Figure 56, highlights the time
1213 difference of the zero-crossings between the first and last signal pair transition.

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Strong 1
¾V A +V/2
+x to -x
+
A ½¼ VV −
Rx_AB
+V/4
AB
BC, CA Weak 1
1→0
¾V B + VRx_AB from +V/2 to -V/2, ∆ = -V Triple
B ½¼ VV −
Rx_BC 0
VRx_BC from -V/4 to +V/4, ∆ = +½V Transition
0→1 Weak 0
¾V -V/4
C + TRIGGER VRx_CA from -V/4 to +V/4, ∆ = +½V
C ½¼ VV −
Rx_CA -V/2 Strong 0
+x -x 0→1 t∆J
Strong 1
¾V A +V/2
+x to +y
+ AB BC
A ½¼ VV −
Rx_AB
+V/4 Weak 1
1→0
¾V B + VRx_AB from +V/2 to -V/4, ∆ = -¾V Double
B ½¼ VV −
Rx_BC 0
VRx_BC from -V/4 to +V/2, ∆ = +¾V Transition
0→1 CA Weak 0
¾V -V/4
C + TRIGGER VRx_CA from -V/4 to -V/4, ∆ = 0
C ½¼ VV −
Rx_CA -V/2 Strong 0
+x +y 0→0 t∆J
Strong 1
¾V A +V/2
+x to -y
+ AB
A ½¼ VV −
Rx_AB
+V/4 Weak 1
1→1
¾V CA VRx_AB from +V/2 to +V/4, ∆ = -¼V Single
B +
B ½¼ VV −
Rx_BC 0
TRIGGER VRx_BC from -V/4 to -V/2, ∆ = -¼V Transition
0→0 Weak 0
¾V -V/4
C + BC VRx_CA from -V/4 to +V/4, ∆ = +½V
C ½¼ VV −
Rx_CA -V/2 Strong 0
+x -y 0→1 Zero jitter! Only one zero crossing.
Strong 1
¾V A +V/2
+x to +z
+ AB CA
A ½¼ VV −
Rx_AB
+V/4 Weak 1
1→0
¾V B + VRx_AB from +V/2 to -V/4, ∆ = -¾V Double
B ½¼ VV −
Rx_BC 0
VRx_BC from -V/4 to -V/4, ∆ = 0 Transition
0→0 BC Weak 0
¾V -V/4
C + TRIGGER VRx_CA from -V/4 to +V/2, ∆ = +¾V
C ½¼ VV −
Rx_CA -V/2 Strong 0
+x +z 0→1 t∆J
Strong 1
¾V A +V/2
+x to -z
+ AB
A ½¼ VV −
Rx_AB
+V/4 Weak 1
1→1 BC
¾V B + VRx_AB from +V/2 to +V/4, ∆ = -¼V Single
B ½¼ VV −
Rx_BC 0
TRIGGER VRx_BC from -V/4 to +V/4, ∆ = +½V Transition
0→1 Weak 0
¾V -V/4
C + CA VRx_CA from -V/4 to -V/2, ∆ = -¼V
C ½¼ VV −
Rx_CA -V/2 Strong 0
0→0 Zero jitter! Only one zero crossing.
1214 +x -z
Figure 56 Illustration of all Possible Transitions from the +x State
1215 The eye pattern shown in Figure 57 has four received signal levels that are the result of three transmitted
1216 single-ended levels (¼ V, ½ V, ¾ V) of the driver circuit in the C-PHY master. Combinations of the three
1217 single-ended levels from the drivers on the three signals of a lane cause a strong and weak 1 and 0 to appear
1218 across the three differential receiver inputs in the C-PHY slave (3 ways to receive 2 signals at a time out of a
1219 total of 3 signals). Only the center of the eye between the weak 0 and weak 1 are considered by the receivers
1220 in the C-PHY slave. The eye pattern shall be drawn by overlapping the three waveforms of all three pairs of
1221 signals, which are: A minus B, B minus C, and C minus A. The eye pattern is drawn in this manner because
1222 all three pairs of signals are used simultaneously when the clock is recovered and data is captured at the C-
1223 PHY slave.
“strong 1”
“weak 1”
Eye
Zero Crossing Opening
“weak 0”
“strong 0”
tphase_offset
1224 Trigger, every n*UI - tphase_offset
Figure 57 Eye Pattern Example, “Conventional” Trigger
1225 As mentioned previously in section 10.1, the slave recovers the clock for data sampling by using the
1226 guaranteed transitions at each UI boundary. Since the receiver can make use of this characteristic, it is
1227 important to know the events at the inputs of the differential receivers leading up to the transitions that occur
1228 at the UI boundary. Events leading up to the first transition are obscured when the eye is viewed in the
1229 conventional manner as shown in Figure 57. The C-PHY eye pattern in Figure 58 is a triggered eye, meaning
1230 that the right side of the eye is aligned at a trigger point. The trigger is the first zero crossing of any of the

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1231 three differential waveforms (A minus B, B minus C, and C minus A) that occur at each UI boundary. This
1232 trigger point is also shown in the individual waveforms shown in Figure 56 for each of the of the transition
1233 types. For UI boundaries that have more than one transition of the differential waveforms, the subsequent
1234 transitions in the triggered eye are drawn at their proper position relative to the first transition. (For example:
1235 compare the relative position of the solid orange transition with the dashed orange transition in Figure 58,
1236 and note how these two transitions are consistent with the same orange transitions in Figure 56.) All of the
1237 first zero crossings at each UI boundary are aligned at the trigger point. Similarly, the transitions that occurred
1238 during the prior UI boundary are drawn at their proper position relative to the trigger point. The eye mask of
1239 the triggered eye diagram represents the worst case that will be observed at a C-PHY receiver that responds
1240 to the first zero crossing.
“strong 1”
“weak 1”
Zero Crossing Eye Mask
“weak 0”
“strong 0”
1241 Trigger, at 1st zero crossing

Figure 58 C-PHY Eye Pattern Example, Triggered Eye
1242 The right-most point of the eye mask is aligned with the first zero crossing trigger point so it is consistent
1243 with sampling the received data just prior to the trigger point.
1244 As mentioned above, the first zero crossing at each UI boundary (the trigger point) is associated with the
1245 sampling of the wire state transmitted prior to that UI boundary. Figure 56 shows that this first transition is
1246 caused by the following types of wire state transitions: weak-to-weak, weak-to-strong, and possibly a strong-
1247 to-strong (in the triple transition case, +x to -x in Figure 56). The difference of the first transition arrival time
1248 at one UI boundary relative to the first transition at the previous UI boundary affects the time period between
1249 sampling of two successive wire states (receiver outputs). The peak-to-peak deviation of this zero-crossing
1250 time (the trigger point) is illustrated by the two pink dashed lines that span across all five waveforms in Figure
1251 56. Sampling clock jitter is also affected by cycle-to-cycle transmit clock jitter, receiver input offset voltage,
1252 and receiver duty-cycle distortion. The jitter caused by the relative difference in zero-crossing time due to
1253 the signal slew rate for each transition type is what is illustrated by the pink dashed lines in Figure 56.
10.3 Timing Specifications

1254 The timing requirements specified in this section shall be met for the signal levels specified in Chapter 9,
1255 with the channel specified in Chapter 8, while transmitting a pseudo-random data pattern having data
1256 transition density similar to the PRBS data patterns described in Chapter 12. The C-PHY Receiver Eye
1257 Diagram shown in Figure 59 defines the receiver eye measurement parameters. The measurement points for
1258 the transmitter and for the receiver are specified in Figure 54.

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|VDIF_RX|
Maximum
|VIDTH,MAX|
0V 0V
|VIDTL,MIN|
Shaded areas |VDIF_RX|
are keep-out Maximum
regions
tEYE_RAMP tEYE_RAMP
tEYE_WIDTH
tUI_AVERAGE
1259 Trigger, at 1st zero crossing

Figure 59 C-PHY Receiver Eye Diagram
1260 𝑉𝑉𝐷𝐷𝐷𝐷𝐷𝐷_𝑅𝑅𝑅𝑅 = 𝑉𝑉𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼,𝑀𝑀𝑀𝑀𝑀𝑀 − 𝑉𝑉𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼,𝑀𝑀𝑀𝑀𝑀𝑀
1261 The timing specifications are based on allocations of the total unit interval as described in Table 33.
1262 Table 33 Transmit Timing Requirements, TLIS and Receive are Informative
Symbol Rate TX tR & tF Transmit CPAD_TX TLIS Receive CPAD_RX
> 1.5Gsps 0.285 UI 0.3 UI ≤ 2pF 0.3 UI 0.4 UI ≤ 2pF
≤ 1.5Gsps 0.4 UI 0.3 UI ≤ 5pF 0.3 UI 0.4 UI ≤ 2pF
10.3.1 Tx Timing Specifications

1263 The transmit signal level requirements and transmit rise and fall time requirements are specified in Section
1264 9.1.1.
1265 The inter-lane skew between lanes that are used together as a group of lanes by a higher layer protocol shall
1266 be ±3.5 UI maximum at the output of the transmitter. Inter-lane skew for the interconnect is described in
1267 section 8.6.5.
10.3.2 Rx Timing Specifications

1268 The receiver eye diagram requirements are specified below in Table 34, which use Figure 59 as a reference.
1269 Table 34 Receiver Timing Specifications

tEYE_RAMP Eye ramp time at the receiver 0.2 UI
tEYE_WIDTH Eye width at the receiver 0.4 UI
tUI_AVERAGE UI average UIINST

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10.4 Reverse High-Speed Data Transmission Timing

1270 High-speed reverse data transmission is not supported.

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11 Regulatory Requirements
1271 All C-PHY based devices should be designed to meet the applicable regulatory requirements.

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12 Built-In Test Circuitry (Informative)
12.1 Introduction
1272 Standardized built-in test circuitry in the C-PHY lane function simplifies production testing, verification,
1273 interoperability testing and even self-test of the mobile device that uses the C-PHY. Compatibility of the
1274 built-in test circuitry benefits both test equipment and device makers. The test circuit specification defines
1275 precise characteristics and behavior of the built-in test circuits, and also includes a register definition for
1276 control of the PHY circuit operating and test modes and for observability of important PHY circuit operating
1277 conditions.
1278 It is recommended to include the built-in test circuitry and associated control and status registers per the
1279 method described in section 12.
12.2 Register Concept

1280 The Lane Configuration and Status Registers can be accessible through any register or memory space that is
1281 associated with or related to the C-PHY function. There is no need to use any specific physical interface to
1282 gain access to the register or memory space. The only general characteristics to ensure compatibility between
1283 test equipment and devices being tested are that each register location be at least 8 bits wide, that the register
1284 space be both readable and writeable, and that there are a sufficient number of available address locations to
1285 accommodate the product of the per-lane register count times the number of lanes being used plus the number
1286 of global registers that are necessary.
12.2.1 Allocation of Register Addresses

1287 Following are specific characteristics of registers that are associated with each C-PHY lane:
1288 3. There is a group of Lane Configuration and Status Registers associated with each C-PHY lane Tx
1289 and Rx function.
1290 4. The group of registers for the Tx lane function is separate from a group of registers for the Rx lane
1291 function. Each C-PHY master lane is associated with one group of Tx Lane Configuration and
1292 Status Registers, and each C-PHY slave lane is associated with one group of Rx Lane
1293 Configuration and Status Registers.
1294 5. The individual registers within a group of Lane Configuration and Status Registers that correspond
1295 to a specific lane are defined to exist in a contiguous block of addresses starting at a Tx Lane Base
1296 Address (Tx_Lane_n_Base) or a Rx Lane Base Address (Rx_Lane_n_Base). The offset of each
1297 Lane Configuration and Status Register relative to the Tx Lane Base Address or Rx Lane Base
1298 Address is defined for each register definition.
1299 6. The exact physical addresseses of each Tx Lane Base Address and Rx Lane Base Address are
1300 flexible. They are defined by the device manufacturer.
1301 7. There can be gaps in the address space between the highest register address within any group of
1302 Lane Configuration and Status Registers and Lane Base Address of any other group of Lane
1303 Configuration and Status Registers depending on the assignment of physical addresses to base
1304 addresses. Device manufacturers may choose to have gaps between Lane Configuration and Status
1305 Register groups to be able to fit groups of registers within available addresses in the register
1306 address space. (There may be gaps in the address space between each group of Lane Configuration
1307 and Status Registers.)
1308 8. Having a unique Tx Lane Base Address or Rx Lane Base Address for each C-PHY lane in a device
1309 allows the attributes and status of each lane to be controlled and read individually.
1310 Following are specific characteristics of registers that apply globally across all C-PHY lanes, or to a defined
1311 group of C-PHY lanes, in a device:

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1312 9. There is a set of Tx Global Configuration and Status Registers that applies globally to all C-PHY
1313 Tx lanes in a device (lanes that have C-PHY master capability) or to a defined group of Tx C-PHY
1314 lanes in a device.
1315 10. There is a set of Rx Global Configuration and Status Registers that applies globally to all Rx lanes
1316 in a device (lanes that have C-PHY slave capability) or to a defined group of Rx C-PHY lanes in a
1317 device.
1318 11. The individual registers within the block of Global Configuration and Status Registers are defined
1319 to exist in a contiguous block of addresses beginning from the Tx Global Registers Base Address
1320 (Tx_Global_Registers_Base) or Rx Global Registers Base Address (Rx_Global_Registers_Base).
1321 The offset of each Global Configuration and Status Register relative to the Tx Global Registers
1322 Base Address or Rx Global Registers Base Address is defined for each register definition.
1323 12. The exact physical addresses of the Tx Global Registers Base Address and Rx Global Registers
1324 Base Address are flexible. They are defined by the device manufacturer.
1325 13. There can be gaps in the address space between the highest register address within the Tx Global
1326 Configuration and Status Registers or Rx Global Configuration and Status Registers and any Tx
1327 Lane Base Address or Rx Lane Base Address depending on the assignment of physical addresses
1328 to base addresses. Device manufacturers may choose to have gaps between register groups to be
1329 able to fit groups of registers within available addresses in the register address space.
1330 A pictorial example of this method is illustrated in Figure 60. This method of register definition enables
1331 compatibility between test equipment or test fixtures and devices under test, where only the device-specific
1332 base addresses need to be programmed into the testers. Compatibility is ensured by consistent use of the
1333 register addressing definition and functional behavior of every bit in the register space defined in this chapter.
Test Register CCI Register CCI Register

Space or CPU Space or CPU Space or CPU
Memory Space Memory Space Memory Space
max max max
Rx Lane 3 Lane Tx Lane 3 Lane Tx Lane 3 Lane

Configuration & Configuration & Configuration &
Status Registers Rx Lane 3 Status Registers Tx Lane 3 Status Registers Tx Lane 3
Lane Base Lane Base Lane Base
Rx Lane 2 Lane Address Tx Lane 2 Lane Address Tx Lane 2 Lane Address
Status Registers Rx Lane 2 Status Registers Tx Lane 2 Status Registers Tx Lane 2
Rx Lane 1 Lane Address Tx Lane 1 Lane Address Tx Lane 1 Lane Address
Status Registers Rx Lane 1 Status Registers Tx Lane 1 Tx Lane 1
Status Registers
Rx Global Address Tx Global Address
Tx Global Address
Configuration & Configuration &
Status Registers Rx Global Status Registers Tx Global Configuration & Tx Global
Registers Registers Status Registers Registers
Base Address Base Address Base Address
1334 0 0 0
Figure 60 Configuration and Status Register mapping
12.2.2 Example of Register Access via CCI

1335 Examples of suitable interfaces to access the C-PHY register space are: CSI-2 CCI in an image sensor,
1336 “flipped” CCI interface or AHB/APB in an application processor, or debug serial bus (JTAG or other) in a
1337 display driver IC. The C-PHY Global and Lane Configuration and Status Registers in the image sensor can
1338 be accessed easily via the CCI interface. These configuration and status registers in the image sensor can be
1339 written and read via CCI without any changes to the intended operating mode of CCI. It is only necessary to
1340 allocate space for the registers within the CCI register space. The registers in the application processor may

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1341 be accessed in a number of ways. One method is via a form of CCI, but a special test mode can be enabled
1342 where the CCI master in the applications processor is disabled and a CCI slave or even an I2C slave is enabled
1343 instead. This CCI slave or I2C slave function is connected to the same SDA and SCL pins as the CCI master,
1344 but the slave is only enabled for test mode. The applications processor code will never simultaneously enable
1345 both the CCI master and CCI or I2C slave. For normal system operation the CCI master is enabled and the
1346 CCI or I2C slave is disabled. For test mode the CCI or I2C slave is enabled and the CCI master is disabled.
1347 The recommended locations of CCI master and CCI or I2C slave in each mode, are shown in Figure 61. Other
1348 command delivery options such as command bridging through an external device are shown as well.
DUT DUT
Image Sensor
(Apps Processor) (Image Sensor)
CCI Slave Tx CCI/I2C Slave Rx CCI Slave Tx
CCI/I2C
C-PHY
C-PHY
C-PHY
CCI
CCI
CCI Master Rx CCI Master Tx CCI Master Rx
Apps Processor Test Equipment Test Equipment
Normal Testing Testing

Operation Apps Processor Image Sensor
DUT DUT DUT

(Apps Processor) (Apps Processor) (Display Driver IC)
CCI/I2C Slave Rx JTAG Port Rx JTAG Port Rx
CCI/I2C
CCI/I2C
JTAG
C-PHY
C-PHY
C-PHY
Command Command Command

Bridging Bridging Bridging
Function Function Function
Test Tx Test Tx Test Tx

Commands Commands Commands
Test Equipment Test Equipment Test Equipment
Testing Testing Testing
Apps Processor, Apps Processor, Display Driver IC,
Bridging Function Bridging Function Bridging Function
1349
Figure 61 Use of CCI for Normal Operation and Test
1350 The Rx Global and Lane Configuration and Status Registers can be accessed in a similar manner via the CCI
1351 slave (for test mode) in the applications processor. It is also possible for the Rx Global and Lane
1352 Configuration and Status Registers to be mapped into the CPU memory space instead of using a special CCI

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1353 slave for test mode. The specific method of register access in the applications processor is an implementation
1354 choice. However, implementation of the specific function and address mapping of these registers defined in
1355 this chapter is recommended.
12.2.3 Register Definitions

1356 A high-level view of the global and lane-specific test circuits is shown in Figure 62. The following sections
1357 describe the global and lane test functions for both Tx and Rx. The test circuits can be controlled and observed
1358 through registers such as those accessible via the CSI-2 CCI interface. The four primary groups of registers
1359 and the abbreviations used in the register names are as follows:
1360 • TLRn – Tx Lane Register n, where n is the number of the lane starting at 1. There is one set of Tx
1361 Lane Configuration and Status Registers per lane. In a system having 6 lanes, TLRn could be
1362 TLR1, TLR2, TLR3, TLR4, TLR5 or TLR6. n can be larger than 6 in chips supporting multiple
1363 camera or display ports. n is limited only by the size of the address space.
1364 • RLRn – Rx Lane Register n, where n is the number of the lane starting at 1. There is one set of Rx
1365 Lane Registers per lane. In a system having 6 lanes, RLRn could be RLR1, RLR2, RLR3, RLR4,
1366 RLR5 or RLR6. n can be larger than 6 in chips supporting multiple camera or display ports. n is
1367 limited only by the size of the address space.
1368 • TGR – Tx Global Configuration and Status Registers, a set of read and write functions that apply
1369 to all Tx lanes in a device or to a defined group of Tx lanes in a device.
1370 • RGR – Rx Global Configuration and Status Registers, a set of read and write functions that apply
1371 to all Rx lanes in a device or to a defined group of Rx lanes in a device.
Tx Rx
Tx Higher Layer Tx Lane 1 Rx Lane 1 Rx Higher Layer
16-bit C-PHY A1 A1 C-PHY
Protocol 16-bit Protocol
mux Tx Lane B1 B1 Rx Lane
Function PRBS Function
Function C1 C1 Function
Generator
PRBS Data
Verification
Higher Layer Lane Tx Lane 2 Rx Lane 2

Protocol Distribution 16-bit C-PHY A2 A2 C-PHY Higher Layer
16-bit Lane Merge
Packet Data Function PRBS
Function
Protocol
Function C2 C2 Function Packet Data
Generator
PRBS Data
Verification
Tx Lane 3 Rx Lane 3
16-bit C-PHY A3 A3 C-PHY
16-bit
PRBS
Function C3 C3 Function
Generator
PRBS Data
Verification
Tx Global
Configuration & Status Registers Rx Global Configuration & Status Registers
1372
Figure 62 High-Level Tx and Rx, Global and Lane Functions
12.3 Tx Lane Test Circuitry

1373 Figure 63 is a high-level block diagram of a single Tx lane circuit. Test circuitry is indicated by yellow fill in
1374 specific blocks. There is one set of Tx Lane Configuration and Status Registers per lane, so a 3-lane system
1375 has three sets of Tx Lane Configuration and Status Registers. The definition of each register is described in
1376 more detail later in this section.

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Tx_Data[15:0]
16-bit to
16-bit 21-bit
mux 7-symbol
PRBS
Mapper
Parallel-to-Serial
Generator
Symbol
TLRn_PRBS_Enable
21-bit 3-bit Encoder, A
TLRn_PRBS_Pattern
TLRn_PRBS_Seed
Fixed Preamble, Preamble mux B
Programmable Sequence, Sync 3-Phase
C
Words, Post pattern generator Driver
Debug Pattern
Generator
Tx Lane TLRn_Debug_Pattern
Config.
Config. State
Bus
Registers Machine
TGR_Test_Enable
Tx Lane Configuration and Status Registers

Tx Lane n
Tx_Lane_n_Base + 4
PRBS Seed 2
Tx Lane n
Tx_Lane_n_Base + 3
PRBS Seed 1
Tx Lane n
Tx_Lane_n_Base + 2
PRBS Seed 0
Tx Lane n
Tx_Lane_n_Base + 1
Test Patterns Select
Tx Lane n
Tx_Lane_n_Base + 0
1377 Lane Configuration
Figure 63 Transmit (Master) Lane Block Diagram with Test Circuitry
1378 The Tx Lane Configuration and Status Registers have the following definitions:
12.3.1 TLRn_Lane_Configuration
write-only, Address: Tx_Lane_n_Base + 0
1379 The Tx Lane n Lane Configuration register is used to configure parameters that are specific to the function
1380 of the lane.
[7:0] – reserved for future use.
12.3.2 TLRn_Test_Patterns_Select
1381 The Tx Lane n Test Patterns Select register provides the means to choose a specific test pattern to be output
1382 by a transmit lane function.
[7:5] – TLRn_PRBS_Pattern =0 – select 16-bit Tx_Data[15:0] from Lane Distribution
Function (normal operation)
=1 to 3 – reserved for future use
=4 – select PRBS9
=5 – select PRBS11
=7 – reserved for future use

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[4] – Reserved for future use

[3:0] – TLRn_Debug_Pattern =0 – select output of 16-to7 Mapper (normal operation) or
PRBS pattern, as selected by TLRn_PRBS_Pattern
=1 – debug pattern is a sequence of 14 symbols defined by
the same Tx Global Registers that define the
Programmable Sequence of the Preamble
=2 – debug pattern is a sequence of wire states that are
defined by the same Tx Global Registers that define the
Programmable Sequence of the Preamble
1383 Since the mux to select the TLRn_Debug_Pattern is “downstream” from the mux that selects the PRBS
1384 pattern, the TLRn_Debug_Pattern selection takes precedence over the TLRn_PRBS_Pattern setting. When
1385 the TLRn_Debug_Pattern selection is equal to 1 then the debug pattern is defined by the Tx Global Registers:
1386 TGR_Preamble_Prog_Sequence_0,1 [Tx_Global_Registers_Base_Address + 3] through
1387 TGR_Preamble_Prog_Sequence_12,13 [Tx_Global_Registers_Base_Address + 9]. These are the same
1388 registers that define the programmable sequence portion of the preamble. The 14-symbol debug pattern is
1389 repeated in the transmitted high speed data following the sync word as shown in Figure 64.
14-symbol 14-symbol 14-symbol

Preamble Sync Word
Debug Pattern Debug Pattern Debug Pattern
... 3 3 3 3 3 4 4 4 4 4 3 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S ...
0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2
1390
Figure 64 Repeating 14-Symbol Debug Pattern in High Speed Data
1391 If the TLRn_Debug_Pattern field is equal to 1 then the debug pattern is a sequence of 14 symbols defined by
1392 the same Tx Global Registers that define the Programmable Sequence of the Preamble. The symbols are
1393 defined using the same 3-bit Flip Rotation Polarity format that is described in Table 4.
1394 If the TLRn_Debug_Pattern field is equal to 2 then the debug pattern is a sequence of 14 wire states defined
1395 by the same Tx Global Registers that define the Programmable Sequence of the Preamble. The wire states
1396 are defined using the 3-bit format described in the table below. When TLRn_Debug_Pattern is set to 2 then
1397 the programmable sequence values are defined as wire states rather than symbol values. The bit numbers in
1398 the column headings of the table correspond to bit numbers in the Transmit Global Registers
1399 TGR_Preamble_Prog_Sequence_0,1 through TGR_Preamble_Prog_Sequence_12,13.
TGR_Preamble_ TGR_Preamble_ TGR_Preamble_
Prog_Sequence…[5] Prog_Sequence…[4] Prog_Sequence…[3]
TGR_Preamble_ TGR_Preamble_ TGR_Preamble_
Wire State
Prog_Sequence…[2] Prog_Sequence…[1] Prog_Sequence…[0]
+x 1 0 0
-x 0 1 1
+y 0 1 0
-y 1 0 1
+z 0 0 1
-z 1 1 0
1400 Note that the first wire state of the programmable sequence transmitted following the last bit of the Sync
1401 Word might happen to be the same wire state transmitted during the last unit interval of the Sync Word. If
1402 this happens then there will be no wire state transition at that unit interval boundary to generate a symbol
1403 clock pulse in a receiver. This is acceptable behavior because the purpose of the programmable wire state
1404 debug pattern is to evaluate electrical and timing characteristics of the driver.

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12.3.3 TLRn_PRBS_Seed_0
1405 The Tx Lane n PRBS Seed 0 register is an 8-bit value used to initialize the least significant 8 bits of the 18-
1406 bit Seed for the Tx Lane PRBS register. Figure 65 shows the method to initialize the Transmit Lane PRBS
1407 register using the fragments of the Seed value.
[7:0] – seed value for Transmit PRBS TLRn_PRBS_Seed_0[7] → Q[8]; through
register Q[8:1] TLRn_PRBS_Seed_0[0] → Q[1];
1408 The Tx Lane n PRBS Seed 1 register is an 8-bit value used to initialize the next least significant 8 bits of the
1409 18-bit Seed for the Tx Lane PRBS register. Figure 65 shows the method to initialize the Transmit Lane PRBS
1411 The Tx Lane n PRBS Seed 2 register is a 2-bit value used to initialize the most significant 2 bits of the 18-
1412 bit Seed for the Tx Lane PRBS register. Figure 65 shows the method to initialize the Transmit Lane PRBS
[7:2] – Reserved for future use
12.3.6 Tx Lane PRBS Register Operation

1414 The Transmit Lane PRBS Register Q[16:1] is the source of data input to TxD[15:0] of the Mapper when the
1415 lane master is transmitting one of the three PRBS patterns as defined by the TLRn_Test_Patterns_Select
1416 register. The Transmit Lane PRBS Register function is defined in Figure 65. The Transmit Lane PRBS
1417 register is initialized using the seed values TLRn_PRBS_Seed_0, TLRn_PRBS_Seed_1 and
1418 TLRn_PRBS_Seed_2, as shown in Figure 65. The first word transmitted from the PRBS generator is equal
1419 to the seed value: [TLRn_PRBS_Seed_1[7:0], TLRn_PRBS_Seed_0[7:0]]. This initial 16-bit value from the
1420 PRBS register is transmitted immediately following transmission of the first Sync Word after the low-power
1421 to high-speed mode transition. The Transmit Lane PRBS Register is shifted 16 bit positions after each 16-bit
1422 word is output to minimize correlation from one data value to the next. This way no bits are re-used in
1423 successive samples.
1424 Example Seed values and data sequences for the chosen PRBS mode are as follows:
1425 PRBS9 – Seed = 0x789a; TLRn_PRBS_Seed_0[7:0] = 0x9a; TLRn_PRBS_Seed_1[7:0] = 0x78;
1426 TLRn_PRBS_Seed_2[7:0] value does not matter;
1427 Transmit data sequence: 0x789a, 0x9980, 0xc651, 0xa5fd, 0x163a, 0xcb3c, 0x7dd0…
1428 PRBS11 – Seed = 0x789a; TLRn_PRBS_Seed_0[7:0] = 0x9a; TLRn_PRBS_Seed_1[7:0] = 0x78;
1429 TLRn_PRBS_Seed_2[7:0] value does not matter;
1430 Transmit data sequence: 0x789a, 0x5e64, 0xfee0, 0xac43, 0xa9a1, 0xe4ce, 0xfea0…
1431 PRBS18 – Seed = 0x2789a; TLRn_PRBS_Seed_0[7:0] = 0x9a; TLRn_PRBS_Seed_1[7:0] =
1432 0x78; TLRn_PRBS_Seed_2[7:0] = 0x02;
1433 Transmit data sequence: 0x789a, 0x8d77, 0x0dbc, 0x74e1, 0x8108, 0x414a, 0x3915…

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Degree 18: x0 + x11 + x18

+
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TxD15 TxD14 TxD13 TxD12 TxD11 TxD10 TxD9 TxD8 TxD7 TxD6 TxD5 TxD4 TxD3 TxD2 TxD1 TxD0
Seed
Register 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TLRn_PRBS_Seed_2 TLRn_PRBS_Seed_1 TLRn_PRBS_Seed_0
Degree 11: x0 + x9 + x11

+
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Seed
Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TLRn_PRBS_Seed_1 TLRn_PRBS_Seed_0
Degree 9: x0 + x5 + x9
+
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Seed
Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TLRn_PRBS_Seed_1 TLRn_PRBS_Seed_0
1434
Figure 65 Tx Lane PRBS Register Function and Seed Value Initialization
12.4 Rx Lane Test Circuitry

1435 Figure 66 shows a high-level block diagram of the Receive Lane with test circuitry.

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A +
Serial-to-Parallel
-
7-symbol Rx_Data[15:0]
B + Symbol 3-bit 21-bit
to 16-bit
16-bit
- Decoder
De-Mapper
C +
-
Clock State PRBS Checker, Word

Recovery Machine Error & Word Count
Circuit
RLRn_PRBS_Error_Count, _Bit_Count, _Status
RLRn_PRBS_Seed
RLRn_PRBS_Pattern
Config. Rx Lane Config.

Bus & St. Registers
Parallel-to-Serial
Compare, 16-bit to
3-bit 21-bit 16-bit PRBS
Count & 7-symbol
Generator
Identify Mapper
TGRn_Preamble_Prog_Sequence_0 to 13
Symbol Error Count & Identify Function *
Rx Lane Configuration and Status Registers

Rx Lane n Rx Lane n
1st Sym Error Location 5 * Rx_Lane_n_Base + 19 Word Count 2 Rx_Lane_n_Base + 9
Rx Lane n Rx Lane n
Rx Lane n Rx Lane n
Rx Lane n Rx Lane n
1st Sym Error Location 2 * Rx_Lane_n_Base + 16 Word Error Count Rx_Lane_n_Base + 6
Rx Lane n Rx Lane n
1st Sym Error Location 1 * Rx_Lane_n_Base + 15 PRBS Seed 2 Rx_Lane_n_Base + 5
Rx Lane n Rx Lane n
1st Sym Error Location 0 * Rx_Lane_n_Base + 14 PRBS Seed 1 Rx_Lane_n_Base + 4
Rx Lane n Rx Lane n
Symbol Error Count * Rx_Lane_n_Base + 13 PRBS Seed 0 Rx_Lane_n_Base + 3
Rx Lane n Rx Lane n
Word Count 5 Rx_Lane_n_Base + 12 Status Rx_Lane_n_Base + 2
Rx Lane n Rx Lane n
Word Count 4 Rx_Lane_n_Base + 11 PRBS Pattern Rx_Lane_n_Base + 1
Rx Lane n Rx Lane n
Word Count 3 Rx_Lane_n_Base + 10 Configuration Rx_Lane_n_Base + 0
1436 * a Symbol Error Count Function, remove if not needed

Figure 66 Receive (Slave) Lane Block Diagram with Test Circuitry

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1437 The Rx Lane Configuration and Status Registers have the following definitions:
12.4.1 RLRn_Lane_Configuration
write-only, Address: Rx_Lane_n_Base + 0
1438 The Rx Lane n Configuration register currently has no assigned bits in the register to affect the lane function.
[7:0] – reserved for future use
12.4.2 RLRn_Test_Pattern_Select
1439 The Rx Lane n Test Pattern register provides the means to choose a specific PRBS pattern to be used by the
1440 PRBS Checker. The register contents also specify which pattern is to be used by the symbol error counting
1441 function, if the symbol error count feature is implemented.
[7:5] – RLRn_PRBS_Pattern_Select =0 – disable error detection and counting

=4 – select PRBS9
=7 – reserved for future use
[4] – reserved for future use
[3:0] – RLRn_Symbol_Error_Count_Function =0 – the symbol error count function, if implemented, is
controlled by bits [7:5]. The symbol error count compares
received symbols with the selected PRBS sequence sent
through the mapper; or if bits [7:5] are all zero then the
symbol error count function is disabled.
=1 – the symbol error count function, if implemented,
compares received symbols with the user-defined debug
pattern, which is defined by the same Tx Global
Registers that define the Programmable Sequence of the
Preamble. For a receive-only device, the receiver would
need to implement the seven Tx Global Registers that
define the programmable sequence, even if that device
does not contain a Tx C-PHY function.
1442 It is not necessary to enable or disable the error counting function. There is no harm in counting errors all of
1443 the time, even when actual packet data is being received. The system software will know to ignore the error
1444 counter value at that time. The enable/disable setting may be useful to prevent activity in the receiver error
1445 measurement system to slightly reduce power consumption when the capability to count errors is not
1446 required.
12.4.3 RLRn_Rx_Lane_Status
read-only, Address: Rx_Lane_n_Base + 2
1447 The Rx Lane n Status register contains status indicators relating to important events that occur when a packet
1448 is received. All bits in the register are reset when the lane detects the transition from LP-111 to LP-001. The
1449 lane status logic keeps track of each event described in the RLRn_Rx_Lane_Status register. The register
1450 contents may be valid prior to the LP-000 to LP-111 transition. The register contents contain the actual status
1451 following the LP-000 to LP-111 transition.
[7] – LP-001 to LP-000 transition was 1 – The transition was detected.
detected. 0 – The transition was not detected.

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[6] – Preamble Programmable Sequence 0 if not used. The specific function of this bit is determined
status (optional) by the device manufacturer.
[5] –Sync Word was detected. 1 – The Sync Word was detected.
0 – The Sync Word was not detected.
[4] – Post sequence was detected 1 – Post was detected.
0 – Post was not detected.
[3:0] – reserved for future use
12.4.4 RLRn_PRBS_Seed_0
1452 The Rx Lane n PRBS Seed 0 register is an 8-bit value used to initialize the least significant 8 bits of the 18-
1453 bit Seed for the Receive Lane PRBS register. Figure 67 shows the method to initialize the PRBS register
1454 using the fragments of the Seed value.
[7:0] – seed value for Receive PRBS RLRn_PRBS_Seed_0[7] → Q[8]; through
register Q[8:1] RLRn_PRBS_Seed_0[0] → Q[1];
1455 The Rx Lane n PRBS Seed 1 register is an 8-bit value used to initialize the next least significant 8 bits of the
1456 18-bit Seed for the Receive Lane PRBS register. Figure 67 shows the method to initialize the PRBS register
1458 The Rx Lane n PRBS Seed 2 register is a 2-bit value used to initialize the most significant 2 bits of the 18-
1459 bit Seed for the Receive Lane PRBS register. Figure 67 shows the method to initialize the PRBS register
[7:2] – Reserved for future use
12.4.7 Rx Lane PRBS Register Operation

1461 The Receive Lane PRBS Register Q[16:1] is the reference data that is compared with RxD[15:0] from the
1462 De-Mapper when the lane slave is operating in one of the three PRBS test modes as defined by the
1463 RLRn_PRBS_Pattern register. The Receive Lane PRBS Register function is defined in Figure 67. The
1464 Receive Lane PRBS Register is initialized using the seed values RLRn_PRBS_Seed_0,
1465 RLRn_PRBS_Seed_1 and RLRn_PRBS_Seed_2, as shown in Figure 67. The first reference word from the
1466 Receive Lane PRBS Register is equal to the seed value: [RLRn_PRBS_Seed_1[7:0],
1467 RLRn_PRBS_Seed_0[7:0]]. This first word from the Receive Lane PRBS Register is compared with the first
1468 word of received data immediately following the first Sync Word after the low-power to high-speed mode
1469 transition. The Receive Lane PRBS Register is shifted 16 bit positions after each 16-bit word of reference
1470 data is output to correspond exactly with the data that was transmitted.

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Degree 18: x0 + x11 + x18

RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD RxD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Compare
+
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Seed
Register 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RLRn_PRBS_Seed_2 RLRn_PRBS_Seed_1 RLRn_PRBS_Seed_0
Degree 11: x0 + x9 + x11

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Compare +
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Seed
Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RLRn_PRBS_Seed_1 RLRn_PRBS_Seed_0
Degree 9: x0 + x5 + x9
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Compare +
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Seed
Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
RLRn_PRBS_Seed_1 RLRn_PRBS_Seed_0
1471
Figure 67 Rx Lane PRBS Register Function and Seed Value Initialization
12.4.8 Rx Lane Word Error Count and Word Count Functionality

1472 The Rx Lane Word Error Count is a count of the number of word errors that were detected in the
1473 corresponding Lane. If there is one or more bit errors in the comparison of RxD[15:0] versus Q[16:1] of the
1474 Receive Lane PRBS Register then the error count is incremented by one. (Note that if there are multiple
1475 errors in the comparison of one received data word then the Rx Lane Word Error Count is incremented by
1476 only one count.) The Rx Lane Word Error Count saturates at 255, so if more than 255 errors are detected then
1477 the count stops at 255 and will not roll-over to zero. The word error count is reset to zero at the transition
1478 from low-power to high-speed mode (the LP-001 to LP-000 transition), and any detected word errors are
1479 counted beginning at the first De-Mapper output word of the Packet Data field following the Sync Word
1480 field.
1481 The Rx Lane Word Count described below is a 48-bit integer value. The Rx Lane Word Count is recorded by
1482 the receiver because the duration of the high-speed data is controlled by an enable/disable bit in the

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1483 Tx_Global_Configuration_Register. Knowing the word count makes it possible to accurately compute the
1484 word error rate or symbol error rate. The Rx Lane Word Count word count is sufficiently large to perform an
1485 error rate test at 2.5Gsps for slightly more than 9 days. A single word error over this maximum test interval
1486 corresponds to a symbol error rate of about 510-16. If there are any symbol errors that cause missing symbol
1487 clocks then the word count will be reduced by 1/7th of a word for each such occurrence, and the error count
1488 will most likely saturate in that instance, so the calculated error rate would not be meaningful. It is anticipated
1489 that even with such a large word counter, the symbol error rates and word error rates will not be measurable
1490 unless the signal amplitude or channel conditions are degraded beyond the required limits specified in this
1491 document. If symbol errors are counted to determine the symbol error rate, then it is necessary to multiply
1492 the word count by 7 to know the symbol count for the symbol error rate calculation:
1493 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠_𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒_𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠_𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒_𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 ⁄(𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤_𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 ∙ 7)
1494 All 48 bits of the Rx Lane Word Count are reset to zero on the transition from low-power mode to high-speed
1495 mode (on the transition from LP-001 to LP-000). The Rx Lane Word Count can be read after the transition
1496 back to low-power mode (following the transition from LP-000 to LP-111). If the Rx Lane Word Count is
1497 read during the error rate measurement test in high-speed mode then the count can contain an invalid result,
1498 depending on the implementation of the word count read circuit.
12.4.9 RLRn_Word_Error_Count
1499 The Rx Lane n Word Error Count is a count of the number of word errors that were detected in the
1500 corresponding Lane.
[7:0] – RLRn_Word_Error_Count Rx Lane Word Error Count
12.4.10 RLRn_Word_Count_0
1501 Rx Lane n Word Count 0 consists of bits 7 through 0 of the 48-bit Rx Lane Word Count value.
[7:0] – RLRn_Word_Count_0 Rx Lane Word Count[7:0]

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12.4.16 Symbol Error Count and Symbol Error Location Functionality

1507 The symbol error count and symbol error location capabilities might have less value than the other built-in-
1508 test capabilities; it may be sufficient to implement only the data generation and word error counting
1509 capabilities described above.
1510 To measure the symbol error count it is necessary to duplicate the data generation, Mapping and Encoding
1511 functions of the transmitter to create a copy of the transmitted symbol stream. Then the received symbol
1512 stream can be compared to the regenerated symbol stream and any differences are counted and can be read
1513 via the RLRn_Symbol_Error_Count register. Any errors that result in a slip of the symbol clock will likely
1514 cause the symbol error count to saturate immediately following the clock slip event. It is anticipated that this
1515 is an extremely unlikely event when the link is operated under the required conditions, but the possibility of
1516 this failure is noted so the system designer is aware of it.
1517 The Receive Lane Symbol Error Count is a count of the number of symbol errors that were detected in the
1518 corresponding Lane. The Receive Lane Symbol Error Count saturates at 255, so if more than 255 errors are
1519 detected then the count stops at 255 and will not roll-over to zero. The Receive Lane Symbol Error Count is
1520 reset to zero at the transition from low-power to high-speed mode, and errors are counted beginning at the
1521 first symbol of the Packet Data field following the first Sync Word after the low-power to high-speed mode
1522 transition.
1523 The Receive Lane 1st Symbol Error Location values are a debug capability that allows the symbol position
1524 of the first error in the Packet Data Field to be identified. This is the value of a rather long counter (a 48-bit
1525 counter) that identifies the symbol offset of the location of the first symbol error in the Packet Data field.
12.4.17 RLRn_Sym_Error_Count
1526 Receive Lane Symbol Error Count is a count of the number of symbol errors that were detected in Lane n.
[7:0] – RLRn_Sym_Error_Count Receive Lane Symbol Error Count
12.4.18 RLRn_1st_Sym_Err_Loc_0
1527 RLRn_1st_Sym_Err_Loc_0 consists of bits 7 through 0 of the 48-bit Receive Lane 1st Symbol Error
1528 Location value.
[7:0] – RLRn_1st_Sym_Err_Loc_0 Receive Lane 1st Symbol Error Location[7:0]

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12.5 Tx Global Configuration and Status Registers

1539 The Tx Global Configuration and Status Registers have the following definitions:
12.5.1 TGR_Global_Configuration
write-only, Address: Tx_Global_Registers_Base + 0
1540 TGR_Global_Configuration is a register to configure parameters and operate controls that apply to all C-
1541 PHY Lanes.
[0] – TGR burst enable/disable TGR burst enable/disable, starts or stops the high-speed
test burst.
=0 – Disable sending high-speed test data
=1 – Enable sending high-speed test data
12.5.2 Burst Enable/Disable Functionality

1542 When the TGR burst enable/disable bit transitions from 0 to 1, the Lane state machines should transmit LP-
1543 001, then LP-000, then Preamble, then Sync Word, then test data is sent in the Packet Data field either from
1544 the Tx Lane PRBS Generator or Debug Pattern Generator. The specific data transmitted depends on the
1545 values written to the TLRn_Test_Patterns_Select register. The Packet Data field contains only the selected
1546 test data and has no high layer protocol packet structure. The selected test data will be sent continuously, as
1547 long as the burst enable/disable bit is set to “1”. There is no limit to the length of the Packet Data field when

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1548 test data is being transmitted. The C-PHY Lane circuit begins in the LP-111 state to respond to the 0-to-1
1549 transition of the TGR burst enable/disable bit. If the C-PHY Lane circuit is not in the LP-111 state during the
1550 0-to-1 transition event then the C-PHY lane will ignore the state of the TGR burst enable/disable bit until it
1551 returns to the 0 state and has a subsequent 0-to-1 transition when the Lane is in the LP-111 state.
1552 When the TGR burst enable/disable bit transitions from 1 to 0 while sending test data, the Lane state machine
1553 causes the Post Sequence (4,4,4,4,4,4,4) to be sent and repeated by the number of times defined in
1554 TGR_Post_Length, and then the termination is disabled and the signals return to the LP-111 state. Figure 68
1555 illustrates the functionality resulting from TGR burst enable/disable changing state.
A/B/C
Pre-Begin Programmable Sequence Pre-End
3 3 3 3 3 3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 3 3 3 3 3 3 3 3 4 4 4 4 4 3 4 4 4 4 4 4 4 4
LP-111 LP-001 LP-000 Preamble Sync Word Packet Post LP-111

Data
TGR burst
enable/disable
A/B/C
Pre-Begin Pre-End
3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 3 4 4 4 4 4 4 4 4
LP-111 LP-001 LP-000 Preamble Sync Word Packet Post LP-111

Data
TGR burst
enable/disable
1556
Figure 68 Example Showing Cause/Effect of TGR burst enable/disable
1557 The lane receiver test circuitry contains a word count field that can be read from RLRn_Word_Count_0
1558 through RLRn_Word_Count_5. From this, it is possible to compute the word error rate, or symbol error rate
1559 by also reading the word error count and symbol error count values.
1560 Note that there are not specific global registers defined for selection of the PRBS polynomial or PRBS seed
1561 value. This allows the PRBS polynomial and seed to be chosen on a per-lane basis. When multiple lanes are
1562 tested simultaneously, it is anticipated that the most frequent use will be to select the same PRBS polynomial
1563 in all lanes and use a different seed value in each lane so that the transmitted data pattern in each lane is
1564 independent of the others.
12.5.3 TGR_Preamble_Length
1565 TGR_Preamble_Length specifies the length of the Preamble and provides a means to enable or disable the
1566 Programmable Sequence in the Preamble.
[7] – enable/disable the Preamble enable or disable the Preamble Programmable Sequence,
Programmable Sequence refer to Figure 69
=0 – Disable the Preamble Programmable Sequence, the
lower waveforms of Figure 69
=1 – Enable the Preamble Programmable Sequence, the
upper waveforms of Figure 69
The default value is 0, which disables the Preamble
Programmable Sequence on system reset.
[6] – reserved for future use.
[5:0] – Begin_Preamble_Length The number of symbols in the PreBegin section of the
preamble is:
(Begin_Preamble_Length + 1)  7

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The default value is 0x3f or 63, which sets the length of the
PreBegin part of the Preamble to 64 Words on system
reset.
1567 The PreBegin part of the Preamble may range from 1 to 64 Words, or 7 to 448 symbols.
12.5.4 TGR_Post_Length
1568 TGR_Post_Length specifies the length of the Post field.
[4:0] – Post_Length The number of symbols in the Post field is:
(Post_Length + 1)  7
The default value is 0x1f or 31, which sets the length of the
PreBegin part of the Preamble to 32 Words on system
reset.
1569 The Post field may range from 1 to 32 Words, or 7 to 224 symbols.
12.5.5 TGR_Preamble_Prog_Sequence_0,1
1570 TGR_Preamble_Prog_Sequence_0,1 specifies the values of symbols 0 and 1 in the Programmable Sequence
1571 portion of the Preamble.
[5:3] – Symbol 1 of the Preamble =0 to 4 – symbol value
Programmable Sequence =5 to 7 – invalid value, not a valid symbol value.
The default value is 3 on system reset.

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1580 TGR_Preamble_Prog_Sequence_10,11 specifies the values of symbols 10 and 11 in the Programmable
1581 Sequence portion of the Preamble.

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1582 TGR_Preamble_Prog_Sequence_12,13 specifies the values of symbols 12 and 13 in the Programmable

1583 Sequence portion of the Preamble.
A/B/C
Pre-Begin Programmable Sequence Pre-End
3 3 3 3 3 3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 3 3 3 3 3 3 3 3 4 4 4 4 4 3
LP-111 LP-001 LP-000 Preamble Sync Word Packet

Preamble is composed of: 3,3,3,3,3,… Sync Word: Data
with mid-section consisting of a programmable sequence. 3,4,4,4,4,4,3
Reset initializes all to 3,3,3,3,3...
A/B/C
Pre-Begin Pre-End
3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 3
LP-111 LP-001 LP-000 Preamble Sync Word Packet

Sync Word: Data
Preamble is composed of: 3,3,3,3,3,…
1584 Prog. sequence in mid-section is disabled. 3,4,4,4,4,4,3
Figure 69 Preamble Programmable Sequence, Showing Bit Order, and Enabled/Disabled
12.6 Rx Global Configuration and Status Registers

1585 There are no anticipated needs for Rx Global Configuration and Status Registers.

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Annex A Logical PHY-Protocol Interface Description

(informative)
1586 The PHY-Protocol Interface (PPI) is used to make a connection between the PHY lane modules and the higher
1587 protocol layers of a communication stack. The interface described here is intended to be generic and
1588 application independent.
1589 This annex is informative only. Conformance to the C-PHY specification does not depend on any portion of
1590 the PPI defined herein. Because of that, this section avoids normative language and does not use words like
1591 “shall” and “should.” Instead, present tense language has been used to describe the PPI, utilizing words like
1592 “is” and “does.” The reader may find it helpful to consider this appendix to be a description of an example
1593 implementation, rather than a specification.
1594 This PPI is optimized for controlling a C-PHY and transmitting and receiving parallel data. The interface
1595 described here is defined as an on-chip connection, and does not attempt to minimize signal count or define
1596 timing parameters or voltage levels for the PPI signals.
A.1 Signal Description

1597 Table 35 defines the signals used in the PPI. For a PHY with multiple lanes, a set of PPI signals is used for
1598 each Lane. Each signal has been assigned into one of six categories: high-speed transmit signals, high-speed
1599 receive signals, escape mode transmit signals, escape mode receive signals, control signals, and error signals.
1600 Bi-directional high-speed lanes with support for bi-directional escape mode include nearly all of the signals
1601 listed in the table. unidirectional lanes include only a subset of the signals. The direction of each signal is
1602 listed as “I” or “O”. Signals with the direction “I” are PHY inputs, driven from the protocol layer. Signals
1603 with the direction “O” are PHY outputs, driven to the protocol layer. For this logical interface, most clocks
1604 are described as being generated outside the PHY, although any specific PHY may implement the clock
1605 circuit differently.
1606 The “Categories” column in Table 35 indicates for which lane module types each signal applies. The category
1607 names are described in Table 2 and are summarized here for convenience. Each category is described using
1608 a four-letter acronym, defined as [Side, HS-capabilities, Escape-Forward, Escape- Reverse]. The first letter,
1609 Side, can be M (Master) or S (Slave). The second letter, high-speed capabilities, can be F (forward data) only.
1610 The third and fourth letters indicate escape mode capability in the forward and reverse directions,
1611 respectively. The third letter can be A (All) or E (Events – Triggers and ULPS only), while the fourth letter
1612 can be A (All, including LPDT), E (Events, triggers and ULPS only), Y (Any but not None: so A or E) or N
1613 (None). Any of the four identification letters can be replaced by an X, to indicate that each of the available
1614 options is appropriate.
1615 Table 35 PPI Signals

Symbol Dir Categories Description
High-Speed Transmit Signals
TxSymbolClkHS I MFXX Lane High-Speed Transmit Symbol Clock.
This clock provides the timing used to transmit high-
speed symbol data over the lane interconnect. All lanes
may use the same TxSymbolClkHS clock signal, or any
subset of lanes down to a single lane may use a
TxSymbolClkHS. Lanes may use different
TxSymbolClkHS clocks as long as the inter-lane skew
requirement is met.

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TxWordClkHS I MFXX High-Speed Transmit Word Clock.
This is used to synchronize PPI signals in the high-speed
transmit clock domain. It is recommended that all
transmitting lane modules share one TxWordClkHS
signal. The frequency of TxWordClkHS is exactly 1/7 the
high-speed symbol rate.
TxDataHS[15:0] I MFXX High-Speed Transmit Data.
Sixteen-bit high-speed data to be transmitted. The signal
connected to TxDataHS[0] is associated with bit 0 of the
C-PHY Mapping function. Data is captured on rising
edges of TxWordClkHS.
TxSendSyncHS I MFXX High Speed Command to Transmit Sync Word.
The protocol adapter attached to the C-PHY may need to
transmit Sync Words to separate multiple copies of a
packet header. This command signal has the same timing
as TxDataHS[15:0] on the PPI, but when TxSendSyncHS
is active on a given TxWordClkHS cycle then
TxDataHS[15:0] is ignored for any Word Clock cycle
where TxSendSyncHS is active.
TxRequestHS I MFXX High-Speed Transmit Request and Data Valid.
A low-to-high transition on TxRequestHS causes the lane
module to initiate a Start-of-Transmission sequence. A
high-to-low transition on TxRequest causes the lane
module to initiate an End-of-Transmission sequence.
This active high signal also indicates that the protocol
layer is driving valid data on TxDataHS to be transmitted.
The lane module accepts the data when both
TxRequestHS and TxReadyHS are active on the same
rising TxWordClkHS clock edge. The protocol layer
always provides valid transmit data when TxRequestHS
is active. Once asserted, TxRequestHS remains high until
the data has been accepted, as indicated by TxReadyHS.
TxRequestHS is only asserted while TxRequestEsc is
low.
TxReadyHS O MFXX High-Speed Transmit Ready.
This active high signal indicates that TxDataHS is
accepted by the lane module to be serially transmitted.
TxReadyHS is valid on rising edges of TxWordClkHS.
High-Speed Receive Signals
RxWordClkHS O SFXX High-Speed Receive Word Clock.
This is used to synchronize signals in the high-speed
receive clock domain. The RxWordClkHS is generated by
dividing the recovered high-speed clock.
RxDataHS[15:0] O SFXX High-Speed Receive Data.
Sixteen-bit high-speed data received by the lane module.
The signal connected to RxDataHS[0] is associated with
bit 0 of the C-PHY De-Mapping function. Data is
transferred on rising edges of RxWordClkHS.

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RxInvalidCodeHS O SFXX High-Speed Invalid Code Word Detection.
A high-speed status signal that indicates the present word
on RxDataHS[15:0] was produced by a group of seven
symbols that were not a valid code word. This is an
indication that the data word being output has a low
confidence of being correct. RxInvalidCodeHS is not
active when either the Sync Word or the Post Pattern is
presented to the De-Mapper.
RxValidHS O SFXX High-Speed Receive Data Valid.
This active high signal indicates that the lane module is
driving data to the protocol layer on the RxDataHS
output. There is no “RxReadyHS” signal, and the protocol
layer is expected to capture RxDataHS on every rising
edge of RxWordClkHS where RxValidHS is asserted.
There is no provision for the protocol layer to slow down
(“throttle”) the receive data.
RxActiveHS O SFXX High-Speed Reception Active.
This active high signal indicates that the lane module is
actively receiving a high-speed transmission from the
Lane interconnect.
RxSyncHS O SFXX Receiver Synchronization Observed.
This active high signal indicates that the lane module has
detected the 7-symbol sync word in the received data. In
a typical high-speed transmission, RxSyncHS is high for
one cycle of RxWordClkHS at the beginning of a high-
speed transmission when RxActiveHS is first asserted,
and also prior to redundant packet headers that may
appear in the data burst.
Escape Mode Transmit Signals
TxClkEsc I MXXX Escape mode Transmit Clock.
SXXY This clock is directly used to generate escape sequences.
The period of this clock determines the phase times for
low-power signals as defined in Section 6.6.2. It is
therefore constrained by the normative part of the C-PHY
specification. See Section 9. Note that this clock is used
to synchronize TurnRequest and is included for any
module that supports bi-directional high-speed operation,
even if that module does not support transmit or
bidirectional escape mode.
TxRequestEsc I MXXX Escape mode Transmit Request.
SXXY This active high signal, asserted together with exactly one
of TxLpdtEsc, TxUlpsEsc, or one bit of TxTriggerEsc, is
used to request entry into escape mode. Once in escape
mode, the Lane stays in escape mode until
TxRequestEsc is de-asserted. TxRequestEsc is only
asserted by the protocol layer while TxRequestHS is low.

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TxLpdtEsc I MXAX Escape mode Transmit Low-Power Data.
SXXA This active high signal is asserted with TxRequestEsc to
cause the lane module to enter low-power data
transmission mode. The lane module remains in this
mode until TxRequestEsc is de-asserted.
TxUlpsEsc and all bits of TxTriggerEsc are low when
TxLpdtEsc is asserted.
TxUlpsExit I MXXX Transmit ULP Exit Sequence.
SXXY This active high signal is asserted when ULP state is
active and the protocol layer is ready to leave ULP state.
The PHY leaves ULP state and begins driving Mark-1
after TxUlpsExit is asserted. The PHY later drives the
Stop state (LP-111) when TxRequestEsc is deasserted.
TxUlpsExit is synchronous to TxClkEsc.
This signal is ignored when the Lane is not in the ULP
State.
TxUlpsEsc I MXXX Escape mode Transmit Ultra-Low Power State.
SXXY This active high signal is asserted with TxRequestEsc to
cause the lane module to enter the Ultra-Low Power
State. The lane module remains in this mode until
TxRequestEsc is de-asserted.
TxLpdtEsc and all bits of TxTriggerEsc are low when
TxUlpsEsc is asserted.
TxTriggerEsc[3:0] I MXXX Escape mode Transmit Trigger 0-3.
SXXY One of these active high signals is asserted with
TxRequestEsc to cause the associated Trigger to be sent
across the Lane interconnect. In the receiving lane
module, the same bit of RxTriggerEsc is then asserted
and remains asserted until the Lane interconnect returns
to Stop state, which happens when TxRequestEsc is de-
asserted at the transmitter.
Only one bit of TxTriggerEsc is asserted at any time, and
only when TxLpdtEsc and TxUlpsEsc are both low.
TxDataEsc[7:0] I MXAX Escape mode Transmit Data.
SXXA This is the eight bit escape mode data to be transmitted
in low-power data transmission mode. The signal
connected to TxDataEsc[0] is transmitted first. Data is
captured on rising edges of TxClkEsc.
TxValidEsc I MXAX Escape mode Transmit Data Valid.
SXXA This active high signal indicates that the protocol layer is
driving valid data on TxDataEsc to be transmitted. The
lane module accepts the data when TxRequestEsc,
TxValidEsc and TxReadyEsc are all active on the same
rising TxClkEsc clock edge.
TxReadyEsc O MXAX Escape mode Transmit Ready.
SXXA This active high signal indicates that TxDataEsc is
accepted by the lane module to be serially transmitted.
TxReadyEsc is valid on rising edges of TxClkEsc.

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Escape Mode Receive Signals
RxClkEsc O MXXY Escape mode Receive Clock.
SXXX This signal is used to transfer received data to the
protocol layer during escape mode. This “clock” is
generated from the two low-power signals in the Lane
interconnect. Because of the asynchronous nature of
escape mode data transmission, this “clock” may not be
periodic.
RxLpdtEsc O MXXA Escape Low-Power Data Receive mode.
SXAX This active high signal is asserted to indicate that the lane
module is in low-power data receive mode. While in this
mode, received data bytes are driven onto the
RxDataEsc output when RxValidEsc is active. The lane
module remains in this mode with RxLpdtEsc asserted
until a Stop state is detected on the Lane interconnect.
RxUlpsEsc O MXXY Escape Ultra-Low Power (Receive) mode.
SXXX This active high signal is asserted to indicate that the lane
module has entered the Ultra-Low Power State. The lane
module remains in this mode with RxUlpsEsc asserted
until a Stop state is detected on the Lane interconnect.
RxTriggerEsc[3:0] O MXXY Escape mode Receive Trigger 0-3.
SXXX These active high signals indicate that a trigger event has
been received. The asserted RxTriggerEsc signal
remains active until a Stop state is detected on the Lane
interconnect.
RxDataEsc[7:0] O MXXA Escape mode Receive Data.
SXAX This is the eight-bit escape mode low-power data
received by the lane module. The signal connected to
RxDataEsc[0] was received first. Data is transferred on
rising edges of RxClkEsc.
RxValidEsc O MXXA Escape mode Receive Data Valid.
SXAX This active high signal indicates that the lane module is
driving valid data to the protocol layer on the RxDataEsc
output. There is no “RxReadyEsc” signal, and the
protocol layer is expected to capture RxDataEsc on every
rising edge of RxClkEsc where RxValidEsc is asserted.
There is no provision for the protocol layer to slow down
(“throttle”) the receive data.
Control Signals
TurnRequest I XRXX Turn Around Request.
XFXY This active high signal is used to indicate that the protocol
layer desires to turn the Lane around, allowing the other
side to begin transmission. TurnRequest is valid on rising
edges of TxClkEsc. TurnRequest is only meaningful for a
lane module that is currently the transmitter (Direction=0).
If the lane module is in receive mode (Direction=1), this
signal is ignored.

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Direction O XRXX Transmit/Receive Direction.
XFXY This signal is used to indicate the current direction of the
Lane interconnect. When Direction=0, the Lane is in
transmit mode (0=Output). When Direction=1, the Lane is
in receive mode (1=Input).
TurnDisable I XRXX Disable Turn-around.
XFXY This signal is used to prevent a (bi-directional) Lane from
going into transmit mode – even if it observes a turn-
around request on the Lane interconnect. This is useful to
prevent a potential “lock-up” situation when a
unidirectional lane module is connected to a bidirectional
lane module.
ForceRxmode I MRXX Force Lane Module Into Receive mode / Wait for Stop
MXXY state.
SXXX This signal allows the protocol layer to initialize a lane
module, or force a bi-directional lane module, into receive
mode. This signal is used during initialization or to resolve
a contention situation. When this signal is high, the lane
module immediately transitions into receive control mode
and waits for a Stop state to appear on the Lane
interconnect. When used for initialization, this signal is
released, i.e. driven low, only when the Dp & Dn inputs
are in Stop state for time tINIT, or longer.
ForceTxStopmode I MXXX Force Lane Module Into Transmit mode / Generate Stop
SRXX state.
SXXY This signal allows the protocol layer to force a lane
module into transmit mode and Stop state during
initialization or following an error situation, e.g. expired
time out. When this signal is high, the lane module
immediately transitions into transmit mode and the
module state machine is forced into the Stop state.
Stopstate O XXXX Lane is in Stop state.
This active high signal indicates that the lane module,
regardless of whether the lane module is a transmitter or
a receiver, is currently in Stop state. Note that this signal
is asynchronous to any clock in the PPI interface. Also,
the protocol layer may use this signal to indirectly
determine if the PHY line levels are in the LP-111 state.
Enable I XXXX Enable Lane Module.
This active high signal forces the lane module out of
“shutdown”. All line drivers, receivers, terminators, and
contention detectors are turned off when Enable is low.
Furthermore, while Enable is low, all other PPI inputs are
ignored and all PPI outputs are driven to the default
inactive state. Enable is a level sensitive signal and does
not depend on any clock.

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UlpsActiveNot O XXXX ULP State (not) Active.
This active low signal is asserted to indicate that the Lane
is in ULP state.
For a transmitter, this signal is asserted sometime after
TxUlpsEsc and TxRequestEsc are asserted. The
transmitting PHY continues to supply TxClkEsc until
UlpsActiveNot is asserted. In order to leave ULP state,
the transmitter first drives TxUlpsExit high, then waits for
UlpsActiveNot to become high (inactive). At that point, the
transmitting PHY is active and has started transmitting a
Mark-1 on the lines. The protocol layer waits for time
twakeup and then drives TxRequestEsc inactive to return
the Lane to Stop state.
For a receiver, this signal indicates that the Lane is in
ULP state. At the beginning of ULP state, UlpsActiveNot
is asserted together with RxUlpsEsc. At the end of the
ULP state, this signal becomes inactive to indicate that
the Mark-1 state has been observed. Later, after a period
of time twakeup, the RxUlpsEsc signal is deasserted.
Error Signals
ErrSotHS O MRXX Start-of-Transmission (SoT) Error.
SXXX If the high-speed SoT Sync Word is corrupted, by having
the least-significant symbol of the 3444443 pattern not
equal to 3, this active high signal is asserted for one cycle
of RxWordClkHS. This is considered to be a “soft error” in
the Sync Word and confidence in the payload data is
reduced.
ErrSotSyncHS O MRXX Start-of-Transmission Synchronization Error.
SXXX If the high-speed SoT Sync Word is corrupted in a way
that proper synchronization cannot be expected, this
active high signal is asserted for one cycle of
RxWordClkHS. (Considered optional, this is an extremely
low-probability event.)
ErrEsc O MXXY Escape Entry Error.
SXXX If an unrecognized escape entry command is received,
this active high signal is asserted and remains asserted
until the next change in line state.
ErrSyncEsc O MXXA Low-Power Data Transmission Synchronization Error.
SXAX If the number of bits received during a low-power data
transmission is not a multiple of eight when the
transmission ends, this active high signal is asserted and
remains asserted until the next change in line state.
ErrControl O MXXY Control Error.
SXXX This active high signal is asserted when an incorrect line
state sequence is detected. For example, if a turn-around
request or escape mode request is immediately followed
by a Stop state instead of the required Bridge state, this
signal is asserted and remains asserted until the next
change in line state.

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ErrContentionLP0 O MXXX LP0 Contention Error.
SXXY This active high signal is asserted when the lane module
detects a contention situation on a line while trying to
drive the line low.
ErrContentionLP1 O MXXX LP1 Contention Error.
SXXY This active high signal is asserted when the lane module
detects a contention situation on a line while trying to
drive the line high.
A.2 High-Speed Transmit from the Master Side

1616 Figure 70 shows an example of a high-speed transmission on the master side. While TxRequestHS is low,
1617 the lane module ignores the value of TxDataHS. To begin transmission, the protocol layer drives TxDataHS
1618 with the first word of data and asserts TxRequestHS. This data word is accepted by the PHY on the first
1619 rising edge of TxWordClkHS with TxReadyHS also asserted. At this point, the protocol logic drives the next
1620 data word onto TxDataHS. After every rising clock cycle with TxReadyHS active, the protocol layer supplies
1621 a new valid data word or ends the transmission. After the last data word has been transferred to the lane
1622 module, TxRequestHS is driven low to cause the lane module to stop the transmission and enter Stop state.
1623 The minimum number of words transmitted could be as small as one.
TxWordClkHS
TxDataHS W1 W2 W3 dc W4 W5 Wn
TxSendSyncHS
TxRequestHS
TxReadyHS
Start-up Shut-down
1624 Time Time
Figure 70 Example High-Speed Transmission from the Master Side
A.3 High-Speed Receive at the Slave Side

1625 Figure 71 shows an example of a high-speed reception at the slave side. The RxActiveHS signal indicates
1626 that a receive operation is occurring. A normal reception starts with a pulse on RxSyncHS followed by valid
1627 receive data on subsequent cycles of RxWordClkHS. Note that the protocol layer is prepared to receive all of
1628 the data. There is no method for the receiving protocol to pause or slow data reception.
1629 If EoT Processing is performed inside the PHY, the RxActiveHS and RxValidHS signals transition low
1630 following the last valid data word, Wn. Refer to Figure 71.
1631 If EoT processing is not performed in the PHY, one or more additional words are presented after the last valid
1632 data word. The first of these additional words, shown as word “C” in Figure 71, is all ones or all zeros.
1633 Subsequent words may or may not be present, and can have any value. For a PHY that does not perform EoT
1634 processing, the RxActiveHS and RxValidHS signals transition low simultaneously sometime after word “C”
1635 is received. Once these signals have transitioned low, they remain low until the next high-speed data reception
1636 begins.

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RxWordClkHS
RxDataHS W1 W2 W3 dc W4 W5 Wn C
RxInvalidCodeHS
RxActiveHS
RxValidHS
RxSyncHS
1637
Figure 71 Example High-Speed Receive at the Slave Side
1638 For D-PHY PPI compatibility, it is recommended that RxWordClkHS toggle continuously while the
1639 high-speed signal is present. An option shown in the waveform above is to prevent RxWordClk from
1640 toggling while RxActiveHS is inactive.
A.4 (Not Used)

1641 Note:
A.5 (Not Used)

1644 Note:
A.6 Low-Power Data Transmission

1647 Furthermore, while the high-speed interface signal TxRequestHS serves as both a transmit request and a data
1648 valid signal, on the low-power interface two separate signals are used. The protocol layer directs the Lane to
1649 enter low-power data transmission escape mode by asserting TxRequestEsc with TxLpdtEsc high. The low-
1650 power transmit data is transferred on the TxDataEsc lines when TxValidEsc and TxReadyEsc are both active
1651 at a rising edge of TxClkEsc. The byte is transmitted in the time after the TxDataEsc is accepted by the lane
1652 module (TxValidEsc = TxReadyEsc = high) and therefore the TxClkEsc continues running for some
1653 minimum time after the last byte is transmitted. The protocol layer knows the byte transmission is finished
1654 when TxReadyEsc is asserted. After the last byte has been transmitted, the protocol layer de-asserts
1655 TxRequestEsc to end the low-power data transmission. This causes TxReadyEsc to return low, after which
1656 the TxClkEsc clock is no longer needed. Whenever TxRequestEsc transitions from high-to-low, it always
1657 remains in the low state for a minimum of two TxClkEsc clock cycles. Figure 72 shows an example low-
1658 power data transmission operation.

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Clock No
Longer Required
TxClkEsc
TxDataEsc D1 D2 D3 Dn
TxRequestEsc
TxLpdtEsc
TxValidEsc
TxReadyEsc
1659 Start-up Time Transmit Last Byte
Figure 72 Low-Power Data Transmission
A.7 Low-Power Data Reception

1660 Figure 73 shows an example low-power data reception. In this example, a low-power escape “clock” is
1661 generated from the lane interconnect by the logical exclusive-OR of the “A” and “C” signals. This “clock”
1662 is used within the lane module to capture the transmitted data. In this example, the “clock” is also used to
1663 generate RxClkEsc.
1664 The signal RxLpdtEsc is asserted when the escape entry command is detected and stays high until the Lane
1665 returns to the Stop state, indicating that the transmission has finished. It is important to note that because of
1666 the asynchronous nature of escape mode transmission, the RxClkEsc signal can stop at any time in either the
1667 high or low state. This is most likely to happen just after a byte has been received, but it could happen at
1668 other times as well.
Uncommon
but possible Common
RxClkEsc
RxDataEsc D1 D2 Dn
RxLpdtEsc
RxValidEsc
1669
Figure 73 Example Low-Power Data Reception
A.8 Turn-around
1670 If the master side and slave side lane modules are both bi-directional, it is possible to turn around the link for
1671 high-speed and/or escape mode signaling. Section 6.5 explains how it is determined which side is allowed to
1672 transmit by passing a “token” back and forth. That is, the side currently transmitting passes the token to the
1673 receiving side. If the receiving side acknowledges the turn-around request, as indicated by driving the
1674 appropriate line state, the direction is switched.

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1675 Figure 74 shows an example of two turn-around events. At the beginning, the local side is the transmitter, as
1676 shown by Direction=0. When the protocol layer on this side wishes to turn the Lane around (i.e. give the
1677 token to the other side), it asserts TurnRequest for at least one cycle of TxClkEsc. This initiates the turn-
1678 around procedure. The remote side acknowledges the turn-around request by driving the appropriate states
1679 on the lines. When this happens, the local Direction signal changes from transmit (0) to receive (1).
1680 Later in the example of Figure 62, the remote side initiates a turn-around request, passing the token back to
1681 the local side. When this happens, the local Direction signal changes back to transmit (0). Note that there is
1682 no prescribed way for a receiver to request access to the link. The current transmitter is in control of the link
1683 direction and decides when to turn the link around, passing control to the receiver.
1684 If the remote side does not acknowledge the turn-around request, the Direction signal does not change.
TxClkEsc
TurnRequest
Direction
(local) (transmit) (receive) (transmit)
Direction (receive) (transmit) (receive)

(remote)
1685
Figure 74 Example Turn-around Actions Transmit-to-Receive and Back to Transmit

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Annex B Interconnect Design Guidelines (informative)

B.1 Practical Distances
1686 The maximum Lane flight time is defined at two nanoseconds. Assuming less than 100ps wiring delay within
1687 the RX-TX modules each, the physical distance that can be bridged with external interconnect is around
1688 54cm/√ε. For most practical PCB and flex materials this corresponds to maximum distances around 25-30
1689 cm.
B.2 RF Frequency Bands: Interference

1690 The most common concern is the case where emissions from the interface are in the same frequency band as
1691 the wireless signal, and the emissions act as a jammer that degrades reception of the intended signal at the
1692 wireless receiver. The path of this interference is illustrated in Figure 75.
EMI, Flex to Antenna
RF metal shield Baseband metal shield

PWB
Camera
Flex Conn
Flex Circuit
Camera
LNA C-PHY Rx (CSI signals) Module
RF Tx/Rx Baseband
Chip Chip
Display
Flex Conn
Flex Circuit
Display
C-PHY Tx
PA
(DSI signals) Module
EMI, Flex to Antenna

1693
Figure 75 Radio Interference from Serial Interface Connections
1694 The reverse of this path is also a possible concern, where a signal transmitted by the wireless transceiver is
1695 coupled to the serial interface signals in such a manner that it cannot be rejected by the common mode
1696 rejection capability of the serial interface receiver. It is also possible that the signal transmitted by the wireless
1697 transceiver is coupled in a manner that it produces an unintended differential mode signal at the serial
1698 interface receiver. Specific concerns are described below.
B.2.1 Specific Recommendations Regarding EMI and EMC

1699 In terms of sensitivity:
1700 • RX (downlink) is more of concern than TX (but TX might have to be considered for EMC)
1701 • GNSS systems are almost always at sensitivity level (it is rare to get close to a satellite!) => they
1702 are the priority for EMI design
1703 • In order of sensitivity: GNSS > Cellular > Connectivity
1704 • Wide band systems (WCDMA/LTE/WiFi) are less sensitive to clock spurs than narrow band
1705 systems (GSM/Bluetooth/FM)
1706 EMI design of MIPI interfaces
1707 • Clock forwarded system (D-PHY) should avoid clock and its harmonics to fall in GNSS system
1708 bands then when feasible it should also avoid GSM bands (2, 3, 5, 8) and Bluetooth (although with
1709 frequency hopping Bluetooth is relatively robust), WCDMA, LTE and WiFi bands are less of a
1710 concern

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1711 • For others (C-PHY/M-PHY) when frequency is low enough it should try to have a null in GNSS
1712 bands
1713 • Noise whitening techniques are essential for data lanes to avoid energy to peak in undesired bands
1714 (note though that even for CSI and DSI that data is pretty random)
1715 Implication for current specs
1716 • Most bands being covered by first lobe of interface, slew control as very little benefit for interface
1717 > 1.5Gbps/GSs/lane
1718 • Above G1 M-PHY has no real need to keep fixed frequencies for gears
1719 Table 36 Cellular Bands Used by Mobile Devices

Downlink Uplink
MS RX (EMI) MS TX (EMC)
Band Flow Fhigh Flow Fhigh Duplex Common Name / region
Band 1 2110.0 2170.0 1920.0 1980.0 FDD IMT / EU-Asia
Band 2 1930.0 1990.0 1850.0 1910.0 FDD PCS / US
Band 3 1805.0 1880.0 1710.0 1785.0 FDD DCS /EU-Asia
Band 4 2110.0 2155.0 1710.0 1755.0 FDD AWS-1 / US
Band 5 869.0 894.0 824.0 849.0 FDD CLR / US
Band 6 875.0 885.0 830.0 840.0 FDD UMTS 800 / Japan
Band 7 2620.0 2690.0 2500.0 2570.0 FDD IMT / EU
Band 8 925.0 960.0 880.0 915.0 FDD E-GSM / EU-Asia
Band 9 1844.9 1879.9 1749.9 1784.9 FDD UMTS 1700 / Japan DCS
Band 10 2110.0 2170.0 1710.0 1770.0 FDD Extended AWS / US
Band 11 1475.9 1495.9 1427.9 1447.9 FDD Lower PDC / Japan
Band 12 729.0 746.0 699.0 716.0 FDD Lower SMH blocks A,B,C / US
Band 13 746.0 756.0 777.0 787.0 FDD Upper SMH block C / US
Band 14 758.0 768.0 788.0 798.0 FDD Upper SMH block D / US
Band 15 2600.0 2620.0 1900.0 1920.0 FDD Reserved
Band 16 2585.0 2600.0 2010.0 2025.0 FDD Reserved
Band 17 734.0 746.0 704.0 716.0 FDD Lower SMH blocks B,C / US
Band 18 860.0 875.0 815.0 830.0 FDD lower 800 / Japan
Band 19 875.0 890.0 830.0 845.0 FDD upper 800 / Japan
Band 20 791.0 821.0 832.0 862.0 FDD Digital Dividend / EU
Band 21 1495.9 1510.9 1447.9 1462.9 FDD Upper PDC / Japan
Band 22 3510.0 3590.0 3410.0 3490.0 FDD
Band 23 2180.0 2200.0 2000.0 2020.0 FDD S-Band
Band 24 1525.0 1559.0 1626.5 1660.5 FDD L-Band
Band 25 1930.0 1995.0 1850.0 1915.0 FDD Extended PCS / US
Band 26 859.0 894.0 814.0 849.0 FDD Extended CLR / US
Band 27 852.0 869.0 807.0 824.0 FDD SMR
Band 28 758.0 803.0 703.0 748.0 FDD / APAC
Band 29 716.0 728.0 n/a n/a FDD Lower SMH blocks D,E / US

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05-Aug-2014
Downlink Uplink
Band Flow Fhigh Flow Fhigh Duplex Common Name / region
Band 30 2350.0 2360.0 2305.0 2315.0 FDD WCS blocks A,B / US
Band 31 462.5 467.5 452.5 457.5 FDD
AWS-2 1995.0 2000.0 1915.0 1920.0 FDD AWS-2 / US
AWS-3 2155.0 2180.0 1755.0 1780.0 FDD AWS-3 / US
Band iDEN 851.0 869.0 806.0 824.0 FDD iDEN / US
Band 33 1900.0 1920.0 1900.0 1920.0 TDD IMT / China
Band 34 2010.0 2025.0 2010.0 2025.0 TDD IMT / China
Band 35 1850.0 1910.0 1850.0 1910.0 TDD PCS (Uplink) / US
Band 36 1930.0 1990.0 1930.0 1990.0 TDD PCS (Downlink) / US
Band 37 1910.0 1930.0 1910.0 1930.0 TDD PCS (Duplex spacing) / US
Band 38 2570.0 2620.0 2570.0 2620.0 TDD IMT / EU-Asia
Band 39 1880.0 1920.0 1880.0 1920.0 TDD / China
Band 40 2300.0 2400.0 2300.0 2400.0 TDD CM / China
Band 41 2496.0 2696.0 2496.0 2696.0 TDD BRS / EBS
Band 42 3400.0 3600.0 3400.0 3600.0 TDD
Band 43 3600.0 3800.0 3600.0 3800.0 TDD
Band 44 703.0 803.0 703.0 803.0 TDD APAC
Note:
All frequencies in MHz

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05-Aug-2014
Table 37 GNSS and Connectivity Bands Used by Mobile Devices

Downlink Uplink
System Band Flow Fhigh Flow Fhigh Duplex Common Name / region
GNSS GPS L1 1574.4 1576.4 na na na / WW
GNSS Glonass 1597.5 1606.5 na na na / WW
GNSS Compass 1560.1 1562.1 na na na / Asia -> WW
GNSS Galileo 1573.4 1577.5 na na na in deployment
Connectivity Bluetooth 2400.0 2483.0 2400.0 2483.0 TDD ISM / WW
Connectivity 802.11b/g/n/ac 2400.0 2483.0 2400.0 2483.0 TDD ISM / WW
Connectivity 802.11a/ac 4915.0 5825.0 4915.0 5825.0 TDD / WW
Connectivity 802.11.ad 57000.0 66000.0 57000.0 66000.0 TDD ISM / WW
Connectivity 802.11.af 54.0 790.0 54.0 790.0 TDD White space WiFi
RFID NFC 13.6 13.6 13.6 13.6 TDD / WW
Audio Broadcast FM 78.0 108.0 78.0 108.0 TDD / WW
Audio Broadcast FM 65.8 74.0 65.8 74.0 TDD / Russia
Audio Broadcast FM 76.0 90.0 76.0 90.0 TDD / Japan
Audio Broadcast DAB-VHF3 174.0 240.0 na na na / EU
Audio Broadcast DAB-L 1452.0 1492.0 na na na / US
Video Broadcast CMMB 470.0 860.0 na na na / China
Note:
All frequencies in MHz

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1720 It is important to identify the lowest interference frequency with significant impact, as this sets ‘fINT,MIN’. For
1721 this specification, fINT,MIN is decided to be 450 MHz, because it is identified as the lowest frequency of interest
1722 in the tables above.
B.3 Transmission Line Design

1723 In most cases the transmission lines will either be designed as striplines and/or micro-striplines. The coupling
1724 between neighboring lines within a pair is small if the distance between them is >2x the dielectric thickness.
1725 For the separation of multiple pairs it is highly recommended to interleave the pairs with a ground or supply
1726 line in order to reduce coupling.
B.4 Reference Layer

1727 In order to achieve good signal integrity and low EMI it is recommended that either a ground plane or a
1728 ground signal is in close proximity of any signal line.
B.5 Printed-Circuit Board

1729 For boards with a large number of conductor layers the dielectric spacing between layers may become so
1730 small that it would be hard to meet the characteristic impedance requirements. In those cases a micro-stripline
1731 in the top or bottom layers may be a better solution. Hybrids consisting of a combination of micro-stripline
1732 and stripline are also viable solutions. A short segment of micro-stripline might be used near the driving or
1733 receiving IC where trace routing may be more intense. Then a short distance away a stripline may be the best
1734 option. Hybrid combinations of three-wire lanes have been evaluated with good results.
B.6 Flex Circuits

1735 Either two conductor layers or a reasonable connected cover layer makes it much easier to meet the
1736 specifications.
B.7 Series Resistance

1737 The DC series resistance of the interconnect should be less than 5 Ohms in order to meet the specifications.
1738 It is strongly recommended to keep the resistance in the ground connection below 0.2 Ohm. Furthermore, it
1739 is recommended that the DC ground shift be less than 50mV, which may require an even lower value if a
1740 large current is flowing through this ground. The lower this ground series resistance value can be made, the
1741 better it is for reliability and robustness.
B.8 Connectors
1742 Connectors usually cause some impedance discontinuity. It is important to carefully minimize these
1743 discontinuities by design, especially with respect to the through-connection of the reference layer. Although
1744 connectors are typically rather small in size, the wrong choice can mess-up signals completely. Please note
1745 that the contact resistance of connectors is part of the total series resistance budget and should therefore be
1746 sufficiently low.

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05-Aug-2014
Participants
The following list includes those persons who participated in the Working Group that developed this
Specification and who consented to appear on this list.
Ahmed Aboulella, Mixel, Inc. Thomas Marik, BitifEye Digital Test Solutions GmbH
Mario Ackers, Toshiba Corporation Raj Kumar Nagpal, STMicroelectronics
Bhupendra Ahuja, NVIDIA Kinshuk Parekh, Cadence Design Systems, Inc.
Andrew Baldman, University of New Hampshire Joao Pereira, Synopsys, Inc
InterOperability Lab (UNH-IOL)
Dominique Brunel, STMicroelectronics Duane Quiet, Intel Corporation
Mara Carvalho, Synopsys, Inc John Raitz, The Moving Pixel Company
Min-Jie Chong, Agilent Technologies Inc. Parthasarathy Raju, Tektronix, Inc
Doug Day, Toshiba Corporation P. E. Ramesh, Tektronix, Inc
Kirill Dimitrov, SanDisk Corporation Jim Rippie, MIPI Alliance, Inc. (staff)
Keyur Diwan, Tektronix, Inc Ravi Rudraraju, Intel Corporation
Ken Drottar, Intel Corporation Joseph Schachner, LeCroy Corporation
Mahmoud El-Banna, Mixel, Inc. Omer Schori, Cadence Design Systems, Inc.
Michael Fleischer-Reumann, Agilent Technologies Jos Sebastian, GDA Technologies
Inc.
Ralf Gaisbauer, Toshiba Corporation Sho Sengoku, Qualcomm Incorporated
Mohamed Hafed, Introspect Test Technology Inc. Sergio Silva, Synopsys, Inc
Will Harris, Advanced Micro Devices, Inc. Scott Silver, The Moving Pixel Company
Hiroaki Hayashi, Sony Corporation Bill Simms, NVIDIA
Henrik Icking, Intel Corporation Dong Hyun Song, SK Hynix
Tom Kopet, Aptina Imaging Corporation Tatsuya Sugioka, Sony Corporation
Marcin Kowalewski, Synopsys, Inc Haran Thanigasalam, Intel Corporation
Amit Laknaur, NVIDIA Aravind Vijayakumar, Cadence Design Systems, Inc.
C. K. Lee, Qualcomm Incorporated Manuel Weber, Toshiba Corporation
Jason Lee, NVIDIA Rick Wietfeldt, Qualcomm Incorporated
Delbert Liao, MediaTek Inc. George Wiley, Qualcomm Incorporated
Kenneth Ma, Broadcom Corporation Charles Wu, OmniVision Technologies, Inc.
Jiri Macku, Silicon Line GmbH

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Specification for

Version 1.0 – 05 August 2014

Copyright © 2013-2014 MIPI Alliance, Inc.

Copyright © 2013-2014 MIPI Alliance, Inc.

Copyright © 2013-2014 MIPI Alliance, Inc.

ii Copyright © 2013-2014 MIPI Alliance, Inc.

Copyright © 2013-2014 MIPI Alliance, Inc. iii

6.6.3 Ultra-Low Power State ............................................................................................... 45

iv Copyright © 2013-2014 MIPI Alliance, Inc.

9.1.1 High-Speed Transmitter.............................................................................................. 61

Copyright © 2013-2014 MIPI Alliance, Inc. v

12.4.19 RLRn_1st_Sym_Err_Loc_1 ................................................................................... 96

vi Copyright © 2013-2014 MIPI Alliance, Inc.

Copyright © 2013-2014 MIPI Alliance, Inc. vii

Figure 32 Point-to-point Interconnect ............................................................................................ 55

viii Copyright © 2013-2014 MIPI Alliance, Inc.

Copyright © 2013-2014 MIPI Alliance, Inc. ix

x Copyright © 2013-2014 MIPI Alliance, Inc.

Table 32 Unit Interval (UI) Specification ....................................................................................... 77

Copyright © 2013-2014 MIPI Alliance, Inc. xi

2014-Oct-07 V1.0 Initial Board Approved Release.

xii Copyright © 2013-2014 MIPI Alliance, Inc.

Copyright © 2013-2014 MIPI Alliance, Inc. 1

46 • Specification of the PHY-Protocol Interface. The C-PHY specification includes a PHY-Protocol

2 Copyright © 2013-2014 MIPI Alliance, Inc.

2.1 Use of Special Terms

Copyright © 2013-2014 MIPI Alliance, Inc. 3

4 Copyright © 2013-2014 MIPI Alliance, Inc.

146 PHY Physical Layer

Copyright © 2013-2014 MIPI Alliance, Inc. 5

6 Copyright © 2013-2014 MIPI Alliance, Inc.

4.1 Summary of PHY Functionality

4.1.1 Summary of Lane Signaling States

Copyright © 2013-2014 MIPI Alliance, Inc. 7

Positive Polarity States Negative Polarity States

8 Copyright © 2013-2014 MIPI Alliance, Inc.

4.1.2 Representation of Symbols in High-Speed Mode

Copyright © 2013-2014 MIPI Alliance, Inc. 9

4.1.3 Representation of High-Speed Signaling States

Take in 16 bits, generate 7 symbols Receive 7 symbols, output 16 bits

16-bit word, output

4.2 Mandatory Functionality

10 Copyright © 2013-2014 MIPI Alliance, Inc.

5.1 Lane Modules

Copyright © 2013-2014 MIPI Alliance, Inc. 11

5.2 Master and Slave

5.3 High Frequency Clock Generation

5.4 Lanes and the PHY-Protocol Interface

12 Copyright © 2013-2014 MIPI Alliance, Inc.

PPI C-PHY C-PHY PPI

APPI PPI C-PHY C-PHY PPI APPI

5.5 Selectable Lane Options

Copyright © 2013-2014 MIPI Alliance, Inc. 13

What is max HS bit rate per lane

Determine max momentary bandwidth and concurrency

Decide on using LPDT

Full Escape mode support

14 Copyright © 2013-2014 MIPI Alliance, Inc.

5.6 Lane Module Types