Open-Access Analog IC Design

Tutorial Series

Hasantha Malavipathirana / Masoume Akbari / Hooman Reyhani

 Overview
1. Motivation & Plans
2. Proposed Specifications
3. ADC Metrics
4. Generic ADC Architectures
5. Publication Survey
6. Architecture Outline
7. Main Building Blocks
8. Block Design
9. Top-Level Simulations
10. Conclusions

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 2

 Overview
1. Motivation & Plans
2. Proposed Specifications
3. ADC Metrics
4. Generic ADC Architectures
5. Publication Survey
6. Architecture Outline
7. Main Building Blocks
8. Block Design
9. Top-Level Simulations
10. Conclusions

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 3

 Motivation & Plans
• Share analog & mixed-signal IC design know-how
• By-product of "Nanoscale Analog IC Design" online course, Sept. 2021
• Encourage next generation of IC design engineers
• Publish series of online tutorials with some hands-on activities
• Outline procedure for designing generic Analog-to-Digital Converter (ADC)
• Host live-virtual design review primarily for undergrad/postgrad students

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 4

 Overview
1. Motivation & Plans
2. Proposed Specifications
3. ADC Metrics
4. Generic ADC Architectures
5. Publication Survey
6. Architecture Outline
7. Main Building Blocks
8. Block Design
9. Top-Level Simulations
10. Conclusions

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 5

 Data Converters
• Data Converters enable measurement & control of “analog” world around us
• Light, weight, sound can be digitised via Analog-to-Digital Converters (ADC)
• Digital information manipulated, stored, transmitted by Digital Processor
• Digital-to-Analog Converters (DAC) recreate “analog” output control signal

[https://commons.wikimedia.org]

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 Data Converters Applications
• Consumer Electronics: Audio, TV, Video, Cameras, Appliances, Toys
• Communications: Mobile Phones, Routers, Modems, Networking
• Computing & Control: Storage Media, Sound Cards; Data Centres
• Instrumentation: Lab Equipment, Scientific Equipment, Medical Equipment
• Data Converters:
– Continuous improvement in performance required for emerging applications
– Key enabling technology to realize complex System-on-Chip (SoC)

ADC DAC

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 Proposed ADC Specifications
• Resolution: 10-bits
• Input Voltage: 2V pk-pk diff.
• LSB(diff): Vref/210 = 2V/1024 ≈ 2mV
• Sampling Frequency (Fs): 500kSPS
• Input Bandwidth (Fin): DC – 250kHz
• Signal-to-Noise-Distortion-Ratio (SNDR) > 59dB
• Effective-Number-Of-Bits (ENOB) > 9.5-Bits
• No Missing Codes: DNL < 1LSB
• Power-Supply: 1.8V + 10%
• Power Consumption < 1mW
• Junction Temperature Range: 0°C to +85°C
• Technology: 0.18um CMOS
• Simulation Tool: LTspice

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 8

 Overview
1. Motivation & Plans
2. Proposed Specifications
3. ADC Metrics
4. Generic ADC Architectures
5. Publication Survey
6. Architecture Outline
7. Main Building Blocks
8. Block Design
9. Top-Level Simulations
10. Conclusions

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 9

 ADC Metrics
• Resolution
• Input Voltage
• Transfer Function
• Quantization Error
• DNL & INL
• Sampling Frequency
• SNR, SNDR, ENOB & SFDR

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 Resolution
• ADC resolution is defined as smallest incremental voltage that causes
change in digital output
• Expressed as number of bits output by ADC
• ADC converting analog signal to 10-bit digital value has resolution of 10 bits
• Smallest incremental voltage that can be recognized is called “LSB”
• LSB = Least Significant Bit
• 1LSB = Vref/2n
where Vref = Reference Voltage & n = Number of ADC digital output bits
• For Vref = 2V ➔ Resolution = LSB = 2/210 = 2/1024 ≈ 2mV

[Carusone, “Analog Integrated Circuit Design”, 2012]

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 Input Voltage
• ADC compares analog input voltage (Vin) with reference voltage (Vref)
• Comparison result produced as digital output
• Single-ended (Vin) or differential (Vinp & Vinm)

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 Ideal Transfer Function
• 10-bit ADC with Vref = 2V & LSB ≈ 2mV

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 Quantization Error
• Quantization Error: Difference between analog signal and closest available
digital value at each ADC sampling instant
• Q.E. “introduces” noise, called Quantization Noise, to the sampled signal
• ADC Resolution ↑, Quantization Error ↓ & Quantization Noise ↓
• Δ = Step size (LSB size); εq = Quantization Error
• εq(rms) = LSB/√12

[Murmann, ISSCC 2022]

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 Static Performance Metrics: DNL & INL
• Differential Non-Linearity (DNL)
• DNL error defined as difference between actual step width & ideal 1LSB
• Ideal ADC, with DNL = 0LSB, each analog step equals 1LSB
• DNL < 1LSB results in monotonic transfer function with no missing codes
• Integral Non-Linearity (INL)
• INL error is described as deviation, in LSB or percent of full-scale range
(FSR), of an actual transfer function from a straight line

[Murmann, ISSCC 2022]

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 Sampling Frequency
• ADC takes continuous analog input signal & converts it to discrete digital
output signal by taking regular samples
• These samples represent input signal’s amplitude at specific points in time
• Sampling frequency (Fs) indicates number of samples taken per second
• Nyquist Sampling: Fs>2*Fin
• If Fs<2*Fin ➔ Aliasing will occur

[Analog Devices, “The Data Conversion Handbook”, 2005]

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 Dynamic Performance Metrics
• Signal-to-Noise Ratio (SNR)
• Signal-to-Noise-Distortion Ratio (SNDR)
• Effective Number Of Bits (ENOB)
• Spurious-Free Dynamic range (SFDR)

[Murmann, ISSCC 2022]

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 17

 Overview
1. Motivation & Plans
2. Proposed Specifications
3. ADC Metrics
4. Generic ADC Architectures
5. Publication Survey
6. Architecture Outline
7. Main Building Blocks
8. Block Design
9. Top-Level Simulations
10. Conclusions

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 18

 ADC Architectures
• Nyquist-Rate:
– Single-Step:
• Flash
• Folding
• Interpolating
– Multi-Step:
• Recycling/Subranging
• Pipeline
• Cyclic (Algorithmic)
• Successive Approximation (SAR)
• Asynchronous Binary Search (ABS)
– Integrating/Dual-Slope

• Non-Nyquist-Rate/Oversampling:
– Sigma-Delta

[Razavi, “Principles of Data Conversion System Design”, 1995]

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 Generic Flash ADC

[Razavi, SSCS Magazine, 2017]

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 Flash ADC
• VLSI approach to A/D conversion
• Evaluate input signal all at once
• Very high-speed conversion rate: Sample-Convert-Sample-Convert…
• Distributed sampling ➔ Does not require front-end Sample-and-Hold (SHA)
• 2N-1 Comparators
• Impractical above 8-bit
• Large nonlinear input capacitance, area & power
• Accuracy depends on resistor ladder linearity & comparator offset
• Ladder linearity must be system accurate, i.e. N-bit
• Comparator dynamic offset can be reduced by preamplifier gain
• Preamplifier offset cancelled by storage & cancellation
• Other errors: slew-dependent sampling points, clock jitter, clock dispersion,
metastability, bubbles, sparkle codes
• Techniques to reduce area & power: Interpolation, Folding

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 Flash ADC with Interpolation

[Razavi, SSCS Magazine, 2017]

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani

 Interpolation Technique
• Maintains one-step nature of flash ADC without adding Sample-and-Hold
• Difference between Vin & Vref quantized at output of each preamp
• Number of preamps reduced by interpolating between their outputs
• Substantial reduction of input capacitance, power & area
• Improved linearity (DNL) due to distribution of errors
• Traditionally bipolar but several CMOS implementations reported

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 Flash ADC with Folding

[Razavi, “Principles of Data Conversion System Design”, 1995]

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 Folding Concept
• Maintains one-step nature of flash ADC by using analog preprocessing
• Coarse flash ADC resolves MSBs
• Residue voltage generated by folding circuit & digitized to obtain LSBs
• Both circuits operate in parallel, i.e. residue generated on-the-fly
• Popular architecture due to simplicity & speed
• Eliminate need for SHA, DAC & subtractors
• Traditionally bipolar but several CMOS attempts reported
• Run into difficulties above 6-bit of resolution
• Folding factor “m” results in frequency multiplication
• Bandwidth of folding circuit must be “m” times that of input frequency
• Substantial nonlinearity (DNL) problems
• High frequency inputs cause rounding of folding points ➔ worsen DNL
• Interpolation may be used to reduce DNL errors
• Timing errors between coarse ADC & folding amplifier to be minimized

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 Multi-Step Converters
• Multi-Step ADCs trade speed for power, area & input capacitance
• Combination of SHA, DAC & Amplifier for coarse & fine measurements
• Conversion sequence: Sample-Coarse-DAC-Subtract-Fine-Sample…
• SHA, DAC & Amplifier play crucial role in ADC performance

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 Generic Two-Step ADC

[Razavi, “Principles of Data Conversion System Design”, 1995]

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 Generic Two-Step ADC
• Fewer comparators but requires SHA, DAC & Amplifier
• n-bit ADC comprised of 2x (coarse) & 2y (fine) comparators (n=x+y)
• Coarse ADC comparators can be low-resolution & high-speed
• Fine ADC comparators must be low-offset & n-bit accurate ➔ Slow
• SHA, DAC & inter-stage amplifier must be n-bit accurate
• ADC conversion rate limited by SHA, DAC & amplifier settling-time
• Input capacitance & kickback noise of coarse stage degrade SHA settling
• Nonlinearity errors in first stage can be digitally corrected

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 Two-Step Recycling ADC

[Razavi, “Principles of Data Conversion System Design”, 1995]

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 Two-Step Recycling ADC
• Same flash ADC comparators used for coarse & fine conversions
• Power & area almost halved
• Need low-offset comparators if subtractor has gain of 1
• High-gain subtractor requires op-amp ➔ Increases inter-stage delay

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 Two-Step Subranging ADC

[Razavi, “Principles of Data Conversion System Design”, 1995]

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 Two-Step Subranging ADC
• Eliminates need for explicit subtractor
• Resistor ladder DACs to implement subranging technique
• Coarse ADC identifies & subdivides Vref range around Vin
• Fine ADC compares Vin against new Vref subset
• Inter-stage processing can be slow due to resistor ladder DAC settling-time
• Fine stage comparators must handle full common-mode range of Vin
• They must also maintain constant small input offset

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 Pipeline ADC

[Razavi, “Principles of Data Conversion System Design”, 1995]

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 Pipeline ADC
• Extension of two-step ADC by inserting an inter-stage SHA to hold residue
• Input signal processed in assembly line fashion
• Dedicated hardware for each pipeline stage
• Compact & modular topology
• << 2n Comparators ➔ 10-14 bit implementation practical
• Very efficient usage of area & power
• Bits/stage & capacitor scaling through pipeline optimize area & power
• Linearity affected by SHA offset & gain-error, comparator offset & DAC
• Improve ADC linearity by DEC, auto-zero, averaging & calibration
• ADC speed limited by inter-stage SHA settling-time
• Data latency may be an issue for some applications, e.g. servo loops

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 Cyclic (Algorithmic) ADC

VX
Vo
Vi SHA 2X

1-b VFS/2
VFS/2 DAC 0

bj

[Chiu, EECT 7327, 2014]

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 Cyclic (Algorithmic) ADC
• Pipeline ADC reduced to single stage that cycles output back to input
• Power & hardware efficient
• Relatively low conversion speeds
• Loop-gain requires use of a residue amplifier (RA)
• Residue gets amplified in each circulation
• Gain accumulated ➔ later conversion steps insensitive to noise & distortion
• Conversion errors made in earlier conversion cycles also get amplified
• Overall accuracy usually limited by MSB conversion step
• RA error mechanisms: cap. mismatch, op-amp gain-error & nonlinearity,
charge-injection, clock feedthrough & finite circuit bandwidth
• Digital redundancy often employed to tolerate comparator/loop offsets
• 1.5-bit/stage with two comparators
• Trimming & calibration used to treat loop-gain error & nonlinearity
• Allows easy programmability for low/medium/high resolution

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 Successive Approximation (SAR) ADC

[Analog Devices, “The Data Conversion Handbook”, 2005]

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 Successive Approximation (SAR) ADC
• Binary search algorithm in feedback loop with 1-bit ADC (comparator)
• Most optimum scheme for low-power & small-area
• Does not require explicit subtractor ➔ speed ↑, power ↓ & area ↓
• SHA function may be merged with DAC
• Eliminates dedicated front-end SHA ➔ speed ↑, power ↓, area ↓, Cin ↑
• Bottom-plate sampling vs. top-plate sampling
• Switch bootstrapping improves ADC distortion & linearity
• ADC performance mostly decided by DAC linearity & settling-time
• DAC: binary scaling vs. non-binary scaling
• Split-Array, C-2C, C-R & R-C schemes improve DAC area & speed
• Comparator offset does not affect ADC linearity
• Allows comparator to be designed for high-speed
• ADC speed: n-bit SAR ADC at least n times slower than n-bit flash ADC
• Many recent innovations to improve resolution, energy & speed

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 Asynchronous Binary Search (ABS) ADC

[Mesgarani, 2012]

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 Asynchronous Binary Search (ABS) ADC
• Operating principle based on binary search similar to SAR ADC
• Comparators with built-in thresholds used to bracket input signal
• Input signal applied to all comparators (same as Flash ADC)
• Comparators connected in binary tree
• Root comparator clocked & based on its decision asynchronously triggers
one of its children
• Second comparator in turn triggers one of its children in third layer
• Outputs of activated comparators are used to derive binary code
• Only n comparators are triggered ➔ Pdiss << Flash ADC
• 2n-1 comparators ➔ Large area
• ADC conversion speed limited by n comparator delays

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 Dual-Slope ADC

[Analog Devices, “The Data Conversion Handbook”, 2005]

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 Dual-Slope ADC
• Low-power, small-area, high-resolution but very slow speed
• Very popular in measurement instruments: DVM
• Conversion performed in two phases: T1=fixed & T2=variable
• T1=2N*Tclk & T2=T1*(Vin/Vref) ➔ Dout=Vin/Vref
• Conversion accuracy independent of integrator time-constant & Tclk
• Proper choice of T1 helps reject certain noise sources: line ripple @ 50Hz
• Error sources: finite gain, over-voltage, integrator saturation, comparator
speed, comparator oscillation, capacitor leakage current, parasitic
capacitance, charge-injection

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 Sigma-Delta ADC

[Analog Devices, “The Data Conversion Handbook”, 2005]

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 Sigma-Delta ADC
• Low-cost, low-power, high-resolution (up to 24-bit) but limited bandwidth
• Ideal for sensor applications: high SNR with self/system/auto calibration
• Key concepts are simple but complex maths: oversampling, quantisation
noise-shaping, digital filtering & decimation
• Simple analog electronics: comparator, voltage reference, switch, one or
more integrators & analog summing circuits
• Complex digital circuitry: digital filter (low-pass vs. band-pass) & decimator
• Continuous-Time (CT) vs. Discrete-Time (DT)
• Oversampling ratio (OSR) spreads noise energy & lowers noise floor
• When quantised samples averaged together, signal portion adds linearly, but
noise portion adds RMS
• SNR(max)=6.02*N+1.76+10*Log(OSR) ➔ OSR=2: +3dB/octave=+0.5-bit
• Noise-shaping: integrator acts as LPF to signal & HPF to quantisation noise
• Helps achieve >3dB/octave per 2x of OSR
• Modulator order: 1st=9dB/octave, 2nd=15dB/octave, 3rd=21dB/octave
• Instability issues for >2nd order loops

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 ADC Architecture Summary

Flash Pipeline SAR Sigma-Delta Integrating

Medium-speed,
Very high-speed, High-speed, Low/Medium-speed, Low-speed,
Suitable Applications Medium/high-
low-resolution medium-resolution high-resolution high-resolution
resolution

N-bit ➔ Signal processed by

Conversion Scheme Binary Search Oversampling Integration
2^(N-1)xComparators chain of stages

Component matching Component matching Component matching Component matching Component matching
Resolution limits resolution to doubles with every bit doubles with every bit doubles with every bit unchanged with
8-bit increase in resolution increase in resolution increase in resolution increase in resolution

Halves with every

Does not change with Reduces linearly with Reduces linearly with Trade-off between data
Speed bit increase in
increased resolution increased resolution increased resolution output rate & resolution
resolution

Die size increases Die size increases Die size increases Die size does not Die size does not
Size exponentially with linearly with increase linearly with increase materially change with materially change with
increase in resolution in resolution in resolution increase in resolution increase in resolution

Successive Digital Decimation

Encoding Method Thermometer Code Digital Error Correction Analog Integration
Approximation Filter

Bubble/sparkle codes,
Op-amps limit speed, Loop stability,
Disadvantages metastability, high Limited speed Slow speed
latency complexity, Pdiss
Pdiss, large area

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 ADC Architecture Classification

[Matsuzawa, 2012]

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 ADC Architecture Classification

[Matsuzawa, 2012]

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 ADC Architecture Classification
• ADCs classified into comparator-based & op-amp-based
• Flash ADC & SAR ADC: comparator-based ➔ Do not require op-amps
• Suitable for low-moderate resolutions
• Flash ADC achieves ultra high-speed conversion
• SAR ADC can deliver ultra low-power conversion
• Pipeline ADC & Sigma-Delta ADC: op-amp-based
• Suitable for moderate-high resolutions
• Pipeline ADC achieves high-speed conversion @ moderate resolution
• Sigma-Delta ADC best for very high-resolution @ low-speed conversion
• Technology scaling reduces operating voltage (Vdd) & amplifier gain
• Op-amp design becoming more difficult
• Comparator-based ADCs more suitable for scaled CMOS technologies

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 Overview
1. Motivation & Plans
2. Proposed Specifications
3. ADC Metrics
4. Generic ADC Architectures
5. Publication Survey (Next Tutorial)
6. Architecture Outline (Next Tutorial)
7. Main Building Blocks
8. Block Design
9. Top-Level Simulations
10. Conclusions

March 2022 H. Malavipathirana / M. Akbari / H. Reyhani 49