WOLLO UNIVERSITY

KOMBOLCHA INSTITUTE OF TECHNOLOGY

KOMBOLCHA
ETHIOPIA

ELECTRICAL ENGINEERING

Digital Logic Design

Module and Question Bank with Answer &
Explanation

DEPARTMENT
OF
ELECTRICAL & COMPUTER ENGINEERING
 Prepared by

EYOB GEDLIE

Department of Electrical & Computer Engineering

Feb, 2022

i
 Contents of Course
Digita logic Design
The Decimal Number System, The Binary Number System, The Octal Number System, The
Hexadecimal Number System, Data Types, Number System, Arithmetic Operation, 1’s, 2’s, 9’s
& 10’s Complements, Binary Coded Decimal(BCD), Boolean Logic Operations, Sum of
Products and Products of Sum, Karnaugh Map, Logic Gates and Networks, Introduction of
Arithmetic Operation, Half Adder & Full Adder, Half & Full Subtractor, 4-Bit Parallel
Adder/Subtractor, BCD Adder, The Design of Combinational Circuits, Combinational Circuits,
Multiplexers (Data Selectors), Demultiplexers (Data Distributors), Encoders, Parity
Generators/Checkers, Latches, Flip Flops, D Flip Flop, Master-Slave Flip-Flops, Counters,
Asynchronous Counter, Asynchronous down counter, Up down counter, Registers, Shift
Registers, Universal Shift Registers, Shift Register Counters, Introduction of Memory Devices,
Random Access Memory, Read Only Memory (ROM), Programmable Read Only Memory,
Erasable Programmable Read Only Memory.

ii
DIGITAL LOGIC DESIGN

DIGITAL LOGIC DESIGN Page no. 1

 DIGITAL LOGIC DESIGN

OBJECTIVES
This course provides in-depth knowledge of switching theory and the logic design techniques of digital
circuits, which is the basis for design of any digital circuit. The course objectives are:
• To learn basic techniques for the design of digital circuits and fundamental concepts used in
the design of digital systems.

• To understand common forms of number representation in digital electronic circuits and to

be able to convert between different representations.
• To implement simple logical operations using combinational logic circuits
• To design combinational logic circuits, sequential logic circuits.
• To impart to student the concepts of sequential circuits, enabling them to analyze sequential
systems in terms of state machines.
• To implement synchronous state machines using flip-flops.

Chapter 1:
Number System and Boolean Algebra :
Number Systems, Base Conversion Methods, Complements of Numbers, Codes- Binary Codes, Binary
Coded Decimal Code and its Properties, Unit Distance Codes, Error Detecting and Correcting Codes.

Digital Logic Gates(AND,NAND,OR,NOR,EX-OR,EX-NOR), Properties of XOR Gates, Universal Gates,

Basic Theorems and Properties, Switching Functions, Canonical and Standard Form.

Chapter 2:
Minimization Techniques:
Introduction, The minimization with theorems, The Karnaugh Map Method, Three, Four and

Five variable K- Maps, Prime and Essential Implications, Don’t Care Map Entries, Using the Maps for
Simplifying, Quine-McCluskey Method, Multilevel NAND/NOR realizations.

DIGITAL LOGIC DESIGN Page no. 2

Chpter 3:
Combinational Circuits:
Design Procedure – Half Adder, Full Adder, Half Subtractor, Full Subtractor, Parallel Binary Adder,
Parallel binary subtractor, Binary Multiplier, Multiplexers/DeMultiplexers, decoder, Encoder, Code
Converters, Magnitude Comparator.

classification of sequential circuits, The binary cell, The S-R-Latch Flip-Flop The D-Latch

Flip-Flop, The “Clocked T” Flip-Flop, The “ Clocked J-K” Flip-Flop, Design of a Clocked Flip-Flop, Timing
and Triggering Consideration.

Chapter 4:
Sequential Circuits:
Introduction, Basic Architectural Distinctions between Combinational and Sequential circuits,
Latches,Flip-Flops, SR,JK,D,T and Master slave, characteristic Tables and equations, Conversion from
one type of Flip-Flop to another,

Counters - Design of Single Mode Counter, Ripple Counter, Ring Counter, Shift Register, Ring counter
using Shift Register UNIT -V:

Memory Devices:
Clasification of memories – ROM : ROM organization, PROM, EPROM,EEPROM, RAM: RAM
organization, Write operation, Read operation, Static RAM , Programmable Logic Devices:
Programmable Logic Array(PLA),Programmable Array Logic, Implementaion of

Combinational Logic circuits using ROM,PLA,PAL.

DIGITAL LOGIC DESIGN Page no. 3

 CHAPTER - 1
NUMBER SYSTEMS & BOOLEAN ALGEBRA

• Introduction about digital system

• Philosophy of number systems
• Complement representation of negative numbers
• Binary arithmetic
• Binary codes
• Error detecting & error correcting codes
• Hamming codes

INTRODUCTION ABOUT DIGITAL SYSTEM

A Digital system is an interconnection of digital modules and it is a system that manipulates

discrete elements of information that is represented internally in the binary form.

Now a day’s digital systems are used in wide variety of industrial and consumer products
such as automated industrial machinery, pocket calculators, microprocessors, digital computers,
digital watches, TV games and signal processing and so on. Characteristics of Digital systems

• Digital systems manipulate discrete elements of information.

• Discrete elements are nothing but the digits such as 10 decimal digits or 26 letters of alphabets
and so on.
• Digital systems use physical quantities called signals to represent discrete elements.
• In digital systems, the signals have two discrete values and are therefore said to be binary. • A
signal in digital system represents one binary digit called a bit. The bit has a value either 0 or 1.

Analog systems vs Digital systems

DIGITAL LOGIC DESIGN Page no. 4

 Analog system process information that varies continuously i.e; they process time varying
signals that can take on any values across a continuous range of voltage, current or any physical
parameter.

Digital systems use digital circuits that can process digital signals which can take either 0 or 1
for binary system.

Advantages of Digital system over Analog system

1. Ease of programmability

The digital systems can be used for different applications by simply changing the program
without additional changes in hardware.

2. Reduction in cost of hardware

The cost of hardware gets reduced by use of digital components and this has been possible
due to advances in IC technology. With ICs the number of components that can be placed in a given
area of Silicon are increased which helps in cost reduction.

3.High speed

Digital processing of data ensures high speed of operation which is possible due to advances in
Digital Signal Processing.

4. High Reliability

Digital systems are highly reliable one of the reasons for that is use of error correction codes.
5. Design is easy

The design of digital systems which require use of Boolean algebra and other digital
techniques is easier compared to analog designing.
DIGITAL LOGIC DESIGN Page no. 5
 6. Result can be reproduced easily

Since the output of digital systems unlike analog systems is independent of temperature,
noise, humidity and other characteristics of components the reproducibility of results is higher in
digital systems than in analog systems.

Disadvantages of Digital Systems

• Use more energy than analog circuits to accomplish the same tasks, thus producing more heat
as well.
• Digital circuits are often fragile, in that if a single piece of digital data is lost or misinterpreted
the meaning of large blocks of related data can completely change.
• Digital computer manipulates discrete elements of information by means of a binary code.
• Quantization error during analog signal sampling.
NUMBER SYSTEM

Number system is a basis for counting varies items. Modern computers communicate and
operate with binary numbers which use only the digits 0 &1. Basic number system used by humans
is Decimal number system.

For Ex: Let us consider decimal number 18. This number is represented in binary as 10010.

We observe that binary number system take more digits to represent the decimal number. For
large numbers we have to deal with very large binary strings. So this fact gave rise to three new
number systems.

i) Octal number systems

ii) Hexa Decimal number system

iii) Binary Coded Decimal number(BCD) system

To define any number system we have to specify •

Base of the number system such as 2,8,10 or 16.

• The base decides the total number of digits available in that number system.

• First digit in the number system is always zero and last digit in the number system is always
base-1.

DIGITAL LOGIC DESIGN Page no. 6

 Binary number system:
The binary number has a radix of 2. As r = 2, only two digits are needed, and these are 0 and 1.
In binary system weight is expressed as power of 2.

The left most bit, which has the greatest weight is called the Most Significant Bit (MSB). And
the right most bit which has the least weight is called Least Significant Bit (LSB).
For Ex: 1001.012 = [ ( 1 ) × 23 ] + [ ( 0 ) × 22 ] + [ ( 0 ) × 21 ] + [ ( 1 ) × 20 ] + [ ( 0 ) ×
2-1 ] + [ ( 1 ) × 22 ]

1001.012 = [ 1 × 8 ] + [ 0 × 4 ] + [ 0 × 2 ] + [ 1 × 1 ] + [ 0 × 0.5 ] + [ 1 × 0.25 ]

1001.012 = 9.2510

Decimal Number system

The decimal system has ten symbols: 0,1,2,3,4,5,6,7,8,9. In other words, it has a base of 10.
Octal Number System
Digital systems operate only on binary numbers. Since binary numbers are often very long, two
shorthand notations, octal and hexadecimal, are used for representing large binary numbers. Octal
systems use a base or radix of 8. It uses first eight digits of decimal number system. Thus it has digits
from 0 to 7.

Hexa Decimal Number System

The hexadecimal numbering system has a base of 16. There are 16 symbols. The decimal digits 0 to 9
are used as the first ten digits as in the decimal system, followed by the letters A, B, C, D, E and F,
which represent the values 10, 11,12,13,14 and 15 respectively.
DIGITAL LOGIC DESIGN Page no. 7
 Decima Binar y Octal Hexadeci
l mal
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
Number Base conversions

The human beings use decimal number system while computer uses binary number system.
Therefore it is necessary to convert decimal number system into its equivalent binary.

i) Binary to octal number conversion ii)

Binary to hexa decimal number conversion

iii) Octal to binary Conversion

DIGITAL LOGIC DESIGN Page no. 8

 Hexa to binary conversion
iv)
v) Octal to Decimal conversion

Ex: convert 4057.068 to octal

=4x83+0x82+5x81+7x80+0x8-1+6x8-2

=2048+0+40+7+0+0.0937

=2095.093710 vi)
Decimal to Octal Conversion

Ex: convert 378.9310 to octal

37810 to octal: Successive division:

8 | 378
|
8 |47 --- 2

8 |5 --- 7 ↑
|
0 --- 5

=5728

0.9310 to octal :

DIGITAL LOGIC DESIGN Page no. 9

 0.93x8=7.44
0.44x8=3.52 ↓

0.53x8=4.16
0.16x8=1.28
=0.73418
378.9310=572.73418 vii)
Hexadecimal to Decimal Conversion
Ex: 5C716 to decimal

=(5x162)+(C x161)+ (7 x160)

=1280+192+7

=14710 viii) Decimal to Hexadecimal

Conversion

Ex: 2598.67510

1 6 2598

16 162 -6 10 -
2

= A26 (16)

0.67510=0.675x16 -- 10.8
=0.800x16 -- 12.8 ↓

=0.800x16 -- 12.8

=0.800x16 -- 12.8
=0.ACCC16

2598.67510 = A26.ACCC16

ix) Octal to hexadecimal conversion:

The simplest way is to first convert the given octal no. to binary & then the binary no. to
hexadecimal.

Ex: 756.6038

DIGITAL LOGIC DESIGN Page no. 10

 7 5 6 . 6 0 3
111 101 110 . 110 000 011
0001 1110 1110 . 1100 0001 1000
1 E E . C 1 8
x) Hexadecimal to octal conversion:

First convert the given hexadecimal no. to binary & then the binary no. to
octal. Ex: B9F.AE16
B 9 F . A E
1011 1001 1111 . 1010 1110
101 110 011 111 . 101 011 100
5 6 3 7 . 5 3 4

=5637.534

Complements:

In digital computers to simplify the subtraction operation & for logical manipulation complements
are used. There are two types of complements used in each radix system.

i) The radix complement or r’s complement

ii) The diminished radix complement or (r-1)’s complement

Representation of signed no.s binary arithmetic in computers:

• Two ways of rep signed no.s

1. Sign Magnitude form
2. Complemented form
• Two complimented forms
1. 1‘s compliment form
2. 2‘s compliment form

DIGITAL LOGIC DESIGN Page no. 11

 Advantage of performing subtraction by the compliment method is reduction in the
hardware.( instead of addition & subtraction only adding ckt‘s are needed.) i. e, subtraction
is also performed by adders only.

Instead of subtracting one no. from other the compliment of the subtrahend is added to
minuend. In sign magnitude form, an additional bit called the sign bit is placed in front of the no. If
the sign bit is 0, the no. is +ve, If it is a 1, the no is _ve.

Ex:

0 1 0 1 0 0 1
↓
Sign bit =+41 magnitude
↑
1 1 0 1 0 0 1

= -41 Note: manipulation is necessary to add a

+ve no to a –ve no
Representation of signed no.s using 2’s or 1’s complement
method:
If the no. is +ve, the magnitude is rep in its true binary form & a sign bit 0 is placed in front
of the MSB.I f the no is _ve , the magnitude is rep in its 2‘s or 1‘s compliment form &a sign
bit 1 is placed in front of the MSB.

Ex:

Given no. Sign mag form 2‘s comp form 1‘s comp form
01101 +13 +13 +13
010111 +23 +23 +23
10111 -7 -7 -8
1101010 -42 -22 -21
Special case in 2’s comp representation:

Whenever a signed no. has a 1 in the sign bit & all 0‘s for the magnitude bits, the decimal
equivalent is -2n , where n is the no of bits in the magnitude . Ex: 1000= -8 & 10000=-16

DIGITAL LOGIC DESIGN Page no. 12

 Characteristics of 2’s compliment no.s:
Properties:
1. There is one unique zero
2. 2‘s comp of 0 is 0
3. The leftmost bit can‘t be used to express a quantity . it is a 0 no. is +ve.
4. For an n-bit word which includes the sign bit there are (2n-1-1) +ve integers, 2n-1
–ve integers & one 0 , for a total of 2n uniquestates.

5. Significant information is containd in the 1‘s of the +ve no.s & 0‘s of the _ve no.s
6. A _ve no. may be converted into a +ve no. by finding its 2‘s comp.

Signed binary numbers:

Decimal Sign 2‘s comp form Sign 1‘s comp form Sign mag form
+7 0111 0111 0111
+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0011 0011 0011
+0 0000 0000 0000

-0 -- 1111 1000
-1 1111 1110 1001
-2 1110 1101 1010
-3 1101 1100 1011
-4 1100 1011 1100
-5 1011 1010 1101
-6 1010 1001 1110
-7 1001 1000 1111
8 1000 -- --
Methods of obtaining 2’s comp of a no:

• In 3 ways
DIGITAL LOGIC DESIGN Page no. 13
 1. By obtaining the 1‘s comp of the given no. (by changing all 0‘s to 1‘s & 1‘s to 0‘s) & then
adding 1.
2. By subtracting the given n bit no N from 2n
3. Starting at the LSB , copying down each bit upto & including the first 1 bit
encountered , and complimenting the remaining bits.
Ex: Express -45 in 8 bit 2‘s comp form

+45 in 8 bit form is

00101101 I method:

1‘s comp of 00101101 & the add 1

00101101

11010010

+1

__ _____ ___

11010011 is 2‘s comp form

II method:

Subtract the given no. N from 2n

2n = 100000000
Subtract 45= -00101101
+1
___

DIGITAL LOGIC DESIGN Page no. 14

 11010011 is 2‘s comp
III method:

Original no: 00101101

Copy up to First 1 bit 1 Compliment
remaining : 1101001

bits 11010011
Ex:
-73.75 in 12 bit 2‘compform
I method

01001001.1100

10110110.0011

+1

10110110.0100 is 2‘s
II method:

28 = 100000000.0000
Sub 73.75=-01001001.1100

10110110.0100 is 2‘s comp

III method :

Orginalno : 01001001.1100

Copy up to 1‘st bit 100

DIGITAL LOGIC DESIGN Page no. 15
 Comp the remaining bits: 10110110.0

10110110.0100
2’s compliment Arithmetic:
• The 2‘s comp system is used to rep –ve no.s using modulus arithmetic . The word
length of a computer is fixed. i.e, if a 4 bit no. is added to another 4 bit no . the result
will be only of 4 bits. Carry if any , from the fourth bit will overflow called the
Modulus arithmetic.
Ex:1100+1111=1011

• In the 2‘s compl subtraction, add the 2‘s comp of the subtrahend to the minuend . If
there is a carry out , ignore it , look at the sign bit I,e, MSB of the sum term .If the
MSB is a 0, the result is positive.& it is in true binary form. If the MSB is a ` ( carry in
or no carry at all) the result is negative.& is in its 2‘s comp form. Take its 2‘s comp to
find its magnitude in binary.

Ex:Subtract 14 from 46 using 8 bit 2‘s comp arithmetic:

+14 = 00001110
-14 = 11110010 2‘s comp

+46 = 00101110
-14 =+11110010 2‘s comp form of -14

-32 (1)00100000 ignore carry

Ignore carry , The MSB is 0 . so the result is +ve. & is in normal binary

form. So the result is +00100000=+32.

EX: Add -75 to +26 using 8 bit 2‘s comp arithmetic

DIGITAL LOGIC DESIGN Page no. 16
 +75 = 01001011
-75 =10110101 2‘s comp
+26 = 00011010
-75 =+10110101 2‘s comp form of -75

-49 11001111 No carry

No carry , MSB is a 1, result is _ve & is in 2‘s comp. The magnitude is 2‘s comp of
11001111. i.e, 00110001 = 49. so result is -49

Ex: add -45.75 to +87.5 using 12 bit arithmetic

+87.5 = 01010111.1000

-45.75=+11010010.0100

-41.75 (1)00101001.1100 ignore carry

MSB is 0, result is +ve. =+41.75

1’s compliment of n number:

• It is obtained by simply complimenting each bit of the no,.& also , 1‘s comp of a no, is
subtracting each bit of the no. form 1.This complemented value rep the – ve of the
original no. One of the difficulties of using 1‘s comp is its rep o f zero. Both
00000000 & its 1‘s comp 11111111 rep zero.
• The 00000000 called +ve zero& 11111111 called –ve zero. Ex: -99 & -77.25 in 8
bit 1‘s comp

+99 = 01100011

-99 = 10011100
DIGITAL LOGIC DESIGN Page no. 17
 +77.25 = 01001101.0100

-77.25 = 10110010.1011

1’s compliment arithmetic:

In 1‘s comp subtraction, add the 1‘s comp of the subtrahend to the minuend. If there is a
carryout , bring the carry around & add it to the LSB called the end around carry. Look at the
sign bit (MSB) . If this is a 0, the result is +ve & is in true binary. If the MSB is a 1 ( carry or no
carry ), the result is –ve & is in its is comp form .Take its 1‘s comp to get the magnitude inn
binary.

so is for 8 and 1 codes, 7 and 2, 6 and 3, 5 and 4. Codes 2421, 5211, and excess-3 are reflective, whereas
the 8421 code is not.

Sequential Codes
A code is said to be sequential when two subsequent codes, seen as numbers in binary representation,
differ by one. This greatly aids mathematical manipulation of data. The 8421 and Excess-3 codes are
sequential, whereas the 2421 and 5211 codes are not.

Non weighted codes

Non weighted codes are codes that are not positionally weighted. That is, each position
within the binary number is not assigned a fixed value. Ex: Excess-3 code

Excess-3 Code

Excess-3 is a non weighted code used to express decimal numbers. The code
derives its name from the fact that each binary code is the corresponding 8421
code plus 0011(3).

DIGITAL LOGIC DESIGN Page no. 18

 Gray Code

The gray code belongs to a class of codes called minimum change codes, in
which only one bit in the code changes when moving from one code to the next.
The Gray code is non-weighted code, as the position of bit does not contain any
weight. The gray code is a reflective digital code which has the special property
that any two subsequent numbers codes differ by only one bit. This is also called a
unit- distance code. In digital Gray code has got a special place.

Binary to Gray Conversion

Gray Code MSB is binary code MSB.

Gray Code MSB-1 is the XOR of binary code MSB and MSB-1.

MSB-2 bit of gray code is XOR of MSB-1 and MSB-2 bit of binary code.

MSB-N bit of gray code is XOR of MSB-N-1 and MSB-N bit of binary code. 8421
BCD code ( Natural BCD code):

Each decimal digit 0 through 9 is coded by a 4 bit binary no. called natural binary
codes. Because of the 8,4,2,1 weights attached to it. It is a weighted code & also sequential .
it is useful for mathematical operations. The advantage of this code is its case of conversion
to & from decimal. It is less efficient than the pure binary, it require more bits.

DIGITAL LOGIC DESIGN Page no. 19

 Ex: 14→1110 in binary
But as 0001 0100 in 8421 ode.

The disadvantage of the BCD code is that , arithmetic operations are more complex than they are in
pure binary . There are 6 illegal combinations 1010,1011,1100,1101,1110,1111 in these codes, they
are not part of the 8421 BCD code system . The disadvantage of 8421 code is, the rules of binary
addition 8421 no, but only to the individual 4 bit groups. BCD Addition:

It is individually adding the corresponding digits of the decimal no,s expressed in 4 bit binary
groups starting from the LSD . If there is no carry & the sum term is not an illegal code , no
correction is needed .If there is a carry out of one group to the next group or if the sum term is an
illegal code then 610(0100) is added to the sum term of that group & the resulting carry is added to
the next group.

Ex: Perform decimal additions in 8421 code

(a)25+13
In BCD 25= 0010 0101

In BCD +13 =+0001 0011

38 0011 1000

No carry , no illegal code .This is the corrected sum

(b). 679.6 + 536.8

679.6 = 0110 0111 1001 .0110 in BCD

+536.8 = +0101 0011 0010 .1000 in BCD

___ _________________

DIGITAL LOGIC DESIGN Page no. 20

 1216.4 1011 1010 0110 . 1110 illegal codes

+0110 + 0011 +0110 . + 0110 add 0110 to each

(1)0001 (1)0000 (1)0101 . (1)0100 propagate carry

/ / / /
+1 +1 +1 +1

0001 0010 0001 0110 . 0100

1 2 1 6 . 4

BCD Subtraction:

Performed by subtracting the digits of each 4 bit group of the subtrahend the digits from the
corresponding 4- bit group of the minuend in binary starting from the LSD . if there is no borrow
from the next group , then 610(0110)is subtracted from the difference term of this group.
(a)38-15

In BCD 38= 0011 -

In BCD 15 = -0001 1000
0101

23 0010 0011

No borrow, so correct
difference.

.(b) 206.7-147.8

DIGITAL LOGIC DESIGN Page no. 21

 206.7 = 0010 0000 0110 . 0111 in BCD

-147.8 = -0001 0100 0111 . 0110 in BCD

__ ________________

58.9 0000 1011 - 1110 . 1111 borrows are present

0110 -0110 . -0110 subtract 0110

0101 1000 . 1001

BCD Subtraction using 9’s & 10’s compliment methods:

Form the 9‘s & 10‘s compliment of the decimal subtrahend & encode that no. in

the 8421 code . the resulting BCD no.s are then added.

EX: 305.5 – 168.8

305.5 = 305.5 9‘s comp of -168.8

-168.8= +83.1
__
end around carry
corrected difference

DIGITAL LOGIC DESIGN Page no. 22

 (1)136.6 0101 9‘s comp of 168.8 in BCD
+1 0001
1011 is illegal code
136.7
0110 add 0110
305.5+831.110 10 == +10000011
0000 01010011 0001 ..

___ _________________
. 0110 +1 End around carry
+1011 0011 0110 .

+0110
. 0111

(1)0001 0011 0110

0001 0011 0110

= 136.7
Excess three(xs-3)code:

It is a non-weighted BCD code .Each binary codeword is the corresponding 8421 codeword plus
0011(3).It is a sequential code & therefore , can be used for arithmetic operations..It is a self-
complementing code.s o the subtraction by the method of compliment addition is more direct in xs-
3 code than that in 8421 code. The xs-3 code has six invalid states 0000,0010,1101,1110,1111.. It
has interesting properties when used in addition & subtraction. Excess-3 Addition:

Add the xs-3 no.s by adding the 4 bit groups in each column starting from the LSD. If there is no
carry starting from the addition of any of the 4-bit groups , subtract 0011 from the sum term of

DIGITAL LOGIC DESIGN Page no. 23

 those groups ( because when 2 decimal digits are added in xs-3 & there is no carry , result in xs-6). If
there is a carry out, add 0011 to the sum term of those groups( because when there is a carry, the
invalid states are skipped and the result is normal binary).

EX: 37 _ 0110 1010

+28 +0101 1011
_ _ ____ ___

65 1011 (1)0101 carry generated

+1 propagate carry
______

1100 0101 add 0011 to correct 0101 &

-0011 +0011 subtract 0011 to correct 1100
________

1001 1000 =6510

Excess -3 (XS-3) Subtraction:

Subtract the xs-3 no.s by subtracting each 4 bit group of the subtrahend from the corresponding 4
bit group of the minuend starting form the LSD .if there is no borrow from the next 4-bit group add
0011 to the difference term of such groups (because when decimal digits are subtracted in xs-3 &
there is no borrow , result is normal binary). I f there is a borrow , subtract 0011 from the
differenceterm(b coz taking a borrow is equivalent to adding six invalid states , result is in xs-6)
Ex: 267-175

267 = 0101 1001 1010

-175= -0100 1010 1000

________

DIGITAL LOGIC DESIGN Page no. 24

 0000 1111 0010

+0011 -0011 +0011

0011 1100 +0011 =9210

Xs-3 subtraction using 9’s & 10’s compliment methods: Subtraction is performed by the 9‘s
compliment or 10‘s compliment Ex:687-348 The subtrahend (348) xs -3 code & its compliment are:
9‘s comp of 348 = 651

Xs-3 code of 348 = 0110 0111 1011

1‘s comp of 348 in xs-3 = 1001 1000 0100

Xs=3 code of 348 in xs=3 = 1001 1000 0100

687 687

-348 → +651 9‘s compl of

348

339 (1)338
+1 end around carry
_

339 corrected difference in decimal

DIGITAL LOGIC DESIGN Page no. 25

 1001 1011 1010 687 in xs-3
+1001 1000 0100 1‘s comp 348 in xs-3
_ _______ __

⁄⁄ _ (1)0010 (1)0011 1110 carry generated

+1 +1 propagate carry
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-

(1)0011 0010 1110

+1 end around carry
______________

0011 0011 1111 (correct 1111 by sub0011 and

+0011 +0011 +0011 correct both groups of 0011 by
___ ____ __ _ adding 0011)
__

0110 0110 1100 corrected diff in xs-3 = 33010

The Gray code (reflective –code):

Gray code is a non-weighted code & is not suitable for arithmetic operations. It is not a BCD code . It
is a cyclic code because successive code words in this code differ in one bit position only i.e, it is a
unit distance code.Popular of the unit distance code.It is also a reflective code i.e,both reflective &
unit distance. The n least significant bits for 2n through 2n+1-1 are the mirror images of thosr for 0
through 2n-1.An N bit gray code can be obtained by reflecting an N- 1 bit code about an axis at the
end of the code, & putting the MSB of 0 above the axis & the MSB of 1 below the axis.
Reflection of gray codes:

DIGITAL LOGIC DESIGN Page no. 26

 Gray Code
Decimal 4 bit binary
1 bit 2 bit 3 bit 4 bit
0 00 000 0000 0 0000
1 01 001 0001 1 0001
11 011 0011 2 0010
10 010 0010 3 0011

110 0110 4 0100

111 0111 5 0101

101 0101 6 0110

110 0100 7 0111

1100 8 1000
1101 9 1001
1111 10 1010
1110 11 1011
1010 12 1100
1011 13 1101
1001 14 1110
1000 15 1111

Binary codes block diagram

DIGITAL LOGIC DESIGN Page no. 27

Error – Detecting codes: When binary data is transmitted & processed,it is susceptible to
noise that can alter or distort its contents. The 1‘s may get changed to 0‘s & 1‘s .because
digital systems must be accurate to the digit, error can pose a problem. Several schemes
have been devised to detect the occurrence of a single bit error in a binary word, so that
whenever such an error occurs the concerned binary word can be corrected &
retransmitted.

Parity: The simplest techniques for detecting errors is that of adding an extra bit known as
parity bit to each word being transmitted.Two types of parity: Oddparity, evenparity
forodd parity, the parity bit is set to a ‗0‘ or a ‗1‘ at the transmitter such that the total no. of
1 bit in the word including the parity bit is an odd no.For even parity, the parity bit is set to
a ‗0‘ or a ‗1‘ at the transmitter such that the parity bit is an even no.

Decimal 8421 code Odd parity Even parity

0 0000 1 0
1 0001 0 1
2 0010 0 1
3 0011 1 0
4 0100 0 1
5 0100 1 0
6 0110 1 0
7 0111 0 1
8 1000 0 1
9 1001 1 0
When the digit data is received . a parity checking circuit generates an error signal if the
total no of 1‘s is even in an odd parity system or odd in an even parity system. This parity
check can always detect a single bit error but cannot detect 2 or more errors with in the
same word.Odd parity is used more often than even parity does not detect the situation.
Where all 0‘s are created by a short ckt or some other fault condition.

Ex: Even parity scheme

(a) 10101010 (b) 11110110 (c)10111001

Ans:

(a) No. of 1‘s in the word is even is 4 so there is no error

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 (b) No. of 1‘s in the word is even is 6 so there is no error (c) No. of 1‘s in
the word is odd is 5 so there is error

Ex: odd parity

(a)10110111 (b) 10011010 (c)11101010

Ans:

(a) No. of 1‘s in the word is even is 6 so word has

error (b) No. of 1‘s in the word is even is 4 so word
has error

(c) No. of 1‘s in the word is odd is 5 so there is no error

Checksums:

Simple parity can‘t detect two errors within the same word. To overcome this, use a sort of 2
dimensional parity. As each word is transmitted, it is added to the sum of the previously transmitted
words, and the sum retained at the transmitter end. At the end of transmission, the sum called the
check sum. Up to that time sent to the receiver. The receiver can check its sum with the transmitted
sum. If the two sums are the same, then no errors were detected at the receiver end. If there is an
error, the receiving location can ask for retransmission of the entire data, used in teleprocessing
systems.

Block parity:

Block of data shown is create the row & column parity bits for the data using odd parity.

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 The parity bit 0 or 1 is added column wise & row wise such that the total no. of 1‘s in each column &
row including the data bits & parity bit is odd as

Data Parity bit data

10110 0 10110
10001 1 10001
10101 0 10101
00010 0 00010
11000 1 11000
00000 1 00000
11010 0 11010

Error –Correcting Codes:

A code is said to be an error –correcting code, if the code word can always be deduced from an
erroneous word. For a code to be a single bit error correcting code, the minimum distance of that
code must be three. The minimum distance of that code is the smallest no. of bits by which any two
code words must differ. A code with minimum distance of 3 can‘t only correct single bit errors but
also detect ( can‘t correct) two bit errors, The key to error correction is that it must be possible to
detect & locate erroneous that it must be possible to detect & locate erroneous digits. If the location
of an error has been determined. Then by complementing the erroneous digit, the message can be
corrected , error correcting , code is the Hamming code , In this , to each group of m information or
message or data bits, K parity checking bits denoted by P1,P2,----------pk located at positions 2 k-1

from left are added to form an (m+k) bit code word. To correct the error, k parity checks are
performed on selected digits of each code word, & the position of the error bit is located by forming
an error word, & the error bit is then complemented. The k bit error word is generated by putting a
0 or a 1 in the 2 k-1th position depending upon whether the check for parity involving the parity bit
Pk is satisfied or not.Error positions & their corresponding values :

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 Error Position For 15 bit code For 12 bit code For 7 bit code

C4 C3 C2 C1 C4 C3 C2 C1 C3 C2 C1
0 0000 0000 000
1 0001 0001 001
2 0010 0010 010
3 0011 0011 011
4 0100 0100 100
5 0101 0101 101
6 0 110 0 1 10 110
7 0 111 0 1 11 111
8 1 0 0 0 1 0 0 0
9 1 001 1 0 01
10 1 010 1 0 10
11 1 011 1 0 11
12 1 10 0 1 1 0 0
13 1 10 1
14 1 11 0
15 1 1 1 1

7- bit Hamming code:

To transmit four data bits, 3 parity bits located at positions 20 21&22 from left are
added to make a 7 bit codeword which is then transmitted.
The word format

P1 P2 D3 P4 D5 D6 D7
D—Data bits P-

Parity
bits

Decimal Digit For BCD For Excess-3

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 P1P2D3P4D5D6D7 P1P2D3P4D5D6D7

0 00 00 0 0 0 1 0 00 0 1 1
1 11 01 0 0 1 1 0 01 1 0 0
2 01 01 0 1 1 0 10 0 1 0 1
3 10 00 0 1 1 1 1 00 1 1 0
4 10 01 1 0 0 0 0 01 1 1 1
5 010 0 1 0 1 1 1 10 0 0 0
6 11 00 1 10 0 0 11 0 0 1
7 00 01 1 11 1 0 11010
8 11 10 0 00 0 1 100 11
9 00 11 0 01 0 1 1 1100
Ex: Encode the data bits 1101 into the 7 bit even parity Hamming Code

The bit pattern is

P1P2D3P4D5D6D7

1 1 0 1

Bits 1,3,5,7 (P1 111) must have even parity, so P1 =1

Bits 2, 3, 6, 7(P2 101) must have even parity, so P2 =0

Bits 4,5,6,7 (P4 101)must have even parity, so P4 =0

The final code is 1010101

EX: Code word is 1001001

Bits 1,3,5,7 (C1 1001) →no error →put a 0 in the 1‘s position→C1=0

Bits 2, 3, 6, 7(C2 0001)) → error →put a 1 in the 2‘s position→C2=1

Bits 4,5,6,7 (C4 1001)) →no error →put a 0 in the 4‘s position→C3=0

15-bit Hamming Code: It transmit 11 data bits, 4 parity bits located 20 21 22 23

Word format is
DIGITAL LOGIC DESIGN Page no. 32
 P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12 D13 D14 D15

12-Bit Hamming Code:It transmit 8 data bits, 4 parity bits located at position 20 21 22 23

Word format is

P1 P2 D3 P4 D5 D6 D7 P8 D9 D10 D11 D12

Alphanumeric Codes:

These codes are used to encode the characteristics of alphabet in addition to the decimal digits. It is
used for transmitting data between computers & its I/O device such as printers, keyboards & video
display terminals.Popular modern alphanumeric codes are ASCII code & EBCDIC code.
Digital Logic Gates

Boolean functions are expressed in terms of AND, OR, and NOT operations, it is easier to
implement a Boolean function with these type of gates.

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Properties of XOR Gates

• XOR (also ) : the “not-equal” function • XOR(X,Y) = X Y=

X’Y + XY’ • Identities:
– X 0=X
– X 1 = X’
– X X=0–X X’ = 1
• Properties:
– X Y=Y X
– (X Y) W=X (Y W)

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 Universal Logic Gates

NAND and NOR gates are called Universal gates. All fundamental gates (NOT, AND, OR) can be
realized by using either only NAND or only NOR gate. A universal gate provides flexibility and offers
enormous advantage to logic designers.

NAND as a Universal Gate

NAND Known as a “universal” gate because ANY digital circuit can be implemented with NAND gates
alone.
To prove the above, it suffices to show that AND, OR, and NOT can be implemented using NAND
gates only.

Boolean Algebra: In 1854, George Boole developed an algebraic system now called Boolean
algebra. In 1938, Claude E. Shannon introduced a two‐valued Boolean algebra called switching
algebra that represented the properties of bistable electrical switching circuits. For the formal
definition of Boolean algebra, we shall employ the postulates formulated by E. V. Huntington in
1904.
Boolean algebra is a system of mathematical logic. It is an algebraic system consisting of the set of
elements (0, 1), two binary operators called OR, AND, and one unary operator NOT. It is the basic

DIGITAL LOGIC DESIGN Page no. 35

mathematical tool in the analysis and synthesis of switching circuits. It is a way to express logic
functions algebraically.
Boolean algebra, like any other deductive mathematical system, may be defined with aset of
elements, a set of operators, and a number of unproved axioms or postulates. A set of elements is
anycollection of objects having a common property. If S is a set and x and y are certain objects, then
x Î Sdenotes that x is a member of the set S, and y ÏS denotes that y is not an element of S. A set with
adenumerable number of elements is specified by braces: A = {1,2,3,4}, i.e. the elements of set A are
thenumbers 1, 2, 3, and 4. A binary operator defined on a set S of elements is a rule that assigns to
each pair ofelements from S a unique element from S._ Example: In a*b=c, we say that * is a binary
operator if it specifies a rule for finding c from the pair (a,b)and also if a, b, c Î S.
Axioms and laws of Boolean algebra

Axioms or Postulates of Boolean algebra are a set of logical expressions that we accept
without proof and upon which we can build a set of useful theorems.

AND Operation OR Operation NOT Operation

Axiom1 : 0.0=0 0+0=0 0=1

Axiom2: 0.1=0 0+1=1 1=0
Axiom3: 1.0=0 1+0=1
Axiom4: 1.1=1 1+1=1

OR Law
Law1: A+0=A
AND Law
Law2: A+1=1
Law1: A.0=0 (Null law)
Law3: A+A=A (Impotence
Law2: A.1=A (Identity law)
law)
Law3: A.A=A (Impotence law)

CLOSURE: The Boolean system is closed with respect to a binary operator if for every pair of
Boolean values,it produces a Boolean result. For example, logical AND is closed in the Boolean
system because it accepts only Boolean operands and produces only Boolean results.

DIGITAL LOGIC DESIGN Page no. 36

_ A set S is closed with respect to a binary operator if, for every pair of elements of S, the binary
operator specifies a rule for obtaining a unique element of S.
_ For example, the set of natural numbers N = {1, 2, 3, 4, … 9} is closed with respect to the binary
operator plus (+) by the rule of arithmetic addition, since for any a, b Î N we obtain a unique c Î N by
the operation a + b = c.

ASSOCIATIVE LAW:
A binary operator * on a set S is said to be associative whenever (x * y) * z = x * (y * z) for all x, y, z Î S,
forall Boolean values x, y and z.
COMMUTATIVE LAW:
A binary operator * on a set S is said to be commutative whenever x * y = y * x for all x, y, z є S

IDENTITY ELEMENT:
A set S is said to have an identity element with respect to a binary operation * on S if there exists an
element e є S with the property e * x = x * e = x for every x є S

BASIC IDENTITIES OF BOOLEAN ALGEBRA

Postulate 1(Definition): A Boolean algebra is a closed algebraic system containing a set K of two or
more elements and the two operators · and + which refer to logical AND and logical OR •x + 0 = x • x
·0=0
• x+1=1

• x·1=1

• x+x=x

• x·x=x

• x + x’ = x

• x · x’ = 0

• x+y=y+x

DIGITAL LOGIC DESIGN Page no. 37

 • xy = yx

• x+(y+z)=(x+y)+z
• x (yz) = (xy) z

• x ( y + z ) = xy + xz

• x + yz = ( x + y )( x + z)

• ( x + y )’ = x’ y’

• ( xy )’ = x’ + y’

• (x’)’ = x

DeMorgan's Theorem

(a) (a + b)' = a'b'

(b) (ab)' = a' + b'

Generalized DeMorgan's Theorem

(a) (a + b + … z)' = a'b' … z'
(b) (a.b … z)' = a' + b' + … z‘

Basic Theorems and Properties of Boolean algebra Commutative law

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Law1: A+B=B+A Law2: A.B=B.A

Associative law
Law2: A(B.C) = (A.B)C

Law1: A + (B +C) = (A +B) +C

Law2: A + BC = (A + B).(A +C)

Distributive law

Law1: A.(B + C) = AB+ AC Law2: A(A +B) = A

Solution: A.A+A.B A+A.B

Absorption law

Law1: A +AB =A

Solution: A(1+B)
A

A(1+B)
A

Consensus Theorem

Theorem1. AB+ A’C + BC = AB + A’C Theorem2. (A+B). (A’+C).(B+C) =(A+B).( A’+C)

The BC term is called the consensus term and is redundant. The consensus term is formed
from a PAIR OF TERMS in which a variable (A) and its complement (A’) are present; the
consensus term is formed by multiplying the two terms and leaving out the selected
variable and its complement
Consensus Theorem1 Proof:

AB+A’C+BC=AB+A’C+(A+A’)BC
=AB+A’C+ABC+A’BC

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 =AB(1+C)+A’C(1+B
) = AB+ A’C

Principle of Duality

Each postulate consists of two expressions statement one expression is transformed into the other
by interchanging the operations (+) and (⋅) as well as the identity elements 0 and 1.
Such expressions are known as duals of each other.
If some equivalence is proved, then its dual is also immediately true. If we prove: (x.x)+(x’+x’)=1,
then we have by duality: (x+x)⋅(x’.x’)=0

The Huntington postulates were listed in pairs and designated by part (a) and part (b) in below
table.
Table for Postulates and Theorems of Boolean algebra
Part-A Part-B
A+0=A A.0=0
A+1=1 A.1=A
A+A=A (Impotence law) A.A=A (Impotence law)
A+ A=1 A. A=0
--

A=A (double inversion law)

Commutative law: A+B=B+A A.B=B.A
Associative law: A + (B +C) = (A +B) +C A(B.C) = (A.B)C
Distributive law: A.(B + C) = AB+ AC A + BC = (A + B).(A +C)
Absorption law: A +AB =A A(A +B) = A
DeMorgan Theorem:
(A.B) = = A + B
(A+B) = A . B
Redundant Literal Rule: A+ A. B=A+B A.(A+B)=AB
Consensus Theorem: AB+ A’C + BC = AB + (A+B). (A’+C).(B+C) =(A+B).( A’+C)
A’C

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 Boolean Function
Boolean algebra is an algebra that deals with binary variables and logic operations.
A Boolean function described by an algebraic expression consists of binary variables, the constants
0 and 1, and the logic operation symbols.
For a given value of the binary variables, the function can be equal to either 1 or 0. F(vars) =
expression

Set of binary Variables Operators (+, •, ‘)

Constants (0, 1)
Groupings (parenthesis)
Variables
Consider an example for the Boolean function
F1 = x + y’z

x y z F1

0 0 0 0
The function F1 is equal to 1 if x is equal to 1 or if both y’ and z
0 0 1 1
are equal to 1. F1 is equal to 0 otherwise. The complement
0 1 0 0
operation dictates that when y’ = 1, y = 0. Therefore, F1 = 1 if x
0 1 1 0 = 1 or if y = 0 and z = 1.
A Boolean function expresses the logical relationship between
1 0 0 1
binary variables and is evaluated by determining the binary value
1 0 1 1
of the expression for all possible values of the variables.
1 1 0 1 A Boolean function can be represented in a truth table.

1 1 1 1 The number of rows in the truth table is 2n, where n is the

number of variables in the function. The binary combinations
for the truth table are obtained from the binary numbers by counting from 0 through 2 - 1.

DIGITAL LOGIC DESIGN Page no. 41

 Truth Table for F1

x y z F1 F2 F3

0 0 0 0 1 1

0 0 1 0 0 1

Note:
Q: Let a function F() depend on n variables. How many rows are there in the truth table of F() ? A: 2n
rows, since there are 2n possible binary patterns/combinations for the n variables.

Truth Tables

• Enumerates all possible combinations of variable values and the corresponding function
value
• Truth tables for some arbitrary functions
F1(x,y,z), F2(x,y,z), and F3(x,y,z) are shown to the below.

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 0 1 0

1 0 1 0 1 0

DIGITAL LOGIC DESIGN Page no. 42

1 1 0 0 0 0

1 1 1 1 0 1

• Truth table: a unique representation of a Boolean function

• If two functions have identical truth tables, the functions are equivalent (and vice- versa).
• Truth tables can be used to prove equality theorems.
• However, the size of a truth table grows exponentially with the number of variables
involved, hence unwieldy. This motivates the use of Boolean Algebra. Boolean
expressions-NOT unique
Unlike truth tables, expressions epresenting a Boolean
x y z F G
function are NOT unique.
• Example: 0 0 0 1 1

– F(x,y,z) = x’•y’•z’ + x’•y•z’ + x•y•z’ 0 0 1 0 0

– G(x,y,z) = x’•y’•z’ + y•z’
0 1 0 1 1
• The corresponding truth tables for F() and G() are to the right. They
are identical. 0 1 1 0 0
• Thus, F() = G()
1 0 0 0 0

1 0 1 0 0

1 1 0 1 1

1 1 1 0 0

Algebraic Manipulation (Minimization of Boolean function)

Boolean algebra is a useful tool for simplifying digital circuits.
Why do it? Simpler can mean cheaper, smaller, faster.
Example: Simplify F = x’yz + x’yz’ + xz.

DIGITAL LOGIC DESIGN Page no. 43

F= x’yz + x’yz’ + xz
= x’y(z+z’) + xz
= x’y•1 + xz
= x’y + xz

Example: Prove
x’y’z’ + x’yz’ + xyz’ = x’z’ + yz’
Proof:
x’y’z’+ x’yz’+ xyz’
= x’y’z’ + x’yz’ + x’yz’ + xyz’
= x’z’(y’+y) + yz’(x’+x)
= x’z’•1 + yz’•1
= x’z’ + yz’

Complement of a Function
The complement of a function is derived by interchanging (• and +), and (1 and 0), and
complementing each variable.
Otherwise, interchange 1s to 0s in the truth table column showing F.
The complement of a function IS NOT THE SAME as the dual of a function.
Example
Find G(x,y,z), the complement of F(x,y,z) = xy’z’ + x’yz
Ans: G = F’ = (xy’z’ + x’yz)’
= (xy’z’)’ • (x’yz)’ DeMorgan
= (x’+y+z) • (x+y’+z’) DeMorgan again
Note: The complement of a function can also be derived by finding the function’s dual, and then
complementing all of the literals

Canonical and Standard Forms

We need to consider formal techniques for the simplification of Boolean functions.
Identical functions will have exactly the same canonical form.
Minterms and Maxterms
Sum-of-Minterms and Product-of- Maxterms

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 • Product and Sum terms
• Sum-of-Products (SOP) and Product-of-Sums (POS)

Definitions

Literal: A variable or its complement

Product term: literals connected by •
Sum term: literals connected by +
Minterm: a product term in which all the variables appear exactly once, either complemented or
uncomplemented.
Maxterm: a sum term in which all the variables appear exactly once, either complemented or
uncomplemented.
Canonical form: Boolean functions expressed as a sum of Minterms or product of Maxterms are said
to be in canonical form.

Minterm
Represents exactly one combination in the truth table.
Denoted by mj, where j is the decimal equivalent of the minterm’s corresponding binary
combination (bj).
A variable in mj is complemented if its value in bj is 0, otherwise is uncomplemented.
Example: Assume 3 variables (A, B, C), and j=3. Then, bj = 011 and its corresponding minterm is
denoted by mj = A’BC
Maxterm

Represents exactly one combination in the truth table.

Denoted by Mj, where j is the decimal equivalent of the maxterm’s corresponding binary
combination (bj).
A variable in Mj is complemented if its value in bj is 1, otherwise is uncomplemented.

Example: Assume 3 variables (A, B, C), and j=3. Then, bj = 011 and its corresponding maxterm is
denoted by Mj = A+B’+C’
Truth Table notation for Minterms and Maxterms
DIGITAL LOGIC DESIGN Page no. 45
 • Minterms and Maxterms are easy to denote using a truth table. Example: Assume 3 variables
x,y,z (order is fixed)

x y z Minterm Maxterm

0 0 0 x’y’z’ = m0 x+y+z = M0

0 0 1 x’y’z = m1 x+y+z’ = M1

0 1 0 x’yz’ = m2 x+y’+z = M2

0 1 1 x’yz = m3 x+y’+z’= M3

1 0 0 xy’z’ = m4 x’+y+z = M4

1 0 1 xy’z = m5 x’+y+z’ = M5

1 1 0 xyz’ = m6 x’+y’+z = M6

1 1 1 xyz = m7 x’+y’+z’ = M7

Canonical Forms
Every function F() has two canonical forms:
Canonical Sum-Of-Products (sum of minterms)
Canonical Product-Of-Sums (product of maxterms) Canonical Sum-Of-Products:
The minterms included are those mj such that F( ) = 1 in row j of the truth table for F( ).
Canonical Product-Of-Sums:
The maxterms included are those Mj such that F( ) = 0 in row j of the truth table for F( ).

a b c f1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

DIGITAL LOGIC DESIGN Page no. 46

Example 1 0 1 0
Consider a Truth table for f1(a,b,c) at right The
1 1 0 1
canonical sum-of-products form for f1 is f1(a,b,c)
= m1 + m2 + m4 + m6 1 1 1 0

= a’b’c + a’bc’ + ab’c’ + abc’ The canonical product-of-sums form for f1 is

f1(a,b,c) = M0 • M3 • M5 • M7 = (a+b+c)•(a+b’+c’)• (a’+b+c’)•(a’+b’+c’).

• Observe that: mj = Mj’

Shorthand: ∑ and ∏

• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and m(1,2,4,6)
indicates that the minterms to be included are m1, m2, m4, and m6.

• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and M(0,3,5,7)
indicates that the maxterms to be included are M0, M3, M5, and M7.

• Since mj = Mj’ for any j,

∑ m(1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)
•

Conversion between Canonical Forms

• Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with
those that do not.

• Example:
f1(a,b,c)= a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)

Standard Forms

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Another way to express Boolean functions is in standard form. In this configuration, the terms that
form the function may contain one, two, or any number of literals.
There are two types of standard forms: the sum of products and products of sums.
The sum of products is a Boolean expression containing AND terms, called product terms, with one
or more literals each. The sum denotes the ORing of these terms. An example of a function expressed
as a sum of products is
F1 = y’ + xy + x’yz’
The expression has three product terms, with one, two, and three literals. Their sum is, in effect, an
OR operation.
A product of sums is a Boolean expression containing OR terms, called sum terms. Each term may
have any number of literals. The product denotes the ANDing of these terms. An example of a
function expressed as a product of sums is
F2 = x(y’ + z)(x’ + y + z’)
This expression has three sum terms, with one, two, and three literals. The product is an AND
operation.
Conversion of SOP from standard to canonical form Example-1.
Express the Boolean function F = A + B’C as a sum of minterms.
Solution: The function has three variables: A, B, and C. The first term A is missing two variables;
therefore,
A = A(B + B’) = AB + AB’
This function is still missing one variable, so
A = AB(C + C’) + AB’ (C + C’)
= ABC + ABC’ + AB’C + AB’C’
The second term B’C is missing one variable; hence,
B’C = B’C(A + A’) = AB’C + A’B’C
Combining all terms, we have
F = A + B’C
= ABC + ABC’ + AB’C + AB’C’+ A’B’C
But AB’C appears twice, and according to theorem (x + x = x), it is possible to remove one of those
occurrences. Rearranging the minterms in ascending order, we finally obtain
F = A’B’C + AB’C + AB’C + ABC’ + ABC
= m1 + m4 + m5 + m6 + m7

DIGITAL LOGIC DESIGN Page no. 48

When a Boolean function is in its sum‐of‐minterms form, it is sometimes convenient to express the
function in the following brief notation:
F(A, B, C) = ∑m (1, 4, 5, 6, 7)

Example-2.
Express the Boolean function F = xy + x’z as a product of maxterms.
Solution: First, convert the function into OR terms by using the distributive law:
F = xy + x’z = (xy + x’)(xy + z)
= (x + x’)(y + x’)(x + z)(y + z)
= (x’+ y)(x + z)(y + z)
The function has three variables: x, y, and z. Each OR term is missing one variable; therefore, x’+ y =
x’ + y + zz’ = (x’ + y + z)(x’ + y + z’) x + z = x + z + yy’ = (x + y + z)(x + y’ + z) y + z = y + z + xx’ = (x + y +
z)(x’ + y + z)
Combining all the terms and removing those which appear more than once, we finally obtain
F = (x + y + z)(x + y’ + z)(x’ + y + z)(x’ + y + z)
F= M0M2M4M5
A convenient way to express this function is as follows: F(x, y, z) = πM(0, 2, 4, 5)
The product symbol, π, denotes the ANDing of maxterms; the numbers are the indices of the
maxterms of the function.

DIGITAL LOGIC DESIGN Page no. 49

 CHAPTER-2
MINIMIZATION TECHNIQUES
Two-variable k-map:

A two-variable k-map can have 22=4 possible combinations of the input variables A and B.
Each of these combinations, , B,A ,AB(in the SOP form) is called a minterm.

The minterm may be represented in terms of their decimal designations – m0 for , m1 for
B,m2 for A and m3 for AB, assuming that A represents the MSB. The letter m stands for
minterm and the subscript represents the decimal designation of the minterm. The
presence or absence of a minterm in the expression indicates that the output of the logic
circuit assumes logic 1 or logic 0 level for that combination of input variables.

The expression f= ,+ B+A +AB , it can be expressed using min

term as F= m0+m2+m3=∑m(0,2,3)

Using Truth Table:

Minterm Inputs Output F

A B
0 0 0 1
1 0 1 0
2 1 0 1
3 1 1 1
A 1 in the output contains that particular minterm in its sum and a 0 in that column
indicates that the particular mintermdoes not appear in the expression for output . this
information can also be indicated by a two-variable k-map.

Mapping of SOP Expresions:

A two-variable k-map has 22=4 squares .These squares are called cells. Each square on
the k- map represents a unique minterm. The minterm designation of the squares are
placed in any square, indicates that the corresponding minterm does output expressions.
And a 0 or no entry in any square indicates that the corresponding minterm does not
appear in the expression for output.

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 The minterms of a two-variable k-map
The mapping of the expressions =∑m(0,2,3)is

k-map of ∑m(0,2,3)

EX: Map the expressions f= B+A

F= m1+m2=∑m(1,2)The k-map is

Minimizations of SOP expressions:

To minimize Boolean expressions given in the SOP form by using the k-map, look for

adjacent adjacent squares having 1‘s minterms adjacent to each other, and combine them to
form larger squares to eliminate some variables. Two squares are said to be adjacent to each
other, if their minterms differ in only one variable. (i.e, B&A differ only in one variable. so
they may be combined to form a 2-square to eliminate the variable B.similarly all other.

The necessary condition for adjacency of minterms is that their decimal designations must
differ by a power of 2. A minterm can be combined with any number of minterms adjacent to it
to form larger squares. Two minterms which are adjacent to each other can be combined to

DIGITAL LOGIC DESIGN Page no. 51

form a bigger square called a 2-square or a pair. This eliminates one variable – the variable that
is not common to both the minterms. For EX:

m0 and m1 can be combined to yield,

f1 = m0+m1= + B= (B+

)= m0 and m2 can be combined to yield,

f2 = m0+m2= + = ( + )=

m1 and m3 can be combined to yield,

f3= m1+m3= B+AB=B( + )=B

m2 and m3 can be combined to

yield, f4 = m2+m3=A +AB=A(B+ )=A

m0 ,m1 ,m2 and m3 can be combined to yield,

= + +A +AB

= (B+ ) +A(B+ )

= +A

=1

f1= f2= f3=B f4=A f5=1

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 The possible minterm groupings in a two-variable k-map.

Two 2-squares adjacent to each other can be combined to form a 4-square. A 4-

square eliminates 2 variables. A 4-square is called a quad. To read the squares on the map
after minimization, consider only those variables which remain constant through the
square, and ignore the variables which are varying. Write the non complemented variable if
the variable is remaining constant as a 1, and the complemented variable if the variable is
remaining constant as a 0, and write the variables as a product term. In the above figure f1
read as , because, along the square , A remains constant as a 0, that is , as , where as B is
changing from 0 to 1.

EX: Reduce the minterm f= +A +AB using mapping Expressed in terms of minterms, the
given expression is F=m0+m1+m2+ m3=m∑(0,1,3)& the figure shows the k-map for f and its
reduction . In one 2-square, A is constant as a 0 but B varies from a 0 to a 1, and in the other
2- square, B is constant as a 1 but A varies from a 0 to a 1. So, the reduced expressions is +B.

It requires two gate inputs for realization as

f= +B (k-map in SOP form, and logic diagram.)

The main criterion in the design of a digital circuit is that its cost should be as low as
possible. For that the expression used to realize that circuit must be minimal.Since the cost
is proportional to number of gate inputs in the circuit in the circuit, an expression is
considered minimal only if it corresponds to the least possible number of gate inputs. &
there is no guarantee for that k-map in SOP is the real minimal. To obtain real minimal
expression, obtain the minimal expression both in SOP & POS form form by using k-maps
and take the minimal of these two minimals.

The 1‘s on the k-map indicate the presence of minterms in the output expressions,
where as the 0s indicate the absence of minterms .Since the absence of a minterm in the
SOP expression means the presense of the corresponding maxterm in the POS expression
of the same .when a SOP expression is plotted on the k-map, 0s or no entries on the k-map
DIGITAL LOGIC DESIGN Page no. 53
represent the maxterms. To obtain the minimal expression in the POS form, consider the 0s
on the k-map and follow the procedure used for combining 1s. Also, since the absence of a
maxterm in the POS expression means the presence of the corresponding minterm in the
SOP expression of the same , when a POS expression is plotted on the k-map, 1s or no
entries on the k-map represent the minterms. Mapping of POS expressions:

Each sum term in the standard POS expression is called a maxterm. A function in two
variables (A, B) has four possible maxterms, A+B,A+ , +B, +

. They are represented as M0, M1, M2, and M3respectively. The uppercase letter M stands for
maxterm and its subscript denotes the decimal designation of that maxterm obtained by
treating the non-complemented variable as a 0 and the complemented variable as a 1 and
putting them side by side for reading the decimal equivalent of the binary number so
formed.

For mapping a POS expression on to the k-map, 0s are placed in the squares
corresponding to the maxterms which are presented in the expression an d1s are placed in
the squares corresponding to the maxterm which are not present in the expression. The
decimal designation of the squares of the squares for maxterms is the same as that for the
minterms. A two-variable k-map & the associated maxterms are asthe maxterms of a two-
variable k-map

The possible maxterm groupings in a two-variable k-map

Minimization of POS Expressions:

To obtain the minimal expression in POS form, map the given POS expression on to
the K-map and combine the adjacent 0s into as large squares as possible. Read the squares
putting the complemented variable if its value remains constant as a 1 and the non-
DIGITAL LOGIC DESIGN Page no. 54
complemented variable if its value remains constant as a 0 along the entire square (
ignoring the variables which do not remain constant throughout the square) and then write
them as a sum term.

Various maxterm combinations and the corresponding reduced expressions are

shown in figure. In this f1 read as A because A remains constant as a 0 throughout the
square and B changes from a 0 to a 1. f2 is read as B‘ because B remains constant along the
square as a 1 and

A changes from a 0 to a 1. f5

Is read as a 0 because both the variables are changing along the square.

Ex: Reduce the expression f=(A+B)(A+B‘)(A‘+B‘) using mapping.

The given expression in terms of maxterms is f=πM(0,1,3). It requires two gates inputs
for realization of the reduced expression as

F=AB‘

K-map in POS form and logic diagram

In this given expression ,the maxterm M2 is absent. This is indicated by a 1 on the k-map. The
corresponding SOP expression is ∑m2 or AB‘. This realization is the same as that for the POS
form.

Three-variable K-map:

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 A function in three variables (A, B, C) expressed in the standard SOP form can have
eight possible combinations: A B C , AB C,A BC ,A BC,AB C ,AB C,ABC , and ABC. Each one of
these combinations designate d by m0,m1,m2,m3,m4,m5,m6, and m7, respectively, is called
a minterm. A is the MSB of the minterm designator and C is the LSB.

In the standard POS form, the eight possible combinations are:A+B+C, A+B+C ,
A+B +C,A+B + C ,A + B+ C,A + B + C ,A + B + C,A + B + C . Each oneof these combinations
designated by M0, M1, M2, M3, M4, M5, M6, and M7respectively is called a maxterm. A is the
MSB of the maxterm designator and C is the LSB.

A three-variable k-map has, therefore, 8(=23) squares or cells, and each square on
the map represents a minterm or maxterm as shown in figure. The small number on the
top right corner of each cell indicates the minterm or maxterm designation.

The three-variable k-map.

The binary numbers along the top of the map indicate the condition of B and C for
each column. The binary number along the left side of the map against each row indicates
the condition of A for that row. For example, the binary number 01 on top of the second
column in fig indicates that the variable B appears in complemented form and the variable
C in non- complemented form in all the minterms in that column. The binary number 0 on
the left of the first row indicates that the variable A appears in complemented form in all
the minterms in that row, the binary numbers along the top of the k-map are not in normal
binary order. They are, infact, in the Gray code. This is to ensure that twophysically
adjacent squares are really adjacent, i.e., their minterms or maxterms differ by only one
variable.

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 Ex: Map the expression f=: C+ + + +ABC

In the given expression , the minterms are : C=001=m 1 ; =101=m5;

=010=m2;

=110=m6;ABC=111=m7.

So the expression is f=∑m(1,5,2,6,7)= ∑m(1,2,5,6,7). The corresponding k-map is

K-map in SOP form

Ex: Map the expression f= (A+B+C),( + + ) ( + + )(A + + )( + + )

In the given expression the maxterms are

:A+B+C=000=M0; + + =101=M5; + + = 111=M7; A + + =011=M3; + + =110=M6.

So the expression is f = π M (0,5,7,3,6)= π M (0,3,5,6,7). The mapping of the expression is

K-map in POS form.

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 Minimization of SOP and POS expressions:

For reducing the Boolean expressions in SOP (POS) form plotted on the k-map, look

at the 1s (0s) present on the map. These represent the minterms (maxterms). Look for the
minterms (maxterms) adjacent to each other, in order to combine them into larger squares.
Combining of adjacent squares in a k-map containing 1s (or 0s) for the purpose of
simplification of a SOP (or POS)expression is called looping. Some of the minterms
(maxterms) may have many adjacencies. Always start with the minterms (maxterm) with
the least number of adjacencies and try to form as large as large a square as possible. The
larger must form a geometric square or rectangle. They can be formed even by wrapping
around, but cannot be formed by using diagonal configurations. Next consider the minterm
(maxterm) with next to the least number of adjacencies and form as large a square as
possible. Continue this till all the minterms (maxterms) are taken care of . A minterm
(maxterm) can be part of any number of squares if it is helpful in reduction. Read the
minimal expression from the k-map, corresponding to the squares formed. There can be
more than one minimal expression.

Two squares are said to be adjacent to each other (since the binary designations
along the top of the map and those along the left side of the map are in Gray code), if
they are physically adjacent to each other, or can be made adjacent to each other by
wrapping around. For squares to be combinable into bigger squares it is essential but
not sufficient that their minterm designations must differ by a power of two.

General procedure to simplify the Boolean expressions:

1. Plot the k-map and place 1s(0s) corresponding to the minterms (maxterms) of the SOP
(POS) expression.
2. Check the k-map for 1s(0s) which are not adjacent to any other 1(0). They are isolated
minterms(maxterms) . They are to be read as they are because they cannot be combined
even into a 2-square.

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 3. Check for those 1s(0S) which are adjacent to only one other 1(0) and make them pairs (2
squares).
4. Check for quads (4 squares) and octets (8 squares) of adjacent 1s (0s) even if they contain
some 1s(0s) which have already been combined. They must geometrically form a square
or a rectangle.
5. Check for any 1s(0s) that have not been combined yet and combine them into bigger
squares if possible.
6. Form the minimal expression by summing (multiplying) the product the product (sum)
terms of all the groups.
Reading the K-maps:
While reading the reduced k-map in SOP (POS) form, the variable which remains
constant as 0 along the square is written as the complemented (non-complemented)
variable and the one which remains constant as 1 along the square is written as non-
complemented (complemented) variable and the term as a product (sum) term. All the
product (sum) terms are added (multiplied).

Some possible combinations of minterms and the corresponding minimal

expressions readfrom the k-maps are shown in fig: Here f6 is read as 1, because along the 8-
square no variable remains constant. F5 is read as , because, along the 4-square formed
by0,m1,m2 and m3 , the variables B and C are changing, and A remains constant as a 0.
Algebraically, f5= m0+m1+m2+m3

= + C+ +
= ( +C)+ B(C+ )

= + B

= ( +B)=

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f3 is read as + , because in the 4-square formed by m0,m2,m6, and m4, the variable A and
B are changing , where as the variable C remains constant as a 0. So it is read as . In the 4-
square formed by m0, m1, m4, m5, A and C are changing but B remains constant as a 0. So it
is read as . So, the resultant expression for f3 is the sum of these two, i.e., + .

f1 is read as + + ,because in the 2-square formed by m0 and m4 , A is changing from

a 0 to a 1. Whereas B and C remain constant as a 0. So it s read as . In the 2-square
formed by m0 and m1, C is changing from a 0 to a 1, whereas A and B remain constant as a 0.
So it is read as .In the 2-square formed by m0 and m2 , B is changing from a 0 to a1
whereas A and C remain constant as a 0. So, it is read as . Therefore, the resultant
SOP expression is
++

Some possible maxterm groupings and the corresponding minimal POS expressions read
from the k-map are

In this figure, along the 4-square formed by M1, M3, M7, M5, A and B are changing from a 0
to a 1, where as C remains constant as a 1. SO it is read as . Along the 4-squad formed by

DIGITAL LOGIC DESIGN Page no. 60

M3, M2, M7, and M6, variables A and C are changing from a 0 to a 1. But B remains constant
as a 1. So it is read as . The minimal expression is the product of these two terms , i.e., f1 = (
)( ).also in this figure, along the 2-square formed by M4 and M6 , variable B is changing from
a 0 to a 1, while variable A remains constant as a 1 and variable C remains constant as a 0.
SO, read it as

+C. Similarly, the 2-square formed by M7 andM6 is read as + , while the 2-square
formed by M2 and M6 is read as +C. The minimal expression is the product of these sum
terms, i.e, f2 =( + )+( + )+( +C)

Ex:Reduce the expression f=∑m(0,2,3,4,5,6) using mapping and implement it in AOI logic
as well as in NAND logic.The Sop k-map and its reduction , and the implementation of the
minimal expression using AOI logic and the corresponding NAND logic are shown in figures
below

In SOP k-map, the reduction is done as:

1. m5 has only one adjacency m4 , so combine m5 and m4 into a square. Along this 2-
square A remains constant as 1 and B remains constant as 0 but C varies from 0 to 1.
So read it as A .
2. m3 has only one adjacency m2 , so combine m3 and m2 into a square. Along this 2-
square A remains constant as 0 and B remains constant as 1 but C varies from 1 to 0.
So read it as B.
3. m6 can form a 2-square with m2 and m4 can form a 2-square with m0, but observe
that by wrapping the map from left to right m0, m4 ,m2 ,m6 can form a 4-square. Out
of these m2 andm4 have already been combined but they can be utilized again. So
make it. Along this 4-square, A is changing from 0 to 1 and B is also changing from 0
to 1 but C is remaining constant as 0. so read it as .
4. Write all the product terms in SOP form. So the minimal SOP expression is

fmin=

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 k-map AOI logic NAND logic
Four variable k-maps:

Four variable k-map expressions can have 24=16 possible combinations of input variables such
as , ,------------ABCD with minterm designations m0,m1 -------------------- m15 respectively
in SOP form & A+B+C+D, A+B+C+ ,---------- + + + with maxterms M0,M1, ---------
-
-M15 respectively in POS form. It has 24=16 squares or cells.The binary number
designations of rows & columns are in the gray code. Here follows 01 & 10 follows 11
called Adjacency ordering.

SOP form POS form

EX:

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 Five variable k-map:

Five variable k-map can have 25 =32 possible combinations of input variable as
, E,--------ABCDE with minterms m0, m1-----m31 respectively in SOP &

A+B+C+D+E, A+B+C+ ,---------- + + + + with maxterms M0,M1, ----------- M31

respectively in POS form. It has 25=32 squares or cells of the k-map are divided into 2
blocks of

16 squares each.The left block represents minterms from m0 to m15 in which A is a 0, and
the right block represents minterms from m16 to m31 in which A is 1.The 5-variable k-map
may contain 2-squares, 4-squares , 8-squares , 16-squares or 32-squares involving these
two blocks. Squares are also considered adjacent in these two blocks, if when
superimposing one block on top of another, the squares coincide with one another.

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Grouping s is

Ex: F=∑m(0,1,4,5,6,13,14,15,22,24,25,28,29,30,31) is SOP

POS is F=πM(2,3,7,8,9,10,11,12,16,17,18,19,20,21,23,26,27)

The real minimal expression is the minimal of the SOP and POS forms.

The reduction is done as

1. There is no isolated 1s
2. M12 can go only with m13. Form a 2-square which is read as A‘BCD‘
3. M0 can go with m2,m16 and m18 . so form a 4-square which is read as B‘C‘E‘
4. M20,m21,m17 and m16 form a 4-square which is read as AB‘D‘

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 5. M2,m3,m18,m19,m10,m11,m26 and m27 form an 8-square which is read as C‘d
6. Write all the product terms in SOP form.

So the minimal expression is

Fmin= A‘BCD‘+B‘C‘E‘+AB‘D‘+C‘D(16 inputs)

In the POS k-map ,the reduction is done as:

1. There are no isolated 0s

3.

4.M8

5. M28

6.M30

7. Sum terms in POS form. So the minimal expression in POS is

Fmin= A‘BcD‘+B‘C‘E‘+AB‘D‘+C‘D

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 Six variable k-map:

Six variable k-map can have 26 =64 combinations as , ,---------

---ABCDEF with minterms m0, m1-----m63 respectively in SOP & (A+B+C+D+E+F), ---------- (
+ + + + + ) with maxterms M0,M1, -----------M63 respectively in POS form. It has
26=64 squares or cells of the k-map are divided into 4 blocks of 16 squares each.

Some possible groupings in a six variable k-map

Don’t care combinations:For certain input combinations, the value of the output is
unspecified either because the input combinations are invalid or because the precise value
of the output is of no consequence. The combinations for which the value of experiments
are not specified are called don‘t care combinations are invalid or because the precise value
of the output is of no consequence. The combinations for which the value of expressions is
not specified are called don‘t care combinations or Optional Combinations, such
expressions stand incompletely specified. The output is a don‘t care for these invalid
combinations.
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 Ex:In XS-3 code system, the binary states 0000, 0001, 0010,1101,1110,1111 are unspecified. &
never occur called don‘t cares.

A standard SOP expression with don‘t cares can be converted into a standard POS
form by keeping the don‘t cares as they are & writing the missing minterms of the SOP form as
the maxterms of the POS form viceversa.

Don‘t cares denoted by ‗X‘ or ‗φ‘

Ex:f=∑m(1,5,6,12,13,14)+d(2,4)

Or f=π M(0,3,7,9,10,11,15).πd(2,4)

SOP minimal form fmin= +B + POS

minimal form fmin=(B+D)( +B)( +D)

=++++(+

Prime implicants, Essential Prime implicants, Redundant prime implicants:

Each square or rectangle made up of the bunch of adjacent minterms is called a subcube.
Each of these subcubes is called a Prime implicant (PI). The PI which contains at leastone
which cannot be covered by any other prime implicants is called as Essential Prime
DIGITAL LOGIC DESIGN Page no. 67
 implicant (EPI).The PI whose each 1 is covered at least by one EPI is called a Redundant
Prime implicant (RPI). A PI which is neither an EPI nor a RPI is called a Selective Prime
implicant (SPI).

The function has unique MSP comprising EPI is

F(A,B,C,D)= CD+ABC+A D + B

The RPI ‗BD‘ may be included without changing the function but the resulting expression
would not be in minimal SOP(MSP) form.

Essential and Redundant Prime Implicants

F(A,B,C,D)=∑m(0,4,5,10,11,13,15) SPI are marked by dotted squares, shows
MSP form of a function need not be unique.

Essential and Selective Prime Implicants

Here, the MSP form is obtained by including two EPI‘s & selecting a set of SPI‘s to cover
remaining uncovered minterms 5,13,15. & these can be covered as
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 (A) (4,5) &(13,15) ---------- B +ABD
(B) (5,13) & (13,15) -------- B D+ABD
(C) (5,13) & (15,11) ------- B D+ACD

F(A,B,C,D)= +A C---------EPI‘s + B +ABD

(OR) F(A,B,C,D)= +A C---------EPI‘s + B D+ABD

(OR) F(A,B,C,D)= +A C---------EPI‘s + B D+ACD False PI’s

Essential False PI’s, Redundant False PI’s & Selective False PI’s:

The maxterms are called falseminterms. The PI‘s is obtained by using the
maxterms are called False PI‘s (FPI). The FPI which contains at least one ‗0‘ which can‘t be
covered by only other FPI is called an Essential False Prime implicant (ESPI)

F(A,B,C,D)= ∑m(0,1,2,3,4,8,12)

=π M(5,6,7,9,10,11,13,14,15)

Fmin= ( + )( + )( + )( + )

All the FPI, EFPI‘s as each of them contain atleast one ‗0‘ which can‘t be covered by any other
FPI

Essential False Prime implicants

Consider Function F(A,B,C,D)= π M(0,1,2,6,8,10,11,12)

DIGITAL LOGIC DESIGN Page no. 69

Essential and Redundant False Prime Implicants

Mapping when the function is not expressed in minterms (maxterms):

An expression in k-map must be available as a sum (product) of minterms (maxterms).

However if not so expressed, it is not necessary to expand the expression algebraically into
its minterms (maxterms). Instead, expansion into minterms (maxterms) can be
accomplished in the process of entering the terms of the expression on the k-map.
Limitations of Karnaugh maps:

• Convenient as long as the number of variables does not exceed six.

• Manual technique, simplification process is heavily dependent on the human abilities.
Quine-Mccluskey Method:

It also known as Tabular method. It is more systematic method of minimizing

expressions of even larger number of variables. It is suitable for hand computation as well
as computation by machines i.e., programmable. . The procedure is based on repeated
application of the combining theorem.

PA+P =P (P is set of literals) on all adjacent pairs of terms, yields the set of all PI‘s from
which a minimal sum may be selected.

Consider expression

∑m(0,1,4,5)= + C+A +A C
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First, second terms & third, fourth terms can be combined

( + )+ (C+ )= +A

Reduced to

( + )=

The same result can be obtained by combining m0& m4 & m1&m5 in first step & resulting
terms in the second step .

Procedure:

• Decimal Representation
• Don‘t cares
• PI chart
• EPI
• Dominating Rows & Columns
• Determination of Minimal expressions in comples cases.

Branching Method:

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 EX:

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 CHAPTER 3
COMBINATIONAL CIRCUITS
Combinational Logic

• Logic circuits for digital systems may be combinational or sequential.

• A combinational circuit consists of input variables, logic gates, and output

variables.

For n input variables,there are 2n possible combinations of binary input variables

.For each possible input Combination ,there is one and only one possible output
combination.A combinational circuit can be described by m Boolean functions one for each
output variables.Usually the input s comes from flip-flops and outputs goto flip-flops.

Design Procedure:

1. The problem is stated

2. The number of available input variables and required output variables is determined.

3.The input and output variables are assigned lettersymbols.

DIGITAL LOGIC DESIGN Page no. 77

 4.The truth table that defines the required relationship between inputs and outputs is
derived.

5.The simplified Boolean function for each output is obtained.

Adders:
Digital computers perform variety of information processing tasks,the one is
arithmetic operations.And the most basic arithmetic operation is the addition of two binary
digits.i.e, 4 basic possible operations are:

0+0=0,0+1=1,1+0=1,1+1=10

The first three operations produce a sum whose length is one digit, but when augends and
addend bits are equal to 1,the binary sum consists of two digits.The higher significant bit of
this result is called a carry.A combinational circuit that performs the addition of two bits is
called a half- adder. One that performs the addition of 3 bits (two significant bits & previous
carry) is called a full adder.& 2 half adder can employ as a full-adder.

The Half Adder: A Half Adder is a combinational circuit with two binary inputs (augends
and addend bits and two binary outputs (sum and carry bits.) It adds the two inputs (A and
B) and produces the sum (S) and the carry (C) bits. It is an arithmetic operation of addition
of two single bit words.

DIGITAL LOGIC DESIGN Page no. 78

The Sum(S) bit and the carry (C) bit, according to the rules of binary addition, the sum (S) is
the X-OR of A and B ( It represents the LSB of the sum). Therefore,

S=A𝐵+𝐴

The carry (C) is the AND of A and B (it is 0 unless both the inputs are 1).Therefore,

C=AB

A half-adder can be realized by using one X-OR gate and one AND gate a

Logic diagrams of half-adder

NAND LOGIC:

DIGITAL LOGIC DESIGN Page no. 79

 NOR Logic:

The Full Adder:

A Full-adder is a combinational circuit that adds two bits and a carry and outputs a
sum bit and a carry bit. To add two binary numbers, each having two or more bits, the LSBs
can be added by using a half-adder. The carry resulted from the addition of the LSBs is
carried over to the next significant column and added to the two bits in that column. So, in
the second and higher columns, the two data bits of that column and the carry bit
generated from the addition in the previous column need to be added.

DIGITAL LOGIC DESIGN Page no. 80

 The full-adder adds the bits A and B and the carry from the previous column called
the carry-in Cin and outputs the sum bit S and the carry bit called the carry-out Cout . The
variable S gives the value of the least significant bit of the sum. The variable Cout gives the
output carry.The eight rows under the input variables designate all possible combinations
of 1s and 0s that these variables may have. The 1s and 0s for the output variables are
determined from the arithmetic sum of the input bits. When all the bits are 0s , the output is
0. The S output is equal to 1 when only 1 input is equal to 1 or when all the inputs are equal
to 1. The Cout has a carry of 1 if two or three inputs are equal to 1.

From the truth table, a circuit that will produce the correct sum and carry bits in response
to every possible combination of A,B and Cin is described by

S = ABCin + ABCin + ABCin + ABCin

Cout = ABCin + ABCin + ABCin + ABCin

and

S=A B Cin

Cout = ACin + BCin + AB

The sum term of the full-adder is the X-OR of A,B, and Cin, i.e, the sum bit the modulo
sum of the data bits in that column and the carry from the previous column. The logic
DIGITAL LOGIC DESIGN Page no. 81
diagram of the full-adder using two X-OR gates and two AND gates (i.e, Two half adders)
and one OR gate is

Even though a full-adder can be constructed using two half-adders, the disadvantage is that
the bits must propagate through several gates in accession, which makes the total
propagation delay greater than that of the full-adder circuit using AOI logic.

The Full-adder neither can also be realized using universal logic, i.e., either only NAND
gates or only NOR gates as

NAND Logic:

DIGITAL LOGIC DESIGN Page no. 82

 NOR Logic:

Subtractors:

The subtraction of two binary numbers may be accomplished by taking the

complement of the subtrahend and adding it to the minuend. By this, the subtraction operation
becomes an addition operation and instead of having a separate circuit for subtraction, the
adder itself can be used to perform subtraction. This results in reduction of hardware. In
subtraction, each subtrahend bit of the number is subtracted from its corresponding
significant minuend bit to form a difference bit. If the minuend bit is smaller than the
subtrahend bit, a 1 is borrowed from the next significant position., that has been borrowed

DIGITAL LOGIC DESIGN Page no. 83

must be conveyed to the next higher pair of bits by means of a signal coming out (output) of a
given stage and going into (input) the next higher stage. The Half-Subtractor:

A Half-subtractor is a combinational circuit that subtracts one bit from the other and

produces the difference. It also has an output to specify if a 1 has been borrowed. . It is used
to subtract the LSB of the subtrahend from the LSB of the minuend when one binary
number is subtracted from the other.

A Half-subtractor is a combinational circuit with two inputs A and B and two

outputs d and b. d indicates the difference and b is the output signal generated that informs
the next stage that a 1 has been borrowed. When a bit B is subtracted from another bit A, a
difference bit (d) and a borrow bit (b) result according to the rules given as

The output borrow b is a 0 as long as A≥B. It is a 1 for A=0 and B=1. The d output is the
result of the arithmetic operation2b+A-B.

A circuit that produces the correct difference and borrow bits in response to every possible
combination of the two 1-bit numbers is , therefore ,

d=A𝐵+𝐴 and b=𝐴 B

That is, the difference bit is obtained by X-OR ing the two inputs, and the borrow bit is
obtained by ANDing the complement of the minuend with the subtrahend.Note that logic
for this exactly the same as the logic for output S in the half-adder.

DIGITAL LOGIC DESIGN Page no. 84

A half-substractor can also be realized using universal logic either using only NAND gates
or using NOR gates as:

NAND Logic:

NOR Logic:

DIGITAL LOGIC DESIGN Page no. 85

The Full-Subtractor:
The half-subtractor can be only for LSB subtraction. IF there is a borrow

during the subtraction of the LSBs, it affects the subtraction in the next higher column; the
subtrahend bit is subtracted from the minuend bit, considering the borrow from that
column used for the subtraction in the preceding column. Such a subtraction is performed
by a full-subtractor. It subtracts one bit (B) from another bit (A) , when already there is a
borrow bi from this column for the subtraction in the preceding column, and outputs the
difference bit (d) and the borrow bit(b) required from the next d and b. The two outputs
present the difference and output borrow. The 1s and 0s for the output variables are
determined from the subtraction of A-B-bi.

From the truth table, a circuit that will produce the correct difference and borrow bits in
response to every possiblecombinations of A,B and bi is

A full-subtractor can be realized using X-OR gates and AOI gates as

DIGITAL LOGIC DESIGN Page no. 86

The full subtractor can also be realized using universal logic either using only NAND gates
or using NOR gates as:

NAND Logic:

NOR Logic:

33
Binary Parallel Adder:

A binary parallel adder is a digital circuit that adds two binary numbers in parallel
form and produces the arithmetic sum of those numbers in parallel form. It consists of full
adders connected in a chain , with the output carry from each full-adder connected to the
input carry of the next full-adder in the chain.

The interconnection of four full-adder (FA) circuits to provide a 4-bit parallel adder.
The augends bits of A and addend bits of B are designated by subscript numbers from right
to left, with subscript 1 denoting the lower –order bit. The carries are connected in a chain
through the full-adders. The input carry to the adder is Cin and the output carry is C4. The S
output generates the required sum bits. When the 4-bit full-adder circuit is enclosed within
an IC package, it has four terminals for the augends bits, four terminals for the addend bits,
four terminals for the
sum bits, and two
terminals for the input and
output carries. AN n-bit
parallel adder requires
n-full adders. It can be
constructed from 4-bit, 2-bit and 1-bit full adder ICs by cascading several packages. The
output carry from one package must be connected to the input carry of the one with the
next higher –order bits. The 4-bit full adder is a typical example of an MSI function.

34
Ripple carry adder:

In the parallel adder, the carry –out of each stage is connected to the carry-in of

the next stage. The sum and carry-out bits of any stage cannot be produced, until sometime
after the carry-in of that stage occurs. This is due to the propagation delays in the logic
circuitry,

which lead to a time delay in the addition process. The carry propagation delay for each
full- adder is the time between the application of the carry-in and the occurrence of the
carry-out.

The 4-bit parallel adder, the sum (S1) and carry-out (C1) bits given by FA1 are not valid, until
after the propagation delay of FA1. Similarly, the sum S2 and carry-out (C2) bits given by FA2
are not valid until after the cumulative propagation delay of two full adders (FA1 and FA2) ,
and so on. At each stage ,the sum bit is not valid until after the carry bits in all the preceding
stages are valid. Carry bits must propagate or ripple through all stages before the most
significant sum bit is valid. Thus, the total sum (the parallel output) is not valid until after
the cumulative delay of all the adders.

The parallel adder in which the carry-out of each full-adder is the carry-in to the next most
significant adder is called a ripple carry adder.. The greater the number of bits that a ripple
carry adder must add, the greater the time required for it to perform a valid addition. If two
numbers are added such that no carries occur between stages, then the add time is simply
the

propagation time through a single full-adder.

35
 4- Bit Parallel Subtractor:

The subtraction of binary numbers can be carried out most conveniently by means of
complements , the subtraction A-B can be done by taking the 2‘s complement of B and
adding
it to A . The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 to
the least significant pair of bits. The 1‘s complement can be implemented with inverters as

Binary-Adder Subtractor:
A 4-bit adder-subtractor, the addition and subtraction operations are combined into
one circuit with one common binary adder. This is done by including an X-OR gate with
each full-adder. The mode input M controls the operation. When M=0, the circuit is an
adder, and when M=1, the circuit becomes a subtractor. Each X-OR gate receives input M
and one of the inputs of B. When M=0, .The full-adder receives the value of B , the
input carry is 0

36
 and the circuit performs A+B. when and C1=1. The B inputs are complemented
and a 1 is through the input carry. The circuit performs the operation A plus the 2‘s
complement of B.

The Look-Ahead –Carry Adder:

In parallel-adder,the speed with which an addition can be performed is governed by

the time required for the carries to propagate or ripple through all of the stages of the
adder. The look-ahead carry adder speeds up the process by eliminating this ripple carry
delay. It examines all the input bits simultaneously and also generates the carry-in bits for
all the stages simultaneously.

The method of speeding up the addition process is based on the two additional

functions of the full-adder, called the carry generate and carry propagate functions.

Consider one full adder stage; say the nth stage of a parallel adder as shown in fig.

we know that is made by two half adders and that the half adder contains an X-OR gate to
produce the sum and an AND gate to produce the carry. If both the bits An and Bn are 1s, a
carry has to be generated in this stage regardless of whether the input carry Cin is a 0 or a 1.
This is called generated carry, expressed as Gn= An.Bn which has to appear at the output
through the OR gate as shown in fig.

37
Thereis another possibility of producing a carry out. X-OR gate inside the half-adder

at the input produces an intermediary sum bit- call it Pn –which is expressed as

. Next Pn and Cn are added using the X-OR gate inside the second half adder to
produce the final

sum bit and and output carryC0= Pn.Cn=( )Cn which becomes carry for the (n+1)
thstage.

Consider the case of both Pn and Cn being 1. The input carry Cn has to be propagated

to the output only if Pn is 1. If Pn is 0, even if Cn is 1, the and gate in the second half-adder
will inhibit Cn . the carry out of the nth stage is 1 when either Gn=1 or Pn.Cn =1 or both Gn and
Pn.Cn are equal to 1.

For the final sum and carry outputs of the nth stage, we get the following
Boolean

expressions.

38
Observe the recursive nature of the expression for the output carry

at the nth stage which becomes the input carry for the (n+1)st stage .it is possible to
express the output carry of a higher significant stage is the carry-out of the previous stage.

Based on these , the expression for the carry-outs of various full adders are as follows,

Observe that the final output carry is expressed as a function of

the input variables in SOP form. Which is two level AND-OR or equivalent NAND-NAND
form. Observe that the full look-ahead scheme requires the use of OR gate with (n+1) inputs
and AND gates with number of inputs varying from 2 to (n+1).

39
2’s complement Addition and Subtraction using Parallel Adders:

Most modern computers use the 2‘s complement system to represent negative
numbers and to perform subtraction operations of signed numbers can be performed
using only the addition operation ,if we use the 2‘s complement form to represent negative
numbers.

The circuit shown can perform both addition and subtraction in the 2‘s complement.
This adder/subtractor circuit is controlled by the control signal ADD/SUB‘. When the
ADD/SUB‘ level is HIGH, the circuit performs the addition of the numbers stored in
registers A and B. When the ADD/Sub‘ level is LOW, the circuit subtract the number in
register B from the number in register A. The operation is:

When ADD/SUB‘ is a 1:

1. AND gates 1,3,5 and 7 are enabled , allowing B0,B1,B2and B3 to pass to the OR gates
9,10,11,12 . AND gates 2,4,6 and 8 are disabled , blocking B0‘,B1‘,B2‘, and B3‘ from
reaching the OR gates 9,10,11 and 12.

40
 2. The two levels B0 to B3 pass through the OR gates to the 4-bit parallel adder, to be
added to the bits A0 to A3. The sum appears at the output S0 to S3

3. Add/SUB‘ =1 causes no carry into the adder.

When ADD/SUB‘ is a 0:

1. AND gates 1,3,5 and 7 are disabled , allowing B0,B1,B2and B3 from reaching the OR
gates 9,10,11,12 . AND gates 2,4,6 and 8 are enabled , blocking B 0‘,B1‘,B2‘, and B3‘
from reaching the OR gates.

2. The two levels B0‘ to B3‘ pass through the OR gates to the 4-bit parallel adder, to be
added to the bits A0 to A3.The C0 is now 1.thus the number in register B is converted
to its 2‘s complement form.

3. The difference appears at the output S0 toS3.

Adders/Subtractors used for adding and subtracting signed binary numbers. In computers ,
the output is transferred into the register A (accumulator) so that the result of the addition
or subtraction always end up stored in the register A This is accomplished by applying a
transfer pulse to the CLK inputs of register A.

Serial Adder:

A serial adder is used to add binary numbers in serial form. The two binary numbers
to be added serially are stored in two shift registers A and B. Bits are added one pair at a

41
time through a single full adder (FA) circuit as shown. The carry out of the full-adder is
transferred to a D flip- flop. The output of this flip-flop is then used as the carry input for
the next pair of significant bits. The sum bit from the S output of the full-adder could be
transferred to a third shift register. By shifting the sum into A while the bits of A are shifted
out, it is possible to use one register for storing both augend and the sum bits. The serial
input register B can be used to transfer a new binary number while the addend bits are
shifted out during the addition.

The operation of the serial adder is:

Initially register A holds the augend, register B holds the addend and the carry flip-
flop is cleared to 0. The outputs (SO) of A and B provide a pair of significant bits for the full-
adder at x and y. The shift control enables both registers and carry flip-flop , so, at the clock
pulse both registers are shifted once to the right, the sum bit from S enters the left most
flip-flop of A , and the output carry is transferred into flip-flop Q . The shift control enables
the registers for a number of clock pulses equal to the number of bits of the registers. For
each succeeding clock pulse a new sum bit is transferred to A, a new carry is transferred to
Q, and both registers are shifted once to the right. This process continues until the shift
control is disabled. Thus the addition is accomplished by passing each pair of bits together
with the previous carry through a single full adder circuit and transferring the sum, one bit
at a time, into register A.

42
 Initially, register A and the carry flip-flop are cleared to 0 and then the first number is
added from B. While B is shifted through the full adder, a second number is transferred to it
through its serial input. The second number is then added to the content of register A while a
third number is transferred serially into register B. This can be repeated to form the addition of
two, three, or more numbers and accumulate their sum in register A.

Difference between Serial and Parallel Adders:

The parallel adder registers with parallel load, whereas the serial adder uses shift
registers. The number of full adder circuits in the parallel adder is equal to the number of bits in
the binary numbers, whereas the serial adder requires only one full adder circuit and a carry
flip- flop. Excluding the registers, the parallel adder is a combinational circuit, whereas the serial
adder is a sequential circuit. The sequential circuit in the serial adder consists of a full-adder and
a flip-flop that stores the output carry.

BCD Adder:

The BCD addition process:

1. Add the 4-bit BCD code groups for each decimal digit position using ordinary binary
addition.

2. For those positions where the sum is 9 or less, the sum is in proper BCD form and no
correction is needed.
 3. When the sum of two digits is greater than 9, a correction of 0110 should be added to
that sum, to produce the proper BCD result. This will produce a carry to be added to
the next decimalposition.

A BCD adder circuit must be able to operate in accordance with the above steps. In other words,
the circuit must be able to do the following:

1. Add two 4-bit BCD code groups, usingstraight binaryaddition.

2. Determine, if the sum of this addition is greater than 1101 (decimal 9); if it is , add 0110
(decimal 6) to this sum and generate a carry to the next decimalposition.

The first requirement is easily met by using a 4- bit binary parallel adder such as the 74LS83
IC .For example , if the two BCD code groups A3A2A1A0and B3B2B1B0 are applied to a 4-bit
parallel adder, the adder will output S4S3S2S1S0 , where S4 is actually C4 , the carry –out of the
MSB bits.

The sum outputs S4S3S2S1S0 can range anywhere from 00000 to 100109when both the
BCD code groups are 1001=9). The circuitry for a BCD adder must include the logic needed to
detect whenever the sum is greater than 01001, so that the correction can be added in. Those
cases , where the sum is greater than 1001 are listed as:

Let us define a logic output X that will go HIGH only when the sum is greater than 01001 (i.e,
for the cases in table). If examine these cases ,see that X will be HIGH for either of the following
conditions:
 1. Whenever S4 =1(sum greater than15)

2. Whenever S3 =1 and either S2 or S1 or both are 1 (sum 10 to 15)

This condition can be expressedas

X=S4+S3(S2+S1)

Whenever X=1, it is necessary to add the correction factor 0110 to the sum bits, and to
generate a carry. The circuit consists of three basic parts. The two BCD code groups A 3A2A1A0
and B3B2B1B0 are added together in the upper 4-bit adder, to produce the sum S4S3S2S1S0. The
logic gates shown implement the expression for X. The lower 4-bit adder will add the correction
0110 to the sum bits, only when X=1, producing the final BCD sum output represented by

∑3∑2∑1∑0. The X is also the carry-out that is produced when the sum is greater than 01001.

When X=0, there is no carry and no addition of 0110. In such cases, ∑3∑2∑1∑0= S3S2S1S0.

Two or more BCD adders can be connected in cascade when two or more digit decimal
numbers are to be added. The carry-out of the first BCD adder is connected as the carry-in of the
second BCD adder, the carry-out of the second BCD adder is connected as the carry-in of the
third BCD adder and so on.

EXCESS-3(XS-3) ADDER:

To perform Excess-3 additions,

1. Add two xs-3 codegroups

2. If carry=1, add 0011(3) to the sum of those two codegroups
 If carry =0, subtract 0011(3) i.e., add 1101 (13 in decimal) to the sum of those two code
groups. Ex: Add 9 and 5

1100 9 in Xs-3

+1000 5 in xs-3
___ _ _ __
1 0100 there is a carry

+0011 0011 add 3 to each group

---------- ----------
0100 0111 14 in xs-3

(1) (4)

EX:

Implementation of xs-3 adder using 4-bit binary adders is shown. The augend (A3

A2A1A0) and addend (B3B2B1B0) in xs-3 are added using the 4-bit parallel adder. If the carry is a

1, then 0011(3) is added to the sum bits S3S2S1S0 of the upper adder in the lower 4-bit
parallel
adder. If the carry is a 0, then 1101(3) is added to the sum bits (This is equivalent to subtracting
0011(3) from the sum bits. The correct sum in xs-3 is obtained

Excess-3 (XS-3) Subtractor:

To perform Excess-3 subtraction,

1. Complement thesubtrahend
 2. Add the complemented subtrahend to theminuend.
3. If carry =1, result is positive. Add 3 and end around carry to the result . Ifcarry=0, the
result is negative. Subtract 3, i.e, and take the 1‘s complement of the result.

Ex: Perform 9-4

1100 9 in xs-3

+1000 Complement of 4 n Xs-3

--------

(1) 0100 There is a carry

+0011 Add 0011(3)

------------

0111

1 End around carry

------------

1000 5 in xs-3

The minuend and the 1‘s complement of the subtrahend in xs-3 are added in the upper 4-
bit parallel adder. If the carry-out from the upper adder is a 0, then 1101 is added to the sum bits
of the upper adder in the lower adder and the sum bits of the lower adder are complemented to
get the result. If the carry-out from the upper adder is a 1, then 3=0011 is added to the sum bits
of the lower adder and the sum bits of the lower adder give the result.

Binary Multipliers:

In binary multiplication by the paper and pencil method, is modified somewhat in digital
machines because a binary adder can add only two binary numbers at a time.

In a binary multiplier, instead of adding all the partial products at the end, they are added two at
a time and their sum accumulated in a register (the accumulator register). In addition, when the
multiplier bit is a 0,0s are not written down and added because it does not affect the final result.
Instead, the multiplicand is shifted left by one bit.

The multiplication of 1110 by 1001 using this processis Multiplicand

1110

Multiplier 1001

1110 The LSB of the multiplier is a 1; write down the

multiplicand; shift the multiplicand one position to the
left (1 1 1 0 0 )
1110 The second multiplier bit is a 0; write down the previous
result 1110; shift the multiplicand to the left again (1 1 1
0
0 0)
+1110000 The fourth multiplier bit is a 1 write down the new multiplicand add it to the first
partial product to obtain the final product. 1111110

This multiplication process can be performed by the serial multiplier circuit , which multiplies two
4-bit numbers to produce an 8-bit product. The circuit consists of following elements
X register: A 4-bit shift register that stores the multiplier --- it will shift right on the falling edge
of the clock. Note that 0s are shifted in from the left.
B register: An 8-bit register that stores the multiplicand; it will shift left on the falling edge of the
clock. Note that 0s are shifted in from the right.
A register: An 8-bit register, i.e, the accumulator that accumulates the partial products.
Adder:An 8-bit parallel adder that produces the sum of A and B registers. The adder outputs S7
through S0 are connected to the D inputs of the accumulator so that the sum can be transferred
to the accumulator only when a clock pulse gets through the AND gate.
The circuit operation can be described by going through each step in the multiplication of 1110
by 1001. The complete process requires 4 clock cycles.
1. Before the first clock pulse: Prior to the occurrence of the first clock pulse, the register
A is loaded with 00000000, the register B with the multiplicand 00001110, and the register X
with the multiplier 1001. Assume that each of these registers is loaded using its asynchronous
inputs(i.e., PRESET and CLEAR). The output of the adder will be the sum of A and B,i.e.,
00001110.
2. First Clock pulse:Since the LSB of the multiplier (X0) is a 1, the first clock pulse gets
through the AND gate and its positive going transition transfers the sum outputs into the
accumulator. The subsequent negative going transition causes the X and B registers to shift
right and left, respectively. This produces a new sum of A andB.
3. Second Clock Pulse: The second bit of the original multiplier is now in X0 . Since this bit
is a 0, the second clock pulse is inhibited from reaching the accumulator. Thus, the sum
outputs are not transferred into the accumulator and the number in the accumulator does not
change. The negative going transition of the clock pulse will again shift the X and B registers.
Again a new sum is produced.
4. Third Clock Pulse:The third bit of the original multiplier is now in X0;since this bit is a 0,
the third clock pulse is inhibited from reaching the accumulator. Thus, the sum outputs are
not transferred into the accumulator and the number in the accumulator does not change. The
 negative going transition of the clock pulse will again shift the X and B registers. Again a new
sum is produced.
5. Fourth Clock Pulse: The last bit of the original multiplier is now in X0 , and since it is a 1,
the positive going transition of the fourth pulse transfers the sum into the accumulator. The
accumulator now holds the final product. The negative going transition of the clock pulse
shifts X and B again. Note that, X is now 0000, since all the multiplier bits have been shifted
out.

Code converters:

The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is sometimes
necessary to use the output of one system as the input to another. A conversion circuit must be

44
 inserted between the two systems if each uses different codes for the same information. Thus a
code converteris a logic circuit whose inputs are bit patterns representing numbers (or
character)in one cod and whose outputs are the corresponding representationin a different
code. Code converters are usually multiple output
circuits.
To convert from binary code A to binary code B, the input linesmust supply thebit
combination of elements as specified by code A and the output lines must generate the
correspondingbit combination of codeB. A combinationalcircuitperforms this transformation
by means of logicgates.
For example, a binary–to-gray code converter has four binary input lines , BB B 2,B 1 and four
gray code output lines 4G,G3,G2,G1. When the input is 0010, for instance,4 the3, output should be
0011and so forth. To design a code converter, we use a code table treating it as a truth table to
express each output as a Boolean algebraic functio
n of all the inputs.
In this example, of binary–to-gray code conversion, we can treat the binary to the
gray code table as four truth tables to derive expressions 4for ,
G3,
G G2, and G1. Each of these
four expressions would, in general, contain all the four input variables B 4, B3,B 2,and B1.
Thus,this code converter is actually equivalent to four logic circuits, one for each of the truth
tables.
The logic expression derived for the code converter can be simplified using the usual
techniques, including ‗don‘t cares‘ if present. Even if the input is an unweighted code, the same
cell numbering method which we used earlier can be used, but the cell numbers --must
correspond to the input combinations as if they were -4-2an
-18weighted code. s
Design of a-bit
4 binary to gray code converter:

45
Design of a 4-bit gray to Binary code converter:

46
D
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g
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f

4
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b
i
t

B
C
D

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o

X
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-
3

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o
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e

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o
n
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e Design of a BCD to gray code converter:
r
t
e
r
:

Design of a SOP circuit to Detect the Decimal numbers 5 through 12 in a 4 - bit gray code
Input:

Design of a SOP circuit to detect the decimal numbers 0,2,4,6,8 in a 4 -bit 5211 BCD code
input:

48
 Design of a Combinational circuit to produce the 2’s complement of a 4-bit binary number:

Comparators:

49
1. Magnitude Comparator:

1- bit Magnitude Comparator:

 50

4- Bit MagnitudeComparator:

51
IC Comparator:

ENCODERS:
 Octal to Binary Encoder:

Decimal to BCD Encoder:

Tristate bus system:

In digital electronicsthree-state, tri-state, or 3-statelogic allows an output port to assume a high

impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit.

This allows multiple circuits to share the same output line or lines (such as a bus which cannot listen to
more than one device at a time).

Three-state outputs are implemented in many registers, bus drivers, and flip-flops in the 7400 and 4000
series as well as in other types, but also internally in many integrated circuits. Other typical uses are
internal and external buses in microprocessors, computer memory, and peripherals. Many devices are
controlled by an active-low input called OE (Output Enable) which dictates whether the outputs should be
held in a high-impedance state or drive their respective loads (to either 0- or 1level).
 Chapter 4

SEQUENTIAL CIRCUITS
The Basic Latch

 Basic latchis a feedback connection of two NOR gates or two NAND gates

 It can store one bit of information

It can be set to 1 using the S input and reset to 0 using the

R input

The Gated Latch

 Gated latch is a basic latch that includes input gating and a control signal

 The latch retains its existing state when the control input is equal to 0

 Its state may be changed when the control signal is equal to 1. In our discussion
we referred to the control input as the clock We consider two types of gated
latches:

 Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to 0,
respectively.

 Gated D latch uses the D input to force the latch into a state that has the
samelogic value as the D input.

Gated S/R Latch

Gated D Latch
 Setup and Hold Times

 Setup Time tsu

The minimum time that the input signal must be stable prior to the edge of the clock
signal.

 Hold Time th

The minimum time that the input signal must be stable after the edge of the
clock signal.

Flip-Flops

 A flip-flop is a storage element based on the gated latch principle

 It can have its output state changed only on the edge of the controlling
clock signal

 We consider two types:

 Edge-triggered flip-flop is affected only by the input values present

when theactive edge of the clock occurs Master-slave flip-flop is built
with two gatedlatches

 The master stage is active during half of the clock cycle, and the slave
stage is active during the other half.

 The output value of the flip-flop changes on the edge of the clock that
activates the transfer into the slave stage.
 Master-Slave D Flip-Flop

A Positive-Edge-Triggered D Flip-Flop

Master-Slave D Flip-Flop with Clear and Preset

T Flip-Flop

Excitation Tables
Conversions of flip-flops
Sequential Circuit Design

• Steps in the design process for sequential circuits

• State Diagrams and State Tables Examples

• Steps in Design of a Sequential Circuit

o 1. Specification – A description of the sequential circuit. Should include a

detailing of the inputs, the outputs, and the operation. Possibly assumes that you
have knowledge of digital system basics.
o 2. Formulation: Generate a state diagram and/or a state table from the
statement of the problem.
o 3. State Assignment: From a state table assign binary codes to thestates.
o 4. Flip-flop Input Equation Generation: Select the type of flip-flop for the circuit
and generate the needed input for the required state transitions
o 5. Output Equation Generation: Derive output logic equations for generation of
the output from the inputs and current state. o 6. Optimization: Optimize the
input and output equations. Today, CAD systems are typically used for this in
real systems.
o 7. Technology Mapping: Generate a logic diagram of the circuit using ANDs, ORs,
Inverters, and F/Fs.
o 8. Verification: Use a HDL to verify the design Registers and Counters
• An n-bit register is a cascade of n flip-flops and can store an n-bit binary data

• A counter can count occurrences of events and can generate timing intervals for
control purposes A Simple Shift Register
Parallel-Access Shift Register
Counters

• Counters are a specific type of sequential circuit.

• Like registers, the state, or the flip-flop values themselves, serves as the “output.”

• The output value increases by one on each clock cycle.

• After the largest value, the output “wraps around” back to 0.

 • Using two bits, we’d get something like this:
Present State Next State

A B A B

0 0 0 1
0 1 1 0

1 0 1 1

1 1 0 0

Benefits of counters

• Counters can act as simple clocks to keep track of

“time.” • You may need to record how many times
something has happened. – How many bits
have been sent or received?

– How many steps have been performed in some computation?

• All processors contain a program counter, or
PC.

– Programs consist of a list of instructions that are to be executed one after

another (for the most part). – The PC keeps track of the instruction
currently being executed.

– The PC increments once on each clock cycle, and the next program
instruction is then executed.
 A Three-Bit Up-Counter
Q1 is connected to clk, Q2 and Q3 are clocked by Q’ of the preceding stage (hence
called asynchronous or ripple counter

A Three-Bit Down-Counter

Shift registers:
In digital circuits, a shift register is a cascade of flip-flops sharing the same clock, in which
the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain,
resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the
data present at its input and shifting out the last bit in the array, at each transition of the
clock input. More generally, a shift register may be multidimensional, such that its "data
in" and stage outputs are themselves bit arrays: this is implemented simply by running
several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often
configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are
also types that have both serial and parallel input and types with serial and parallel output.
There are also bi- directional shift registers which allow shifting in both directions: L→R
or R→L. The serial input and last output of a shift register can also be connected to create a
circular shift register

Shift registers are a type of logic circuits closely related to counters. They are basically for
the storage and transfer of digital data.

Buffer register:
The buffer register is the simple set of registers. It is simply stores the binary word. The buffer
may be controlled buffer. Most of the buffer registers used D Flip-flops.

Figure: logic diagram of 4-bit buffer register

The figure shows a 4-bit buffer register. The binary word to be stored is applied to the data
terminals. On the application of clock pulse, the output word becomes the same as the
word applied at the terminals. i.e., the input word is loaded into the register by the
application of clock pulse.

When the positive clock edge arrives, the stored word becomes:
Q4Q3Q2Q1=X4X3X2X1

Q=X

Controlled buffer register:

If goes LOW, all the FFs are RESET and the output becomes, Q=0000.
When is HIGH, the register is ready for action. LOAD is the control input. When

LOAD is HIGH, the data bits X can reach the D inputs of FF‘s.

Q4Q3Q2Q1=X4X3X2X1

Q=X

When load is low, the X bits cannot reach the FF‘s.

Data transmission in shift registers:

A number of ff‘s connected together such that data may be shifted into and shifted out of
them is called shift register. data may be shifted into or out of the register in serial form or
in parallel form. There are four basic types of shift registers.
 1. Serial in, serial out, shift right, shift registers
2. Serial in, serial out, shift left, shift registers
3. Parallel in, serial out shift registers
4. Parallel in, parallel out shift registers
Serial IN, serial OUT, shift right, shift left register:

The logic diagram of 4-bit serial in serial out, right shift register with four stages. The
register can store four bits of data. Serial data is applied at the input D of the first FF. the Q
output of the first FF is connected to the D input of another FF. the data is outputted from
the Q terminal of the last FF.

When serial data is transferred into a register, each new bit is clocked into the first FF at
the positive going edge of each clock pulse. The bit that was previously stored by the first
FF is transferred to the second FF. the bit that was stored by the Second FF is transferred to
the third FF.

Serial-in, parallel-out, shift register:

In this type of register, the data bits are entered into the register serially, but the data stored
in the register is shifted out in parallel form.
 Once the data bits are stored, each bit appears on its respective output line and all
bits are available simultaneously, rather than on a bit-by-bit basis with the serial output.
The serial-in, parallel out, shift register can be used as serial-in, serial out, shift register if
the output is taken from the Q terminal of the last FF.

Parallel-in, serial-out, shift register:

For a parallel-in, serial out, shift register, the data bits are entered simultaneously into
their respective stages on parallel lines, rather than on a bit-by-bit basis on one line as with
serial data bits are transferred out of the register serially. On a bit-by-bit basis over a single
line.

There are four data lines A,B,C,D through which the data is entered into the register in
parallel form. The signal shift/ load allows the data to be entered in parallel form into the
register and the data is shifted out serially from terminalQ4

Parallel-in, parallel-out, shift register

 In a parallel-in, parallel-out shift register, the data is entered into the register in parallel
form, and also the data is taken out of the register in parallel form. Data is applied to the D
input terminals of the FF‘s. When a clock pulse is applied, at the positive going edge of the
pulse, the D inputs are shifted into the Q outputs of the FFs. The register now stores the
data. The stored data is available instantaneously for shifting out in parallel form.

Bidirectional shift register:

A bidirectional shift register is one which the data bits can be shifted from left to right

or from right to left. A fig shows the logic diagram of a 4-bit serial-in, serial out,
bidirectional shift register. Right/left is the mode signal, when right /left is a 1, the logic
circuit works as a shift-register.the bidirectional operation is achieved by using the mode
signal and two NAND gates and one OR gate for each stage.

A HIGH on the right/left control input enables the AND gates G1, G2, G3 and G4 and
disables the AND gates G5,G6,G7 and G8, and the state of Q output of each FF is passed
through the gate to the D input of the following FF. when a clock pulse occurs, the data bits
are then effectively shifted one place to the right. A LOW on the right/left control inputs
enables the AND gates G5, G6, G7 and G8 and disables the And gates G1, G2, G3 and G4 and
the Q output of each FF is passed to the D input of the preceding FF. when a clock pulse
occurs, the data bits are then effectively shifted one place to the left. Hence, the circuit
works as a bidirectional shift register

Figure: logic diagram of a 4-bit bidirectional shift register

Universal shift register:

A register is capable of shifting in one direction only is a unidirectional shift register. One
that can shift both directions is a bidirectional shift register. If the register has both shifts
and parallel load capabilities, it is referred to as a universal shift registers. Universal shift
register is a bidirectional register, whose input can be either in serial form or in parallel
form and whose output also can be in serial form or I parallel form.

The most general shift register has the following capabilities.

1. A clear control to clear the register to 0

2. A clock input to synchronize the operations
3. A shift-right control to enable the shift-right operation and serial input and output
lines associated with the shift-right
4. A shift-left control to enable the shift-left operation and serial input and output lines
associated with the shift-left
5. A parallel loads control to enable a parallel transfer and the n input lines associated
with the parallel transfer
6. N parallel output lines
 7. A control state that leaves the information in the register unchanged in the presence
of the clock.

A universal shift register can be realized using multiplexers. The below fig shows the
logic diagram of a 4-bit universal shift register that has all capabilities. It consists of 4 D
flip-flops and four multiplexers. The four multiplexers have two common selection inputs
s1 and s0. Input 0 in each multiplexer is selected when S1S0=00, input 1 is selected when
S1S0=01 and input 2 is selected when S1S0=10 and input 4 is selected when S1S0=11. The
selection inputs control the mode of operation of the register according to the functions
entries. When S1S0=0, the present value of the register is applied to the D inputs of flip-
flops. The condition forms a path from the output of each flip-flop into the input of the same
flip-flop. The next clock edge transfers into each flip-flop the binary value it held
previously, and no change of state occurs. When S1S0=01, terminal 1 of the multiplexer
inputs have a path to the D inputs of the flip-flop. This causes a shift-right operation, with
serial input transferred into flip-flopA4. When S1S0=10, a shift left operation results with
the other serial input going into flip-flop A1. Finally when S1S0=11, the binary information
on the parallel input lines is transferred into the register simultaneously during the next
clock cycle
 Figure: logic diagram 4-bit universal shift register
Function table for theregister

mode control

S0 S1 register operation

0 0 No change

0 1 Shift Right

1 0 Shift left
1 1 Parallel load

Counters:

Counter is a device which stores (and sometimes displays) the number of times
particular event or process has occurred, often in relationship to a clock signal. A Digital
counter is a set of flip flops whose state change in response to pulses applied at the input to
the counter. Counters may be asynchronous counters or synchronous counters.
Asynchronous counters are also called ripple counters

In electronics counters can be implemented quite easily using register-type circuits such
as the flip-flops and a wide variety of classifications exist:

• Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state
flip-flops
• Synchronous counter – all state bits change under control of a singleclock
• Decade counter – counts through ten states per stage
• Up/down counter – counts both up and down, under command of a control input
• Ring counter – formed by a shift register with feedback connection in a ring
• Johnson counter – a twisted ring counter
Cascaded counter
Modulus counter.
Each is useful for different applications. Usually, counter circuits are digital in nature, and
count in natural binary Many types of counter circuits are available as digital building
blocks, for example a number of chips in the 4000 series implement different counters.

Occasionally there are advantages to using a counting sequence other than the natural
binary sequence such as the binary coded decimal counter, a linear feed-back shift register
counter, or a gray-code counter.

Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.

Asynchronous counters:

An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input
fed from its own inverted output. This circuit can store one bit, and hence can count from
zero to one before it overflows (starts over from 0). This counter will increment once for
every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate
between a transition from 0 to 1 and a transition from 1 to 0. Notice that this creates a new
clock with a 50% duty cycle at exactly half the frequency of the input clock. If this output is
then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the
output to the input), one will get another 1 bit counter that counts half as fast. Putting them
together yields a two-bit counter:

Two-bit ripple up-counter using negative edge triggered flip flop:

Two bit ripple counter used two flip-flops. There are four possible states from 2 – bit up-
counting I.e. 00, 01, 10 and 11.

· The counter is initially assumed to be at a state 00 where the outputs of the tow flip-flops are
noted as Q1Q0. Where Q1 forms the MSB and Q0 forms the LSB.

· For the negative edge of the first clock pulse, output of the first flip-flop FF1 toggles its state.
Thus Q1 remains at 0 and Q0 toggles to 1 and the counter state are now read as 01.
· During the next negative edge of the input clock pulse FF1 toggles and Q0 = 0. The output
Q0 being a clock signal for the second flip-flop FF2 and the present transition acts as a
negative edge for FF2 thus toggles its state Q1 = 1. The counter state is now read as 10.

· For the next negative edge of the input clock to FF1 output Q0 toggles to 1. But this
transition from 0 to 1 being a positive edge for FF2 output Q1 remains at 1. The counter
state is now read as 11.

· For the next negative edge of the input clock, Q0 toggles to 0. This transition from 1 to 0
acts as a negative edge clock for FF2 and its output Q1 toggles to 0. Thus the starting state 00
is attained. Figure shown below

Two-bit ripple down-counter using negative edge triggered flip flop:

A 2-bit down-counter counts in the order 0,3,2,1,0,1…….,i.e, 00,11,10,01,00,11 …..,etc. the above
fig. shows ripple down counter, using negative edge triggered J-K FFs and its timing diagram.
• For down counting, Q1‘ of FF1 is connected to the clock of Ff2. Let initially all the FF1
toggles, so, Q1 goes from a 0 to a 1 and Q1‘ goes from a 1 to a 0.
• The negative-going signal at Q1‘ is applied to the clock input of FF2, toggles Ff2 and,
therefore, Q2 goes from a 0 to a 1.so, after one clock pulse Q2=1 and Q1=1, I.e., the
state of the counter is 11.
• At the negative-going edge of the second clock pulse, Q1 changes from a 1 to a 0 and
Q1‘ from a 0 to a 1.
• This positive-going signal at Q1‘ does not affect FF2 and, therefore, Q2 remains at a 1.
Hence , the state of the counter after second clock pulse is 10
• At the negative going edge of the third clock pulse, FF1 toggles. So Q1, goes from a 0 to
a 1 and Q1‘ from 1 to 0. This negative going signal at Q1‘ toggles FF2 and, so, Q2
changes from 1 to 0, hence, the state of the counter after the third clock pulse is 01.
 • At the negative going edge of the fourth clock pulse, FF1 toggles. So Q1, goes from a 1
to a 0 and Q1‘ from 0 to 1. . This positive going signal at Q1‘ does not affect FF2 and,
so, Q2 remains at 0, hence, the state of the counter after the fourth clock pulse is 00.

Two-bit ripple up-down counter using negative edge triggered flip flop:

Figure: asynchronous 2-bit ripple up-down counter using negative edge triggered flip
flop:

• As the name indicates an up-down counter is a counter which can count both in
upward and downward directions. An up-down counter is also called a
forward/backward counter or a bidirectional counter. So, a control signal or a mode
signal M is required to choose the direction of count. When M=1 for up counting, Q1 is
transmitted to clock of FF2 and when M=0 for down counting, Q1‘ is transmitted to
clock of FF2. This is achieved by using two AND gates and one OR gates. The external
clock signal is applied to FF1.
• Clock signal to FF2= (Q1.Up)+(Q1‘. Down)= Q1m+Q1‘M‘

Design of Asynchronous counters:

To design a asynchronous counter, first we write the sequence , then tabulate the
values of reset signal R for various states of the counter and obtain the minimal expression
for R and R‘ using K-Map or any other method. Provide a feedback such that R and R‘ resets
all the FF‘s after the desired count

Design of a Mod-6 asynchronous counter using T FFs:

 A mod-6 counter has six stable states 000, 001, 010, 011, 100, and 101. When the
sixth clock pulse is applied, the counter temporarily goes to 110 state, but immediately
resets to 000 because of the feedback provided. it is ―divide by-6-counter‖, in the
sense that it divides the input clock frequency by 6.it requires three FFs, because the
smallest value of n satisfying the conditionN≤2n is n=3; three FFs can have 8 possible states,
out of which only six are utilized and the remaining two states 110and 111, are invalid. If
initially the counter is in 000 state, then after the sixth clock pulse, it goes to 001, after the
second clock pulse, it goes to 010, and so on.

After sixth clock pulse it goes to 000. For the design, write the truth table with present
state outputs Q3, Q2 and Q1 as the variables, and reset R as the output and obtain an
expression for R in terms of Q3, Q2, and Q1that decides the feedback into be provided.
From the truth table, R=Q3Q2. For active-low Reset, R‘ is used. The reset pulse is of very
short duration, of the order of nanoseconds and it is equal to the propagation delay time of
the NAND gate used. The expression for R can also be determined as follows.
 R=0 for 000 to 101, R=1 for 110, and R=X=for111

Therefore,

R=Q3Q2Q1‘+Q3Q2Q1=Q3Q2

The logic diagram and timing diagram of Mod-6 counter is shown in the above fig.

The truth table is as shown in below.

After States
pulses Q3 Q2 Q1 R

0 0 0 0 0
1 0 0 1 0

2 0 1 0 0

3 0 1 1 0

4 1 0 0 0

5 1 0 1 0

6 1 1 0 1

0 0 0
0
7 0 0 0 0

Design of a mod-10 asynchronous counter using T-flip-flops:

A mod-10 counter is a decade counter. It also called a BCD counter or a divide-by-10
counter. It requires four flip-flops (condition 10 ≤2n is n=4). So, there are 16 possible
states, out of which ten are valid and remaining six are invalid. The counter has ten stable
state, 0000 through 1001, i.e., it counts from 0 to 9. The initial state is 0000 and after nine
clock pulses it goes to 1001. When the tenth clock pulse is applied, the counter goes to state
1010 temporarily, but because of the feedback provided, it resets to initial state 0000. So,
there will be a glitch in the waveform of Q2. The state 1010 is a temporary state for which
the reset signal R=1, R=0 for 0000 to 1001, and R=C for 1011 to 1111.

The count table and the K-Map for reset are shown in fig. from the K-Map R=Q4Q2. So,
feedback is provided from second and fourth FFs. For active –HIGH reset, Q4Q2 is applied
to the clear terminal. For active-LOW reset 4 2 is connected isof all Flip=flops.

After Count
pulses Q4 Q3 Q2 Q1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 0 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 0 1 0 1
10 0 0 0 0

Synchronous counters:
 Asynchronous counters are serial counters. They are slow because each FF can change
state only if all the preceding FFs have changed their state. if the clock frequency is very
high, the asynchronous counter may skip some of the states. This problem is overcome in
s
y
n
c
h
r
o
nous counters or parallel counters. Synchronous counters are counters in which all the flip
flops are triggered simultaneously by the clock pulses Synchronous counters have a
common clock pulse applied simultaneously to all flip- -Bit Synchronous Binary Counter

Design of synchronous counters:

For a systematic design of synchronous counters. The following procedure is used.

Step 1:State Diagram: draw the state diagram showing all the possible states state diagram
which also be called nth transition diagrams, is a graphical means of depicting the
sequence of states through which the counter progresses.

Step2: number of flip-flops: based on the description of the problem, determine the
required number n of the flip-flops- the smallest value of n is such that the number of states
N≤2n--- and the desired counting sequence.

Step3: choice of flip-flops excitation table: select the type of flip-flop to be used and write
the excitation table. An excitation table is a table that lists the present state (ps) , the next
state(ns) and required excitations.

Step4: minimal expressions for excitations: obtain the minimal expressions for the
excitations of the FF using K-maps drawn for the excitation of the flip-flops in terms of the
present states and inputs.
Step5: logic diagram: draw a logic diagram based on the minimal expressions

Design of a synchronous 3-bit up-down counter using JK flip-flops:

Step1: determine the number of flip-flops required. A 3-bit counter requires three FFs. It
has 8 states (000,001,010,011,101,110,111) and all the states are valid. Hence no don‘t
cares. For selecting up and down modes, a control or mode signal M is required. When the
mode signal M=1 and counts down when M=0. The clock signal is applied to all the FFs
simultaneously.

Step2: draw the state diagrams: the state diagram of the 3-bit up-down counter is drawn as

Step3: select the type of flip flop and draw the excitation table: JK flip-flops are selected and
the excitation table of a 3-bit up-down counter using JK flip-flops is drawn as shown in fig.

PS mode NS required excitations

Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 1 1 1 1 x 1 x 1 x
0 0 0 1 0 0 1 0 x 0 x 1 x
0 0 1 0 0 0 0 0 x 0 x x 1
0 0 1 1 0 1 0 0 x 1 x x 1
0 1 0 0 0 0 1 0 x x 1 1 x
0 1 0 1 0 1 1 0 x x 0 1 x
0 1 1 0 0 1 0 0 x x 0 x 1
0 1 1 1 1 0 0 1 x x 1 x 1
1 0 0 0 0 1 1 x 1 1 x 1 x
1 0 0 1 1 0 1 x 0 0 x 1 x
1 0 1 0 1 0 0 x 0 0 x x 1
1 0 1 1 1 1 0 x 0 1 x x 1
1 1 0 0 1 0 1 x 0 x 1 1 x
1 1 0 1 1 1 1 x 0 x 0 1 x
1 1 1 0 1 1 0 x 0 x 0 x 1
1 1 1 1 0 0 0 x 1 x 1 x 1
 Step4: obtain the minimal expressions: From the excitation table we can conclude that
J1=1 and K1=1, because all the entries for J1and K1 are either X or 1. The K-maps for J3,
K3,J2 and K2 based on the excitation table and the minimal expression obtained from them
are shown in fig.

1
1
X X X X
X X X X

00 01 11 10
Q3Q2 Q1M

Step5: draw the logic diagram: a logic diagram using those minimal expressions can be drawn as
shown in fig.

Design of a synchronous modulo-6 gray cod counter:

Step 1: the number of flip-flops: we know that the counting sequence for a modulo-6 gray code
counter is 000, 001, 011, 010, 110, and 111. It requires n=3FFs (N≤2 n, i.e., 6≤23). 3 FFs can
have

8 states. So the remaining two states 101 and 100 are invalid. The entries for excitation
corresponding to invalid states are don‘t cares.

Step2: the state diagram: the state diagram of the mod-6 gray code converter is drawn as
shown in fig.
Step3: type of flip-flop and the excitation table: T flip-flops are selected and the excitation
table of the mod-6 gray code counter using T-flip-flops is written as shown in fig.

required
PS NS excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 0 1
0 1 0 1 1 0 1 0 0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Step4: The minimal expressions: the K-maps for excitations of FFs T3,T2,and T1 in terms
of outputs of FFs Q3,Q2, and Q1, their minimization and the minimal expressions for
excitations obtained from them are shown if fig
Step5: the logic diagram: the logic diagram based on those minimal expressions is drawn as
shown in fig.

Design of a synchronous BCD Up-Down counter using FFs:

Step1: the number of flip-flops: a BCD counter is a mod-10 counter has 10 states (0000
through 1001) and so it requires n=4FFs(N≤2n,, i.e., 10≤24). 4 FFS can have 16 states. So out of
16 states, six states (1010 through 1111) are invalid. For selecting up and down mode, a
control or mode signal M is required. , it counts up when M=1 and counts down when M=0. The
clock signal is applied to all FFs.

Step2: the state diagram: The state diagram of the mod-10 up-down counter is drawn as
shown in fig.

Step3: types of flip-flops and excitation table: T flip-flops are selected and the excitation table
of the modulo-10 up down counter using T flip-flops is drawn as shown in fig.

The remaining minterms are don‘t cares(∑d(20,21,22,23,24,25,26,37,28,29,30,31))

from the excitation table we can see that T1=1 and the expression for T4,T3,T2 are
asfollows. T4=∑m(0,15,16,19)+d(20,21,22,23,24,25,26,27,28,29,30,31)
T3=∑m(7,15,16,8)+d(20,21,22,23,24,25,26,27,28,29,30,31)

T2=∑m(3,4,7,8,11,12,15,16)+d(20,21,22,23,24,25,26,27,28,29,30,31)

PS NS

mode required excitations

Q4 Q3 Q2 Q1 M Q4 Q3 Q2 Q1 T4 T3 T2 T1
0 0 0 0 0 1 0 0 1 1 0 0 1
0 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 1 0 1 0 0 1 1 0 0 0 1
0 0 1 1 0 0 0 1 0 0 0 0 1
 0 0 1 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 0 0 1 1 0 1 1 1
0 1 0 0 1 0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 0 1 1 0 1 1 0 0 0 1 1
0 1 1 0 0 0 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 0 0 0 1
0 1 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 0 0 0 1
1 0 0 1 0 1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 0 0 1 0 0 1
Step4: The minimal expression: since there are 4 state variables and a mode signal, we
require 5 variable kmaps. 20 conditions of Q4Q3Q2Q1M are valid and the remaining 12
combinations are invalid. So the entries for excitations corresponding to those invalid
combinations are don‘t cares. Minimizing K-maps for T2 we get

T 2= Q4Q1‘M+Q4‘Q1M+Q2Q1‘M‘+Q3Q1‘M‘

Step5: the logic diagram: the logic diagram based on the above equation is shown in fig.

Shift register counters:

One of the applications of shift register is that they can be arranged to form several types of
counters. The most widely used shift register counter is ring counter as well as the twisted ring
counter.
Ring counter: this is the simplest shift register counter. The basic ring counter using D flip-
flops is shown in fig. the realization of this counter using JK FFs. The Q output of each stage
is connected to the D flip-flop connected back to the ring counter.

FIGURE: logic diagram of 4-bit ring counter using D flip-flops

Only a single 1 is in the register and is made to circulate around the register as long as
clock pulses are applied. Initially the first FF is present to a 1. So, the initial state is 1000,
i.e., Q1=1, Q2=0,Q3=0,Q4=0. After each clock pulse, the contents of the register are shifted
to the right by one bit and Q4 is shifted back to Q1. The sequence repeats after four clock
pulses. The number

of distinct states in the ring counter, i.e., the mod of the ring counter is equal to number of
FFs used in the counter. An n-bit ring counter can count only n bits, where as n-bit ripple
counter can count 2n bits. So, the ring counter is uneconomical compared to a ripple
counter but has advantage of requiring no decoder, since we can read the count by simply
noting which FF is set. Since it is entirely a synchronous operation and requires no gates
external FFs, it has the further advantage of being very fast. Timing diagram:
Twisted Ring counter (Johnson counter):

This counter is obtained from a serial-in, serial-out shift register by providing

feedback from the inverted output of the last FF to the D input of the first FF. the Q output
of each is connected to the D input of the next stage, but the Q‘ output of the last stage is
connected to the D input of the first stage, therefore, the name twisted ring counter. This
feedback arrangement produces a unique sequence of states.

The logic diagram of a 4-bit Johnson counter using D FF is shown in fig. the
realization of the same using J-K FFs is shown in fig.. The state diagram and the sequence
table are shown in figure. The timing diagram of a Johnson counter is shown in figure.

Let initially all the FFs be reset, i.e., the state of the counter be 0000. After each clock

pulse, the level of Q1 is shifted to Q2, the level of Q2to Q3, Q3 to Q4 and the level of Q4‘to Q1
and the sequences given in fig.

Figure: Johnson counter with JK flip-flops

Figure: timing diagram

 CHAPTER 5

MEMORY

Memory structures are crucial in digital design. – ROM, PROM, EPROM, RAM, SRAM,
(S)DRAM, RDRAM,..

➢ All memory structures have an address bus and a data bus – Possibly other control
signals to control output etc. •E.g. 4 Bit Address bus with 5 Bit Data Bus ADDR DOUT

There are two types of memories that are used in digital systems:

o Random-access memory(RAM): perform both the write and read

operations.
o Read-only memory(ROM): perform only the read operation.

The read-only memory is a programmable logic device. Other such units are the
programmablelogic array(PLA), the programmable array logic(PAL), and the field-
programmable gatearray(FPGA).

Random-Access Memory:

A memory unit stores binary information in groups of bits called words.

• byte = 8 bits
• word = 2 bytes

The communication between a memory and its environment is achieved through data
input andoutput lines, address selection lines, and control lines that specify the
direction oftransfer.
In random-access memory, the word locationsmay be thoughtof as being separated in space, with

each word occupying one particular location.

In sequential-access memory, the information stored in some medium is not

immediately accessible, but is available only certain intervals of time. A magnetic disk or
tape unit is of this type.

In a random-access memory, the access time is always the same regardless of the
particular locationof the word.
 In a sequential-access memory, the time it takes to access a word depends on the position of the
word with respect to the reading head position; therefore, theaccess time is variable.
Static RAM

SRAM consists essentially of internal latches that store the binaryinformation.

The stored information remains valid as long as power is applied to the unit.

SRAM is easier to use and has shorter read and write cycles.

Low density, low capacity, high cost, high speed, high power consumption.

Dynamic RAM

DRAM stores the binary information in the form of electric charges oncapacitors.

The capacitors are provided inside the chip by MOS transistors.

The capacitors tends to discharge with time and must be periodically recharged by refreshing the
dynamic memory.

DRAM offers reduced power consumption and larger storage capacity in a single memorychip.

High density, high capacity, low cost, low speed, low power consumption.
Memory decoding

The equivalent logic of a binary cell that stores one bitof information is shownbelow.

 Read/Write = 0, select = 1, input data to S-R latch

 Read/Write = 1, select = 1, output data from S-R latch
 Programmable Logic Array:

The decoder in PROM is replaced by an array of AND gates that can be programmed to
generate any product term of the input variables.

The product terms are then connected to OR gates to provide the sum of products
forthe required Boolean functions.

➢ The output is inverted when the XOR input is connected to 1 (since x⊕1 = x’). The
output doesn’t change and connect to 0 (since x⊕0 = x).

F1 =

AB’+AC+A’BC’

F2 = (AC+BC)’
 Implement the following two Boolean functions with a PLA:
• F ( A, B, C) = ∑(0, 1, 2, 4)
1
• F ( A, B, C) = ∑(0, 5, 6, 7)
2

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JOB
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 DIGITAL LOGIC DESIGN
Question Bank with Answer &
Explanation

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The Decimal Number System

1. The value of base in a decimal number system is ____________

a) 8
b) 2
c) 10
d) 16
Answer: c
Explanation: A decimal number system consists of 10 digits from 0 to 9.
The definition of base describes it as a quantity to represent the number of digits present in that
particular number system.
Therefore, here, the base is 10.

2. Convert : (110)2 = ( __ )10.

a) 4
b) 5
c) 6
d) 9
Answer: c
Explanation: The base 2 represents that the number is binary ,whereas, the base 10 represents
that it is to be converted to the decimal format.
Conversion: 22 * 1 + 21 * 1 + 20 *0 = 6.

3. The 2’s complement of 15 is ____________

a) 0000
b) 0001
c) 0010
d) 0100
Answer: b
Explanation: 2’s complement is obtained by adding 1 to the 1’s complement of the number.
Here, Binary of 15 = 1111
1’s complement of 15= 0000
2’s complement of 15= 0000+1=0001.

4. Another name for base is __________

a) root
b) radix
c) entity
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d) median
Answer: b
Explanation: Another name for base is radix. Base refers to the number of digits that a particular
number system consists of.
The base of decimal number system is 10, binary is 2 and so on.

5. The decimal equivalent of (0.101)2 will be ____________

a) 0.5
b) 0.625
c) 0.25
d) 0.875
Answer: b
Explanation: Since the base is 2 , it could be easily guessed that the number is binary.
Conversion: 2-1 * 1 + 2-2 * 0 + 2-3 * 1 = 0.625.

6. The signed magnitude for -3 will be ___________

a) 00000011
b) 10000011
c) 11111101
d) 11111100
Answer: b
Explanation: Signed Magnitude of a number is a representation to determine if the number is
positive or negative.
If the MSB of a number is 0, the number is positive, else if it is 1 the number is negative.
Here, +3 = 00000011
-3= 100000011.

7. A number with both integer and a fractional part has digits raised to both positive and negative
powers of 2 in a decimal number system.
a) True
b) False
Answer: b
Explanation: In a decimal number system, a number with both integer and a fractional part has
digits raised to both positive and negative powers of 10 and not 2.
e.g. 22.34 = 2 * 101 + 2 * 100 + 3 * 10-1 + 4 * 10-2.

8. The hexadecimal representation of 14 is _______________

a) A
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b) F
c) D
d) E
Answer: d
Explanation: The hexadecimal representations are as follows:
10 : A
11 : B
12 : C
13 : D
14 : E
15 : F.

9. Which of the following is not a decimal number?

a) 114
b) 43.47
c) 99.9A
d) 10101
Answer: c
Explanation: All the numbers except 99.9A are decimal numbers.
This number has a hexadecimal component A in it, therefore , it is not a valid decimal number.
The decimal equivalent of A is 10.

10. Select the incorrect option:

a) (101)10 = (1100101)2
b) G is valid in hexadecimal system.
c) C represents 12
d) The base of a decimal number system is 10.
Answer: b
Explanation: G is not a valid hexadecimal number. In this system, only representations from A to
E are used to represent the numbers from 10 to 15. The base of the hexadecimal number system
is 16.

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The Binary Number System
11. Which of the following is not a positional number system?
a) Roman Number System
b) Octal Number System
c) Binary Number System
d) Hexadecimal Number System
Answer: a
Explanation: The Roman number system isn’t a positional number system since it uses symbols
to represent numbers.
The octal number system uses digits from 0-7, the binary number system uses digits from 0-1
whereas, the hexadecimal number system uses digits from 0-15.

12. The value of radix in binary number system is _____________

a) 2
b) 8
c) 10
d) 1
Answer: a
Explanation: In a binary number system, the value of base or radix is 2. The binary system uses
only two digits for the representation of numbers, therefore its base id has chosen to be 2.

13. The binary equivalent of the decimal number 10 is __________

a) 0010
b) 10
c) 1010
d) 010
Answer: c
Explanation: To get the binary equivalent of any number, we need to divide the number by 2 and
obtain the remainders as :

We then write the remainders in the reverse order as 1010 .

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14. A computer language that is written in binary codes only is _____
a) machine language
b) C
c) C#
d) pascal
Answer: a
Explanation: Machine Language is written in binary codes only. It can be easily understood by
the computer and is very difficult for us to understand. A machine language, unlike other
languages, requires no translators or interpreters.

15. The octal equivalent of 1100101.001010 is ______

a) 624.12
b) 145.12
c) 154.12
d) 145.21
Answer: b
Explanation: The octal equivalent is obtained by grouping the numbers into three, from right to
left before decimal and from right to left after the decimal place.
Here,

i.e. 145.12 is the octal equivalent of the number.

16. The input hexadecimal representation of 1110 is _______________

a) 0111
b) E
c) 15
d) 14
Answer: b
Explanation: In hexadecimal number system, 1110 = 15, which is represented by the alphabet E.
Some representations are:
A 10

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B 11
C 12
D 13
E 14
F 15.

17. A bit in a computer terminology means either 0 or 1.

a) True
b) False
Answer: a
Explanation: A bit stands for a binary digit. A binary digit can have only two digits i.e. 0 or 1. A
binary number consisting of n-bits is called an n-bit number.

18. Convert the binary equivalent 10101 to its decimal equivalent.

a) 21
b) 12
c) 22
d) 31
Answer: a
Explanation: To convert a binary number to its decimal equivalent follow these steps :
24 * 1 + 23 * 0 + 22 *1 + 21 * 0 + 20 * 1 = 21.
Therefore, the answer is 21.

19. Which of the following is not a binary number?

a) 1111
b) 101
c) 11E
d) 000
Answer: c
Explanation: A binary number can have only two possible digits, 0 and 1. In the third option,
there is an alphabet E present which makes it an invalid binary number. Alphabets are only
allowed in the hexadecimal number system.

20. Which of the following is the correct representation of a binary number?

a) (124)2
b) 1110
c) (110)2
d) (000)2
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Answer: d
Explanation: The binary numbers should comprise only two digits 0 and 1.
Also, for the base, the value should be 2 and it should be written as a subscript enclosing the
entire number. Here, the fourth option gives the correct representation.

The Octal Number System

21. What could be the maximum value of a single digit in an octal number system?
a) 8
b) 7
c) 6
d) 5
Answer: b
Explanation: The maximum value in any number system is one less than the value of the base.
The base in an octal number system is 8, therefore, the maximum value of the single digit is 7. It
takes digits from 0 to 7.

22. In a number system, each position of a digit represents a specific power of the base.
a) True
b) False
Answer: a
Explanation: In a number system, every digit is denoted by a specific power of base. Like in an
octal system, consider the number 113, it will be represented as :
82 * 1 + 81 * 1 + 80 *3.

23. The maximum number of bits sufficient to represent an octal number in binary is _______
a) 4
b) 3
c) 7
d) 8
Answer: b
Explanation: The octal number system comprises of only 8 digits. Hence, three bits (23 = 8) are
sufficient to represent any octal number in the binary format.

24. The binary number 111 in octal format is ________________

a) 6
b) 7

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c) 8
d) 5
Answer: b
Explanation: Certain binary to octal representations are :
000=0
001=1
010=2
011=3
100=4
101=5
110=6
111=7.

25. Convert (22)8 into its corresponding decimal number.

a) 28
b) 18
c) 81
d) 82
Answer: b
Explanation: To convert an octal number to decimal number:
81 * 2 + 80 * 2 = 16 + 2 = 18.
Hence, the decimal equivalent is 18.

26. The octal equivalent of the binary number (0010010100)2 is ______________

a) 422
b) 242
c) 224
d) 226
Answer: c
Explanation: To obtain the octal equivalent, we take numbers in groups of 3, from right to left as
:
000 010 010 100

0 2 2 4 = (224)₈.
27. Octal subtraction of (232)8 from (417)8 will give ______________
a) 165
b) 185
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c) 815
d) 516
Answer: a
Explanation: Octal subtraction is done as follows:
417
– 232
________
165
The octal subtraction is the same as that of any other number system. The only difference is, like
in a decimal number system, we borrow a group of 10, in a binary system we borrow a group of
2, in an octal number system, we borrow in groups of 8.

28. The 1’s complement of 0.101 is _________________

a) 1.010
b) 0.010
c) 0.101
d) 1.101
Answer: a
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0
and the bits with value 0 to 1.
Here, 0.101 gets converted to 1.010 in its 1’s complement format.

29. Convert (5401)8 to hexadecimal.

a) A01
b) A02
c) B01
d) C01
Answer: c
Explanation: To convert octal to hexadecimal, we first write binary format of the number and
then make groups of 4 bits from right to left, as follows:
5 4 0 1
101 100 000 001 (octal -> binary)
1011 0000 0001 ( groups of 4)
B 0 1 ( hexadecimal equivalent)
Therefore, the hexadecimal equivalent is (B01)16.

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30. Express the decimal format of the signed binary number (10010)2 .
a) 2
b) 12
c) -12
d) -2
Answer: d
Explanation: The first bit is the sign bit whereas the rest of the bits are magnitude bits. So the
number is: 0010 = 21 * 1 =2
But, the sign bit is 1, Therefore the answer is : (-2)10.

The Hexadecimal Number System

31. What does the symbol D represent in a hexadecimal number system?
a) 8
b) 16
c) 13
d) 14
Answer: c
Explanation: The symbols A, B, C, D, E and F represent 10, 11, 12, 13, 14 and 15 respectively in
a hexadecimal system. This system comprises of 15 numbers in total: digits from 0-9 and
symbols from A to F.

32. ABC is a valid hexadecimal number.

a) True
b) False
Answer: a
Explanation: In a hexadecimal number system, alphabets are used for the representation of
numbers from 10 to 15. Here, A represents 10, B represents 11 and C represents 12. Therefore, it
is a valid hexadecimal number.

33. The maximum number of bits sufficient to represent a hexadecimal number in binary:
a) 4
b) 3
c) 7
d) 8
Answer: a

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Explanation: The hexadecimal number system comprises of only 15 symbols: 10 digits and 5
symbols. Hence, three bits (24 = 16 ) are sufficient to represent any hexadecimal number in the
binary format.

34. The binary number 1110 in hexadecimal format is _____________

a) 6
b) E
c) 14
d) 15
Answer: b
Explanation: Certain binary to hexadecimal representations are :
1010=A
1011=B
1100=C
1101=D
1110=E
1111=F.

35. Convert (52)16 into its decimal equivalent.

a) 28
b) 83
c) 80
d) 82
Answer: d
Explanation: To convert a hexadecimal number to decimal number:
161 * 5 + 160 * 2 = 80 + 2 = 82
Hence, the decimal equivalent is 82.

36. The hexadecimal equivalent of the binary number (0010010100)2 is :

a) 0B4
b) 0A4
c) 224
d) 0114
Answer: c
Explanation: To obtain the octal equivalent, we take numbers in groups of 3, from right to left as

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:

37. Hexadecimal Addition of (3A5)16 and (1B2)16 will give :

a) 165
b) 185
c) 815
d) 516
Answer: a
Explanation: Octal subtraction is done as follows:
3A5
+ 1B2
________
557
In hexadecimal addition of alphabets, we add the corresponding numbers they represent and then
subtract the result from 16, then generate a carry of 1 to the next set of numbers.
Here, 5+2=7
A+B=10+11=21-16=5
3+1+1(carry)=5.

38. The 2’s complement of 10.11 :

a) 10
b) 0.010
c) 01.01
d) 10.01
Answer: a
Explanation: The 1’s complement of a number is obtained by reversing the bits with value 1 to 0
and the bits with value 0 to 1. Here, 10.11 gets converted to 01.00 in its 1’s complement format.
Further, to convert 1’s complement into 2’s, we add 1 to the result. Here, 01.00+1=10.00.

39. Convert (6532)8 to hexadecimal.

a) A01

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b) A02
c) B01
d) C01
Answer: c
Explanation: To convert octal to hexadecimal, we first write binary format of the number and
then make groups of 4 bits from right to left, as follows:
6 5 3 2
110 101 011 010 (octal -> binary)
1101 0101 1010 ( groups of 4)
D 5 A ( hexadecimal equivalent)
Therefore, the hexadecimal equivalent is (D5A)16.

40. What do we call the point(decimal) in any hexadecimal number of the form 111.A3?
a) radix
b) hexadecimal point
c) decimal
d) octal point
Answer: b
Explanation: The decimal is often referred to as the hexadecimal point in hexadecimal
representation of numbers.
It is referred to as the octal point in octal numbers.

Data Types
41. Which of the following is not a data type?
a) Symbolic Data
b) Alphanumeric Data
c) Numeric Data
d) Alphabetic Data
Answer: a
Explanation: Data types are of three basic types: Numeric, Alphabetic and Alphanumeric.
Numeric Data consists of only numbers.
Alphabetic Data consists of only letters and a blank character and alphanumeric data consists of
symbols.

42. *@Ac# is a type of ________________ data.

a) Symbolic

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b) Alphanumeric
c) Alphabetic
d) Numeric
Answer: b
Explanation: Alphanumeric data consists of symbols. Alphanumeric data may be a letter, either
in uppercase or lowercase or some special symbols like #,^,*,(, etc.

43. Which of the following is not a valid representation in bits?

a) 8-bit
b) 24-bit
c) 32-bit
d) 64-bit
Answer: b
Explanation: There are no criteria like the 24-bit representation of numbers. Numbers can be
written in 8-bit, 16-bit, 32-bit and 64-bit as per the IEEE format.

44. What are the entities whose values can be changed called?
a) Constants
b) Variables
c) Modules
d) Tokens
Answer: b
Explanation: Variables are the data entities whose values can be changed. Constants have a fixed
value. Tokens are the words which are easily identified by the compiler.

45. Which of the following is not a basic data type in C language?

a) float
b) int
c) real
d) char
Answer: c
Explanation: There are 5 basic data types in C language: int, char, float, double, void.
Int is for the representation of integers, char is for strings and characters, float and double are for
floating point numbers whereas void is a valueless special data type.

46. BOOLEAN is a type of data type which basically gives a tautology or fallacy.
a) True
b) False
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Answer: a
Explanation: A Boolean representation is for giving logical values. It returns either true or false.
If a result gives a truth value, it is called tautology whereas if it returns a false term, it is referred
to as fallacy.

47. What does FORTRAN stands for?

a) Formula Transfer
b) Formula Transformation
c) Formula Translation
d) Format Transformation
Answer: c
Explanation: FORTRAN is a type of computer language. It was developed for solving
mathematical and scientific problems. It is very commonly used among the scientific
community.

48. The program written by the programmer in high level language is called _____________
a) Object Program
b) Source Program
c) Assembled Program
d) Compiled Program
Answer: b
Explanation: The program written by the programmer is called a source program. The program
generated by the compiler after compilation is called an object program. The object program is in
machine language.

49. A standardized language used for commercial applications.

a) C
b) Java
c) COBOL
d) FORTRAN
Answer: c
Explanation: COBOL is a language used in business and commercial applications. It stands for
Common Business Oriented Language. It is imperative, procedural as well as object oriented
language.

50. ______________ define how the locations can be used.

a) Data types
b) Attributes
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c) Links
d) Data Objects
Answer: b
Explanation: Attributes can determine how any location can be used. Attributes can be type,
name, component, etc. Data objects are the variables and constants in a program.

Number System
51. Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble
Answer: a
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.

52. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
Answer: c
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a
combination of four bits and Byte is a combination of 8 bits. It is “word” which is said to be a
collection of 16-bits on most of the systems.

53. If the decimal number is a fraction then its binary equivalent is obtained by ________ the
number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Answer: b
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is

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obtained by the collection of the integer part. However, if it’s an integer, then it’s binary
equivalent is determined by dividing the number by 2 and collecting the remainders.

54. The representation of octal number (532.2)8 in decimal is ________

a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10

55. The decimal equivalent of the binary number (1011.011)2 is ________

a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base
index along with the value at that index position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10

56. An important drawback of binary system is ________

a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Answer: a
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s
and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for
calculation purposes as it compresses the long binary strings into small parts.

57. The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
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d) (501)10
Answer: c
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = (421)10.

58. The largest two digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Answer: c
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal
system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.

59. Representation of hexadecimal number (6DE)H in decimal:

a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Answer: a
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of
base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.

60. The quantity of double word is ________

a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.

61. The given hexadecimal number (1E.53)16 is equivalent to ____________

a) (35.684)8
b) (36.246)8
c) (34.340)8
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d) (35.599)8
Answer: b
Explanation: First, the hexadecimal number is converted to it’s equivalent binary form, by
writing the binary equivalent of each digit in form of 4 bits. Then, the binary equivalent bits are
grouped in terms of 3 bits and then for each of the 3-bits, the respective digit is written. Thus, the
octal equivalent is obtained.
(1E.53)16 = (0001 1110.0101 0011)2
= (00011110.01010011)2
= (011110.010100110)2
= (011 110.010 100 110)2
= (36.246)8

62. The octal number (651.124)8 is equivalent to ______

a) (1A9.2A)16
b) (1B0.10)16
c) (1A8.A3)16
d) (1B0.B0)16
Answer: a
Explanation: First, the octal number is converted to it’s equivalent binary form, by writing the
binary equivalent of each digit in form of 3 bits. Then, the binary equivalent bits are grouped in
terms of 4 bits and then for each of the 4-bits, the respective digit is written. Thus, the
hexadecimal equivalent is obtained.
(651.124)8 = (110 101 001.001 010 100)2
= (110101001.001010100)2
= (0001 1010 1001.0010 1010)2
= (1A9.2A)16

63. The octal equivalent of the decimal number (417)10 is _____

a) (641)8
b) (619)8
c) (640)8
d) (598)8
Answer: a
Explanation: Octal equivalent of decimal number is obtained by dividing the number by 8 and
collecting the remainders in reverse order.
8 | 417

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8 | 52 — 1
8|6–4
So, (417)10= (641)8

64. Convert the hexadecimal number (1E2)16 to decimal:

a) 480
b) 483
c) 482
d) 484
Answer: c
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of
base index along with the value at that index position.
(1E2)16 = 1 * 162 + 14 * 161 + 2 * 160 (Since, E = 14)
= 256 + 224 + 2 = (482)10

65. (170)10 is equivalent to

a) (FD)16
b) (DF)16
c) (AA)16
d) (AF)16
Answer: c
Explanation: Hexadecimal equivalent of decimal number is obtained by dividing the number by
16 and collecting the remainders in reverse order.
16 | 170
16 | 10 – 10
Hence, (170)10 = (AA)16

66. Convert (214)8 into decimal:

a) (140)10
b) (141)10
c) (142)10
d) (130)10
Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
(214)8 = 2 * 8v + 1 * 81 + 4 * 80
= 128 + 8 + 4 = (140)10

JOB
67. Convert (0.345)10 into an octal number:
a) (0.16050)8
b) (0.26050)8
c) (0.19450)8
d) (0.24040)8
Answer: b
Explanation: Converting decimal fraction into octal number is achieved by multiplying the
fraction part by 8 everytime and collecting the integer part of the result, unless the result is 1.
0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.26050)8

68. Convert the binary number (01011.1011)2 into decimal:

a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.7893)10
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base
index along with the value at that index position.
(01011)2 = 0 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 1 * 20 = 11
(1011)2 = 1 * 2-1 + 0 * 2-2 + 1 * 2-3 + 1 * 2-4 = 0.6875
So, (01011.1011)2 = (11.6875)10

69. Octal to binary conversion: (24)8 =?

a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
Answer: b
Explanation: Each digit of the octal number is expressed in terms of group of 3 bits. Thus, the
binary equivalent of the octal number is obtained.
(24)8 = (010100)2

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70. Convert binary to octal: (110110001010)2 =?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
Answer: b
Explanation: The binary equivalent is segregated into groups of 3 bits, starting from left. And
then for each group, the respective digit is written. Thus, the octal equivalent is obtained.
(110110001010)2 = (6612)8

Arithmetic Operation
71. What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
Answer: c
Explanation: The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
1

11011011010

+00010100101
_______________________
11101111111
_______________________
72. Perform binary addition: 101101 + 011011 = ?
a) 011010
b) 1010100
c) 101110
d) 1001000
Answer: d
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Explanation:The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
111111
101101
+011011
_______________
1001000
_______________
Therefore, the addition of 101101 + 011011 = 1001000.

73. Perform binary subtraction: 101111 – 010101 = ?

a) 100100
b) 010101
c) 011010
d) 011001
Answer: c
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
101111
-010101
____________
011010
_____________
Therefore, The subtraction of 101111 – 010101 = 011010.

74. Binary subtraction of 100101 – 011110 is

a) 000111
b) 111000
c) 010101
d) 101010
Answer: a
Explanation: The rules for Binary Subtraction are :

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0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
100101
-011110
___________
000111
___________
Therefore, The subtraction of 100101 – 011110 = 000111.

75. Perform multiplication of the binary numbers: 01001 × 01011 = ?

a) 001100011
b) 110011100
c) 010100110
d) 101010111
Answer: a
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
01001
x01011
____________
01001
010010
0000000
01001000
000000000
___________________
001100011
___________________
Therefore, 01001 × 01011 = 001100011.

76. 100101 × 0110 = ?

a) 1011001111
b) 0100110011
c) 101111110

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d) 0110100101
Answer: c
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
100101
x 0110
___________
000000
1001010
10010100
000000000
__________________
011011110
___________________
Therefore, 100101 x 0110 = 011011110.

77. On multiplication of (10.10) and (01.01), we get

a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
Answer: c
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
1 0.1 0
x 0 1.0 1
__________
1010
00000
101000
0000000
_______________
0 1 1.0 0 1 0
_________________
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Therefore, 10.10 x 01.01 = 011.0010.

78. Divide the binary numbers: 111101 ÷ 1001 and find the remainder
a) 0010
b) 1010
c) 1100
d) 0011
Answer: d
Explanation: Binary Division is accomplished using long division method.
1001)111101(11
1001
__________
01100
1001
___________
0111
Therefore, the remainder of 111101 ÷ 1001 = 0111.

79. Divide the binary number (011010000) by (0101) and find the quotient
a) 100011
b) 101001
c) 110010
d) 010001
Answer: b
Explanation:
0101)011010000(010111
0000
_____________________
01101
00101
______________
010000
000000
______________________
10000
00101
____________________
010110
000101
____________________
100010

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 000101
________________________
111010
000101
________________________
10101
00101
________________________
10000
Therefore, the quotient of 011010000 ÷ 1001 = 101001.

80. Binary subtraction of 101101 – 001011 = ?

a) 100010
b) 010110
c) 110101
d) 101100
Answer: a
Explanation: The rules for binary subtraction are:
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
101101
-001011
____________
100010
____________
Therefore, the subtraction of 101101 – 001011 = 100010.

1’s, 2’s, 9’s & 10’s Complements

81. 1’s complement of 1011101 is ____________
a) 0101110
b) 1001101
c) 0100010
d) 1100101
Answer: c
Explanation: 1’s complement of a binary number is obtained by reversing the binary bits. All the
1’s to 0’s and 0’s to 1’s.
JOB
Thus, 1’s complement of 1011101 = 0100010.

82. 2’s complement of 11001011 is ____________

a) 01010111
b) 11010100
c) 00110101
d) 11100010
Answer: c
Explanation: 2’s complement of a binary number is obtained by finding the 1’s complement of
the number and then adding 1 to it.
2’s complement of 11001011 = 00110100 + 1 = 00110101.

83. On subtracting (01010)2 from (11110)2 using 1’s complement, we get ____________
a) 01001
b) 11010
c) 10101
d) 10100
Answer: d
Explanation: Steps For Subtraction using 1’s complement are:
-> 1’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and 1 is added to the last bit of the result.
-> Else, if there is no carry, then 1’s complement of the result is found out and a ‘-’ sign preceeds
the result.
111
Minuend - 11110
1’s complement of subtrahend - 10101
____________
Carry over - 1 10011
1
_____________
10100
84. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ____________
a) 0111001
b) 1100101
c) 0110110
d) 1000011
Answer: d
Explanation: Steps For Subtraction using 2’s complement are:

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-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds
the result.
1’s complement of subtrahend - 1101001
_________________
111
Minuend - 1011001
2’s complement of subtrahend - 1101010
_________________

Carry over - 1 1000011

Answer: 1000011
85. On subtracting (001100)2 from (101001)2 using 2’s complement, we get ____________
a) 1101100
b) 011101
c) 11010101
d) 11010111
Answer: b
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds
the result.
1’s complement of subtrahend - 110011
_________________
Minuend - 101001
2’s complement of subtrahend - 110100
_________________
Carry over - 1 011101

Answer: 011101
86. On addition of 28 and 18 using 2’s complement, we get ____________
a) 00101110
b) 0101110
c) 00101111
d) 1001111
Answer: b
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Explanation: Steps for Binary Addition Using 2’s complement:
-> The binary equivalent of the two numbers are obtained and added using the rules of binary
addition.
Augend - 0 011100

Addend - 0 010010
_________________
0 101110

Answer: 0 1 0 1 1 1 0
87. On addition of +38 and -20 using 2’s complement, we get ____________
a) 11110001
b) 100001110
c) 010010
d) 110101011
Answer: c
Explanation: Steps for Binary Addition Using 2’s complement:
-> The 2’s complement of the addend is found out and added to the first number.
-> The result is the 2’s complement of the sum obtained.
Augend - 0100110
2’s Complement of Subtrahend: 1101100
_________________
1 0010010

Answer: 0 1 0 0 1 0
88. On addition of -46 and +28 using 2’s complement, we get ____________
a) -10010
b) -00101
c) 01011
d) 0100101
Answer: a
Explanation: The BCD form is written of the two given numbers, in their signed form. After
which, normal binary addition is performed.
Augend is 28 and Subtrahend is -46.

Augend - 0 0 1 1 1 0 0 .....(a)

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 2’s Complement of Subtrahend: 1 0 1 0 0 1 0 .....(b)
_________________
Addiing (a) and (b): 1101110
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
0010001
+ 1
_________________
0010010

Answer: - 1 0 0 1 0
89. On addition of -33 and -40 using 2’s complement, we get ____________
a) 1001110
b) -110101
c) 0110001
d) -1001001
Answer: d
Explanation: The BCD form is written of the two given numbers, in their signed form. After
which, normal binary addition is performed.
Augend is -40 and Subtrahend is -33.
Augend - 1 0 1 0 0 0 0 1 .....(a)
2’s Complement of Subtrahend: 1 1 0 1 1 0 0 1 .....(b)
______________________
Addiing (a) and (b): 10 1001000
Since, there is no carry, so answer will be negative
and 2's complement of the above result is determined.
1001000
+ 1
_________________
1001001
Answer: -1001001
90. On subtracting +28 from +29 using 2’s complement, we get ____________
a) 11111010
b) 111111001
c) 100001
d) 1
Answer: d
Explanation: Steps For Subtraction using 2’s complement are:
-> 2’s complement of the subtrahend is determined and added to the minuend.

JOB
-> If the result has a carry, then it is dropped and the result is positive.
-> Else, if there is no carry, then 2’s complement of the result is found out and a ‘-’ sign preceeds
the result.
1’s complement of subtrahend - 100011
Minuend - 011101
2’s complement of subtrahend - 100100
____________________

Carry over - 1 0 0 0 0 0 1

Answer: 000001 = 1

91. If the number of bits in the sum exceeds the number of bits in each added numbers, it results
in _________
a) Successor
b) Overflow
c) Underflow
d) Predecessor
Answer: b
Explanation: If the number of bits in the sum exceeds the number of bits in each added numbers,
it results in overflow and is also known as excess-one. In case of any arithmetic operation, if the
result has less number of bits than the operands, then it is known as underflow condition.

92. An overflow is a _________

a) Hardware problem
b) Software problem
c) User input problem
d) Input Output Error
Answer: b
Explanation: An overflow is a software problem which occurs when the processor cannot handle
the result properly when it produces an out of the range output.

93. An overflow occurs in _________

a) MSD position
b) LSD position
c) Middle position
d) Signed Bit

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Answer: a
Explanation: An overflow occurs at Most Significant Digit position. It occurs when the processor
cannot handle the result properly when it produces an out of the range output.

94. Logic circuitry is used to detect _________

a) Underflow
b) MSD
c) Overflow
d) LSD
Answer: c
Explanation: To check the overflow logic circuitry is used in each case. Overflow occurs when
the processor cannot handle the result properly when it produces an out of the range output.

95. 1’s complement can be easily obtained by using _________

a) Comparator
b) Inverter
c) Adder
d) Subtractor
Answer: b
Explanation: With the help of inverter the 1’s complement is easily obtained. Since, during the
operation of 1’s complement 1 is converted into 0 and vice-versa and this is well suited for the
inverter.

96. The advantage of 2’s complement system is that _________

a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required
Answer: a
Explanation: The advantage of 2’s complement is that only one arithmetic operation is required
for 2’s complement’s operation and that is only addition. Just by adding a 1 bit to 1’s
complement, we get 2’s complement.

97. The 1’s complements requires _________

a) One operation
b) Two operations
c) Three operations
d) Combined Operations
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Answer: a
Explanation: Only one operation is required for 1’s complement operation. This includes only
inversion of 1’s to 0’s and 0’s to 1’s.

98. Which one is used for logical manipulations?

a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
Answer: c
Explanation: For logical manipulations 1’s complement is used, as all logical operations take
place with binary numbers.

99. For arithmetic operations only _________

a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
Answer: b
Explanation: Only 2’s complement is used for arithmetic operations, as it is more fast.

100. The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110
Answer: d
Explanation: The decimal numbers are converted to their respective binary equivalent and then
the binary addition rules are applied.

Binary Coded Decimal(BCD)

101. Binary coded decimal is a combination of __________
a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits

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Answer: c
Explanation: Binary coded decimal is a combination of 4 binary digits. For example-8421.

102. Add the two BCD numbers: 1001 + 0100 = ?

a) 10101111
b) 01010000
c) 00010011
d) 00101011
Answer: c
Explanation: Firstly, Add the 1001 and 0100. We get 1101 as output but it’s not in BCD form.
So, we add 0110 (i.e. 6) with 1101. As a result we get 10011 and it’s BCD form is 0001 0011.

103. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000
Answer: a
Explanation: First the two numbers are converted into their respective BCD form using 8421
sequence. Then binary subtraction is carried out.

104. Code is a symbolic representation of __________ information.

a) Continuous
b) Discrete
c) Analog
d) Both continuous and discrete
Answer: b
Explanation: Code is a symbolic representation of discrete information, which may be present in
the form of numbers, letters or physical quantities. Mostly, it is represented using a particular
number system like decimal or binary and such like.

105. When numbers, letters or words are represented by a special group of symbols, this process
is called __________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
Answer: b
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Explanation: When numbers, letters or words are represented by a special group of symbols, this
process is called encoding. Encoding in the sense of fetching the codes or words in a computer. It
is done to secure the transmission of information.

106. A three digit decimal number requires ________ for representation in the conventional
BCD format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits
Answer: c
Explanation: The number of bits needed to represent a given decimal number is always greater
than the number of bits required for a straight binary encoding of the same. Hence, a three digit
decimal number requires 12 bits for representation in BCD format.

107. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary
codes?
a) 12
b) 14
c) 16
d) 18
Answer: c
Explanation: Total number of decimals to be represented = 10000 = 104 = 2n (where n is the
number of bits required) = 213.29. Therefore, the number of bits required for straight binary
encoding = 14.

108. The excess-3 code for 597 is given by __________

a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
Answer: a
Explanation: The addition of ‘3’ to each digit yields the three new digits ‘8’, ’12’ and ’10’.
Hence, the corresponding four-bit binary equivalents are 100011001010, in accordance to 8421
format.

109. The decimal equivalent of the excess-3 number 110010100011.01110101 is

_____________
JOB
a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
Answer: a
Explanation: The conversion of binary numbers into digits ‘1100’, ‘1010’, ‘0011’, ‘0111’ and
‘0101’ gives ’12’, ‘5’, ‘3’, ‘7’ and ‘5’ respectively. Hence, the decimal number is 970.42.

110. The BCD representation of (34)10 is _______________

a) 6
b) 7
c) 8
d) 5
Answer: b
Explanation: BCD numbers are represented as:
34 = (0011 0100)BCD.
Each digit is individually taken and an equivalent standard 4 bit term is written for the respective
digit.

Boolean Logic Operations

111. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C &
A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.

112. The expression for Absorption law is given by _________

a) A + AB = A
b) A + AB = B
c) AB + AA’ = A

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d) A + B = B + A
Answer: a
Explanation: The expression for Absorption Law is given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s Property).

113. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’
Answer: a
Explanation: A + 1 = 1, as per 1’s Property.

114. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0
Answer: a
Explanation: The involution of A means double inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A

115. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
Answer: d
Explanation: A(A + B) = AA + AB (By Distributive Property) = A + AB (A.A = A By
Commutative Property) = A(1 + B) = A*1 (1 + B = 1 by 1’s Property) = A.

116. DeMorgan’s theorem states that _________

a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Answer: a

JOB
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the
Dual Property.

117. (A + B)(A’ * B’) = ?

a) 1
b) 0
c) AB
d) AB’
Answer: b
Explanation: The DeMorgan’s law states that (AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the
Dual Property.

118. Complement of the expression A’B + CD’ is _________

a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Answer: b
Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By DeMorgan’s Theorem) = (A” + B’)(C’ + D”)
(By DeMorgan’s Theorem) = (A + B’)(C’ + D).

119. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Answer: a
Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 =
(AB’ + C).

120. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC (By Commutative
Property) = A(1 + C + B) + BC = A + BC (1 + B + C =1 By 1’s Property).
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Sum of Products and Products of Sum
121. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
Answer: a
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum of
product). The logical product of two or more logical sum terms, is called POS (i.e. product of
sums).

122. The expression Y=AB+BC+AC shows the _________ operation.

a) EX-OR
b) SOP
c) POS
d) NOR
Answer: b
Explanation: The given expression has the operation product as well as the sum of that. So, it
shows SOP operation. POS will be the product of sum terms.

123. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND
Answer: b
Explanation: The given expression has the operation sum as well as the product of that. So, it
shows POS(product of sum) operation. SOP will be the sum of product terms.

124. A product term containing all K variables of the function in either complemented or
uncomplemented form is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
Answer: a
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Explanation: A product term containing all K variables of the function in either complemented or
uncomplemented form is called a minterm. A sum term containing all K variables of the function
in either complemented or uncomplemented form is called a maxterm.

125. According to the property of minterm, how many combination will have value equal to 1 for
K input variables?
a) 0
b) 1
c) 2
d) 3
Answer: b
Explanation: The main property of a minterm is that it possesses the value 1 for only one
combination of K input variables and the remaining will have the value 0.

126. The canonical sum of product form of the function y(A,B) = A + B is __________
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
Answer: b
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB + AB’
+ A’B = AB + AB’ + A’B.

127. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word
Answer: b
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z,
X’ etc.

128. Maxterm is the sum of __________ of the corresponding Minterm with its literal
complemented.
a) Terms
b) Words
c) Numbers
d) Nibble
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Answer: a
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal
complemented.

129. Canonical form is a unique way of representing ____________

a) SOP
b) Minterm
c) Boolean Expressions
d) POS
Answer: c
Explanation: Boolean Expressions are represented through canonical form. An example of
canonical form is A’B’C’ + AB’C + ABC’.

130. There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1
Answer: c
Explanation: Minterm is given by 2n. So, 23 = 8 minterms are required.

131. _____________ expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
Answer: c
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.

Karnaugh Map
132. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a
matrix of squares.
a) Venn Diagram
b) Cycle Diagram

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c) Block diagram
d) Triangular Diagram
Answer: a
Explanation: A Karnaugh map (K-map) is an abstract form of Venn diagram organized as a
matrix of squares, where each square represents a Maxterm or a Minterm.

133. There are ______ cells in a 4-variable K-map.

a) 12
b) 16
c) 18
d) 8
Answer: b
Explanation: There are 16 = (24) cells in a 4-variable K-map.

134. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ =
1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
Answer: b
Explanation: The given expression A +A’ = 1 is based on non-impact unifying theorem.

135. Each product term of a group, w’.x.y’ and w.y, represents the ____________in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
Answer: c
Explanation: In a minterm, each variable w, x or y appears once either as the variable itself or as
the inverse. So, the given expression satisfies the property of Sum of Minterm.

136. The prime implicant which has at least one element that is not present in any other implicant
is known as ___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
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Answer: a
Explanation: Essential prime implicants are prime implicants that cover an output of the function
that no combination of other prime implicants is able to cover.

137. Product-of-Sums expressions can be implemented using ___________

a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
Answer: d
Explanation: Product-of-Sums expressions can be implemented using 2-level OR-AND & NOR
logic circuits.

138. Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible
product term of the given ___________
a) Function
b) Value
c) Set
d) Word
Answer: a
Explanation: Each group of adjacent Minterms (group size in powers of twos) corresponds to a
possible product term of the given function.

139. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
Answer: c
Explanation: Don’t care conditions can be used for simplifying Boolean expressions in K-maps
which helps in pairing with 1/0.

140. It should be kept in mind that don’t care terms should be used along with the terms that are
present in ___________
a) Minterms
b) Expressions
c) K-Map
d) Latches
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Answer: a
Explanation: It should be kept in mind that don’t care terms should be used along with the terms
that are present in minterms as well as maxterms which reduces the complexity of the boolean
expression.

141. Using the transformation method you can realize any POS realization of OR-AND with
only.
a) XOR
b) NAND
c) AND
d) NOR
Answer: d
Explanation: Using the transformation method we can realize any POS realization of OR-AND
with only NOR.

142. There are many situations in logic design in which simplification of logic expression is
possible in terms of XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
Answer: a
Explanation: There are many situations in logic design in which simplification of logic
expression is possible in terms of XOR and XNOR operations.
Expression of XOR : AB’ + A’B
Expression of XNOR : AB + A’B’

143. These logic gates are widely used in _______________ design and therefore are available
in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
Answer: b
Explanation: These logic gates(XOR,XNOR,NOR) are widely used in digital design and
therefore are available in IC form as digital circuits deals with data transmission in the form of
binary digits.

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144. In case of XOR/XNOR simplification we have to look for the following _______________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
Answer: d
Explanation: In case of XOR/XNOR simplification we have to look for the following diagonal
and offset adjacencies. XOR gives output 1 when odd number of 1s are present in input while
XNOR gives output 1 when even number of 1s or all 0s are present in input.

145. Entries known as _______________ mapping.

a) Diagonal
b) Straight
c) K
d) Boolean
Answer: a
Explanation: Entries known as diagonal mapping. The diagonal mapping holds true when for any
relation, there is a projection of product on the factor.

Logic Gates and Networks

146. The output of a logic gate is 1 when all the input are at logic 0 as shown below:
INPUT OUTPUT

A B C

0 0 1

0 1 0

1 0 0

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1 1 0

INPUT OUTPUT

A B C

0 0 1

0 1 0

1 0 0

1 1 1

The gate is either _________

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR
Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is NOR. The
output of a logic gate is 1 when all inputs are at logic 0 or all inputs are at logic 1, then it is EX-
NOR. (The truth tables for NOR and EX-NOR Gates are shown in above table).

147. The code where all successive numbers differ from their preceding number by single bit is
__________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Answer: d
Explanation: The code where all successive numbers differ from their preceding number by
single bit is gray code. It is an unweighted code. The most important characteristic of this code is

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that only a single bit change occurs when going from one code number to next. BCD Code is one
in which decimal digits are represented by a group of 4-bits each, whereas, in Excess-3 Code, the
decimal numbers are incremented by 3 and then written in their BCD format.

148. The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
Answer: c
Explanation: 4 to 16 line decoder as the minterms are ranging from 1 to 14.

149. How many AND gates are required to realize Y = CD + EF + G?

a) 4
b) 5
c) 3
d) 2
Answer: d
Explanation: To realize Y = CD + EF + G, two AND gates are required and two OR gates are
required.

150. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Answer: a
Explanation: In 01, 10 or 11 output is low if any of the I/P is high. So, the correct option will be
00.

151. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
Answer: a
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Explanation: Y = CD + EF + G
The number of two input AND gate = 2
The number of two input OR gate = 2.

152. A universal logic gate is one which can be used to generate any logic function. Which of the
following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Answer: d
Explanation: An Universal Logic Gate is one which can generate any logic function and also the
three basic gates: AND, OR and NOT. Thus, NOR and NAND can generate any logic function
and are thus Universal Logic Gates.

153. A full adder logic circuit will have __________

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
Answer: d
Explanation: A full adder circuit will add two bits and it will also accounts the carry input
generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there. In
case of half adder circuit, there are only two inputs bits and two outputs (SUM and CARRY).

154. How many two input AND gates and two input OR gates are required to realize Y = BD +
CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
Answer: a
Explanation: There are three product terms. So, three AND gates of two inputs are required. As
only two input OR gates are available, so two OR gates are required to get the logical sum of
three product terms.

155. Which of following are known as universal gates?

a) NAND & NOR
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b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
Answer: a
Explanation: The NAND & NOR gates are known as universal gates because any digital circuit
can be realized completely by using either of these two gates, and also they can generate the 3
basic gates AND, OR and NOT.

156. The gates required to build a half adder are __________

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
Answer: c
Explanation: The gates required to build a half adder are EX-OR gate and AND gate. EX-OR
outputs the SUM of the two input bits whereas AND outputs the CARRY of the two input bits.

157. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
Answer: c
Explanation: A transistor can be used as a switch. That is, when base is low collector is high
(input zero, output one) and base is high collector is low (input 1, output 0).

158. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
Answer: d
Explanation: For 4 inputs: 24 = 16 truth table entries are necessary.

159. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
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d) All inputs are LOW
Answer: c
Explanation: For AND gate, the output is high only when both inputs are high. That’s why the
high output in AND will occurs only when all the inputs are high. However, in case of OR gate,
if atleast one input is high, the output will be high.

160. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
Answer: c
Explanation: Expression for XOR is: A.(B’)+(A’).B
So in the above expression, the following logic gates are used: AND, OR, NOT.
Thus, 2 AND gates with two-inputs and 1 OR gate with two-inputs will be required for
constructing a XOR gate.

161. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
Answer: c
Explanation: It is also called NOT gate and it simply inverts the input, such that 1 becomes 0 and
0 becomes 1.

162. The AND function can be used to ___________ and the OR function can be used to
_____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
Answer: a
Explanation: The AND gate and OR gate are used for enabling and disabling respectively
because of their multiplicity and additivity property. The AND gate outputs 1 when all inputs are
at logic 1, whereas the OR gate outputs 0 when all inputs are at logic 0.

JOB
163. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
Answer: a
Explanation: The dependency notation “>=1” inside a block stands for OR operation.

164. If we use an AND gate to inhibit a signal from passing one of the inputs must be
___________
a) LOW
b) HIGH
c) Inverted
d) Floating
Answer: a
Explanation: AND gate means A*B and OR gate means A+B and to inhibit means to get low
signal, one of the input must be low. It means (0*1=0 or 1*0=0) we will get low output signal.
Thus, AND gate outputs 1 only when all inputs are at logic level 1 else it outputs 0.

165. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
Answer: b
Explanation: Logic gate circuits contain predictable gate functions that open their inputs because
we are free to give any types of inputs.

166. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8
Answer: c
Explanation: 7400 IC’s pin has total 14 pin. Pin no 7 use for GND and pin no 14 used for +vcc
and remaining pins used for connections. For a NAND gate two inputs are required and one
output is obtained means for NAND gate 3 pin connections are required. Thus, a 7400IC

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contains 4 NAND gates with each having 3 pins. Therefore, total 12 pins dedicated for the
NAND operation. Rest 2 pins for power supply.

Introduction of Arithmetic Operation

167. The basic building blocks of the arithmetic unit in a digital computers are __________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
Answer: b
Explanation: The basic building blocks of the arithmetic unit in digital computers are adders.
Since a parallel adder is constructed with a number of full-adder circuits connected in cascade.
By controlling the data inputs to the parallel adder, it is possible to obtain different types of
arithmetic operations.

168. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: A digital system consists of two types of circuits and these are a combinational and
sequential logic circuit. Combinational circuits are the ones which do not depend on previous
inputs while Sequential circuits depend on past inputs.

169. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) Clock pulses
Answer: c
Explanation: In a combinational circuit, the output at any time depends only on the input values
at that time and not on past or intermediate values.

170. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values

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b) Intermediate values
c) Both past output and present input
d) Present input values
Answer: c
Explanation: In a sequential circuit, the output at any time depends on the present input values as
well as past output values. It also depends on clock pulses depending on whether it’s
synchronous or asynchronous sequential circuits.

171. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
Answer: c
Explanation: Combinational circuits are the ones which do not depend on previous inputs and
depends only on the present values. The given arrangement A, B, E, C, D is the right sequence
for the designing of the combinational circuits.

172. All logic operations can be obtained by means of __________

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
Answer: d
Explanation: Since the logic gates NOR and NAND are known as universal logic gates, therefore
it can be used to design all the three basic gates AND, OR and NOT. Thus, it means that any
operations can be obtained by implementation of these gates.

173. The design of an ALU is based on __________

a) Sequential logic

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b) Combinational logic
c) Multiplexing
d) De-Multiplexing
Answer: b
Explanation: The design of an ALU is based on combinational logic. Because the unit has a
regular pattern, it can be broken into identical stages connected in cascade through carries.

174. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a
possible _____ result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
Answer: d
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry
and a possible zero result.

175. If the two numbers include a sign bit in the highest order position, the bit conditions of
interest are the sign of the result, a zero indication and __________
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) One indication
Answer: c
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions
of interest are the sign of the result, a zero indication and an overflow condition.

176. The flag bits in an ALU is defined as ___________

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
d) All of the Mentioned
Answer: b
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag
bits. It is so called because they tend to represent the status of the respect flags after any
operation.

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Half Adder & Full Adder
177. In parts of the processor, adders are used to calculate ____________
a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Answer: d
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the
processor, adders are used to calculate addresses, table indices, increment and decrement
operators, and similar operations.

178. Total number of inputs in a half adder is __________

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs
and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them
being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.

179. In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example
carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 –
1 = 1 (borrow 1).

180. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B

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b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the
carry is given by A AND B.

181. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while the
sum is given by A XOR B.

182. Half-adders have a major limitation in that they cannot __________

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a
previous stage, meaning that they cannot be chained together to add multi-bit numbers. However,
the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both
being high.

183. The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference
between them, while both have two outputs SUM and CARRY.

184. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
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b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B XOR
C.

185. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR
(A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).

186. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full
adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2
OR and 2 EXOR.

Half & Full Subtractor

187. Half subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Answer: a
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of
two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.

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188. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because
carry is taken into consideration during addition process.

189. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: There are two outputs required for the implementation of a subtractor. One for the
difference and another for borrow.

190. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
Answer: a
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In
both of the situation subtractor gives 0 as the output.

191. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Answer: a
Explanation: The subtractor has two outputs BOROW and DIFFERENCE. Since, the difference
output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final
difference output is AB’ + BA’.

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192. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
Answer: b
Explanation: The borrow of a subtractor is received through AND gate whose one input is
inverted. On that basis the borrow will be (A’ AND B).

193. What does minuend and subtrahend denotes in a subtractor?

a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Answer: c
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the
two inputs of a subtractor then A is called minuend and B as subtrahend.

194. Full subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit,
subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs
BORROW and DIFFERENCE.

195. The full subtractor can be implemented using ___________

a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Answer: b
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and
DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR
gate.

JOB
196. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
Answer: b
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A
XOR B XOR X.

197. The output of a full subtractor is same as ____________

a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
Answer: b
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A, B
and C are the input of a full adder and a full subtractor then the output will be given by (A XOR
B XOR C), respectively.

4-Bit Parallel Adder/Subtractor

198. Controlled inverter is also known as ____________
a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate
Answer: c
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well. It is
used between output and a bus so that one can control whether the output is fed to the bus or not.

199. Why XOR gate is called an inverter?

a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) It behaves like a AND gate
Answer: c

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Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different.
When one input is true, the output is the inversion of the other. When one input is false, the
output is the non-inversion of the other.

200. Controlled buffers can be useful ____________

a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
d) All of the Mentioned
Answer: a
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose
value should match the output of one of several components. By placing a controlled buffer
between each component output and the bus, you can control whether that component’s output is
fed onto the bus or not.

201. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
____________
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
Answer: a
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are
same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs
HIGH or both inputs are LOW. Thus, EX-NOR produces output for even number of 1’s or all 0s,
while EXOR produces output for odd number of 1’s.

202. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
Answer: d
Explanation: HDL stands for Hardware Description Language. In order to use a macro function,
one needs to have experience in HDL for representing the structure and behaviour of digital
circuits.

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203. What is the major difference between half-adders and full-adders?
a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
Answer: c
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number
like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is
1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second
bits addition of the number. So, half adders are useless. But in full adders, one more carry input
is present, so that, if carry of one stage is present, it can be added with the next stage as it is done
in normal addition. So, therefore, full adders have a carry input capability.

204. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
Answer: a
Explanation: The binary subtraction of 0 – 0 = 0. Thus, it’s difference is 0 as well as it’s borrow.

205. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
Answer: b
Explanation: 4 basic binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0

206. When performing subtraction by addition in the 2’s-complement system ____________

a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement

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d) The minuend and subtrahend are both left in their original form
Answer: c
Explanation: When performing subtraction by addition in the 2’s-complement system, the
minuend is left in its original form and the subtrahend is changed to its 2’s-complement. It is
then added to the minuend. If the result has carry, then it’s dropped and that’s the final answer.
Else, if the result has no carry, then the result is again converted to it’s 2’s complement form and
that’s the final answer with a ‘negative’ sign.

207. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
Answer: b
Explanation: There are two types of adder circuits: half-adder and full-adder. Half-Adder has 2
inputs while Full-Adder has 3 inputs. Whereas, both have two outputs SUM and CARRY.

208. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
Answer: d
Explanation: By using maximum of two half adders we can make a full adder for the first stage
of a Parallel Full adder.

209. The selector inputs to an arithmetic/logic unit (ALU) determine the ____________
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
Answer: b
Explanation: An ALU performs basic arithmetic and logic operations and stores it in the
accumulator. Examples of arithmetic operations are addition, subtraction, multiplication, and
division. Examples of logic operations are comparisons of values such as NOT, AND and OR
and any logical operations.

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210. One way to make a four-bit adder to perform subtraction is by ___________
a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs
Answer: c
Explanation: A adder is a digital circuit which adds bits along with a carry bit from a previous
stage, thus producing 2 outputs SUM and CARRY. Since, a four bit adder has four A, four B and
a carry at the input end. So, for subtraction to be performed, all the Bs terminal should be
inverted.

BCD Adder
211. The decimal number system represents the decimal number in the form of ____________
a) Hexadecimal
b) Binary coded
c) Octal
d) Decimal
Answer: b
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers
where each decimal digit is represented by a fixed number of bits, usually four or eight.
Hexadecimal and Octal are number systems having base 16 and 8 respectively.

212. 29 input circuit will have total of ____________

a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
Answer: d
Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.

213. BCD adder can be constructed with 3 IC packages each of ____________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits

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Answer: c
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers
where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD
adder can be constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale
Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration)
package.

214. The output sum of two decimal digits can be represented in ____________
a) Gray Code
b) Excess-3
c) BCD
d) Hexadecimal
Answer: c
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded
decimal). Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where
each decimal digit is represented by a fixed number of bits, usually four or eight.

215. The addition of two decimal digits in BCD can be done through ____________
a) BCD adder
b) Full adder
c) Ripple carry adder
d) Carry look ahead
Answer: a
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every
input inserted, in addition by the user converted into binary and then proceed for the addition.
Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary
bits.

216. 3 bits full adder contains ____________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Answer: d
Explanation: 3 bits full adder contains 23 = 8 combinational inputs.

217. The simplified expression of full adder carry is ____________

a) c = xy+xz+yz
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b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
Answer: a
Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM
and CARRY. The simplified expression of full adder carry is c = xy+xz+yz.

218. Complement of F’ gives back __________

a) F’
b) F
c) FF
d) FF’
Answer: b
Explanation: Complement means inversion. So, complement of F’ gives back F, as per the Law
of Involution.

219. Decimal digit in BCD can be represented by ____________

a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines
Answer: d
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers
where each decimal digit is represented by a fixed number of bits, usually four or eight. Decimal
digit in BCD can be represented by 4 input lines. Since it is constructed with 4-bits.

220. The number of logic gates and the way of their interconnections can be classified as
____________
a) Logical network
b) System network
c) Circuit network
d) Gate network
Answer: a
Explanation: The number of different levels of logic gates is represented in a fashion which is
known as a logical network.

The Design of Combinational Circuits

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221. The basic building blocks of the arithmetic unit in a digital computers are ____________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
Answer: b
Explanation: The basic building blocks of the arithmetic unit in a digital computers are adders.
Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade.
By controlling the data inputs to the parallel adder, it is possible to obtain different types of
arithmetic operations.

222. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: A digital system consists of two types of circuits and these are combinational and
sequential logic circuit. Combinational circuits are the ones which do not depend on previous
inputs while Sequential circuits depend on past inputs.

223. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) Clock pulses
Answer: c
Explanation: In a combinational circuit, the output at any time depends only on the input values
at that time and not on past or intermediate values.

224. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
b) Intermediate values
c) Both past output and present input
d) Present input values
Answer: c
Explanation: In a sequential circuit, the output at any time depends on the present input values as

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well as past output values. It also depends on clock pulses depending whether it’s synchronous or
asynchronous sequential circuits.

225. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) B, A, E, C, D
Answer: c
Explanation: Combinational circuits are the ones which do not depend on previous inputs and
depends only on the present values. The given arrangement in option c is the right sequence for
the designing of the combinational circuits.

226. All logic operations can be obtained by means of ____________

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
Answer: d
Explanation: Since, the logic gates NOR and NAND are known as universal logic gates,
therefore it can be used to design all the three basic gates AND, OR and NOT. Thus, it means
that any operations can be obtained by implementation of these gates.

227. The design of an ALU is based on ____________

a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
Answer: b

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Explanation: The design of an ALU is based on combinational logic. Because the unit has a
regular pattern, it can be broken into identical stages connected in cascade through carries.

228. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a
possible _____ result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
Answer: d
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry
and a possible zero result.

229. If the two numbers include a sign bit in the highest order position, the bit conditions of
interest are the sign of the result, a zero indication and ___________
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) One indication
Answer: c
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions
of interest are the sign of the result, a zero indication and an overflow condition.

230. The flag bits in an ALU is defined as ____________

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
d) All of the Mentioned
Answer: b
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag
bits. It is so called because they tend to represent the status of the respect flags after any
operation.

JOB
Combinational Circuits
231. Which of the circuits in figure (a to d) is the sum-of-products implementation of figure (e)?

a) a
b) b
c) c
d) d
Answer: d
Explanation: SOP means Sum Of Products form which represents the sum of product terms

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having variables in complemented as well as in uncomplemented form. Here, the diagram of d
contains the OR gate followed by the AND gates, so it is in SOP form.

232.Which of the following logic expressions represents the logic diagram shown?

a) X=AB’+A’B
b) X=(AB)’+AB
c) X=(AB)’+A’B’
d) X=A’B’+AB
Answer: d
Explanation: 1st output of AND gate is = A’B’
2nd AND gate’s output is = AB and,
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.

233. The device shown here is most likely a ________

a) Comparator
b) Multiplexer
c) Inverter
d) Demultiplexer
Answer: d
Explanation: The given diagram is demultiplexer, because it takes single input & gives many
outputs. A demultiplexer is a combinational circuit that takes a single output and latches it to
multiple outputs depending on the select lines.

JOB
234. What type of logic circuit is represented by the figure shown below?

a) XOR
b) XNOR
c) AND
d) XAND
Answer: b
Explanation: After solving the circuit we get (A’B’)+AB as output, which is XNOR operation.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is
odd number of 1s.

235. For a two-input XNOR gate, with the input waveforms as shown below, which output
waveform is correct?

a) d
b) a
c) c
d) b
Answer: a
Explanation: When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P

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001
010
100
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is
odd number of 1s.

236. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate
b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one OR gate
d) One 4-input NAND gate, one inverter
Answer: b
Explanation: For decoding any number output must be high for that code and this is possible in
One 4-input NAND gate, one inverter option only. A decoder is a combinational circuit that
converts binary data to n-coded data upto 2n outputs.

237. What is the indication of a short to ground in the output of a driving gate?
a) Only the output of the defective gate is affected
b) There is a signal loss to all load gates
c) The node may be stuck in either the HIGH or the LOW state
d) The affected node will be stuck in the HIGH state
Answer: b
Explanation: Short to ground in the output of a driving gate indicates of a signal loss to all load
gates. This results in information being disrupted and loss of data.

238. For the device shown here, assume the D input is LOW, both S inputs are LOW and the
input is LOW. What is the status of the Y’ outputs?

a) All are HIGH

b) All are LOW
c) All but Y0 are LOW

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d) All but Y0 are HIGH
Answer: d
Explanation: In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.

239. The carry propagation can be expressed as ________

a) Cp = AB
b) Cp = A + B
c) All but Y0 are LOW
d) All but Y0 are HIGH
Answer: b
Explanation: This happens in parallel adders (where we try to add numbers in parallel via more
than one adders). A carry propagation occurs when carry from one adder needs to be forwarded
to other adder and that second adder is holding the computation (addition) because carry from
first adder has not come yet. So, there is a slight delay for second adder and this is known as
carry propagation.

240. 3 bits full adder contains ________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Answer: d
Explanation: Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY
and SUM. Three bits full adder requires 23 = 8 combinational circuits.

Multiplexers (Data Selectors)

241. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one

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c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Answer: b
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line, depending on the active select
lines.

242. Which combinational circuit is renowned for selecting a single input from multiple inputs &
directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
Answer: a
Explanation: Data Selector is another name of Multiplexer. A multiplexer (or MUX) is a device
that selects one of several analog or digital input signals and forwards the selected input into a
single line, depending on the active select lines.

243. It is possible for an enable or strobe input to undergo an expansion of two or more MUX
ICs to the digital multiplexer with the proficiency of large number of ___________
a) Inputs
b) Outputs
c) Selection lines
d) Enable lines
Answer: a
Explanation: It is possible for an enable or strobe input to undergo an expansion of two or more
MUX ICs to the digital multiplexer with the proficiency of large number of inputs.

244. Which is the major functioning responsibility of the multiplexing combinational circuit?
a) Decoding the binary information
b) Generation of all minterms in an output function with OR-gate
c) Generation of selected path between multiple sources and a single destination
d) Encoding of binary information
Answer: c
Explanation: The major functioning responsibility of the multiplexing combinational circuit is
generation of selected path between multiple sources and a single destination because it makes
the circuit too flexible. A multiplexer (or MUX) is a device that selects one of several analog or

JOB
digital input signals and forwards the selected input into a single line, depending on the active
select lines.

245. What is the function of an enable input on a multiplexer chip?

a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Answer: c
Explanation: Enable input is used to active the chip, when enable is high the chip works
(ACTIVE), when enable is low the chip does not work (MEMORY). However, Enable can be
Active-High or Active-Low, indicating it is active either when it is connected to VCC or GND
respectively.

246. One multiplexer can take the place of ___________

a) Several SSI logic gates
b) Combinational logic circuits
c) Several Ex-NOR gates
d) Several SSI logic gates or combinational logic circuits
Answer: d
Explanation: A multiplexer (or MUX) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line, depending on the active select
lines. Since many operational behaviour can be performed by using a multiplexer. Whereas, a
combinational circuit is a combination of many logic gates which makes the circuit more
complex.

247. A digital multiplexer is a combinational circuit that selects ___________

a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information
Answer: a
Explanation: A digital multiplexer is a combinational circuit that selects one digital information
from several sources and transmits the selected information on a single output line depending on
the status of the select lines. That is why it is also known as a data selector.

248. In a multiplexer, the selection of a particular input line is controlled by ___________

a) Data controller
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b) Selected lines
c) Logic gates
d) Both data controller and selected lines
Answer: b
Explanation: The selection of a particular input line is controlled by a set of selected lines in a
multiplexer, which helps to select a particular input from several sources.

249. If the number of n selected input lines is equal to 2^m then it requires _____ select lines.
a) 2
b) m
c) n
d) 2n
Answer: b
Explanation: If the number of n selected input lines is equal to 2^m then it requires m select lines
to select one of m select lines.

250. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer: d
Explanation: 2n input lines, n control lines and 1 output line available for MUX. Here, 8 input
lines mean 23 inputs. So, 3 control lines are possible. Depending on the status of the select lines,
the input is selected and fed to the output.

251. A basic multiplexer principle can be demonstrated through the use of a ___________
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
Answer: c
Explanation: A basic multiplexer principle can be demonstrated through the use of a rotary
switch. Since its behaviour is similar to the multiplexer. There are around 10 digits out of which
one is selected one at a time and fed to the output.

252. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
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b) 4
c) 2
d) 5
Answer: c
Explanation: There are two NOT gates required for the construction of 4-to-1 multiplexer. x0,
x1, x2 and x3 are the inputs and C1 and C0 are the select lines and M is the output.
The diagram of a 4-to-1 multiplexer is shown below:

253. In the given 4-to-1 multiplexer, if c1 = 0 and c0 = 1 then the output M is ___________

a) X0
b) X1
c) X2
d) X3
Answer: b
Explanation: The output will be X1, because c1 = 0 and c0 = 1 results into 1 which further
results as X1. And rest of the AND gates gives output as 0.

254. The enable input is also known as ___________

a) Select input
b) Decoded input

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c) Strobe
d) Sink
Answer: c
Explanation: The enable input is also known as strobe which is used to cascade two or more
multiplexer ICs to construct a multiplexer with a larger number of inputs. Enable input activates
the multiplexer to operate.

255. 4 to 1 MUX would have ____________

a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
Answer: c
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0)

and 1 output (M). It can be observed from this diagram:

256. The two input MUX would have ____________

a) 1 select line
b) 2 select lines
c) 4 select lines
d) 3 select lines
Answer: a

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Explanation: The two input multiplexer would have n select lines in 2n. Thus n =1. Therefore, it
has 1 select line.

257. A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer
Answer: d
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer.
Whereas, a combinational circuit that divides one input into multiple outputs is known as
Demultiplexer.

258. 4 to 1 MUX would have ____________

a) 1 output
b) 2 outputs
c) 3 outputs
d) 4 outputs
Answer: a
Explanation: 4 to 1 multiplexer would have 4 inputs (X0, X1, X2, X3), 2 select lines (C1, C0)
and 1 output (M). It can be observed from this diagram:

259. Which of the following circuit can be used as parallel to serial converter?
a) Multiplexer
b) Demultiplexer

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c) Decoder
d) Digital counter
Answer: a
Explanation: A combinational circuit that selects one from many inputs is known as Multiplexer.
In multiplexer, different inputs are inserted parallely and then it gives one output which is in
serial form.

260. A combinational circuit is one in which the output depends on the ____________
a) Input combination at the time
b) Input combination and the previous output
c) Input combination at that time and the previous input combination
d) Present output and the previous output
Answer: a
Explanation: A combinational circuit is one in which the output depends on the input
combination at the time, whereas, a sequential circuit is one in which the output depends on
present input as well past outputs.

Demultiplexers (Data Distributors)

261. The word demultiplex means ___________
a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
Answer: d
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer
sends a single input to multiple outputs, depending on the select lines. It is clear from the
diagram:

JOB
262. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. For one input, the demultiplexer gives several outputs. That is why, it is called a data
distributor.

263. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. Demultiplexer converts single input into multiple outputs.

264. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
Therefore, for 1:4 demultiplexer, 2 select lines are required.

265. In a multiplexer the output depends on its ___________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. As the select input changes, the output of the multiplexer varies according to that input.

JOB
266. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Answer: b
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =0, Y1 will be the output as 0 and 1 are the bit combinations of 1.

267. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________

a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
Explanation: It can be calculated from the figure shown below:

JOB
For C0 =1 and C1 =0, Y3 will be the output as 0 and 1 are the bit combinations of 1.

268. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
In this case n = 3 since 23 = 8.

269. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.

JOB
270. The output Q4 of this 1-to-8 demultiplexer is ____________

a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
Answer: c
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100.

271. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138

JOB
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is
inverted input.

272. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input gives single output
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. For one input, the demultiplexer gives several outputs. That is why it is called a data
distributor.

273. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. Demultiplexer converts single input into multiple outputs.

274. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
Therefore, for 1:4 demultiplexer, 2 select lines are required.

275. In a multiplexer the output depends on its ____________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
JOB
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. As the select input changes, the output of the multiplexer varies according to that input.

276. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________

a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
Explanation: It can be calculated from the figure shown below:

For C0 =1 and C1 =1, Y3 will be the output as 0 and 1 are the bit combinations of 1.

277. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select lines.
In this case n = 3 since 23 = 8.

278. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8

JOB
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.

279. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is
inverted input.

Encoders
280. How many inputs will a decimal-to-BCD encoder have?
a) 4
b) 8
c) 10
d) 16
Answer: c
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to
n output lines, thus producing the binary equivalent of the input. Thus, a Decimal-to-bcd
converter has decimal values as inputs which range from 0-9. So, total 10 inputs are there in a
decimal-to-BCD encoder.

281. How many outputs will a decimal-to-BCD encoder have?

a) 4
b) 8
c) 12
d) 16
Answer: a
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to
n output lines, thus producing the binary equivalent of the input. Thus, a decimal to BCD
encoder has 4 outputs.

JOB
282. How is an encoder different from a decoder?
a) The output of an encoder is a binary code for 1-of-N input
b) The output of a decoder is a binary code for 1-of-N input
c) The output of an encoder is a binary code for N-of-1 output
d) The output of a decoder is a binary code for N-of-1 output
Answer: a
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to
n output lines, thus producing the binary equivalent of the input. It performs the opposite
operation of a decoder which results in 2n outputs from n inputs. Thus, an encoder different from
a decoder because of the output of an encoder is a binary code for 1-of-N input.

283. If we record any music in any recorder, such types of process is called ___________
a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
Answer: b
Explanation: If we record any music in any recorder, it means that we are giving data to a
recorder. So, such process is called encoding. Getting back the music from the recorded data, is
known as decoding.

284. Can an encoder be a transducer?

a) Yes
b) No
c) May or may not be
d) Both are not even related slightly
Answer: a
Explanation: Of course, a transducer is a device which has the capability to emit data as well as
to accept. Transducer converts signal from one form of energy to another.

285. How many OR gates are required for a Decimal-to-bcd encoder?

a) 2
b) 10
c) 3
d) 4
Answer: d
Explanation: An encoder is a combinational circuit encoding the information of 2^n input lines

JOB
to n output lines, thus producing the binary equivalent of the input.
This is clear from the diagram that it requires 4 OR gates:

286. How many OR gates are required for an octal-to-binary encoder?

a) 3
b) 2
c) 8
d) 10
Answer: a
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to
n output lines, thus producing the binary equivalent of the input. Thus, in octal to binary encoder
there are 8 (=23) inputs, thus 3 output lines.

287. For 8-bit input encoder how many combinations are possible?
a) 8
b) 2^8
c) 4
d) 2^4
Answer: b
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to
n output lines, thus producing the binary equivalent of the input. There are 28 combinations are
possible for an 8-bit input encoder but out of which only 8 are used using 3 output lines. It is a
disadvantage of encoder.

288. The discrepancy of 0 output due to all inputs being 0 or D0, being 0 is resolved by using
additional input known as ___________
JOB
a) Enable
b) Disable
c) Strobe
d) Clock
Answer: a
Explanation: Such problems are resolved by using enable input, which behaves as active if it gets
0 as input since it is an active-low pin.

289. Can an encoder be called as multiplexer?

a) No
b) Yes
c) Sometimes
d) Never
Answer: b
Explanation: A multiplexer or MUX is a combination circuit that contains more than one input
line, one output line and more than one selection line. Whereas, an encoder is also considered a
type of multiplexer but without a single output line and without any selection lines.

290. If two inputs are active on a priority encoder, which will be coded on the output?
a) The higher value
b) The lower value
c) Neither of the inputs
d) Both of the inputs
Answer: a
Explanation: An encoder is a combinational circuit encoding the information of 2n input lines to
n output lines, thus producing the binary equivalent of the input. If two inputs are active on a
priority encoder, the input of higher value will be coded in the output.

Parity Generators/Checkers
291. How many outputs are present in a BCD decoder?
a) 4
b) 5
c) 15
d) 10
Answer: d

JOB
Explanation: A binary decoder is a combinational logic circuit which decodes binary information
from n-inputs to a maximum of 2n outputs. A BCD to Decimal decoder has 10 number of outputs
because the decimal digit’s range is from 0 to 9.

292. Which digital system translates coded characters into a more useful form?
a) Encoder
b) Display
c) Counter
d) Decoder
Answer: d
Explanation: A binary decoder is a combinational logic circuit which decodes binary information
from n-inputs to a maximum of 2n outputs. Decoder converts the coded characters into our
required data form.

293. What control signals may be necessary to operate a 1-line-to-16 line decoder?
a) Flasher circuit control signal
b) A LOW on all gate enable inputs
c) Input from a hexadecimal counter
d) A HIGH on all gate enable circuits
Answer: b
Explanation: A LOW on all gate enable inputs is necessary to operate a 1-line-to-16 line decoder
because enable pins are usually, active-low pins.

294. How many inputs are required for a 1-of-10 BCD decoder?
a) 4
b) 8
c) 10
d) 2
Answer: a
Explanation: A binary decoder is a combinational logic circuit which decodes binary information
from n-inputs to a maximum of 2n outputs. Therefore, for a BCD to decimal decoder, No. of
inputs = 4 such that number of outputs is <= 2n.

295. A BCD decoder will have how many rows in its truth table?
a) 10
b) 9
c) 8
d) 3
JOB
Answer: a
Explanation: A binary decoder is a combinational logic circuit which decodes binary information
from n-inputs to a maximum of 2n outputs. Thus, BCD decoder will have 10 rows as it’s input
ranges from 0 to 9.

296. How many possible outputs would a decoder have with a 6-bit binary input?
a) 32
b) 64
c) 128
d) 16
Answer: c
Explanation: The possible outputs would be: 2n = 64 (Since n = 6 here).

297. One way to convert BCD to binary using the hardware approach is:
a) By using MSI IC circuits
b) By using a keyboard encoder
c) By using an ALU
d) By using UART
Answer: a
Explanation: One way to convert BCD to binary using the hardware approach is MSI (medium
scale integration) IC circuits.

298. How many inputs are required for a 1-of-16 decoder?

a) 2
b) 16
c) 8
d) 4
Answer: d
Explanation: A binary decoder is a combinational logic circuit which decodes binary information
from n-inputs to a maximum of 2n outputs. Here, number of outputs = 16.
16 = 24 = 2n. Thus, number of inputs is 4.

299. A truth table with output columns numbered 0–15 may be for which type of decoder IC?
a) Hexadecimal 1-of-16
b) Dual octal outputs
c) Binary-to-hexadecimal
d) Hexadecimal-to-binary
Answer: a
JOB
Explanation: A binary decoder is a combinational logic circuit which decodes binary information
from n-inputs to a maximum of 2n outputs. A truth table with output columns numbered 0–15
may be for Hexadecimal 1-of-16. Because, hexadecimal occupies less space in a system.

300. How can the active condition (HIGH or LOW) or the decoder output be determined from
the logic symbol?
a) A bubble indicates active-HIGH
b) A bubble indicates active-LOW
c) A triangle indicates active-HIGH
d) A triangle indicates active-LOW
Answer: b
Explanation: A bubble indicates active-LOW in a decoder always. Enable pin of the decoder is
usually active-LOW and is triggered on input being at 0.

Latches
301. A latch is an example of a ___________
a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
Answer: c
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in
which the circuit is stable in either of two states. It can be flipped from one state to the other state
and vice-versa.

302. Latch is a device with ___________

a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
Answer: b
Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable
multivibrator is one in which the circuit is stable in either of two states. It can be flipped from
one state to the other state and vice-versa. So a latch has two stable states.

JOB
303. Why latches are called a memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
Answer: c
Explanation: Latches can be memory devices, and can store one bit of data for as long as the
device is powered. Once device is turned off, the memory gets refreshed.

304. Two stable states of latches are ___________

a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
Answer: c
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator.
There are two stable states of latches and these states are high-output and low-output.

305. How many types of latches are ___________

a) 4
b) 3
c) 2
d) 5
Answer: a
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a
modified form of SR latch whereas, T latch is an advanced form of JK latch.

306. The full form of SR is ___________

a) System rated
b) Set reset
c) Set ready
d) Set Rated
Answer: b
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.

307. The SR latch consists of ___________

a) 1 input
b) 2 inputs
JOB
c) 3 inputs
d) 4 inputs
Answer: b
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states.
The diagram of SR latch is shown below:

308. The outputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) q and q’
Answer: d
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the
diagram:

309. The NAND latch works when both inputs are ___________
a) 1
b) 0
c) Inverted
d) Don’t cares
Answer: a

JOB
Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs are
inverted in a NAND latch.

310. The first step of analysis procedure of SR latch is to ___________

a) label inputs
b) label outputs
c) label states
d) label tables
Answer: b
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because
the flip flops have inverting gates inside them, hence in order to have both Q and Q complement
available, we have atleast one output labelled.

311. The inputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) j and k
Answer: c
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the
diagram:

312. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
Answer: a

JOB
Explanation: S input of a SR latch is directly connected to the output Q. So, when a high is
applied Q output goes high and Q’ low.
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313. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it’s present state.
There is no change in the output.

314. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
Answer: c
Explanation: When both gates are identical and this is “metastable”, and the device will be in an
undefined state for an indefinite period.

Flip Flops
315. Latches constructed with NOR and NAND gates tend to remain in the latched condition due
to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a
latch are directly connected to the other’s output. Such types of structure is called cross coupling
and due to which latches remain in the latched condition.

JOB
316. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which
is the unwanted noise caused during the switching of electronic devices.

317. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The
Invalid or Undefined State occurs at both S and R being at 1.

318. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0
and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle
complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.

319. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q also

JOB
high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid
state at both inputs being 1.

320. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND
gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-
versa.

321. The logic circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The
circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on
the present state, then it’s known as combinational circuits.

322. Whose operations are more faster among the following?

a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the
combinational circuits do not require memory elements whereas the sequential circuits need
memory devices to perform their operations in sequence. Latches and Flip-flops come under
sequential circuits.

323. How many types of sequential circuits are?

a) 2
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b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii)
asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a
clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock
signal.

324. The sequential circuit is also called ___________

a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which
are capable of storing one bit of information.

325. The basic latch consists of ___________

a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0
then the second output Q’ = 1 and vice versa.

326. If Q = 0, the output is said to be ___________

a) Set
b) Reset
c) Previous state
d) Current state
Answer: a
Explanation: If Q = 0, the output is said to be set and reset for Q’ = 1.

327. The output of latches will remain in set/reset untill ___________

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
JOB
c) They don’t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to
change the state.

328. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.

329. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the other
gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as
asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they
function in the absence of a clock pulse.

330. What is an ambiguous condition in a NAND based S’-R’ latch?

a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
Answer: d
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’)
goes HIGH and this condition is called as ambiguous/forbidden state. This state is also known as
an Invalid state as the system goes into an unexpected situation.

331. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
a) No change
b) Set
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c) Reset
d) Forbidden
Answer: a
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the
state. It remains in its prior state. This state is used for the storage of data.

332. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
Answer: d
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D
latch or an inverter at its input as it’s operations will be complementary.

333. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is
____________
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch
Answer: a
Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0
but 1 for NAND latch.

334. The characteristic equation of S-R latch is ____________

a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific output
in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S +
Q(n))R’.

335. The difference between a flip-flop & latch is ____________

a) Both are same
b) Flip-flop consist of an extra output
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c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
Answer: c
Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an
additional control input is provided to the latch.

336. How many types of flip-flops are?

a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced
version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.

337. The S-R flip flop consist of ____________

a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates
Answer: b
Explanation: The S-R flip flop consist of two additional AND gates at the S and R inputs of S-R
latch.

338. What is one disadvantage of an S-R flip-flop?

a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
Answer: d
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high,
which is referred to as Invalid State.

339. One example of the use of an S-R flip-flop is as ____________

a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
JOB
Answer: c
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is
referred to as binary storage element. It functions as memory storage during the No Change
State.

340. When is a flip-flop said to be transparent?

a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
Answer: b
Explanation: Flip-flop have the property of responding immediately to the changes in its inputs.
This property is called transparency.

341. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Answer: c
Explanation: Edge triggered device will follow when there is transition. It is a positive edge
triggered when transition takes place from low to high, while, it is negative edge triggered when
the transition takes place from high to low.

342. What is the hold condition of a flip-flop?

a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
Answer: b
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is
the No Change State or Memory Storage state if a flip-flop.

343. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R
input goes to 0, the latch will be ________
a) SET
b) RESET
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c) Clear
d) Invalid
Answer: b
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no
change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.

344. The circuit that is primarily responsible for certain flip-flops to be designated as edge-
triggered is the _____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
Answer: a
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as
edge-triggered is the edge-detection circuit.

345. Which circuit is generated from D flip-flop due to addition of an inverter by causing
reduction in the number of inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
Answer: d
Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this
causes reduction in the number of inputs.

346. The characteristic of J-K flip-flop is similar to _____________

a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) Gated T flip-flop
Answer: a
Explanation: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same
behaviour is shown by J-K flip-flop.

347. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________
a) Two AND gates
b) Two NAND gates
JOB
c) Two NOT gates
d) Two OR gates
Answer: a
Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two
AND gates.

348. How is a J-K flip-flop made to toggle?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer: d
Explanation: When j=k=1 then the race condition is occurs that means both output wants to be
HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is
device is either set or reset.

349. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is
HIGH is called ___________
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital filtering
Answer: b
Explanation: Ones catching means that the input transitioned to a 1 and back very briefly
(unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it
caught the 1. Similarly for 0’s catching.

350. In J-K flip-flop, “no change” condition appears when ___________

a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
Answer: d
Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.

351. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
JOB
c) A 20 kHz square wave
d) A 10 kHz square wave
Answer: d
Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse.
So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop
during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a
time period twice that of the clock. Frequency is inversely related to time period and hence
frequency gets halved.

352. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and
the J input is also HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use
Answer: c
Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the
integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the
toggling of states.

353. On a J-K flip-flop, when is the flip-flop in a hold condition?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer: a
Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing
state.

354. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters.
After four input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10
Answer: a

JOB
Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So
mod = 22 = 4). So after 4 clock pulses the O/P repeats i.e. 00.

355. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency
(fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
Answer: b
Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:-
fourth flip-flop. Since the output frequency is determined on basis of the 4th flip-flop.

356. Determine the output frequency for a frequency division circuit that contains 12 flip-flops
with an input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
Answer: b
Explanation: 12 flip flops = 212 = 4096
Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.

357. How many flip-flops are in the 7475 IC?

a) 2
b) 1
c) 4
d) 8
Answer: c
Explanation: There are 4 flip-flops used in 7475 IC and those are D flip-flops only

D Flip Flop
358. In D flip-flop, D stands for _____________
a) Distant
b) Data

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c) Desired
d) Delay
Answer: b
Explanation: The D of D-flip-flop stands for “data”. It stores the value on the data line.

359. The D flip-flop has _______ input.

a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the
value on the data line.

360. The D flip-flop has ______ output/outputs.

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one
input. The D of D-flip-flop stands for “data”. It stores the value on the data line.

361. A D flip-flop can be constructed from an ______ flip-flop.

a) S-R
b) J-K
c) T
d) S-K
Answer: a
Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter
between S and R and assigning the symbol D to the S input.

362. In D flip-flop, if clock input is LOW, the D input ___________

a) Has no effect
b) Goes high
c) Goes low
d) Has effect
Answer: a
JOB
Explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and
reset inputs of the NAND flip-flop are kept HIGH.

363. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle
Answer: a
Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from this
diagram:

364. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?

a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input
Answer: a
Explanation: By the truth table of D flip flop, we can observe that Q always depends on D.

JOB
Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.

365. Which of the following is correct for a gated D flip-flop?

a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH
Answer: d
Explanation: If clock is high then the D flip-flop operate and we know that input is equals to
output in case of D flip-flop. It stores the value on the data line.

366. With regard to a D latch ________

a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN’s input state
Answer: c
Explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop
output follows the input. It stores the value on the data line.

367. Which of the following is correct for a D latch?

a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled
Answer: b

JOB
Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals to
output in case of D flip flop. It stores the value on the data line.

368. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
output on the trailing edge of the clock
Answer: b
Explanation: Edge-triggered flip-flop means the device will change state during the rising or
falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will
follow the i/p when the enable pin is HIGH.

369. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input
actions will cause it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
Answer: d
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going
Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage
output will be 1 and hence the stage will be changed.

370. A positive edge-triggered D flip-flop will store a 1 when ________

a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
Answer: b
Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and
the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store
a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.

371. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
JOB
c) Due to its capability to transfer the data into flip-flop
d) Due to erasing the data from the flip-flop
Answer: c
Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value
on the data line.

372. The characteristic equation of D-flip-flop implies that ___________

a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state
Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific output
in order to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) =
D; which indicates that the next state is independent of the present state.

Master-Slave Flip-Flops
373. The asynchronous input can be used to set the flip-flop to the ____________
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
Answer: c
Explanation: The asynchronous input can be used to set the flip-flop to the 1 state or clear the
flip-flop to the 0 state at any time, regardless of the condition at the other inputs.

374. Input clock of RS flip-flop is given to ____________

a) Input
b) Pulser
c) Output
d) Master slave flip-flop
Answer: b
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or
determination of corresponding states.

JOB
375. D flip-flop is a circuit having ____________
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
Answer: c
Explanation: D flip-flop is a circuit having 4 NAND gates. Two of them are connected with each
other.

376. In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will
oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is
uncertain. The situation is referred to as?
a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
Answer: b
Explanation: A race around condition is a flaw in an electronic system or process whereby the
output and result of the process is unexpectedly dependent on the sequence or timing of other
events.

377. Master slave flip flop is also referred to as?

a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop
Answer: b
Explanation: The term pulse triggered means the data is entered on the rising edge of the clock
pulse, but the output does not reflect the change until the falling edge of the clock pulse.

378. In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state
b) Low state
c) Toggle state
d) No Change State
Answer: d
Explanation: In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.

JOB
379. If one wants to design a binary counter, the preferred type of flip-flop is ____________
a) D type
b) S-R type
c) Latch
d) J-K type
Answer: d
Explanation: If one wants to design a binary counter, the preferred type of flip-flop is J-K type
because it has capability to recover from toggle condition. SR flip-flop is not suitable as it
produces the “Invalid State”.

380. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
____________
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
Answer: c
Explanation: S-R type flip-flop can be converted into D type flip-flop if S is connected to R
through an Inverter gate.

381. Which of the following flip-flops is free from the race around the problem?
a) T flip-flop
b) SR flip-flop
c) Master-Slave Flip-flop
d) D flip-flop
Answer: a
Explanation: T flip-flop is free from the race around condition because its output depends only
on the input; hence there is no any problem creates as like toggle.

382. Which of the following is the Universal Flip-flop?

a) S-R flip-flop
b) J-K flip-flop
c) Master slave flip-flop
d) D Flip-flop
Answer: b
Explanation: There are lots of flip-flops can be prepared by using J-K flip-flop. So, the name is a
universal flip-flop. Also, the JK flip-flop resolves the Forbidden State.

JOB
383. How many types of triggering takes place in a flip flops?
a) 3
b) 2
c) 4
d) 5
Answer: a
Explanation: There are three types of triggering in a flip-flop, viz., level triggering, edge
triggering and pulse triggering.

384. Flip-flops are ____________

a) Stable devices
b) Astable devices
c) Bistable devices
d) Monostable devices
Answer: c
Explanation: Flip-flops are synchronous bistable devices known as bistable multivibrators as
they have 2 stable states.

385. The term synchronous means ____________

a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
Answer: b
Explanation: The term synchronous means the output changes state only when the clock input is
triggered. That is, changes in the output occur in synchronization with the clock.

386. The S-R, J-K and D inputs are called ____________

a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
Answer: b
Explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these
inputs are transferred to the flip-flop’s output only on the triggering edge or level triggering of
the clock pulse. Moreover, flip-flops have a clock input whereas latches don’t. Hence, known as
synchronous inputs.

JOB
387. The circuit that generates a spike in response to a momentary change of input signal is
called ____________
a) R-C differentiator circuit
b) L-R differentiator circuit
c) R-C integrator circuit
d) L-R integrator circuit
Answer: a
Explanation: The circuit that generates a spike in response to a momentary change of input signal
is called R-C differentiator circuit.

Counters
388. In digital logic, a counter is a device which ____________
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and sometimes
displays) the number of times a particular event or process has occurred, often in relationship to
a clock signal.

389. A counter circuit is usually constructed of ____________

a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Answer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in
cascade. Preferably, JK Flip-flops are used to construct counters and registers.

390. What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1

JOB
d) 0 to 2n+1/2
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will
count till 22-1 = 3. Thus, it will count from 0 to 3.

391. How many types of the counter are there?

a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-
mode & (iii)modulus counter. These further can be subdivided into Ring Counter, Johnson
Counter, Cascade Counter, Up/Down Counter and such like.

392. A decimal counter has ______ states.

a) 5
b) 10
c) 15
d) 20
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also
known as Decade Counter counting from 0 to 9.

393. Ripple counters are also called ____________

a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous counters,
only the first flip-flop is connected to an external clock while the rest of the flip-flops have their
preceding flip-flop output as clock to them.

394. Synchronous counter is a type of ____________

a) SSI counters
b) LSI counters
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c) MSI counters
d) VLSI counters
Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous
Counters, the clock pulse is supplied to all the flip-flops simultaneously.

395. Three decade counter would have ____________

a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would
require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.

396. BCD counter is also known as ____________

a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same number
of stages and both count from 0 to 9.

397. The parallel outputs of a counter circuit represent the _____________

a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
Answer: d
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter counts
the number of times an event takes place in accordance to the clock pulse.

Asynchronous Counter
398. How many natural states will there be in a 4-bit ripple counter?
a) 4

JOB
b) 8
c) 16
d) 32
Answer: c
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.

399. A ripple counter’s speed is limited by the propagation delay of _____________

a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series of
Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed
of FF only and no gates are there other than FF, so only propagation delay of FF will be taken
into account. Propagation delay refers to the amount of time taken in producing an output when
the input is altered.

400. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and
low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-
frequency applications
Answer: b
Explanation: One of the major drawbacks to the use of asynchronous counters is that High-
frequency applications are limited because of internal propagation delays. Propagation delay
refers to the amount of time taken in producing an output when the input is altered.

401. Internal propagation delay of asynchronous counter is removed by ____________

a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
Answer: d

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Explanation: Propagation delay refers to the amount of time taken in producing an output when
the input is altered. Internal propagation delay of asynchronous counter is removed by
synchronous counter because clock input is given to each flip-flop individually in synchronous
counter.

402. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
Answer: b
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st flip-flop is
given to second flip-flop as clock input. So, in case of binary down counter the output word
decreases by 1.

403. How many flip-flops are required to construct a decade counter?

a) 4
b) 8
c) 5
d) 10
Answer: a
Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n.
24=16and23=8, therefore, 4 flip flops needed.

404. The terminal count of a typical modulus-10 binary counter is ____________

a) 0000
b) 1010
c) 1001
d) 1111
Answer: c
Explanation: A binary counter counts or produces the equivalent binary number depending on
the cycles of the clock input. Modulus-10 means count from 0 to 9. So, terminal count is 9
(1001).

405. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
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c) 8
d) 16
Answer: c
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.

406. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in
the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits =
12ns * 5 = 60ns.

407. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many
transitional states are required?
a) 1
b) 2
c) 8
d) 15
Answer: d
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore,
transition states = 24 – 1 = 15. So, total transitional states are 15.

408. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of
____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in

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the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 =
60.

409. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000
Answer: d
Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e.
10*10*10=1000 states.

410. A ripple counter’s speed is limited by the propagation delay of ____________

a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series of
Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed
of FF only and no gates are there other than FF, so only propagation delay of FF will be taken
into account. Propagation delay refers to the amount of time taken in producing an output when
the input is altered.

Asynchronous down counter

411. Which of the following statements are true?
a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
Answer: a
Explanation: Asynchronous events does not occur at the same time because of propagation delay

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and they do need a clock pulse to trigger them. Whereas, synchronous events occur in presence
of clock pulse.

412. A down counter using n-flip-flops count ______________

a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
Answer: a
Explanation: As the name suggests down counter means counting occurs from a higher value to
lower value (i.e. (2^n – 1) to 0).

413. UP Counter is ____________

a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
d) Toggles between Up and Down count
Answer: a
Explanation: UP counter counts in an upward manner from 0 to (2^n – 1).

414. DOWN counter is ____________

a) It counts in upward manner
b) It count in downward manner
c) It counts in both the direction
d) Toggles between Up and Down count
Answer: b
Explanation: DOWN counter counts in a downward manner from (2^n – 1) to 0.

415. How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8
Answer: d
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.

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416. In a down counter, which flip-flop doesn’t toggle when the inverted output of the
preceeding flip-flop goes from HIGH to LOW.
a) MSB flip-flop
b) LSB flip-flop
c) Master slave flip-flop
d) Latch
Answer: b
Explanation: Since, the LSB flip-flop changes its state at each negative transition of clock. That
is why LSB flip-flop doesn’t have toggle.

417. In a 3-bit asynchronous down counter, the initial content is ____________

a) 000
b) 111
c) 010
d) 101
Answer: a
Explanation: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first
negative transition of the clock, the counter content becomes 101.

418. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the
counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
Answer: b
Explanation: Since, in the down counter, the counter content is decremented by 1 for every
negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition
of the clock, the counter content becomes 111.

419. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the
counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
Answer: c

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Explanation: Since, in the down counter, the counter content is decremented by 1 for every
negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative transition
of the clock, the counter content becomes 101.

420. The hexadecimal equivalent of 15,536 is ________

a) 3CB0
b) 3C66
c) 63C0
d) 6300
Answer: a
Explanation: You just divide the number by 16 at the end and store the remainder from bottom to
top.

Up down counter
421. UP-DOWN counter is a combination of ____________
a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter
Answer: d
Explanation: As the name suggests UP-DOWN, it means that it has up-counter and down-
counter as well. It alternatively counts up and down.

422. UP-DOWN counter is also known as ___________

a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter
Answer: c
Explanation: UP-DOWN counter is also known as multimode counter because it has capability
of counting upward as well as downwards.

423. In an UP-counter, each flip-flop is triggered by ___________

a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop

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d) The inverted output of the preceding flip-flop
Answer: b
Explanation: In an UP-counter, each flip-flop is triggered by the normal output of the preceding
flip-flop. UP-counter counts from 0 to a maximum value.

424. In DOWN-counter, each flip-flop is triggered by ___________

a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
Answer: d
Explanation: In DOWN-counter, each flip-flop is triggered by the inverted output of the
preceding flip-flop. DOWN-counter counts from a maximum value to 0.

425. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
Answer: a
Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN
counter/multimode counter. It alternately counts up and down.

426. Once an up-/down-counter begins its count sequence, it ___________

a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered
Answer: d
Explanation: In up/down ripple counter once the counting begins, we can simply change the
pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.

427. In 4-bit up-down counter, how many flip-flops are required?

a) 2
b) 3
c) 4
d) 5
Answer: c
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Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there are
4 J-K flip-flops required.

428. A modulus-10 counter must have ________

a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking
Answer: b
Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we
require 4 FFs.

429. Which is not an example of a truncated modulus?

a) 8
b) 9
c) 11
d) 15
Answer: a
Explanation: An n-bit counter whose modulus is less than the maximum possible is called a
truncated counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas,
modulus-8 is not a truncated counter.

430. The designation means that the ________

a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH
Answer: a
Explanation: The designation means that the up count is active-HIGH, the down count is active-
LOW. Active-High means that up-count would be triggered when clock is 1 else when clock is 0,
down-count would be triggered, which is referred to as Active-low.

Registers
431. A register is defined as ___________
a) The group of latches for storing one bit of information

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b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
Answer: d
Explanation: A register is defined as the group of flip-flops suitable for storing binary
information. Each flip-flop is a binary cell capable of storing one bit of information. The data in
a register can be transferred from one flip-flop to another.

432. The register is a type of ___________

a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches
Answer: a
Explanation: Register’s output depends on the past and present states of the inputs. The device
which follows these properties is termed as a sequential circuit. Whereas, combinational circuits
only depend on the present values of inputs.

433. How many types of registers are?

a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-Out,
Parallel-In/Serial-Out and Parallel-In/Parallel-Out.

434. The main difference between a register and a counter is ___________

a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
Answer: a
Explanation: The main difference between a register and a counter is that a register has no
specific sequence of states except in certain specialised applications.

435. In D register, ‘D’ stands for ___________

a) Delay
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b) Decrement
c) Data
d) Decay
Answer: c
Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a
group of flip-flops.

436. Registers capable of shifting in one direction is ___________

a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
Answer: b
Explanation: The register capable of shifting in one direction is unidirectional shift register. The
register capable of shifting in both directions is known as a bidirectional shift register.

437. A register that is used to store binary information is called ___________

a) Data register
b) Binary register
c) Shift register
d) D – Register
Answer: b
Explanation: A register that is used to store binary information is called a binary register. A
register in which data can be shifted is called shift register.

438. A shift register is defined as ___________

a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
Answer: b
Explanation: The register capable of shifting information either to the right or to the left is
termed as shift register. A register in which data can be shifted only in one direction is called
unidirectional shift register, while if data can shifted in both directions, it is known as a
bidirectional shift register.

439. How many methods of shifting of data are available?

a) 2
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b) 3
c) 4
d) 5
Answer: a
Explanation: There are two types of shifting of data are available and these are serial shifting &
parallel shifting.

440. In serial shifting method, data shifting occurs ____________

a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
Answer: a
Explanation: As the name suggests serial shifting, it means that data shifting will take place one
bit at a time for each clock pulse in a serial fashion. While in parallel shifting, shifting will take
place with all bits simultaneously for each clock pulse in a parallel fashion.

Shift Registers
441. Based on how binary information is entered or shifted out, shift registers are classified into
_______ categories.
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as shift
registers. Based on how binary information is entered or shifted out, shift registers are classified
into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-
In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).

442. The full form of SIPO is ___________

a) Serial-in Parallel-out
b) Parallel-in Serial-out

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c) Serial-in Serial-out
d) Serial-In Peripheral-Out
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.

443. A shift register that will accept a parallel input or a bidirectional serial load and internal
shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Answer: c
Explanation: A shift register can shift it’s data either left or right. The universal shift register is
capable of shifting data left, right and parallel load capabilities.

444. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Answer: d
Explanation: Because no other flip-flops are connected with the output Q, therefore one can use
the Q out of each FF to take out parallel data.

445. What is meant by parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Answer: a
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus
input is definitely 1.

446. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output
shift register with an initial state 01110. After three clock pulses, the register contains ________
a) 01110
b) 00001

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c) 00101
d) 00110
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.

447. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with every
clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.

448. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is
waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every
clock pulse. Therefore,
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk

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0 | 1110 3rd clk
X | 1111 4th clk.

449. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Answer: b
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded
= 8 * 5 = 40 micro-sec.

450. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve
a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
Answer: c
Explanation: One clock period is = (½) micro-s = 0.5 microseconds. In serial transmission, data
enters one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required to transmit
information of 8 bits.

Universal Shift Registers

451. A sequence of equally spaced timing pulses may be easily generated by which type of
counter circuit?
a) Ring shift
b) Clock
c) Johnson
d) Binary
Answer: a
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input.
Thus, it generates equally spaced timing pulses.

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452. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble
1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift
register is storing ________
a) 1101
b) 0111
c) 0001
d) 1110
Answer: b
Explanation: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits
are 011 and remained bit in register is 1. Therefore, 0111 is required solution.
1011 | 1101
101 | 1110 -> 1st clock pulse
10 | 1111 -> 2nd clock pulse
1 | 0111 -> 3rd clock pulse.

453. To operate correctly, starting a ring shift counter requires __________

a) Clearing all the flip-flops
b) Presetting one flip-flop and clearing all others
c) Clearing one flip-flop and presetting all others
d) Presetting all the flip-flops
Answer: b
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s input.
To operate correctly, starting a ring shift counter requires presetting one flip-flop and clearing all
others so that it can shift to the next bit.

454. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by
________ position for each clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
Answer: a
Explanation: If register shifts towards left then it shift by a bit to the left and if register shifts
right then it shift to the right by one bit. Since, it receives parallel data, then by default, it will
shift to right by one position.

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455. How many clock pulses will be required to completely load serially a 5-bit shift register?
a) 2
b) 3
c) 4
d) 5
Answer: d
Explanation: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1 shift
register. So, for 5-bit shift register we would require of 5 clock pulses.

456. How is an strobe signal used when serially loading a shift register?
a) To turn the register on and off
b) To control the number of clocks
c) To determine which output Qs are used
d) To determine the FFs that will be used
Answer: b
Explanation: A strobe is used to validate the availability of data on the data line. It (an auxiliary
signal used to help synchronize the real data in an electrical bus when the bus components have
no common clock) signal is used to control the number of clocks during serially loading a shift
register.

457. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is
the time delay between the serial input and the Q3 output?
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
Answer: b
Explanation: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4 bit
shifting takes place. Therefore, 4/150kHz = 26.67 microseconds.

458. What are the three output conditions of a three-state buffer?

a) HIGH, LOW, float
b) High-Z, 0, float
c) Negative, positive, 0
d) 1, Low-Z, float
Answer: a
Explanation: Three conditions of a three-state buffer are HIGH, LOW & float.

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459. The primary purpose of a three-state buffer is usually ____________
a) To provide isolation between the input device and the data bus
b) To provide the sink or source current required by any device connected to its output without
loading down the output device
c) Temporary data storage
d) To control data flow
Answer: a
Explanation: The primary purpose of a three-state buffer is usually to provide isolation between
the input device or peripheral devices and the data bus. Three conditions of a three-state buffer
are HIGH, LOW & float.

460. What is the difference between a ring shift counter and a Johnson shift counter?
a) There is no difference
b) A ring is faster
c) The feedback is reversed
d) The Johnson is faster
Answer: c
Explanation: A ring counter is a shift register (a cascade connection of flip-flops) with the output
of the last one connected to the input of the first, that is, in a ring. Whereas, a Johnson counter
(or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a
modified ring counter, where the output from the last stage is inverted and fed back as input to
the first stage.

Shift Register Counters

461. What is a recirculating register?
a) Serial out connected to serial in
b) All Q outputs connected together
c) A register that can be used over again
d) Parallel out connected to Parallel in
Answer: a
Explanation: A recirculating register is a register whose serial output is connected to the serial
input in a circulated manner.

462. When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input

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b) When all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs
Answer: a
Explanation: When two or more outputs are connected to the same input, in such situation we
use of tristate buffer always because it has the capability to take upto three inputs. A buffer is a
circuit where the output follows the input.

463. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble
0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift
register is storing ________
a) 1110
b) 0111
c) 1000
d) 1001
Answer: d
Explanation: Stored nibble | waiting nibble
0111 | 1110, Initially
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.

464. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three

clock pulses, the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
Answer: b
Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock
pulses, the data outputs are 0001.

465. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state 11110000. After two clock pulses, the register contains
a) 10111000
b) 10110111
c) 11110000
d) 11111100

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Answer: d
Explanation: After first clock pulse, the register contains 11111000. After second clock pulse,
the register would contain 11111100. Since, the bits are shifted to the right at every clock pulse.

466. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a
________ ________ and ________ out register.
a) Parallel-in, serial, parallel
b) Serial-in, parallel, serial
c) Series-parallel-in, series, parallel
d) Bidirectional in, parallel, series
Answer: a
Explanation: One bit shifting takes place just after the output obtained on every register. Hence,
by adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-
in, Serial, and Parallel-out register. Since, the bots can be inputted all at the same time, while the
data can be outputted either one at a time or simultaneously.

467. What type of register would have a complete binary number shifted in one bit at a time and
have all the stored bits shifted out one at a time?
a) Parallel-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-in Parallel-out
Answer: c
Explanation: Serial-in Serial-out register would have a complete binary number shifted in one bit
at a time and have all the stored bits shifted out one at a time. Since in serial transmission, bits
are transmitted or received one at a time and not simultaneously.

468. In a 4-bit Johnson counter sequence, there are a total of how many states, or bit patterns?
a) 1
b) 3
c) 4
d) 8
Answer: d
Explanation: In johnson counter, total number of states are determined by 2N = 2*4 = 16
Total Number of Used states = 2N = 2*4 = 8
Total Number of Unused states = 16 – 8 = 8.

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469. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second
clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
Answer: b
Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at
1st position and 2nd position which came from the last two bits). As in a ring counter, the bits
rotate in clockwise direction.

470. How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits
Answer: a
Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a shift
register has the capability to store one bit and if another bit is to store, in such situation it deletes
the previous data and stores them.

Introduction of Memory Devices

471. Memory is a/an ___________
a) Device to collect data from other computer
b) Block of data to keep data separately
c) Indispensable part of computer
d) Device to connect through all over the world
Answer: c
Explanation: Memory is an indispensable unit of a computer and microprocessor based systems
which stores permanent or temporary data.

472. The instruction used in a program for executing them is stored in the __________
a) CPU
b) Control Unit
c) Memory

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d) Microprocessor
Answer: c
Explanation: All of the program and the instructions are stored in the memory. The processor
fetches it as and when required.

473. A flip flop stores __________

a) 10 bit of information
b) 1 bit of information
c) 2 bit of information
d) 3-bit information
Answer: b
Explanation: A flip-flop has capability to store 1 bit of information. It can be used further after
erasing previous information.

474. A register is able to hold __________

a) Data
b) Word
c) Nibble
d) Both data and word
Answer: b
Explanation: Register is also a part of memory inside a computer. It stands there to hold a word.
A word is a group of 16-bits or 2-bytes.

475. A register file holds __________

a) A large number of word of information
b) A small number of word of information
c) A large number of programs
d) A modest number of words of information
Answer: d
Explanation: A register file is different from a simple register because of capability to hold a
modest number of words of information. A word is a group of 16-bits or 2-bytes.

476. The very first computer memory consisted of __________

a) A small display
b) A large memory storage equipment
c) An automatic keyboard input
d) An automatic mouse input
Answer: b
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Explanation: The very first computer memory consisted of a minute magnetic toroid, which
required large, bulky circuit boards stored in large cabinates.

477. A minute magnetic toroid is also called as __________

a) Large memory
b) Small memory
c) Core memory
d) Both small and large memory
Answer: c
Explanation: A minute magnetic toroid is also called as core memory which is made up of a
semiconductor. A semiconductor is a device whose electrical conductivity lies between that of
conductor and insulator.

478. Which one of the following has capability to store data in extremely high densities?
a) Register
b) Capacitor
c) Semiconductor
d) Flip-Flop
Answer: c
Explanation: Semiconductor has capability to store data in extremely high densities.

479. A large memory is compressed into a small one by using __________

a) LSI semiconductor
b) VLSI semiconductor
c) CDR semiconductor
d) SSI semiconductor
Answer: b
Explanation: VLSI (Very Large Scale Integration) semiconductor is used in modern computers
to short the size of memory.

480. VLSI chip utilizes __________

a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
Answer: d
Explanation: VLSI (Very Large Scale Integration) is a memory chip which is made up of
NMOS, CMOS, BJT, and BiCMOS. It can include 10,000 to 100,000 gates per IC.
JOB
481. CD-ROM refers to __________
a) Floppy disk
b) Compact Disk-Read Only Memory
c) Compressed Disk-Read Only Memory
d) Compressed Disk- Random Access Memory
Answer: b
Explanation: CD-ROM refers to Compact Disk-Read Only Memory.

482. Data stored in an electronic memory cell can be accessed at random and on demand using
__________
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
Answer: b
Explanation: Direct addressing eliminates the need to process a large stream of irrelevant data in
order to the desired data word.

483. The full form of PLD is __________

a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device
Answer: c
Explanation: The full form of PLD is Programmable Logic Device.

484. The evolution of PLD began with __________

a) EROM
b) RAM
c) PROM
d) EEPROM
Answer: a
Explanation: The evolution of PLD (Programmable Logic Device) began with Programmable
Read Only Memory (i.e. PROM). Here, the ROM can be externally programmed as per the user.

485. A ROM is defined as __________

a) Read Out Memory
b) Read Once Memory
JOB
c) Read Only Memory
d) Read One Memory
Answer: c
Explanation: A ROM is defined as Read Only Memory which can read the instruction stored in a
computer.

Random Access Memory

486. What is access time?
a) The time taken to move a stored word from one bit to other bits after applying the address bits
b) The time taken to write a word after applying the address bits
c) The time taken to read a stored word after applying the address bits
d) The time taken to erase a stored word after applying the address bits
Answer: c
Explanation: The access time is the time taken to read a stored word after applying the address
bits in a MOS EPROM. It is the time required to fetch data from the memory.

487. What are the typical values of tOE?

a) 10 to 20 ns for bipolar
b) 25 to 100 ns for NMOS
c) 12 to 50 ns for CMOS
d) All of the Mentioned
Answer: d
Explanation: The access time is the time taken to read a stored word after applying the address
bits in a MOS EPROM. It is the time required to fetch data from the memory. The typical values
of tOE (i.e. access time) are 10 to 20 ns for bipolar, 25 to 100 ns for NMOS and 12 to 50 ns for
CMOS.

488. Which of the following is not a type of memory?

a) RAM
b) FPROM
c) EEPROM
d) ROM

JOB
Answer: c
Explanation: EEPROM (Electrical Erasable Programmable ROM) is not a type of memory
because it is used for erasing purpose only. Through EEPROM, data can be erased electrically,
thereby consuming less time.

489. The chip by which both the operation of read and write is performed __________
a) RAM
b) ROM
c) PROM
d) EPROM
Answer: a
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the
read and write operations can be performed. Since it is volatile, therefore it stores data as long as
power is on.

490. RAM is also known as __________

a) RWM
b) MBR
c) MAR
d) ROM
Answer: a
Explanation: A Random Access Memory (RAM) is a volatile chip memory in which both the
read and write operations can be performed. Since it is volatile, therefore it stores data as long as
power is on. RAM is also known as RWM (i.e. Read Write Memory).

491. If a RAM chip has n address input lines then it can access memory locations upto
__________
a) 2(n-1)
b) 2(n+1)
c) 2n
d) 22n
Answer: c
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is
also known as RWM (i.e. Read Write Memory). If a RAM chip has n address input lines then it
can access memory locations upto 2n.

492. The n-bit address is placed in the __________

a) MBR
JOB
b) MAR
c) RAM
d) ROM
Answer: b
Explanation: The n-bit address is placed in the Memory Address Register (MAR) to select one of
2n memory locations. It stores the address of the instruction which is to be executed next.

493. Which of the following control signals are selected for read and write operations in a RAM?
a) Data buffer
b) Chip select
c) Read and write
d) Memory
Answer: c
Explanation: Read and write are control signals that are used to enable memory for read and
write operations respectively.

494. Computers invariably use RAM for __________

a) High complexity
b) High resolution
c) High speed main memory
d) High flexibility
Answer: c
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is
also known as RWM (i.e. Read Write Memory). Computers invariably use RAM for their high
high-speed main memory and then use backup or slower-speed memories to hold auxiliary data.

495. How many types of RAMs are?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two types of RAM and these are static and dynamic. Static RAM(SRAM)
is faster than dynamic RAM(DRAM) as the access time for DRAM is more compared to that of
SRAM.

496. Static RAM employs __________

a) BJT or MOSFET
JOB
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Answer: d
Explanation: Static RAM employs bipolar or MOS flip-flops because both the semiconductor has
storing capacity. Thus, it’s access time is less and it is faster in operation.

497. Dynamic RAM employs __________

a) Capacitor or MOSFET
b) FET or JFET
c) Capacitor or BJT
d) BJT or MOS
Answer: a
Explanation: Dynamic RAM employs a capacitor or MOSFET. Thus, it’s access time is more
and it is slower in operation.

498. Which one of the following is volatile in nature?

a) ROM
b) EROM
c) PROM
d) RAM
Answer: d
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is
also known as RWM (i.e. Read Write Memory). RAMs are volatile because the stored data will
be lost once the d.c. power applied to the flip-flops is removed.

499. The magnetic core memories have been replaced by semiconductor RAMs, why?
a) Semiconductor RAMs are highly flexible
b) Semiconductor RAMs have highest storing capacity
c) Semiconductor RAMs are smaller in size
d) All of the Mentioned
Answer: d
Explanation: RAM is a volatile memory, therefore it stores data as long as power is on. RAM is
also known as RWM (i.e. Read Write Memory). The magnetic core memories have been
replaced by semiconductor RAMs because of smaller in size, high storing capacity as well as
flexibility.

JOB
500. The data written in flip-flop remains stored as long as __________
a) D.C. power is supplied
b) D.C. power is removed
c) A.C. power is supplied
d) A.C. power is removed
Answer: a
Explanation: Since flip-flops are made up of semiconductor materials. So, it can’t accept A.C.
source and the data written in flip-flop remains stored as long as the dc power is maintained.

Read Only Memory (ROM)

501. Which of the following has the capability to store the information permanently?
a) RAM
b) ROM
c) Storage cells
d) Both RAM and ROM
Answer: b
Explanation: ROM (Read Only Memory) has the capability to store the information permanently.
RAM provides random access to memory. Storage cells are responsible for the transfer of data
from and into the memory.

502. ROM has the capability to perform _____________

a) Write operation only
b) Read operation only
c) Both write and read operation
d) Erase operation
Answer: b
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read
operation only. No write or erase operation could be performed in the ROM.

503. Since, ROM has the capability to read the information only then also it has been designed,
why?
a) For controlling purpose
b) For loading purpose
c) For booting purpose
d) For erasing purpose

JOB
Answer: c
Explanation: ROM means “Read Only Memory”. Hence, it has capability to perform read
operation only. No write or erase operation could be performed in the ROM. It has designed to
provide the computer with resident programmes and for booting purpose.

504. The ROM is a ___________

a) Sequential circuit
b) Combinational circuit
c) Magnetic circuit
d) Static circuit
Answer: b
Explanation: ROM is a combination of different ICs. So, it is a combinational circuit.
It depends on present input and not past states.

504. ROM is made up of ___________

a) NAND and OR gates
b) NOR and decoder
c) Decoder and OR gates
d) NAND and decoder
Answer: c
Explanation: ROM (Read Only Memory) has the capability to store the information permanently.
ROM is made up of decoder and OR gates within a single IC package.

506. Why are ROMs called non-volatile memory?

a) They lose memory when power is removed
b) They do not lose memory when power is removed
c) They lose memory when power is supplied
d) They do not lose memory when power is supplied
Answer: b
Explanation: Volatile memory stores data as long as it is powered. ROMs are called non-volatile
memory because of they do not lose memory when power is removed.

507. In ROM, each bit is a combination of the address variables is called ___________
a) Memory unit
b) Storage class
c) Data word
d) Address
Answer: d
JOB
Explanation: In ROM, each bit combination that comes out of the output lines is called data
word. Usually, a word consists of 16-bits or 2-bytes.

508. Which is not a removable drive?

a) Zip
b) Hard disk
c) Super Disk
d) Jaz
Answer: c
Explanation: Hard disk is present inside a computer. So, it is not a removable drive.

509. In ROM, each bit combination that comes out of the output lines is called ___________
a) Memory unit
b) Storage class
c) Data word
d) Address
Answer: c
Explanation: In ROM, each bit combination that comes out of the output lines is called data
word. Usually, a word consists of 16-bits or 2-bytes.

510. VLSI chip utilizes ___________

a) NMOS
b) CMOS
c) BJT
d) All of the Mentioned
Answer: d
Explanation: Very Large Scale Integration (VLSI) (ranging from 10,000 to 100,000 gates per IC)
is a memory chip which is made up of NMOS, CMOS, BJT, and BiCMOS.

Programmable Read Only Memory

511. The time from the beginning of a read cycle to the end of tACS/tAA is called as
____________
a) Write enable time
b) Data hold
c) Read cycle time
d) Access time

JOB
Answer: d
Explanation: The time from the beginning of a read cycle to the end of tACS/tAA is called as
access time. It is the time in which data is fetched from the storage.

512. Why did PROM introduced?

a) To increase the storage capacity
b) To increase the address locations
c) To provide flexibility
d) To reduce the size
Answer: c
Explanation: In order to provide some flexibility in the possible applications of ROM, PROM is
introduced. PROM stands for Programmable ROM, in which the ROM is programmed by the
user.

513. Which of the following is programmed electrically by the user?

a) ROM
b) EPROM
c) PROM
d) EEPROM
Answer: c
Explanation: Programmable ROMs can be programmed electrically by the user but can’t be
reprogrammed. EEPROMs can be electrically erased and re-programmed by the user.

514. PROMs are available in ___________

a) Bipolar and MOSFET technologies
b) MOSFET and FET technologies
c) FET and bipolar technologies
d) MOS and bipolar technologies
Answer: d
Explanation: PROMs (Programmable ROMs) can be programmed electrically by the user but
can’t be reprogrammed. PROMs are available in both bipolar and MOS (Metal Oxide
Semiconductor) technologies.

515. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each address is
___________
a) 4096
b) 16384
c) 32768
JOB
d) 8129
Answer: b
Explanation: 1 address can store 8 bits. Therefore, total capacity of a memory having n addresses
= 8 * n.
Therefore, for 2048 addresses,
total capacity of a memory = 2048 * 8 = 16384 bits.

516. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8 k and
a word length of eight bits?
a) Eight
b) Two
c) One
d) Four
Answer: a
Explanation: RAM stands for Random Access Memory in which any memory address can be
accessed in any order. It requires word of length 8 bits. So, one word needs of 1 bit and 8 bit
requires 8 bits.

517. Which of the following best describes the fusible-link PROM?

a) Manufacturer-programmable, reprogrammable
b) Manufacturer-programmable, one-time programmable
c) User-programmable, reprogrammable
d) User-programmable, one-time programmable
Answer: d
Explanation: The fusible-link PROM is user programmable and one time programmable. It
means that a written program can not be reprogrammed. EPROMs can be erased and re-
programmed.

518. How can ultraviolet erasable PROMs be recognized?

a) There is a small window on the chip
b) They will have a small violet dot next to the #1 pin
c) Their part number always starts with a “U”, such as in U12
d) They are not readily identifiable, since they must always be kept under a small cover
Answer: a
Explanation: An ultraviolet erasable PROMs have small window on the chip with black marked.
Such type of PROMS are called EPROMS which are cleared by exposing it to UV radiation.
They are re-programmable.

JOB
519. Which part of a Flash memory architecture manages all chip functions?
a) Program verify code
b) Floating-gate MOSFET
c) Command code
d) Input/Output pins
Answer: b
Explanation: MOSFET technology is the best one in the manufacturing of chip because it has
high flexibility and storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory
architecture manages all chip functions.

520. How much locations an 8-bit address code can select in memory?
a) 8 locations
b) 256 locations
c) 65,536 locations
d) 131,072 locations
Answer: b
Explanation: An 8 bit address code requires 32 memory locations and it can hold maximum upto
32 * 8 = 256 locations = 28.

521. What is a fusing process?

a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) It is a process by which data is fetched through the memory
Answer: c
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it
can not be reprogrammed if any error occurs.

522. Fusing process is ___________

a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
Answer: b
Explanation: Since, any program cannot be reprogrammed in a PROM, so this process is
irreversible as PROMs are programmed using the Fusing process. Fusing is a process by which
programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.

JOB
523. The cell type used inside a PROM is ___________
a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
Answer: c
Explanation: The cell type used inside a PROM is fuse cells by which a program is burnout.
Fusing is a process by which programs are burnout to the diode/transistors and it can not be
reprogrammed if any error occurs.

524. How many types of fuse technologies are used in PROMs?

a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it
can not be reprogrammed if any error occurs. Three types of fuse technologies are used in
PROMs and these are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.

525. Metal links are made up of ___________

a) Polycrystalline
b) Magnesium sulphide
c) Nichrome
d) Silicon dioxide
Answer: c
Explanation: Metal links are made up of Nichrome materials.

Erasable Programmable Read Only Memory

526. EPROM uses an array of _______________
a) p-channel enhancement type MOSFET
b) n-channel enhancement type MOSFET
c) p-channel depletion type MOSFET
d) n-channel depletion type MOSFET
Answer: b

JOB
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV
radiation and re-programmed. EPROM uses an array of n-channel enhancement type MOSFET
with an insulated gate structure.

527. The EPROM was invented by ______________

a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell
Answer: b
Explanation: The EPROM was invented by Dov Frohman of Intel in 1971. EPROMs are
Erasable Programmable ROMs which can be erased using UV radiation and re-programmed.

528. Address decoding for dynamic memory chip control may also be used for ______________
a) Chip selection and address location
b) Read and write control
c) Controlling refresh circuits
d) Memory mapping
Answer: a
Explanation: Address decoding for dynamic memory chip control may also be used for chip
selection and address location. Chip Selection enables or disables the functioning of the chip.

529. Which of the following describes the action of storing a bit of data in a mask ROM?
a) A 0 is stored by connecting the gate of a MOS cell to the address line
b) A 0 is stored in a bipolar cell by shorting the base connection to the address line
c) A 1 is stored by connecting the gate of a MOS cell to the address line
d) A 1 is stored in a bipolar cell by opening the base connection to the address line
Answer: c
Explanation: The action of storing a bit of data in a mask ROM is that when a 1 is stored by
connecting the gate of a MOS cell to the address line. Mask ROMs are programmed by the
manufacturer and are custom made as per the user.

530. The check sum method of testing a ROM ______________

a) Allows data errors to be pinpointed to a specific memory location
b) Provides a means for locating and correcting data errors in specific memory locations
c) Indicates if the data in more than one memory location is incorrect
d) Simply indicates that the contents of the ROM are incorrect
Answer: d
JOB
Explanation: If checking of a sum method goes wrong, it simply indicates that the contents of the
ROM are incorrect.

531. The initial values in all the cells of an EPROM is ______________

a) 0
b) 1
c) Both 0 and 1
d) Alternate 0s and 1s
Answer: b
Explanation: The initial values in all the cells of a EPROM is 1.

532. To store 0 in such a cell, the floating point must be ______________

a) Reprogrammed
b) Restarted
c) Charged
d) Power off
Answer: c
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV
radiation and re-programmed. To store 0 in the cell of an EPROM, the floating point must be
charged.

533. The major disadvantage of RAM is?

a) Its access speed is too slow
b) Its matrix size is too big
c) It is volatile
d) High power consumption
Answer: c
Explanation: RAM is volatile memory. Thus, RAM stores the data as long as it is powered on
and once the power goes out, it loses its data.

534. Which one of the following is used for the fabrication of MOS EPROM?
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
Answer: c
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV
radiation and re-programmed. TMS 2516 is a MOS EPROM device.
JOB
535. How many addresses a MOS EPROM have?
a) 1024
b) 512
c) 2516
d) 256
Answer: c
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV
radiation and re-programmed. MOS EPROM (i.e. TMS 2516) has 2048 (2^11 = 2048) addresses.

536. To read from the memory, the select input and the power down/program input must be
______________
a) HIGH
b) LOW
c) Sometimes HIGH and sometimes LOW
d) Alternate HIGH and LOW
Answer: b
Explanation: To read from the memory, the select input and the power down/program input must
be LOW.

537. ROMs retain data when ______________

a) Power is on
b) Power is off
c) System is down
d) All of the Mentioned
Answer: d
Explanation: ROM retains the data when power is off/on/down because it has to read the data
from memory only and it is done in every condition. It is non-volatile memory.

538. Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How many
bytes could be stored in this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Answer: c
Explanation: 8K = 8 * 1024 = 8192.

JOB
539. When a RAM module passes the checker board test it is ______________
a) Able to read and write only 0s
b) Faulty
c) Probably good
d) Able to read and write only 1s
Answer: c
Explanation: When a RAM module passes the checker board test it is probably good. It is a
volatile memory. Thus, RAM stores the data as long as it is powered on and once the power goes
out, it loses its data.

540. What is the difference between static RAM and dynamic RAM?
a) Static RAM must be refreshed, dynamic RAM does not
b) There is no difference
c) Dynamic RAM must be refreshed, static RAM does not
d) SRAM is slower than DRAM
Answer: c
Explanation: Dynamic RAM must be refreshed because it made up of capacitor, and capacitor
required refresh. Static RAM made up of flip flop and it doesn’t required a refresh.

JOB