2021 IEEE 4th International Conference on Computing, Power and Communication Technologies (GUCON)

University of Malaya, Kuala Lumpur, Malaysia. Sep 24-26, 2021

Implementation of Sequence Detector using

Optimized GDI Technique
Prasanna Kumar K Kishore Sanapala V S V Prabhakar
Department of ECE Department of ECE, Department of ECE,
Koneru Lakshmaiah Education Marri Laxman Reddy Institute of Koneru Lakshmaiah Education
2021 IEEE 4th International Conference on Computing, Power and Communication Technologies (GUCON) | 978-1-7281-9951-1/21/$31.00 ©2021 IEEE | DOI: 10.1109/GUCON50781.2021.9573941

Foundation, Technology And Management, Foundation,

Guntur, AP, India, Hyderabad, Telangana, India Guntur, AP, India,
[email protected]

D. Pavan
Department of ECE,
Koneru Lakshmaiah Education
Foundation,
Guntur, AP, India,

Abstract: In the recent times, power economizing is In the previous work a new technique called as OGDI
becoming most essential factor of a circuit due to the technique is proposed and implemented in Cadence Virtuoso
technology scaling beyond sub-100nm. Besides the at 45nm technology for a combinational circuit to overcome
combinational logic, sequential logic blocks also play a major the drawbacks in GDI techniques. The basic idea of OGDI is
role in the design of power efficient complex computational shown in Figure 2. For implementation of the complex logic
systems. This paper introduces the Optimized GDI Technique circuits, the regenerator is added only at the output signal. So
(OGDI) for the design of sequential logic blocks. A Sequence only 4 more transistors are required to implement a logic
detector is designed using OGDI technique and the
using the OGDI technique. A full adder is implemented
performance is compared with the conventional CMOS
using OGDI technique and compared with CMOS technique.
technique. The results obtained using OGDI logic has shown
significant improvement and achieved more than 28% power
Results showed that the power consumed by the circuit
savings in comparison with the CMOS logic. Cadence Virtuoso designed with OGDI is less than 50% of the power
is used for simulation and analysis, and 45nm technology is consumed by the CMOS technique [14]-[26].
used. The combinational part of a circuit deals with arithmetic
and logical operations on the data. When an application
Key words: Complementary metal–oxide–semiconductor
needs to store data along with combinational circuitry, the
(CMOS), Optimized Gate Diffusion Input (OGDI), Sequence
sequential circuitry plays a key role as memory element.
Detector, Cadence, Sequential circuit.

I. INTRODUCTION
The prime factor and consideration of any designer is the
energy consumed by the system. The basic element of any
electrical system is a transistor. The number of transistors
increases the complexity and in turn energy consumed by the
circuit also increases. When compared to last few decades
the devices existing is more and denser i.e., the number of
transistors that are used in the same unit area increases
rapidly. With the increase of the transistors the switching
actions of the circuit also increases which leads to more
power consumption of the circuit. Even though the
conventional CMOS technique is the best suited technique
for design of low power circuits, there is still need for the
advancement in the design techniques to minimize the Fig. 1. GDI cell
complexity and power consumption of the electronic circuits.
The basic memory element of any circuit is Flip Flop. In
Gate Diffusion Input (GDI) [3]-[13] is found to be one of this paper, D-Flip Flop is implemented with OGDI and
the techniques that reduce the complexity by reducing the CMOS techniques and compared the key considerations like
number of transistors in the design of digital circuits. The power and area of the circuit. Besides to verify the OGDI
number of transistors required to implement basic logic gates logic in the coalition of both combinational and sequential
is shown in Table 1. N and P are the source terminals of circuits, a sequence detector [27] is implemented using D-
NMOS and PMOS respectively and G is the common gate Flip Flop and the outputs of OGDI and CMOS techniques
terminal. Figure 1 shows the basic GDI cell. But the GDI are compared.
logic lags in giving full swing at the output. This limitation
of the GDI technique is overwhelmed by Optimized Gate
Diffusion Input (OGDI).

978-1-7281-9951-1/21/$31.00 ©2021 IEEE 1

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 A. Design of multiplexer
As discussed 2X1 MUX is designed to implement the
logic gates. The logic expression and truth table of 2X1
MUX is shown in Eq. 1 and Table 2 respectively.

TABLE II. MUX TRUTH TABLE

S A B OUT
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
Fig. 2. Optimized GDI cell
1 1 0 0
1 1 1 1
TABLE I. COMPARISON OF GDI AND CMOS

N P G OUT FUNCTION GDI CMOS OUT = S’.A+S.B (1)

0 1 A A’ Inverter 2 2 Where S is Selection Line, A and B are input lines.
0 B A A’B Function 1 2 6
B 1 A A’+B Function 2 2 6 Where S is Selection Line, A and B are input lines.
1 B A A+B OR 2 6
B 0 A A.B AND 2 6 B. CMOS technique
C B A A’B+AC MUX 2 12 In CMOS technique to design a 2X1 MUX, 12 transistors
B’ B A A’B+AB’ XOR 4 16 are required. The schematic of 2X1 MUX is shown in
B B’ A A’B’+AB XNOR 4 16 Figure 3.

The contribution of this paper is accompanied as below:

Section II is describing about methodology and design
techniques. Section III shows the results of designed
techniques and finally the paper is ended with conclusion
followed by references in Section IV.
II. METHODS AND DESIGNS
The circuits in this paper are designed and simulated in
the Cadence Virtuoso tool using 45nm technology. The logic
gates are designed using multiplexer, the advantages of using
multiplexer to implement the logic are:
x The multiplexer (MUX) reduces the cost and
complexity of the transmission circuit.
x Analog switching current is of low order which is
from 10mA-20mA. Fig. 3. Schematic of 2X1 MUX using CMOS technique

x Due to low switching current, the heat dissipation is C. Optimized OGDI technique:
very low.
By using GDI technique as shown in Table 1, 2X1 MUX
x The capacity of MUX to switch digital signals can is implemented using only 2 transistors. The schematic of
be expanded to include video, audio, and other types MUX implemented using GDI technique is shown in Figure
of signals. 4. In OGDI technique the output of the GDI is connected to
input of the regenerator in order to get full swing at the
First and foremost, this section describes about design of
output which is shown in Figure 5. The selection line is
MUX by using OGDI technique and CMOS technique then
given to common gate terminal of PMOS and NMOS; inputs
designing the NAND gate using MUX. After designing the
A and B are given to source terminals of PMOS and NMOS
NAND gate a negative edged D-Flip Flop is designed in
respectively.
master slave configuration using this NAND gate. At last a
101-sequence detector is designed using D-Flip Flop and
logic gates.

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 whenever A is ‘0’ MUX input A is connected to output,
therefore according to Table 2 MUX input A is always
connected to VDD. If NAND input A is ‘1’ MUX input B is
connected with output. So, inverted NAND input B gate is
given to MUX input B.

Fig. 6. NAND gate using 2X1 MUX

2) Design of D-Flip Flop

The negative edged D-Flip Flop is designed using NAND
Fig. 4. Schematic of 2X1 MUX using GDI technique gate in master slave configuration. In designing one D-Flip
Flop eight NAND gates are required and each NAND gate
has in turn one MUX. In the conventional techniques like
CMOS, 96 transistors are required entirely for a MUX logic
to design one flip flop but by using the GDI technique with
only 16 transistors the MUX logic can be implemented for
each flip flop. As OGDI technique consisting of 2 outputs,
for each output four transistors are required. Besides to GDI
logic eight transistors are required.
The complexity in switching is reduced to a great extent
in OGDI technique with full swing output when compared to
CMOS technique. Simulation results are shown in next
section. The schematic of D-Flip Flop with NAND gates is
Fig. 5. Schematic of 2X1 MUX using OGDI technique shown in Figure 7.

As observed from Figure 3, Figure 4 and Figure 5 the

complexity of designing MUX has reduced to a great extent
by using the GDI and OGDI technique than the conventional
CMOS technique.
1) NAND gate using MUX
Multiplexer is also known as universal logic function.
The design with Multiplexer is also simpler and more Fig. 7. Schematic of negative edged D-Flip Flop in Master Slave
economical when compared with the function implemented configuration
with the logic gates. A NAND gate is implemented using
2X1 multiplexer which is designed using OGDI technique Truth table of negative edged D-Flip Flop is shown in
shown in Figure 6. Table 4. Whenever the clock has raising edge i.e., positive
edge, the output remains at same state. When the clock has
The NAND gate that is designed using MUX is shown in falling edge i.e., negative edge the output is directly
Figure 5. Truth table of 2 input NAND gate is shown in connected to input.
Table 3.
TABLE IV. TRUTH TABLE OF NEGATIVE EDGED D-FLIP FLOP
TABLE III. NAND GATE TRUTH TABLE
CLK D Q Q’
A B OUT ↑ 0 Q Q’
0 0 1 ↑ 1 Q Q’
0 1 1 ↓ 0 0 1
1 0 1 ↓ 1 1 0
1 1 0 3) Design of Sequence Detector
A 101-sequence detector as a Finite State Machine
(FSM) is implemented with both CMOS and OGDI
As shown in Table 2 and Eq.1 for MUX output is techniques. The schematic of FSM in both CMOS and OGDI
depended on the selection line depending on the selection techniques is shown in Figure 8 and Figure 9 respectively. In
line the input line is connected to output line. The NAND Figure 8 there is regenerator at the output in order to get full
gate input A is connected as selection line for MUX, i.e., swing which overcomes the drawback of GDI technique.

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 . 2) CMOS technique
The transient response of D-Flip Flop and sequence
detector implemented with CMOS technique is shown in
Figure 12 and Figure 13 respectively.

Fig. 8. Block Diagram of 101 sequence detector using CMOS technique

Fig. 12. Transient response of D-Flip Flop implemented with CMOS

technique

Fig. 9. Block Diagram of 101 sequence detector using OGDI technique

III. RESULTS AND DISCUSSION

This section deals with the simulation waveforms, power
analysis and layout area calculations of D-Flip Flop and
Sequence detector shown in previous section. The detailed
analysis is carried out in Cadence Virtuoso at 45nm
technology.
A. Waveforms Fig. 13. Transient response of sequence detector implemented with CMOS
technique
Conservative transient analysis is carried out and the
resultant waveforms of each response is explained and The output response of the sequence detector
compared in this section. implemented with CMOS technique in Figure 13 shows
1) OGDI technique some glitches when compared with sequence detector
The transient response of D-Flip Flop and sequence implemented with OGDI technique in Figure 11. From this
detector implemented with OGDI technique is shown in comparison of transient response, OGDI technique stands
Figure 10 and Figure 11 respectively. The response of the beside CMOS even better than CMOS for implementing
both circuits shows that there are no glitches and deviations sequential circuits.
from the voltage levels to the given input. The output shows B. Power Consumption
very accurate and perfect response to the given input. In the previous discussion it is determined that OGDI
technique is best suited for implementing sequential circuits
with respect to the output response with the input. In this
section the efficiency of the OGDI technique is determined
when compared to widely use conventional CMOS technique
with respect to power consumption of the circuit.

TABLE V. POWER CONSUMPTION

Power Consumed by Power Consumed
circuit in by circuit in
CIRCUIT
OGDI technique CMOS technique
(nW) (nW)
Fig. 10. Transient response of D-Flip Flop implemented with OGDI D flip flop 90.645 208.87
technique
Sequence
535.60 746.60
Detector

The power consumption of D-Flip Flop and sequence

detector implemented in different techniques is tabulated in
Table 5. Among the two design techniques, the circuit
implemented with OGDI technique consumes less power
than the circuit implemented with CMOS technique. More
than 200nW power is consumed by the CMOS circuit when
compared with OGDI circuit approximately. So, from this
Fig. 11. Transient response of sequence detector implemented with OGDI
technique

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discussion, OGDI technique can be used to implement a low Layout of sequence detector implemented in OGDI logic
power sequential circuit. and CMOS logic is shown in Figure 16 and Figure 17
respectively. The layout area is calculated and tabulated in
C. Area Table 6.
According to Moore’s law [28] the transistors used in a
chip doubles for every 18 months. This statement describes
that the devices become compact as the time passes. So, the
utilization area plays a key roll besides power consumption
of the circuit.
To compare the area used to implement a logic in OGDI
technique with CMOS technique the layout of each circuir is
drawn in cadence. Layout of D-Flip Flop implemented in
OGDI logic and CMOS logic is shown in Figure 14 and
Figure 15 respectively. The layout area is calculated and
tabulated in Table 6.

Fig. 16. Layout of sequence detector implemented in OGDI technique

Fig. 14. Layout of D-Flip Flop implemented using OGDI technique Fig. 17. Layout of sequence detector implemented in CMOS technique

TABLE VI. LAYOUT AREA

Area used to
Area used to implement in
implement in CMOS
CIRCUIT OGDI technique
technique
(μm2)
(μm2)

D FLIP FLOP 40.513225 69.0561

SEQUENCE
331.24 564.300025
DETECTOR

From Table 6, the layout area of circuit implemented

with OGDI technique is less than the layout area of circuit
implemented with CMOS technique.
The power consumed by the D-Flip Flop is only 43% of
the total power consumed by the D-Flip Flop designed with
CMOS technique. Similarly, the power consumed by
sequence detector implemented using OGDI technique is
only 71% of total power consumed by sequence detector
implemented using CMOS technique. Hence an overall
power savings of more than 28% has achieved using OGDI.
The power consumed by D-Flip Flop and Sequence detector
Fig. 15. Layout D-Flip Flop implemented using CMOS technique implemented in OGDI and CMOS is graphically represented
in Figure 18.

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