Tutorial 9
Tutorial 9
Program 1:
1. If register pair BC for Program 1 is loaded with 8000H, calculate the loop delay T L if
the system clock frequency is 3.072 MHz (ignore three T-state difference of the last
cycle).
1 1
Clock Frequency, T= = = 0.3255 μs = 0.0003255 ms
f 3.072
2. For Question 1, calculate the total delay, T D by considering the adjusted loop delay,
TLA.
TD = TO + TLA
= 0.003225 + 255.9826
= 255.9856 ms
3. Load register pair BC with 0000H for Program 1 and calculate the total delay TD if the
system clock period is 325 ns (adjust for the last cycle).
T = 325 ns
= 0.000325 ms
TD = TO + TLA
= 0.00325 + 511.1798
= 511.1830 ms
7. Calculate the COUNT to obtain a 100 µs loop delay and express the value in Hex.
Use any clock frequency of your preference.
TD = 100 μs = 0.1 ms
TD = TO + TLA
0.1 = 0.014 + (0.044 x COUNT - 0.006)
2200H = 04H
2201H = 20H
2202H = 15H
2203H = 13H
2204H = 22H