IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO.

7, JULY 2021 2287

An Impedance Adapting Compensation Scheme for

High Current NMOS LDO Design
Haixiao Cao , Xu Yang , Graduate Student Member, IEEE, Wuhua Li , Member, IEEE,
Yong Ding , Member, IEEE, and Wanyuan Qu , Member, IEEE

Abstract—This brief presents a simple and power-efficient

impedance adapting compensation scheme for high current
NMOS low-dropout regulators (LDOs). By the proposed tech-
nique, the low-frequency node impedance retains to high
value, while the high-frequency impedance is greatly attenu-
ated. Therefore, both high gain and decent transient response is
achieved simultaneously. Besides, the proposed impedance adap-
tion waived the need for a commonly required power-hungry
driver circuit, leading to a more simplified and energy-efficient
design. In addition, the load-tracking technique is applied to
further cancel the effect of load current variations, and helps
achieve decent frequency and transient responses over a wide
load range. Fabricated in a 0.35 µm CMOS process, the chip
regulates an output voltage form 0.8 V to 1.8 V with 6 A current
capacity and 114 mV maximum dropout voltage. The measure-
ment results show an over-/undershoot voltages of 35.4 mV and
−32.2 mV, respectively, for load transitions between 400 mA and
5A. The load and line regulations are 0.7mV/A and 0.12 mV/V,
respectively, and the power supply rejections are −55 dB and
−30 dB at 10 KHz and 1 MHz, respectively.
Index Terms—Low dropout regulator, high current capability,
impedance adapting compensation.
Fig. 1. Typical LDOs adopting: (a) high-gain stages with Miller compensa-
tion, or (b) multiple low-gain stages for wide bandwidth.

I. I NTRODUCTION
For example, tight regulation usually dictates large open-loop
OW-DROPOUT regulators (LDOs) are widely used as
L power supplies for RF, analog, and mixed-signal sub-
blocks because of LDOs’ low noise and high power sup-
gain, which quite often conflicts fast transient responses that
demand a wide loop bandwidth. Besides, high current capac-
ity and low dropout voltage, as the one in this design, both
ply rejection (PSR) features [1]. With the advances in the points to an excessively large power transistor which further
5th -generation communications and big-data computations, complicates the frequency compensations.
devices are becoming more and more power hungry. An LDO Fig. 1 shows two kinds of typical LDO architectures that
is usually required following a DC-DC converter to power up address the aforementioned issues. Fig. 1 (a) employs sev-
noise sensitive sub-blocks. In such applications, LDOs with eral high-gain stages to boost the overall loop-gain [2]. The
high current capacity, tight static regulation, decent transient high-gain stages, however, impose several low frequency
response and high PSR are increasingly important. However, poles which rely on complicated Miller compensation for
achieving such goals at the same time is a non-trivial task. decent stability margins [3], and requires a power-hungry
driver to drive the bulky power transistor. In Fig. 1 (b),
Manuscript received November 14, 2020; revised December 18, 2020; instead, the loop is constituted with multiple low-gain
accepted January 6, 2021. Date of publication January 14, 2021; date of cur-
rent version June 29, 2021. This work was supported in part by the National
stages [4], in which the inner poles are extended beyond
Natural Science Foundation of China under Grant 61804133, and in part by the the gain bandwidth (GBW). The multiple low-gain stages,
Zhejiang Provincial Natural Science Foundation under Grant LZ20F040002. nevertheless, contribute significant offset, noise and suf-
This brief was recommended by Associate Editor S.-W. Sin. (Corresponding fer from process and corner variations. Other designs
author: Wanyuan Qu.) also include current feedback design [5], [6] or multi-loop
Haixiao Cao, Xu Yang, Yong Ding, and Wanyuan Qu are with the
Institute of VLSI Design, School of Microelectronics, Zhejiang University, designs [7] which sacrifice either energy efficiency or circuit
Hangzhou 310058, China (e-mail: [email protected]; [email protected]; complexity.
[email protected]; [email protected]). In this brief, an impedance adapting compensated LDO is
Wuhua Li is with the School of Electrical Engineering, Zhejiang University, presented that features high current capacity, tight static reg-
Hangzhou 310027, China (e-mail: [email protected]).
Color versions of one or more figures in this article are available at
ulation, decent transient responses and design simplicity. By
https://doi.org/10.1109/TCSII.2021.3051634. applying the proposed impedance adapting compensation, the
Digital Object Identifier 10.1109/TCSII.2021.3051634 low-frequency node impedance retains to high value, while
1549-7747 
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2288 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 7, JULY 2021

the high-frequency impedance is greatly attenuated. Therefore,

this brief achieves the advantages of both above mentioned
high-gain and low-gain architectures. In the low-frequency
range, since the node impedance retains their high values,
a simple two-stage design can achieve decent loop gain and
tight regulations. While in the high-frequency range, each
inner node impedance is greatly attenuated to low impedance,
similar as the low-gain architecture. Therefore, the frequency
compensation is greatly simplified. Besides, the proposed com-
pensation waived the need for a commonly-required power-
hungry driver with little cost, leading to simplified design and Fig. 2. Proposed load-tracking and impedance adapting compensated LDO,
improved energy efficiency. Finally, a load-tracking scheme featuring both high-gain stages and wide bandwidth.
is implemented that maintains decent frequency and tran-
sient performances over a wide load range. This brief is
organized as follows. Section II presents the proposed load-
tracking and impedance adapting compensation. Section III
describes the detailed LDO implementation. Section IV
depicts the measurement results and finally a conclusion
is given.

II. S YSTEM A RCHITECTURE

A. Architecture
Fig. 2 shows the simplified small-signal model of the
proposed load-tracking and impedance adapting compensated
LDO. Here, Gmi is the transconductance of the operational Fig. 3. Transfer curves of the overall LDO and each stage.
transconductance amplifier, Ri and Ci are the equivalent out-
put impedance and the lumped parasitic capacitance of the i-th
stage, respectively, where i = 1 or 2. The output stage, which
is a large NMOS power MOSFET in this design, is modeled from 1/R1 C1 to 1/RC C1 , while retaining the first stage DC
as a unity-gain buffer in series with an internal resistance of gain of Gm1 R1 . Impedance adaption at the node V2 comes in
1/Gmn . The load resistance and capacitance are modeled as Ro a similar manner, where the impedance transform is achieved
and Co , respectively. Finally, the series connected RC and CC by a feed-forward resistor RZ . At low frequencies, the volt-
constitute the impedance adaption for the first stage, while the age buffer delivers a near unity gain from the node V2 to VO ,
feed-forward connected RZ serves as the impedance adaption the voltage across RZ is thus almost zero, indicating little cur-
for the second gain stage. rent flow through RZ . Hence, the feed-forward path through
As Fig. 2 indicates, the overall LDO consists of two RZ is essentially “open” and the DC gain of the second stage
high-gain stages and one voltage buffer. Owing to the high- still approximates Gm2 R2 . As frequency goes higher, the gain
gain stages, the loop gain is large and tight static regula- of the voltage buffer starts to degrade from unity as the pole
tion is guaranteed. Besides, since the first high-gain stage at the output node emerges. Therefore, the voltage across RZ
suppresses the offset and noise contributions of the follow- becomes nonzero and current starts flowing through the RZ .
ing stages, traditional offset/noise optimization techniques Since the output capacitor CO is large, during the mid-band
can be easily applied to the first stage design for decent frequency, the node VO becomes effectively “short” to ground
overall performance. The conventional high-gain architecture, so the impedance at node V2 is transformed into R2 ||RZ ≈
however, could possibly suffer from the corresponding low- RZ . Similarly, the low-frequency poles at 1/R2 C2 is trans-
frequency poles. In this design, before the proposed frequency formed into a high-frequency pole at 1/RZ C2 while retaining
compensation is applied, the high-gain stages generate two the second stage DC gain. Finally, load-tracking technique
low-frequency poles, 1/R1 C1 and 1/R2 C2 , at nodes V1 and is applied to the resistors RC and RZ to further desensi-
V2 , respectively. As will be addressed in the following, the tize the load variation effects on the bandwidth and phase
proposed impedance adapting compensation greatly attenu- margins.
ates the node impedance at high-frequency while retaining As can be seen from the above qualitative analysis, the
their high values at low-frequency to obtain decent DC gain. proposed circuit keeps the node impedance at V1 and V2 to
The operation principle of the impedance adapting compen- R1 and R2 respectively, at low frequencies, while transforms
sation is described from both qualitative and quantitative the corresponding impedance to the low value of approxi-
perspectives. mately RC and RZ , respectively, at high frequencies. Therefore,
From the qualitative aspect, the impedance adaption at the the advantages of both conventional high-gain and low-gain
node V1 is achieved by the insertion of a series resistor RC and architectures are obtained.
capacitor CC network, as in [8] for high performance ampli-
fier design. Because of the compensation capacitor CC , the B. Transfer Function
impedance starts to roll off at low frequency. As frequency
goes higher, the impedance is dominated by R1 //RC ≈ RC From the quantitative aspect, the efficacy of the proposed
during the mid-band frequency. Since RC is designed much impedance adapting compensation is also verified. Eq. (1-4)
smaller than R1 , the pole at node V1 is effectively transformed describe the overall transfer function and the detailed pole-zero

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CAO et al.: IMPEDANCE ADAPTING COMPENSATION SCHEME FOR HIGH CURRENT NMOS LDO DESIGN 2289

Fig. 4. Circuit implementation of the proposed LDO. Fig. 7. Simulated phase margin and GBW of the proposed LDO over the
whole load range.

Fig. 8. Chip die photograph.

Fig. 5. The position of pole-zero with different load capacity:(left) with
2.2mA load current (right) with 6A load current.

Fig. 9. Measurement results: (left) Summarized load and line regulation

errors and (right) quiescent current and dropout curves.

Fig. 6. Simulated frequency response of the proposed LDO with different curves clearly indicate that the impedance adaption generates
load. a low impedance region during the mid-band frequency and
pushes the parasitic poles to the high frequency well above the
overall GBW. Because of the low-frequency pole-zero cancel-
placements. lation, the phase margin is mainly determined by the output
gm1 R1 (CC RC s+1) gm2 R2 (CL s+1/RZ +gmn ) pole po and the high frequency poles p1_hf and p2_hf .
T(s) ≈ ·
CC C1 RC R1 s2 +R1 CC s+1 C2 CL R2 s2 +(CL R2 /RZ +CL +C2 gmn R2 )s+gmn
gmn
× (1)
gmn +sCL
III. C IRCUIT I MPLEMENTATION
1 1 1
nodeV1 : p1 ≈ , z1 ≈ , p1_hf ≈ (2) Fig. 4 gives the circuit implementation of the proposed
R 1 CC R C CC R C C1
gmn gmn +1/RZ 1 LDO, which consists of a simple 5-transistor amplifier, an
nodeV2 : p2 ≈ , z2 ≈ ,p2_hf ≈ (3)
(1+R2 /RZ )CL +C2 gmn R2 CL R Z C2 energy efficient current mirror type amplifier, and an NMOS
gmn
nodeVO : po ≈ (4) power transistor. Besides, the blue dashed boxes give the cir-
CL
cuit components for the proposed impedance adaption and
As is seen, the impedance adaption at nodes V1 and the purple path through the capacitor CB helps enhance PSR
V2 , respectively, is manifested as a combination of a low- performance. As can be seen, the load current information is
frequency pole-zero pair and a high-frequency pole. Hence, sensed by two current mirrors, i.e., MN2 -MN and MP1 -MP2 .
the phase lag and the overall bandwidth is mainly limited by The current through MN1 and MN2 are thus load dependent
the resulting high frequency poles, i.e., p1_hf and p2_hf instead and the desired load-tracking resistance RC and RZ is obtained
of the original low-frequency poles. with proper size ratios. Since the load-tracking [9] scheme is
Fig. 3 depicts the simulated transfer curves of the overall achieved by current mirror ratios, the design is corner insensi-
LDO and each stage. The blue (V1 /Vi ) and red (V2 /V1 ) dashed tive and robust. Moreover, since the current through MN2 and

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2290 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 7, JULY 2021

Fig. 12. Measured PSR versus frequency at Vo = 1 V, VIN = 1.3 V and

IO = 1 A.

(V1 /VFB ), the driver stage (V2 /V1 ), and the buffer (VO /V2 )
stages. From the figure, higher load current pushes the out-
put pole po to higher frequencies. The zeros’ locations, which
track the load current tightly, adaptively move to higher
frequencies to compensate this change. Owing to the proposed
current mirror design, both load tracking and loop gain robust-
ness is achieved. Fig. 6 depicts the overall gain and phase
curves for different load conditions. Fig. 7 shows the simu-
Fig. 10. Measurement output voltage VO and output current IO waveforms lated GBW and phase margin plots over the whole load range.
under load transitions between 0.5 A and 5 A with VIN = 1.3 V and VO = 1 V.
The circuit achieves a GBW between 26.5 kHz and 1.48 MHz
and a phase margin between 14.9◦ and 61◦ with load from
1µA to 6A. The simulations verified the robustness of the
proposed design.

C. Power Supply Rejection

Since an NMOS is adopted as a power transistor, it is
beneficial to suppress the supply ripple at the gate of the
NMOS for high PSR design [10]. In this design, both the
amplifier and the driver are designed with supply ripple as
the common mode signal, leading to significant suppression
of supply ripple at the gate of NMOS. In addition, a capaci-
Fig. 11. Measurement:(left)load transitent responses between 0 A and tor CB is inserted that forms a high frequency local feedback
4.6 A with VIN = 1.3 V and VO = 1 V. (right) input line transitions with loop and further improves the PSR performance during the
load current at IO = 0.1 A and Vo = 1 V.
high frequency band.
R3 flows to the load, the proposed impedance adaption con-
sumes no extra current, leading to improved energy efficiency IV. M EASUREMENT R ESULTS
compared with the traditional driving scheme. Lastly, the R2 The proposed low-dropout regulator was implemented and
and R3 limit the maximum power consumption and the R1 and verified using a 0.35 µm CMOS process. Fig. 8 (left) gives the
R4 help current bleeding during no load condition. die photo of the prototype with a chip area of around 6.3 mm2 .
The prototype operates with an input voltage from 0.8 V to
A. NMOS Power Transistor 3.3 V, and generates a regulated output from 0.8 V to 1.8 V
High current LDOs usually dictate large size transistors. with load current capacity up to 6 A.
Here, an NMOS, instead of a PMOS, power transistor is Fig. 9(a) gives the measured load and line regulation perfor-
adopted considering the electron mobility superiority and the mances. Owing to the large loop gain, the regulator achieved
resulting smaller size and lower parasitic capacitance of the a load regulation of 0.7 mV/A from 0 A to 5 A with input of
NMOS. Besides, the proposed impedance adaption through 1.1 V, output of 1V and supply of 2.5 V, and a line regulation
a unity-gain voltage buffer can be easily implemented using of 0.12 mV/V from 0.8 V to 3.3 V with 100 mA load, output
the NMOS source follower stage. The PMOS pass transistor, of 0.8 V and supply of 3.3 V. Fig. 9(b) summarizes the mea-
which also introduces an inverting gain stage, is usually more sured quiescent current and dropout voltage over the entire
suitable for Miller compensation. In order to drive the NMOS load range. The circuit shows a measured quiescent current of
properly, the controller supply VDD is designed larger than the 0.79 mA during zero load condition. Although the quiescent
power input VIN . current increases with the increasing load, the majority of this
current flows to the load through MN2 . Lastly, the maximum
dropout voltage at 6 A is just 114 mV.
B. Load-Tracking Technique Fig. 10 shows the measured load transient responses when
Fig. 5 shows the simulated gain and phase plots of each the load changes between 0.4 A and 5 A with 1.3 V input and
stage under different load conditions, i.e., the amplifier stage 2.5 V supply. From the figure, the output VO shows undershoot

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CAO et al.: IMPEDANCE ADAPTING COMPENSATION SCHEME FOR HIGH CURRENT NMOS LDO DESIGN 2291

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON W ITH THE S TATE - OF - THE -A RT

and overshoot voltages of −32.2 mV and 35.4 mV, respec- deliver up to 6 A load current with 114 mV maximum dropout.
tively. The corresponding 0.1% settling times are 34.8 µsec The measurement results show an over-/undershoot voltages
and 29.3 µsec, respectively. The enlarged figures at the bot- of 32.2 mV and −35.4 mV, respectively, for load transitions
tom shows that, even with the IO changes by around 4.6 A, between 400 mA and 5A. The load and line regulations are
the output voltage VO shows negligible regulation errors. In 0.7mV/A and 0.12 mV/V, respectively, and the power supply
addition, the waveform of the VO shows negligible peaking, rejections are −55 dB and −30 dB at 10 KHz and 1 MHz,
indicating sufficient stability margins and near optimized loop respectively.
parameters.
Fig. 11 (left) shows the measured load transient responses R EFERENCES
when the load changes between 0 A and 4.6 A, the undershoot
and overshoot are both below 55 mV. Fig. 11 (right) is the [1] Y. Lu, Y. Wang, Q. Pan, W.-K. Ki, and C. P. Yue, “A fully-integrated
low-dropout regulator with full-spectrum power supply rejection,” IEEE
measured line transient responses with load current of 100 mA Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 707–716,
and supply of 2.5 V. When the input voltage switches between Mar. 2015.
1.3 V and 2.5 V, the VO shows under-/overshoot voltages of [2] S. Bu, K. N. Leung, Y. Lu, J. Guo, and Y. Zheng, “A fully integrated low-
−4.7 mV and 2.5 mV, respectively. dropout regulator with differentiator-based active zero compensation,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 10, pp. 3578–3591,
The measured PSR at 1A loads is illustrated in Fig. 12. At Oct. 2018.
10 kHz and 1 MHz, the PSR are −55dB and −30dB, respec- [3] W. Qu, S. Singh, Y. Lee, Y.-S. Son, and G.-H. Cho, “Design-oriented
tively. Due to the wide bandwidth and the local feedback, the analysis for miller compensation and its application to multistage ampli-
fier design,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 517–527,
PSR is better than −15dB for the entire frequency range. Feb. 2017.
Table I demonstrates the performance summary of the [4] M. Ho, K. N. Leung, and K.-L. Mak, “A low-power fast-transient 90-
proposed work and the prior state-of-the-art. It can be inferred nm low-dropout regulator with multiple small-gain stages,” IEEE J.
from the table that the proposed work achieved superior Solid-State Circuits, vol. 45, no. 11, pp. 2466–2475, Nov. 2010.
[5] B. Talele, R. Magod, K. Kunz, S. Manandhar, and B. Bakkaloglu,
current capacity, decent static regulation and power supply “A scalable and PCB-friendly daisy-chain approach to parallelize LDO
rejections. regulators with 2.613% current-sharing accuracy using dynamic element
matching for integrated current sensing,” in Proc. IEEE Int. Solid-State
Circuits Conf. (ISSCC), Feb. 2020, pp. 494–496.
[6] H. Fan et al., “An external capacitor-less low-dropout voltage regulator
V. C ONCLUSION using a transconductance amplifier,” IEEE Trans. Circuits Syst. II, Exp.
In this brief, an impedance adapting compensation scheme Briefs, vol. 66, no. 10, pp. 1748–1752, Oct. 2019.
[7] L. Kan, C. Yang, T. Guo, and Y. Zheng, “A multi-loop slew-rate-
for high current NMOS LDO is presented. By the proposed enhanced NMOS LDO handling 1-A-load-current step with fast transient
impedance adaption design, the low-frequency impedance is for 5G applications,” IEEE J. Solid-State Circuits, vol. 55, no. 11,
retained to large value and the high-frequency impedance pp. 3076–3086, Nov. 2020.
is greatly attenuated. Therefore, the circuit achieves high [8] X. Peng, W. Sansen, L. Hou, J. Wang, and W. Wu, “Impedance adapting
compensation for low-power multistage amplifiers,” IEEE J. Solid-State
open-loop gain and decent transient responses. Besides, the Circuits, vol. 46, no. 2, pp. 445–451, Feb. 2011.
impedance adaption attenuates the impedance at the gate of [9] P. Y. Or and K. N. Leung, “A fast-transient low-dropout regulator with
NMOS pass transistor, waived the commonly-required power- load-tracking impedance adjustment and loop-gain boosting technique,”
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 10, pp. 757–761,
hungry driver that is needed to drive the bulky NMOS pass Oct. 2010.
transistor, leading to better energy efficiency. Finally, a load- [10] J. Jiang et al., “A 65-nm CMOS low dropout regulator featuring>60-dB
tracking scheme is implemented that largely cancels the effect PSRR over 10-MHz frequency range and 100-mA load current range,”
of load current variations and achieves decent frequency and IEEE J. Solid-State Circuits, vol. 53, no. 8, pp. 2331–2342, Aug. 2018.
[11] “5 A, low VIN, low noise, CMOS linear regulator,” Data Sheet
transient performances over a wide load range. With a quies- ADP1765, Analog Devices, Inc., Norwood, MA, USA, 2017. [Online].
cent current of 0.79 mA during zero load condition, the LDO Available: www.analog.com

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