Chapter six

Input Output

Computer Organization & Architecture

(SE 1023)
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 INPUT-OUTPUT ORGANIZATION

• Peripheral Devices

• Input-Output Interface

• Asynchronous Data Transfer

• Modes of Transfer

• Priority Interrupt

• Direct Memory Access

• Input-Output Processor

• Serial Communication

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 Peripheral Devices

PERIPHERAL DEVICES

Input Devices Output Devices

• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Impact, Ink Jet,
- Paper Tape Reader Laser, Dot Matrix)
- Bar code reader • Plotter
- Digitizer • Analog
- Optical Mark Reader • Voice
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices

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 Input/Output Interfaces

INPUT/OUTPUT INTERFACES
* Provides a method for transferring information between internal storage
(such as memory and CPU registers) and external I/O devices

* Resolves the differences between the computer and peripheral devices

- Peripherals - Electromechanical Devices

CPU or Memory - Electronic Device

- Data Transfer Rate

Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed

- Unit of Information
Peripherals - Byte
CPU or Memory - Word

- Operating Modes
Peripherals - Autonomous, Asynchronous
CPU or Memory - Synchronous
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 Input/Output Interfaces

I/O BUS AND INTERFACE MODULES

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Each peripheral has an interface module associated with it

Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)
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 Input/Output Interfaces

CONNECTION OF I/O BUS

Connection of I/O Bus to CPU
Op. Device Function Accumulator Computer
code address code register I/O
control
CPU
Sense lines
Data lines
Function code lines
I/O
bus
Device address lines

Connection of I/O Bus to One Interface

Data lines
Peripheral
register

Device Buffer register

Output
address peripheral
I/O device
AD = 1101 Interface and
bus Logic controller

Function code Command

decoder

Sense lines Status

register
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 Input/Output Interfaces

I/O BUS AND MEMORY BUS

Functions of Buses

* MEMORY BUS is for information transfers between CPU and the MM

* I/O BUS is for information transfers between CPU
and I/O devices through their I/O interface

Physical Organizations
* Many computers use a common single bus system
for both memory and I/O interface units
- Use one common bus but separate control lines for each function
- Use one common bus with common control lines for both functions
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces
I/O Bus
- Communication between CPU and all interface units is via a common
I/O Bus
- An interface connected to a peripheral device may have a number of
data registers , a control register, and a status register
- A command is passed to the peripheral by sending
to the appropriate interface register
- Function code and sense lines are not needed (Transfer of data, control,
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and status information is always via the common I/O Bus)
 Input/Output Interfaces

ISOLATED vs MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

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 Input/Output Interfaces

I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

CPU Chip select CS

I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
- Information in each port can be assigned a meaning
depending on the mode of operation of the I/O device
-> Port A = Data; Port B = Command; Port C = Status
- CPU initializes(loads) each port by transferring a byte to the Control Register
-> Allows CPU can define the mode of operation of each port
-> Programmable Port: By changing the bits in the control register, it is
9 possible to change the interface characteristics
 Asynchronous Data Transfer

ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations

Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted

Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur

Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
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 Asynchronous Data Transfer

STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe

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 Asynchronous Data Transfer

HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer

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 Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
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 Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
14 -> Can be detected by means of a timeout mechanism
 Asynchronous Data Transfer

ASYNCHRONOUS SERIAL TRANSFER

Asynchronous serial transfer
Four Different Types of Transfer Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1 1 0 0 0 1 0 1
Start Character bits Stop
bit bits
(1 bit) (at least 1 bit)

A character can be detected by the receiver from the knowledge of 4 rules;

- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected
by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time
The receiver knows in advance the transfer rate of the
15 bits and the number of information bits to expect
 Asynchronous Data Transfer
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER
- UART -
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock

Internal Bus
register control
and clock
Chip select CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether
to generate and check parity, and no. of stop bits
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 Modes of Transfer
 Data transfer to and from peripherals
 1) Programmed I/O :
Read status register

 2) Interrupt-initiated I/O :
 3) Direct Memory Access (DMA) : Check flag bit

 4) I/O Processor (IOP) : =0

Flag

 Example of Programmed I/O : =1

Read data register

Data bus Interface I/O bus

Address bus Data register Transfer data to memory

Data valid I/O

CPU
I/O read device

Status Operation no
I/O write F complete ?
register Data accepted

yes

F = Flag bit Continue

with
program

 Interrupt-initiated I/O
 1) Non-vectored : fixed branch address
 2) Vectored : interrupt source supplies the branch address
17 (interrupt vector)
  Software Considerations
 I/O routines
 software routines for controlling peripherals and for
transfer of data between the processor and peripherals
 I/O routines for standard peripherals are provided by the
manufacturer (Device driver, OS or BIOS)
 I/O routines are usually included within the operating system
 I/O routines are usually available as operating system
procedures ( OS or BIOS function call)
Priority Interrupt
 Priority Interrupt
 Identify the source of the interrupt when several sources will
request service simultaneously
 Determine which condition is to be serviced first when two or
more requests arrive simultaneousl
 1) Software : Polling

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 2) Hardware : Daisy chain, Parallel priority
  Polling
 Identify the highest-priority source by software means
 One common branch address is used for all interrupts
 Program polls the interrupt sources in sequence
 The highest-priority source is tested first
 Polling priority interrupt
 If there are many interrupt sources, the time required to
poll them can exceed the time available to service the I/O
device
 Hardware priority interrupt
 Daisy-Chaining :
Processor data bus
VAD 1 VAD 2 VAD 3

Device 2
Interrupt Request “1” PIDevicePO
1
“1” Device 2
PI PO “0” Device 3
PI PO
To next
Device

Interrupt request
INT
CPU
Interrupt acknowledge
INTACK

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 VAD

INTACK Priority in
PI Enable
Vector address

 One stage of the daisy-chain priority arrangement : Fig. 11-13

INT Priority out
RF PO
Interrupt S Q
request
from device PI RF PO Enable
R
 0 0 0 0
Delay  0 1 0 0
Open-collector  1 0 1 0
inverter Interrupt request to CPU  1 1 1 1

 No interrupt request
 Invalid : interrupt request, but no acknowledge
 No interrupt request : Pass to other device (other device
requested interrupt )
 Interrupt request

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  Parallel Priority
 Priority Encoder arallel Priority :
 Interrupt Enable F/F (IEN) : set or
cleared by the program Interrupt
register
VAD
 Interrupt Status F/F (IST) : set or disk 0
I0
to CPU
y
cleared by the encoder output Printer 1
x
I1
 Priority Encoder Truth Table : Priority
encoder
0
0

 Interrupt Cycle
Reade 2
I2
r 0
0
 At the end of each instruction cycle, Keyboard 3
I3
0

CPU checks IEN and IST 0

 if both IEN and IST equal to “1” IEN IST

Enable

 CPU goes to an Instruction Cycle

 Sequence of microoperation during 0

Instruction Cycle Interrupt

1 to CPU

SP  SP  1 : Decrement stack point

M [ SP ]  PC : Push PC into stack 2 INTACK
from CPU
Branch to ISR
INTACK  1 : Enable INTACK 3
PC  VAD : Transfer VAD to PC
Mask
IEN  0 : Disable further interrupts register

Go to Fetch next instruction

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  Initial Operation of ISR
 1) Clear lower-level mask register bit
 2) Clear interrupt status bit IST
 3) Save contents of processor registers
 4) Set interrupt enable bit IEN
 5) Proceed with service routine
 Final Operation of ISR
 1) Clear interrupt enable bit IEN
 2) Restore contents of processor registers
 3) Clear the bit in the interrupt register belonging to the
source that has been serviced
 4) Set lower-level priority bits in the mask register
 5) Restore return address into PC and set IEN

Direct Memory Access (DMA)

 DMA
 DMA controller takes over the buses to manage the transfer
directly between the I/O device and memory (Bus
Request/Grant )

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 Transfer Modes
 1) Burst transfer : Block
 2) Cycle stealing transfer : Byte
 DMA Controller ( Intel 8237 DMAC ) :
 DMA Initialization Process Address bus
 1) Set Address register :
o memory address for read/write
Data bus Address bus
 2) Set Word count register : Data bus
buffers buffers

o the number of words to transfer

 3) Set transfer mode :

Internal bus
Address register
o read/write, DMA select CS
Register select RS
o burst/cycle stealing, Word count register
Read RD
o I/O to I/O, Write WR
Control
o I/O to Memory, Bus request BR logic Control register

o Memory to Memory Bus grant BG

DMA request
o Memory search Interrupt Interrupt
to I/O device
DMA Acknowledge
o I/O search
23  4) DMA transfer start : next section
 5) EOT (End of Transfer) :
 DMA Transfer (I/O to Memory)
 1) I/O Device sends a DMA request
 2) DMAC activates the BR line
Interrupt
 3) CPU responds with BG line BG CPU
Random access
memory (RAM)
BR
 4) DMAC sends a DMA acknowledge
RD WR Address Data RD WR Address Data
to the I/O device
Read control
 5) I/O device puts a word in the data Write control

bus (for memory write) Data bus

Address bus
 6) DMAC write a data to the address
specified by Address register Address
select
 7) Decrement Word count register
 8) Word count register RD WR Address Data
DMA acknowledge
DS
EOT interrupt RS Direct memory I/O
access (DAM) Peripheral
 9) Word count register BR controller
DMA request
device
BG
DMAC checks the DMA request from Interrupt

I/O device

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Input-Output Processor (IOP)
 IOP :
 Communicate directly with all I/O devices
 Fetch and execute its own instruction
 IOP instructions are specifically designed to facilitate I/O
transfer
 DMAC must be set up entirely by the CPU
 Designed to handle the details of I/O processing
Central Processing
unit (CPU)
Memory bus

Peripheral devices
Memory unit PD PD PD PD

Input-output
processor (IOP) I/O bus

 Command
 Instruction that are read form memory by an IOP
 Distinguish from instructions that are read by the CPU
 Commands are prepared by experienced programmers and
are stored in memory
25  Command word = IOP program
  CPU - IOP Communication :
 Memory units acts as a message center : Information
 each processor leaves information for the other

CPU operations IOP operations

Send instruction
Transfer status word
to test IOP path
to memory location

Message Center
If status OK. , send
start I/O instruction Access memory for
to IOP IOP program

Conduct I/O transfer

CPU continues with
another program
using DMA ; prepare IOP Program
status report
CPU Program

I/O transfer completed

interrupt CPU

Request IOP status

Transfer status word

to memory location

Check status word

for correct transfer

Continue

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 IBM 370 I/O Channel
 Channel = I/O Processor in IBM 370 computer
 Three types of channel
 1) Multiplexer channel : slow-medium speed device, operating with
a number of I/O devices simultaneously
 2) Selector channel : high-speed device, one I/O operation at a time
 3) Block-Multiplexer channel : 1) + 2)
 I/O instruction format :
 Operation code : 8
o Start I/O, Start I/O fast release (less CPU time),
Test I/O, Clear I/O, Halt I/O, Halt device, Operation Channel Device
code address address
Test channel, Store channel ID (a) I/O instruction format

 Channel Status Word :

 Always stored in Address 64 in memory Key Address Status Count

 Key : Protection used to prevent unauthorized (b) Channel status word format

access
Command
Data address Flags Count
 Address : Last channel command word address code

27 used by channel (c) Channel command word format

 Count : 0 (if successful transfer)

 Channel Status Word :
 Always stored in Address 72 in memory
 Command Code
o Write : transfer data from memory to I/O device
o Read : transfer data I/O device to memory
o Read backwards : read magnetic tape with tape moving backward
o Control : rewinding of tape, positioning a disk-access mechanism
(HDD head control)
o Sense : inform the channel status word to the address 64 (Status
Read)
o Transfer in channel : channel jump command (Channel change)
Memory Separate record Tape
 Flags same device
o 100000 : data chaining (same record) 3000 40
40
o 010000 : command chaining (same device)
o 000000 : separate record, and End of I/O 4000
operation 60
+
6000 20
Same record 80

28 same device
 Intel 8089 IOP :

8086  Location of Information :

CPU
Control block Parameter block Task block

Busy CCW TB address

attention
Channel
Interrupt

 
Select

Bus System
Memory unit 8089
Controller bus PB address Memory address
IOP
program
Byte count

Device address
8089 Local bus
IOP
Track and sector

Interface Interface Status

Input device Output device  Channel Command Word (CCW) :

message center
» Start command
 CPU enables channel attention
» Suspend command
 Select one of two channels of 8089 » Resume command
 8089 gets attention of the CPU by » Halt command
sending an interrupt request
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Serial Communication
 Difference between I/O Processor and Data Communication Processor
 I/O Processor
 communicate with peripherals through a common I/O bus (data,
address, control bus)
 Data Communication Processor
 communicate with each terminal through a single pair of wires
 Modem ( = Data Sets, Acoustic Couplers )
 Convert digital signals into audio tones to be transmitted over
telephone lines
 Various modulation schemes are used (FM, AM, PCM)
 Block transfer
 An entire block of characters is transmitted in synchronous
transmission
 Transmitter sends one more character (error check) after the entire
block is sent
 Error Check
 LRC (Longitudinal Redundancy Check) : XOR
 CRC (Cyclic Redundancy Check) : Polynomial
 3 Transmission System
 Simplex : one direction only

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 Half-duplex : both directions but only one direction at a time
 Full-duplex : both directions simultaneously
  Data Link
 The communication lines, modems, and other equipment used
in the transmission of information between two or more
stations
 Data Link Protocol
 1) Character-Oriented Protocol
 2) Bit-Oriented Protocol
 Character-Oriented Protocol
 Message
SYN format
SYN SOHfor Character-Oriented
Header STX Protocol :ETX
Text BCC

 TEXT :
 BCC : Block Check Character (LRC or CRC)
 ASCII Communication Control Character :
 SYN (0010110) : Establishes synchronism
 SOH (0000001) : Start of Header (address or control
information)
 STX (0000010) : Start of Text
31  ETX (0000011) : End of Text
  Data Transparency
 Character-Oriented Protocol
 Character-Oriented Protocol Data Transparency DLE (Data Link Escape)
 DLE
 Inserting a DLE character (bit pattern = 00010000) before each control
character
 Exam) DLE ETX DLE SYN
 DLE character is inefficient and somewhat complicated to implement
 Bit-Oriented Protocol
 Bit-Oriented Protocol
 Transmit a serial bit stream (Frame) of any length without character
boundaries
 Examples of bit-oriented protocol
 1) SDLC (Synchronous Data Link Control) : IBM
 2) HDLC (High-level Data Link Control) : ISO
 3) ADCCP (Advanced Data Communication Control Procedure) :
 Frame format for bit-oriented protocol :
Flag Address Control Information Frame check Flag
01111110 8 bits 8 bits any number of bits 16 bits 01111110

32  Flag : A frame starts and ends with 8-bit flag (01111110)

  Zero Insertion
Prevent a flag from occurring in the middle of a data frame

 Zero (0) is inserted by transmitting station after any
succession of five continuous 1’s
o Example of zero insertion : 01111110 (data) 011111010
 Receiver always removes a 0 that follows a succession of five
1’s
 Control field format :
1 2 3 4 5 6 7 8
Information transfer : 0 NS P/F Nr

Supervisory : 1 0 Code P/F Nr

Unumbered : 1 1 Code P/F Code

NS Send count P/F Poll/final

Nr Receive count Code Binary code

 1) Information Transfer : for ordinary data transmission

 2) Supervisory : for ready, busy condition check, ...
 3) Unnumbered : for initialization of link functions,
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reporting errors, ...
  Control Fields
 Ns : send frame count
 Nr : error free receive frame count
 P/F :
o P = 1 : primary station is finished and ready for the
secondary station to respond
P = 0 : each frame sent to the secondary station from the
primary station
o F = 1 : secondary station sends the last frame
F = 0 : secondary station responds with a number of
frame (when primary station is finished)
 Code : type of command/response

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