Addressing Conventions 6-1

6. Addressing Conventions

6.1 Operand & Module Identifiers, Module List

Operand & module identifiers

Abbrev. indexed Operand Access / Data width Image update

A, B, C, D Standard arithmetical X, B, W, D, R, L
registers
I I[R] Input Image/ in I/O state
X, B, W, D, R, L
Q Q[R] Output Image/ in I/O state
X, B, W, D, R, L
M M[R] Marker X, B, W, D, R, L
SM SM[R] Special marker X, B, W, D, R, L
T T[R] Timer X (status), W (value)
C C[R] Counter X (status), W (value)
D D[R] Data word, 1st current DM X, B, W, D, R, L
DX DX[R] Data word, 1nd current DM
DB DB[R] Data buffer X, B, W, D, R, L
DF DF[R] Data field X, B, W, D, R, L
S S[R] System data range X, B, W, D, R, L
P P[R] Parameter X, B, W, D
FI FIFO max. 512 bytes
TI Time-controlled interrupt
b#www Constant X, B, W, D, R, L
DM DM[R] Data module CM DMnn ; calls 1st DM
BX DMnn ; calls 2nd DM
PM PM[R] Program module
In the above enumeration, R is replaced by X = bit, B = byte, W = word,
the register IDs A, B, C or D. D = double word, R = REAL, L = LREAL

Module list
The PCL manages the following modules:

Name Signal Comment

OM1 Cyclical program processing
OM2 Initialization table Refer to Section "Initialization Table"
OM5 Startup module after Power-ON
OM7 Startup module after STOP/RUN
OM8 Shutdown module
OM18 - OM25 Time-controlled modules Time matrix defined in OM2 or S18 - S32;
lowest module no. = highest priority.
OM42 - OM63 reserved
FC0 – FC1023 Program modules
DM0 - DM1023 Data modules

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6-2 Addressing Conventions

6.2 Assignments in Special Marker Area

The PCL features a special marker area of 16-word size, i.e., SM0
through SM30.

It contains essential system flags and PLC cycle time information.

The unused addresses are reserved for internal system functions, and
may not be changed.

Address Contents Comment

SM14 PLC program and system error messages (hex):
12 Cycle time error
16 Module stack overflow
17 Application stack overflow
18 Application stack underflow
19 DM too short
1A OpCode error
1B Parameter error
1C Parameter not found
1D Address error, access to invalid address, e.g., transfer to
constant or timer or actual counter value.
1E Nonexistent PM called
1F Nonexistent DM called
20 HALT instruction
21 Controller in STOP
22 Hardware fault
23 "C" application error
24 "C" application warning
25 Reentrant module call
26 Assignment list error
27 No PLC program
28 Error in call for peripheral driver
29 Error in peripheral driver installation
2B Nonexistent interrupt OM
2C Instruction not yet integrated
2D Error in direct jump
2E Wrong operand number
2F DM not active
30 Illegal DM size
31 Nonreproducible error
32 Undersized module stack of "C" module
33 Fixation list not found
34 Unable to allocate dynamic DM Instantiation of standard FUNs under
35 Standard FUN parameter error structured text ST
40 Server2 work task error
41 System software error
SM16
SM18

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 Addressing Conventions 6-3

Address Contents Comment

SM20 Bit Read-only for entire bit field
20.0 Trigger pulse upon each startup
20.1 Buffer failure =1
PCL: Fault data backup to static RAM of
PCI-BMxx card
CL550: Low Battery warning /battery fault.
20.2 Flashing marker
20.3 Outputs disabled
20.4 Fixation active
20.5 Data backup error = 1, memory error on PC hard disk
20.6 Cold start flag
20.7 Trigger pulse after Power-ON or loading
SM21 21.0 Windows (WinPanel) no longer responds
21.7 Backup of operands into static RAM not supported
by hardware version.
SM22 Actual cycle time of last complete cycle Read-only
SM24 Maximum measured cycle time
SM26 Minimum measured cycle time
SM28 Error word 1 All errors are read-only
28.0 Addressing error
28.1 Parameter error
28.2 Nonexistent module called
28.3 Module stack error
28.4 Application stack underflow
28.5 Application stack overflow
28.6
28.7
29.0
29.1 OpCode error
29.2
29.3
29.4
29.5 No DM active
29.6 Group fault message/indication For detailed information, refer to SM14.
29.7 Cycle time error
SM30 Auxiliary marker word All markers are read-only
30.0
30.1
30.2
30.3 Always 0
30.4
30.5
30.6
30.7
31.0 Logical greater flag Influenced only by CPL instruction
31.1 Always 1
31.2
31.3
31.4
31.5
31.6 Carry flag, logical less at 1 Influenced only by CPL instruction
31.7 Zero flag, logical equal at 1 Influenced only by CPL instruction

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6-4 Addressing Conventions

6.3 System Area Assignment

The PCL features a system area of 512-word size, i.e., S0 through S511.
It contains the system configuration data for the respective controller.
Essential declarations made in OM2 are copied into the system area, and
can thus be read by the PLC program.

To the extent deemed useful, the system declarations may be changed

upon runtime. This also includes the time intervals of time-controlled
organization modules.

Segments of the system area are used by default function modules which
make data available that is also used by other PLC program parts.
Example: Date and time.

The unassigned addresses in the system area are reserved for internal
purposes, and may not be modified.

Addr. Contents Comment

S0 Initialization flags, e.g., OM2_DW2 Writing in OM5 / OM7 *
S2 System settings, as in OM2_DW3
S4 Error response, as in OM2_DW4 Writing in OM5 / OM7
S6 Maximum cycle time, as in OM2_DW5 Writing in OM5 / OM7
S8 DM to be copied, as in OM2_DW6 Read-only
S10 First remanent timer, as in OM2_DW7 Writing in OM5 / OM7
S12 First remanent counter, as in OM2_DW8 Writing in OM5 / OM7
S14 First remanent marker address, as in OM2_DW9 Writing in OM5 / OM7
S16 First remanent data buffer address, as in OM2_DW10 Writing in OM5 / OM7
S18 OM18 time interval, as in OM2_DW11 Transfer during startup and EP, possibly active timer
S20 OM19 time interval, as in OM2_DW12 must expire before new matrix is activated.
S22 OM20 time interval, as in OM2_DW13
S24 OM21 time interval, as in OM2_DW14
S26 OM22 time interval, as in OM2_DW15
S28 OM23 time interval, as in OM2_DW16
S30 OM24 time interval, as in OM2_DW17
S32 OM25 time interval, as in OM2_DW18

S62 First remanent data field address, as in OM2_DW33

S64 Current processing time, in microseconds Program cycle time: OM1 start through I/O state end.
S66 Current processing time, in milliseconds
S68 Max. processing time, in microseconds Program cycle time: OM1 start through I/O state end.
S70 Max. processing time, in milliseconds
S72 Min. processing time, in microseconds Program cycle time: OM1 start through I/O state end.
S74 Min. processing time, in milliseconds
S76 PCL status: 0 = RUN, 1 = STOP RUN = READY contact closed

S78 Temperature CPU board in degrees centigrade Only CL550

S100 Real-time: minutes / seconds Read-only; entered by operating system

S102 day/ hours 0 = Su, 1 = Mo ... 6 = Sa
S104 year / month
S106 ----- / day of week

S114 Periphery Status See section 6.4, Periphery Status

S116 Remanence status See section 3.5.6 , Startup characteristics CL550

S120
S122 Field bus type 1: PROFIBUS-DP, 2: CAN, 3: INTERBUS S
S124 I-size I/O information
S126 O-size
S128 Hardware / software version

S140 Rack ID Only CL550

S141 ZS ID
S142 reserved
S143 Total status

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 Addressing Conventions 6-5

S144 Entry status module 1

:
S158

S160 Entry status module 2

:
S174

S176 Entry status module 3

:
S190

S192 Entry status module 4

:
S206

S208 Entry status module 5

:
S222

S224 Entry status module 6

:
S238

PROFIBUS-DP Slave diagnostics Bit status:

S240 BTN 15 .............. 0 0 = Slave working OK
: 1 = Slave reports diagnostics (not reachable or error)
S255 BTN 127 ........... 112
Classified diagnosis – SNE: Slave is not reachable Bit status: see section 6.4
S256 BTN 15 .............. 0 0 = Slave working OK
: 1 = Slave reports diagnostics (or error)
S271 BTN 127 ........... 112
Classified diagnosis – SKF: Slave configuration error
S272 BTN 15 .............. 0
:
S287 BTN 127 ........... 112
Classified diagnosis – DPS: Slave reports static diagnosis
S288 BTN 15 .............. 0
:
S303 BTN 127 ........... 112
Classified diagnosis – EXD: Slave reports extended diagnosis
S304 BTN 15 .............. 0
:
S319 BTN 127 ........... 112
Classified diagnosis – SNB: Slave is not ready
S320 BTN 15 .............. 0
:
S335 BTN 127 ........... 112
Classified diagnosis – SF: Slave reports error of another type
S336 BTN 15 .............. 0
:
S351 BTN 127 ........... 112

S510

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6-6 Addressing Conventions

6.4 Periphery Status

The periphery status word S114 provides an overview of the status of the
bus master; it has the following format:

Bit Explanation
0 BMF Bus master fault
1 KSD Classified slave diagnostics
2 SD Slave diagnostics / System diagnostics
3 Reserved
4 Init Init phase: Waiting until periphery is operation-ready, or until
PLC STOP time has elapsed.
5 BmClab Bus master has switched DP bus to CLEAR status: BmClab
= [SNE - SKF - SNB] & Error_Action_Flag = 1. The timing
for the restart after the remedy of BmClab causes can be
controlled by the PLC program.
6 PgStop Programming Unit keeps DP bus in STOP state.
7 Aktiv Active ID
8 SNE One or more slaves are not reachable on the bus.
9 SKF One or more slaves report configuration errors.
10 DPS One or more slaves report static diagnostics.
11 EXD One or more slaves report extended diagnostics.
12 SNB One or more slaves not ready for cyclical data exchange.
13 SF One or more slaves report error of another type.
14 reserved
15 reserved
The bits Init, BmClab, and PgStop are not relevant to the PLC program
because, in the RUN state of the PCL, they always have the value 0..

BMF – Bus Master Fault

This bit indicates that a bus master fault has been detected.

KSD – Classified Slave Diagnostics

The KSD bit in the DP status word represents the OR link of bits 8
through 13.

The individual error types for the KSD are indicated in bits 8 though 13 of
the DP status word.

The KSD messages for each slave are saved in the status words range
from S256 to S351.

The classified slave diagnosis differs the following error cases:

SNE Slave is not reachable

The Slave is not reachable on the bus.
Possible causes:
" Slave is not existent
" Slave is switched off
" Faulty bus installation
" Physical disturbance
SKF Slave Configuration error
The type or the I/O configuration of the slave does not correspond to
the entries in the fieldbus configuration file of the master.
DPS Slave reports static diagnosis
The slave does not deliver valid user data. The application layer of
the slave is not ready to exchange date with the master.

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 Addressing Conventions 6-7

EXD Slave reports extended diagnosis

The extended diagnosis is specific for each slave and is described in
the slave manual. Possible causes:
" Load voltage error (e.g. by emergency stop)
" Short circuit on output
" Overload
" Overtemperature
" Open circuit

SNB Slave is not ready

The slave is yet not ready for data exchange, because it is not
completely set to operation mode by the master (report from the
protocol layer of the slave).
SF Slave reports error of another type

# Every fieldbus system forms its own fieldbus specific diagnosis

according to the fitting message of the KSD. Therefore, according to
the used fieldbus system, not all KSD messages are used.

SD – System Diagnostics as per DP standard

The DP standard differentiates between system diagnostics and slave
diagnostics. System diagnostics comprise a bit field that indicates which
slaves report diagnostics. In addition, there is a detailed diagnostic
routine for individual slaves, the slave diagnostics.

The SD bit in the DP status word represents the OR link of all system
diagnostics bits. Therefore, when SD = HIGH, at least one slave reports
diagnostics.

Active ID
This bit must always have a value of 1. If this is not the case, this
indicates a fatal error in the bus master software.

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6-8 Addressing Conventions

6.5 Data Formats

Bit
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

31 2523 1615 87 3 0
Byte = B
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte
31 25 23 16 15 8 7 0
This addressing mode differentiates between load and transfer
instructions:

Load instruction
The source operand may be either the even-numbered (LOW) byte or the
odd-numbered (HIGH) byte. In the case of the destination operand
(register), the LOW byte is always addressed.

Examples
L B M1,A

M0
HIGH byte LOW byte

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

L B M2,A

M2
HIGH byte LOW byte

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

Transfer instruction
For the source operand, the LOW byte is addressed. The destination
operand (DEST_OPD) may be both the even-numbered (LOW) byte and
the odd-numbered (HIGH) byte.

Examples
T B A,M1

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

M0
HIGH byte LOW byte

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 Addressing Conventions 6-9

T B A,M2

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

M2
HIGH byte LOW byte

Word = W
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte
31 25 23 16 15 8 7 0

In binary word processing, the Load or Transfer instruction always

specifies an even-numbered byte address.

Without exception, for the Load instruction, the specified byte and its
subsequent byte are loaded into the LOW word of the Register (32-bit);
the HIGH word of the Register remains unchanged.

Without exception, for the Transfer instruction, the specified byte and its
subsequent byte are loaded into the LOW word of the Register (32-bit).

Sample LOAD Instruction

L W M2,A

M2
HIGH byte LOW byte

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

Double word = D
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte
31 25 23 16 15 8 7 0

For double word processing when loading or transferring, the base byte
address, which must be divisible by 4, is always specified.

Loading always requires the base byte and the following 3 bytes to be
loaded into the specified Register (32-bit).

Transferring always requires the base byte and the following 3 bytes from
the specified Register (32-bit) to be written to.

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6-10 Addressing Conventions

Examples
L D M4,A

M6 M4
HIGH byte LOW byte HIGH byte LOW byte

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

T D A,M4

Register A
HIGH word LOW word
HIGH byte LOW byte HIGH byte LOW byte

M6 M4
HIGH byte LOW byte HIGH byte LOW byte

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 Addressing Conventions 6-11

6.6 Register Structure

The controller features 4 working registers, which can be addressed in a
bit-wise, byte-wise or word-by-word fashion. In this context, it should be
noted that byte/word addressing always addresses the LOW-byte/word.

Register A, B, C, D
31 24 23 16 15 8 7 0
HIGH byte LOW byte HIGH byte LOW byte
HIGH word LOW word

For operations that exceed the 32-bit format, the registers are combined
to form permanent register pairs.

Register pair A + B
31 24 23 16 15 8 7 0
Word 4 = HIGH word B Word 3 = LOW word B
Word 2 = HIGH word A Word 1 = LOW word A

Register pair C + D
31 24 23 16 15 8 7 0
Word 4 = HIGH word D Word 3 = LOW word D
Word 2 = HIGH word C Word 1 = LOW word C

Status bits
N O C Z
Zero
Carry
Overflow
Negative

# The negative flag always corresponds to the MSB (most significant

bit) of the specified data format. Therefore, for byte operations, this
is Bit 7, for word operations, it is Bit 15, and for double-word
operations, it is bit 31.

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6-12 Addressing Conventions

6.7 Representing Constants

Data Type WinSPS
Explanation Notation PLC Utility Program
UINT (unsigned integer) Binary / Dual, Word 2#00000000_00000000 through 2#11111111_11111111
Decimal, Word 0 through 65535
Double word 0 through 4294967295
Hexadecimal, Word 16#0000 through 16#FFFF
Double word 16#00000000 through 16#FFFFFFFF
INT (signed integer) Decimal, Word -32768 through +32767
Double word -2147483648 through +2147483647
Floating-Point REAL Double word 1.175494351e-38 through 3.402823466e+38
LREAL Quad word 2.2250738585072014e-308 through 1.7976931348623158e+308
Text, STRING(2) ASCII, Word 'AB'
Double word 'ABCD'
Time value TVALUE Time value (+time base r) T#10ms through T#10230s
r: 0 = 10 ms, 1 = 100 ms, T#0.r through T#1023.r
2 = 1 s, 3 = 10 s
TCPIP addresses, ISTRING Double word ‘‘1.2.3.4‘‘

6.8 Program Module Calls

WinSPS
PLC Utility Program
Program module / function call (IEC1131-3) CM PM

6.9 Jump Instructions

WinSPS
PLC Utility Program
Jump instruction JPx label
Jump destination label:

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 Addressing Conventions 6-13

6.10 Bit & Module Addresses

Operand Addresses [decimal]
I 0.0 through 8191.7
Q 0.0 through 8191.7
M 0.0 through 8191.7
SM 0.0 through 31.7
D 0.0 through 511.7
DX 0.0 through 511.7
DB 0.0 through 511.7
DF 0.0 through 32767.7
T-status 0 through 255
C-status 0 through 255
P 0 through 62
DM 0 through 1023
PM 0 through 1023

6.11 Byte, Word & Double Word Addresses

Operand Address [decimal] Comment
I 0 through 8191
Q 0 through 8191
T-actual val. 0 through 256 Timer range 10 ms through 1023 s;
T-status 0 through 256 Matrix: 0.01; 0.1; 1; 10 s
C-actual val. 0 through 256 Counter range: 0 through 8191
C-status 0 through 256
M 0 through 8191
S 0 through 511 Managed values:
- System clock
- Error codes
- Timers for time-controlled process.
- Versions, etc.
P 0 through 62
DF 0 through 32767
DB 0 through 511
D 0 through 511
DX 0 through 511
The even-numbered byte addresses are used as word addresses; for
double word addresses, the byte addresses must be divisible by 4.

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6-14 Addressing Conventions

6.12 Addressing Modes

6.12.1 Absolute addressing operands

Reading
Byte / Word / I, O, M, T, C and P for T/C, actual values apply
Double word / REAL / LREAL K, DF, DB, D, DX, SM, S
Writing
Byte / Word / A, M, P P writing, depending on assigned operand
Double word / REAL / LREAL DF, DB, D, DX, S

6.12.2 Direct addressing of all absolute addressable operands

Register A

Register B Operand adress

Register C

Register D

Example

L B I10,B ; Loads the status of input byte I10 into the

; LOW byte of LOW word in B.
L W 100,C ; Loads the value 100 into the Low word of
; register C

6.12.3 Register-to-register addressing

Register A

Register B

Register C

Register D

Example

L W C,B ; Loads contents of LOW word from register

; C into LOW word of register B.

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 Addressing Conventions 6-15

6.12.4 Register indirect addressing

Register A Index address

Register B

Register C

Register D Peripherals

Example

L D 10,A ; Load index address as byte number Low

; word from A; High word is deleted
L W I[A],D ; Load status of I10 (address in A) into
; Low word of register D

6.12.5 Indirect addressing

Indirect addressing, whether word/byte or bit-oriented, is accomplished
with the use of an operand prefix containing the operand identifier
(operand ID) and operand address. This greatly facilitates the handling
and monitoring of operand addresses.

In addition, all data and program modules can be called indirectly.

The operand prefix is structured as follows:

OPD[R] OPD = Operand ID

[R] = Operand address (index addr.) in register A, B, C, D
# When loading index addresses in one of the registers, double word
D must always be used as a supplement because the registers are
32 bits wide, and the HIGH word must be deleted!

Principle of indirect addressing, using the example of a block transfer via

program loop:

Task to be accomplished: Transfer of 5 input words starting at address

I10 into marker words from address M50 upward.

L D 5,A ; Loads the loop counter

L D 10,B ; Loads the byte base address I10
L D 50,C ; Loads the byte base address M50
further: ; Loop entry label
L W I[B],D ; Reads contents (operand status)
T W D,M[C] ; Writes status that was read
INC D B,2 ; Next E-word (byte address + 2)
INC D C,2 ; Next M-word
DEC D Q,1 ; Loop counter -1
JPN further ; No all words processed as yet

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6-16 Addressing Conventions

Indirect byte addresses

OPD Identifier Byte address Instructions Examples
[decimal] ... [Reg]
I 0 through 8191 L L D 10,A
Q 0 through 8191 L, T L W OPD[A],B
T-actual value 0 through 255 L L D 10,A
T W B,OPD[A]
C-actual value 0 through 255 L
M 0 through 8191 L, T
P 0 through 62 L
S 0 through 511 L, T
SM 0 through 31 L, T
DF 0 through 32767 L, T
DB 0 through 511 L, T
D 0 through 511 L, T
DX 0 through 511 L, T
To address the next byte or next T/C, the address must be incremented
by 1. To address the next word, the address must be incremented by 2.

Indirect bit addresses

OPD Identifier Bit Address Instructions Examples
[decimal] See column 1 for
OPD
I 0 through A, AN, O, ON
65535
Q 0 through A, AN, O, ON, S, R, = L D 10,A
65535 A OPD[A]
M 0 through A, AN, O, ON, S, R, = = OPD[A]
65535
S 0 through 4095 A, AN, O, ON
SM 0 through 255 A, AN, O, ON
D 0 through 4095 A, AN, O, ON, S, R, =
DX 0 through 4095 A, AN, O, ON, S, R, =
DB 0 through 4095 A, AN, O, ON, S, R, =
DF 0 through A, AN, O, ON, S, R, =
262143
T-status 0 through 255 A, AN, O, ON
C-status 0 through 255 A, AN, O, ON
To address the next bit relative to a given starting address, this address
must be incremented by 1.

Indirect module addresses

Operand Module No. Instructions Example
... [Reg]
DM 0 through 1023 CMx L D 10,A
BXx CM DM[A]
PM 0 through 1023 CMx L D 100,A
CMx CM PM[A]
To address the next module relative to a given module number, this
number must be incremented by 1.

In the case of a range violation or if the module is not available, the

controller will enter STOP mode. In both instances, the cause of the error
can be indicated with the use of the Programming Unit (PG).

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 Addressing Conventions 6-17

6.13 Parameter Transfer

When a program module is called up, up to 63 parameter values can be
transferred. The number of transferred parameters is declared with the
module start command. This is followed by the parameters, starting with
P0. In a PM that has been called, these parameters can also be
processed independently: (L D P[R],R).

# Indirect parameter processing is available only with WinSPS v3.0

and WinPanel v2.0 and higher.

The applicable operand attributes are listed below:

" D – Double word (default)
" W – Word
" B – Byte

Bit operands are programmed without the use of attributes.

# Timers and counters are transferred without operand attribute to

facilitate their use as both word( i.e., timer / counter value), and as
bit (i.e., timer / counter status) in the module to be called.

Example of parameter transfer:

CM PM100,7 ; Call PM100 using 7 parameters

P0 D 43 ;Parameter P0: PM no. as constant 43
P1 D 4 ;Parameter P1: DM no. as constant K4
P2 W Q56 ;Parameter P2: Output word at byte addr. O56
P3 I7.3 ;Parameter P3: Input bit I7.3
P4 T2 ;Parameter P4: Timer T2
P5 C13 ;Parameter P5: Counter C13
P6 O10.0 ;Parameter P6: Output bit O10.0

Utilization of parameters in called-up module PM100:

L D P1,A ;Load data module no. 4

CM DM[A] ;Open DM4
BX -DB5

L D P0,A ;Load PM no. 43

CM PB[A],2 ;Use 2 parameters to call PM43
P0 W D2 ;Parameter P0: D2 of active 1st DM (DM4)
P1 W DX6 ;Parameter P1: DX6 of active 2nd DM (DM5)

L W P2,A ;Load output word O56

L W P4,B ;Load timer value from T2 to B

A P3 ;I7.3
A P4 ;Status of T2
A P5 ;Status of C13
= P6 ;O10.0

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6-18 Addressing Conventions

6.14 Addressing Limits

Direct addressing
In direct addressing, addressing limits are determined by the operand
attribute.

Byte Address as desired

Word Address even-numbered
Double word Address divisible by 4
Real Address divisible by 4
Lreal Address divisible by 8
Example:

Operand B W D R L
M0 x x x x x
M1 x
M2 x x
M3 x
M4 x x x x
M5 x
M6 x x
M7 x
M8 x x x x x

Indirect addressing
Indirect addressing is subject to the same addressing limits as direct
addressing.

# It should be noted however, that address corrections are made to

the next lower addressing limit. This correction is contingent on the
operand attribute.

Example:

L D 0,A ;Address byte 0

L D M[A],B ;Reads the status of M0+M1+M2+M3
INC D A,1 ;Address byte 1
L D M[A],B ;Reads the status of M0+M1+M2+M3
INC D A,1 ;Address byte 2
L D M[A],B ;Reads the status of M0+M1+M2+M3
INC D A,1 ;Address byte 3
L D M[A],B ;Reads the status of M0+M1+M2+M3
INC D A,1 ;Address byte 4
L D M[A],B ;Reads the status of M4+M5+M6+M7

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 Addressing Conventions 6-19

Parameterized addressing
Parameterized addressing is subject to the same addressing limits as
direct addressing.

# It should be noted however, that address corrections are made to

the next lower addressing limit. This correction is contingent on the
operand attribute.

Example:

Parameter definition Parameter query Reads the following:

P0 M1 L B P0,A M1
P1 M3 L W P1,A M2 and M3
P2 M5 L D P2,A M4 through M7
P3 M7 L D P3,A M4 through M7
P1 M11 L L P1,A M8 through M15

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6-20 Addressing Conventions

1070 072 189 - 108 (02.09) GB

 Instruction List 7-1

7. Instruction List

7.1 Structure of Controller Instructions

Controller Instruction Comment
Operation part Operand attribute Source OPD Destination
OPD
OPP OPA SRC , DEST ; Description

Examples
U I0.0
U W -Name ,A
L B O0 ,B
T D C , M12
MUL W 1234 ,D

7.2 Flags
The flags are influenced by the following instruction groups:

" Bit instructions " Shift

" Compare " Rotate
" Convert " Add
" Swap " Subtract
" Increment " Multiply
" Decrement " Divide

They can be used not only in program processing instructions (jumps,

module instruction) but also in logical links (special marker queries).

Flags PG display indication JP... Flag query Explanation

CM...
CY=1 C ...C U CY Carry
CY=0 ...CN AN CY Carry Not
O=1 O ...O U O Overflow
O=0 ...ON AN O Overflow Not
Z=1 Z ...Z U Z Zero
Z=0 ...N AN Z Zero Not
N=1 N ...M U N Negative / minus
N=0 ...P AN N Positive
AG=1 ...AG No flag linking Arithmetical greater
AG=0 N-Z ...MZ U Z Minus / Zero
O N
AN O
ON N
U O
LG=1 ...LG AN Z Logical greater
AN CY
LG=0 C-Z ...CZ U Z Carry / Zero
O CY

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7-2 Instruction List

7.3 Key to Abbreviations

OPP Operation
OPA Operand attribute
B Byte
W Word
D Double word
R REAL
L LREAL
SRC Source operand
DEST Destination operand
E Input
A Output
M Marker
K Constant
SM Special marker
T Timer
Z Counter
D Data word, within data modules
DM Data buffer
DF Data field
FI FIFO
S System area
DM Data module
DX 2. 2nd active data module
PM Program module
SYM Symbolic
R.bit Register bit w/ R = A, B, C, D, and bit = 0 thru 31
OPD[R] Register indirect w/ operand prefix
TI Time interrupt, time-controlled processing
RG Program branch
A Operation permitted at RG beginning
E Operation concluding RG
Addr. Addressing mode
D Direct
R Register A, B, C, or D
[R] Register indirect w/ operand prefix
Flag
V Link result RES
CY Carry
O Overflow
Z Zero
N Negative

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 Instruction List 7-3

7.4 Bit instructions

Bit instructions modify the flags CY, Z, O, and N.

Exception: Flags themselves are not changed by a binary flag query.

Links are interpreted in accordance with the Boolean AND before OR

logic principle. Parenthesized instructions are used to form logical
intermediate results.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
U I/O/M/SM " " " " " " U E0.0 AND link, query status 1
T/C/SYM " " " " " " U T0
R.bit " " " " " " U A.0
OPD[R] " " " " " " U M[A]
P/ " " " " " " U P0
S/D/DX/DF/DP " " " " " " " U D0.0
CY/Z/O/N " U CY
"
AN I/O/M/SM " " " " " " AN A0.0 AND link, query status 0
T/C/SYM " " " " " " AN Z0
R.bit " " " " " " AN B0.0
OPD[R] " " " " " " AN M[B]
P " " " " " " AN P1
S/D/DX/DF/DP " " " " " " " AN D0.0
CY/Z/O/N " AN CY
"
O I/O/M/SM " " " " " " O M0.0 OR link, query status 1
T/C/SYM " " " " " " O -SYMBOL
R.bit " " " " " " O C0.0
OPD[R] " " " " " " O MD[C]
P " " " " " " O P10
S/D/DX/DF/DP " " " " " " " O D0.0
CY/Z/O/N " O CY
"
ON I/O/M/SM " " " " " " ON SM31.7 OR link, query status 0
T/C/SYM " " " " " " ON -Name
R.bit " " " " " " ON D.0
OPD[R] " " " " " " ON M[D]
P " " " " " " ON P62
S/D/DX/DF/DP " " " " " " " ON D0.0
CY/Z/O/N " ON CY
"
= A/M/SYM " " " " " " = A0.0 Assign result when RES = 1
S/D/DX/DF/DP " " " " " " = D0.0
P " " " " " " = P0
OPD[R] " " " " " " = M[A]
R.bit " " " " " " = A.0
S A/M/SYM " " " " " " S M0.0 Set bit HIGH when RES = 1
S/D/DX/DF/DP " " " " " " S D0.0
P " " " " " " S P1
OPD[R] " " " " " " S M[B]
R.bit " " " " " " S B.0
R A/M/SYM " " " " " " R -SYMBOL Set bit LOW when RES = 1
S/D/DX/DF/DP " " " " " " R D0.0
P " " " " " " R P62
OPD[R] " " " " " " R M[C]
R.bit " " " " " " R C0.0
P R.bit " " " " " P A.0 Check register bit for status = 1, when
met: C = 1
PN R.bit " " " " " PN A.15 Check register bit for status = 0, when
met: C = 1
( " " " " ( AND opening bracket
) " " " " ) Closing bracket
O( " " " " O( OR opening bracket
)N " " " " )N Negation of bracket contents

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7-4 Instruction List

7.5 Timer Programming

The PCL provides 256 timer circuits, T0 through T255.

These can be utilized in the following modes:

" SP Pulse
" SPE Start pulse extended
" SR Start time as raising delay
" SF Start time as falling delay
" SRE Start time as raising delay extended

Starting the nonremanent starting timers SP, SPE, SR and SRE requires
a positive transition of the timer start condition. However, they are started
also if the start condition, at the time of first addressing (1st PLC cycle)
equals 1.

In the case of remanent timers, the flank marker is retained, i.e., whether
a 1 will start the timer at the time of first addressing (1st PLC cycle) after
startup or restart, depends on the start condition prior to STOP or Power-
OFF.

In the case of the start time as falling delay, a 0 will not start the timer
during the initial processing. Predefining the timer start condition with 1 is
possible as early as in the startup OM, provided that the information
about remanence characteristic (see Section on Remanence
Characteristics) is considered.

The timers are decremented in the I/O state. A timeout is thus recognized
only in the I/O state, and not during the program cycle!

Because a timer is decremented in the I/O state by a multiple of the

declared time matrix, it is useful to select a time matrix that is a small as
possible.

The timer starts immediately upon a positive transition of the timer start
condition.

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 Instruction List 7-5

7.5.1 Timer instructions

Timer starts are activated only when the RES signal undergoes a
transition from 0*1. In advance of the timer start, the time value is loaded
into the register being used. Reset and stop functions of timers are
always RES signal-dependent. The timer status for logical links is
instruction-dependent, and may be taken from the timer diagrams.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SP R , Tn " " SP A,T0 Pulse
, SYM " SP A,-Symbol
, T[R] " SP A,T[B]
, P " SP A,P0
SPE R , Tn " " SPE A,T0 Start pulse extended
, SYM " SPE A,-Symbol
, T[R] " SPE A,T[B]
, P " SPE A,P0
SR R , Tn " " SR A,T0 Start time as raising delay
, SYM " SR A,-Symbol
, T[R] " SR A,T[B]
, P " SR A,P0
SF R , Tn " " SF A,T0 Start time as falling delay
, SYM " SF A,-Symbol
, T[R] " SF A,T[B]
, P " SF A,P0
SRE R , Tn " " SRE A,T0 Start time as raising delay extended
, SYM " SRE A,-Symbol
, T[R] " SRE A,T[B]
, P " SRE A,P0
RT Tn " " RT T0 Set timer LOW when RES = 1
SYM " RT -Symbol
T[R] " RT T[B]
P " RT P0
TH Tn " " TH T0 Timer stop when RES = 1,
SYM " TH -Symbol
Timer continues when RES = 0
T[R] " TH T[B]
P " TH P0

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7-6 Instruction List

7.5.2 Time format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x x x x R R W W W W W W W W W W
Time matrix Timer 1 - 1023
value:
0 0 0: 10 ms :
0 1 1: 100 ms Program entry of time constant:
1 0 2: 1 s w.r with time value w = 1 -1023
1 1 3: 10 s and time matrix r = 0 - 3

Example:

Timer T100 shall be started at 15 sec:

L W T#15s,A ;15s declaration in 1-sec time matrix
A B -start
SPE A,T100

Same function with higher matrix resolution, i.e., higher accuracy:

L W T#15000ms,A ;15s declaration in 1oo-ms time matrix
A B -start
SPE A,T100

Timer start with the assistance of the PG time matrix:

L W T#15.2,A ;15s declaration in 1-ms time matrix of PG
A B -start
SPE A,T100

Same function with higher matrix resolution, i.e., higher accuracy:

L W T#150.1,A ;15s declaration in 1oo-ms time matrix of PG
A B -start
SPE A,T100

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 Instruction List 7-7

7.5.3 Timer diagrams

SP – Start time as pulse

Start condition

Reset condition

Timer status + t ( +<t(

SPE – Start pulse extended

Start condition

Reset condition

Timer status + t ( + t ( + t ( +<t(

SR – Start time as raising delay

Start condition

Reset condition

Timer status + t ( +<t(

SF – Start time as falling delay

Start condition

Reset condition

Timer status + t ( + t (

SRE – Start time as raising delay extended

Start condition

Reset condition

Timer status + t ( + t ( + t ( +<t(

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7-8 Instruction List

7.6 Counter Instructions

The setting of counters and counting up and down occurs only at the
RES signal transition from 0 ( 1.

In advance of the reset, the required counter content is loaded into the
register being used.

Counter reset functions are always RES signal-dependent.

The counter status for logical links depends on the counter content. For
counter contents > 0, the status is = 1 (HIGH); counter content = 0 will
have status = 0 (LOW).

Counting range: 0 through 8191.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SC R , Zn " " SC A,Z0 Set counter HIGH
, SYM " SC A,-Symbol
, Z[R] " SC A,Z[B]
, P " SC A,P0
CU Zn " " CU Z0 Count up
SYM " CU -Symbol
Z[R] " CU Z[B]
P " CU P0
CD Zn " " CD Z0 Count down
SYM " CD -Symbol
Z[R] " CD Z[B]
P " CD P0
RC Zn " " RC Z0 Set counter LOW when RES = 1
SYM " RC -Symbol
Z[R] " RC Z[B]
P " RC P0

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 Instruction List 7-9

7.7 Digital Links

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
U B I/O/M/SM , R " 0 0 " " U B E0,A Digital AND link between source
W T/C/K/SYM " 0 0 " " U W T0,B
and destination. The result is written
D S/DF/DP " 0 0 " " U B S0,C
D/DX " 0 0 " " U W D0,D to destination.
R " 0 0 " " U W A,B
OPD[R] " 0 0 " " U B M[B],C
P " 0 0 U W P0,D
" "
AN B I/O/M/SM , R " 0 0 " " AN B E127,A Digital AND NOT link between
W T/C/K/SYM " 0 0 " " AN W T127,B
source and destination. The result is
D S/DF/DP " 0 0 " " AN B S511,C
D/DX " 0 0 " " AN W D510,D written to destination.
R " 0 0 " " AN W A,B
OPD[R] " 0 0 " " AN B M[B],C
P " 0 0 AN W P62,D
" "
O B I/O/M/SM , R " 0 0 " " O B E0,A Digital OR link between source and
W T/C/K/SYM " 0 0 " " O W T0,B
destination. The result is written to
D S/DF/DP " 0 0 " " O B S0,C
D/DX " 0 0 " " O W D0,D destination.
R " 0 0 " " O W A,B
OPD[R] " 0 0 " " O B M[B],C
P " 0 0 O W P0,D
" "
ON B I/O/M/SM , R " 0 0 " " ON B E127,A Digital OR NOT link between source
W T/C/K/SYM " 0 0 " " ON W T127,B
and destination. The result is written
D S/DF/DP " 0 0 " " ON B S511,C
D/DX " 0 0 " " ON W D510,D to destination.
R " 0 0 " " ON W A,B
OPD[R] " 0 0 " " ON B M[B],C
P " 0 0 ON W P62,D
" "
XO B I/O/M/SM , R " 0 0 " " XO B E0,A EXCLUSIVE OR link between
W T/C/K/SYM " 0 0 " " XO W T0,B
source and destination. The result is
D S/DF/DP " 0 0 " " XO B S0,C
D/DX " 0 0 " " XO W D0,D written to destination.
R " 0 0 " " XO W A,B
OPD[R] " 0 0 " " XO B M[B],C
P " 0 0 XO W P0,D
" "
XON B I/O/M/SM , R " 0 0 " " XON B E127,A EXCLUSIVE OR NOT link between
W T/C/K/SYM " 0 0 " " XON W T127,B
source and destination. The result is
D S/DP/DF/DP " 0 0 " " XON B S511,C
D/DX " 0 0 " " XON W D510,D written to destination.
R " 0 0 " " XON W A,B
OPD[R] " 0 0 " " XON B M[B],C
P " 0 0 XON W P62,D
" "

7.8 SWAP Instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SWAP W R " SWAP W A Change in Register High-Byte . Low-Byte
D SWAP D A High-Wort . Low-Wort

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7-10 Instruction List

7.9 COMPARE Instruction

The universally applicable CPLA (Compare Logical and Arithmetical)
instruction is available for Compare operations. This facilitates both
logical and arithmetical compare operations.

Also, for reasons of compatibility, the purely logical CPL instruction was
implemented; it is used to map binary result queries also in special
markers.

The logical compare operation regards the bytes, words, or double words
to be compared as unsigned integers, i.e., as "unsigned 8", "unsigned
16", or "unsigned 32".

The arithmetical compare operation regards the bytes, words, or double

words to be compared as signed integers, i.e., as "signed 8", "signed 16",
or "signed 32".

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z AG LG
CPLA B I/O/M/SM , R " " " " " " " CPLA W E62,A Arithmetical Compare function.
W T/C/K/SYM " " " " " " " CPLA B 255,B
The result may be used for logical
D S/DF " " " " " " " CPLA W DF510,C
D/DX/DP " " " " " " " CPLA B D511,D and arithmetical purposes.
R " " " " " " " CPLA B B,C
OPD[R] " " " " " " " CPLA W M[C],D
P " CPLA B P62,A
" " " " " "
CPL B I/O/M/SM , R " " " " " " " CPL W E62,A Logical Compare operation. The
W T/C/K/SYM " " " " " " " CPL B 255,B
result may be used for logical
D S/DF " " " " " " " CPL W DF510,C
D/DX/DP " " " " " " " CPL B D511,D purposes only, i.e., the values will
R " " " " " " " CPL B B,C be treated as positive integers.
OPD[R] " " " " " " " CPL W M[C],D
P " CPL B P62,A
" " " " " "

CPLA compare values:

" Logical: positive, integer
" Arithmetical: two's complement, signed integer
As a result of a compare operation, the flags or special markers provide
information about the result.

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 Instruction List 7-11

Examples:

Compare DEST A with CPL B,A CPLA B,A

SRC B Logical Logical Arithmetic
Jump Flag query Jump Flag query Jump
instruction instruction instruction
Equal A=B JPZ U SM31.7 JPZ U Z JPZ
Unequal A/B JPN AN SM31.7 JPN AN Z JPN
Less than A<B JPCY U SM31.6 JPCY U CY JPM
Less than / A'B JPCZ AN SM31.0 JPCZ U Z JPMZ
O CY
equal
Greater than A>B JPLG U SM31.0 JPLG AN CY JPAG
AN Z
Greater than/ A)B JPCN AN SM31.6 JPCN AN CY SPP
equal

# When using the CPLA instruction, the evaluation of the compare

results must always be programmed immediately following the
compare instruction itself. The user is advised to bear in mind that
with the exception of flag queries, binary operations will cause a
modification of the flags. Therefore, a compare result can be used
only in a link. Following this, another CPLA instruction must again
be programmed.

# The special markers that are influenced only by the CPL instruction
will remain unaffected until the next CPL instruction.

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7-12 Instruction List

7.10 LOAD Instructions

Load instructions are used to write statuses or values from operands into
registers. Signal statuses of inputs / outputs are loaded from the
periphery image.

In the event that the status of inputs is to be loaded directly from the dual-
port RAM of the bus master during the program cycle, this status must be
loaded into the image with the use of the load instruction LD before the
load instruction L is issued.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
L B I/O/M/SM , R " L W E0,A Load contents of SRC into DEST.
W T/C/K/SYM " L B 0,B
D DF/DP " L W DF0,C
D/DX " L B D0,D
R " L B B,C
OPD[R] " L W M[C],D
P " L B P0,A
P[R] " L D P[A],B
OM, FC, DM " L DB10,A Load DB10 module size
LD E , K " LD E0,20 Load 20 bytes* of input statuses into image, starting with I0.
E[R] , [R] "
LD E0,[B] Load I-statuses into image, starting with I0; byte* count in B.

LD E[A],[B] Load I statuses into image (start address in A), byte* count in
B.

* maximum byte count = 256

Example of direct loading:
LD D I12,4 ; Load 4 bytes from bus master into I-image,
; starting with I12.
L D I12,A ; Load statuses I12 thru I15 into register A

# When using the "indirect" load instruction parameter (L D

P[R],R), the WinSPS is unable to perform a syntax check because
it cannot foresee which operand parameter will actually be
addressed by the parameter. The controller may enter STOP mode.
The user is therefore advised to ensure the required syntax for this
instruction.

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 Instruction List 7-13

7.11 TRANSFER Instructions

Transfer instructions (T) are used to write statuses or values from
registers into operands. Signal statuses from outputs are written into the
periphery image. During the I/O state this image is then transferred to the
outputs.

In the event that the statuses of outputs are to be sent directly to the
dual-port RAM of the bus master during the program cycle, the TD
transfer instruction will be used.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
T B R , A/M/SYM " T W A,M0 Transfer contents of SRC to DEST.
W , S/DF " T B B,DF0
D , D/DX/DP " T W C,D0
, R " T W A,B
, OPD[R] " T B B,M[C]
, P " T W D,P0
TD A , K " TD O0,20 Send 20 bytes* of output statuses from image to
A[R] , [R] " outputs, starting with O0.
TD O0,[B] Send O-statuses from image to outputs, starting
with O0. Byte count* in B.

TD A[A],[B] Send O-statuses from image to outputs (start

address in A). Byte count* in B.

* max. byte count = 256

Example of direct transfer:

L D 16#1234FFFF,A ; Load hex constant into register A,
T D A,A12 ; and write into O-image.
TD D A12,4 ; Transfer 4 bytes for O12-O15 into ,
bus master.

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7-14 Instruction List

7.12 CONVERT Instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
BID B R " 0 " 0 " BID W A Binary ( BCD (decimal), result >
W BID B B
D 9999 sets the overflow bit.
DEB B R " 0 " 0 " DEB W C BCD (decimal) ( Binary, wrong BCD
W DEB B D
D coding sets the overflow bit.
CMP B R " " " " " CMP W A Converts register contents to the two's
W CMP B B
D
complement.
N B R " 0 " 0 " N W C Negates register contents, one's
W N B D
D
complement.

Positive and negative numbers are differentiated by the status of the

MSB.

OPA Positive Range Negative Range

Double word Bit 31 = 0 0 through +2,147,483,647 Bit 31 = 1 0 through -
2,147,483,648
Word Bit 15 = 0 0 through +32,767 Bit 15 = 1 0 thru -32.768
Byte Bit 7 = 0 0 through +127 Bit 7 = 1 0 through -128
Example of the representation of positive and negative numbers

By way of illustration, a 4-bit number (nibble) is used here; the nibble data
format ("tetrade") is not supported by the controller.

0 1 1 0 positive number 6
1 0 0 1 Negation, one's complement
+ 1
1 0 1 0 Two's complement = negative number 6

1111 0000
-1 0
1110 0001
-2 +1
1101 0010
-3 +2
1100 0011
-4 +3
1011 negativ positive 0100
-5 e +4
1010 0101
-6 +5
1001 0110
-7 +6
1000 0111
-8 +7

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 Instruction List 7-15

7.13 INCREMENT & DECREMENT Instructions

Increment / decrement the contents of source operand SRC:
" by the number n, where n = 1 through 127
" when n = 0, and when [C], by the number stored in C, max. 127.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
INC B R , n " " " " " INC B A,5 Increment the contents of the SRC
W , 0 " " " " " INC W A,0
D , [C] " " " " " INC W B,[C]
DEC B R , n " " " " " DEC B A,5 Increment the contents of the SRC
W , 0 " " " " " DEC W A,0
D , [C] " " " " " DEC W B,[C]

7.14 STACK Instructions

The available stack size comprises 256 double words. In the event of
underflow, special marker S28.4 in the system area goes HIGH; overflow
sets the S28.5 to HIGH. The I/O state resets/deletes the entire
application stack.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
PUSH D R " PUSH D A Saves the register contents to application
stack, and lowers the stack address.
POP D R " POP D B Raises the application stack address, and
reads the saved contents from the stack.

7.15 No Operation Instructions & CARRY Manipulations

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
NOP NOP No operation
SCY " SCY Unconditionally set CARRY flag HIGH.
RCY " RCY Unconditionally set CARRY flag LOW.

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7-16 Instruction List

7.16 SHIFT Instructions

Shift the contents of source operand SRC:
" by the number n
" when n=0, and when [C], by the number stored in C
when OPA = D, n = 1 through 31
when OPA = W, n = 1 through 15
when OPA = B, n = 1 through 7

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SLR B R , n " " " " " SLR W A,7 SHIFT logical RIGHT
W , 0 " " " " " SLR B B,[C]
D , [C] " " " " "
SLL B R , n " " " " " SLL W A,7 SHIFT logical LEFT
W , 0 " " " " " SLL B B,[C]
D , [C] " " " " "
SAR B R , n " " " " " SAR W A,7 SHIFT arithmetical RIGHT
W , 0 " " " " " SAR B B,[C]
D , [C] " " " " "

Logical SHIFT
MSB LSB CY

SLR B,n
o( o " ( " ,( o

MSB LSB CY

SLL B,n
" + " o +0 o
0 *
,(

Arithmetical SHIFT

All bits being vacated are filled up with the contents of the MSB.
MSB LSB CY

SAR B,n
" ( " ( " ,( o
In the case of shift operations exceeding one space (n > 0), the overflow
bit is set HIGH after a "1" was shifted through CY.

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 Instruction List 7-17

7.17 ROTATE Instructions

Shift the contents of source operand SRC:
" by the number n
" when n=0, and when [C], by the number stored in C
when OPA = D, n = 1 through 31
when OPA = W, n = 1 through 15
when OPA = B, n = 1 through 7

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
ROR B R , n " " " " " ROR B A,7 Rotate RIGHT
W , 0 " " " " " ROR W A,0
D , [C] " " " " " ROR W B,[C]
ROL B R , n " " " " " ROL B A,7 Rotate LEFT
W , 0 " " " " " ROL W A,0
D , [C] " " " " " ROL W B,[C]
RCR B R , n " " " " " RCR B A,7 Rotate RIGHT THROUGH CARRY
W , 0 " " " " " RCR W A,0
D , [C] " " " " " RCR W B,[C]
RCL B R , n " " " " " RCL B A,7 Rotate LEFT THROUGH CARRY
W , 0 " " " " " RCL W A,0
D , [C] " " " " " RCL W B,[C]

Rotate RIGHT
MSB LSB CY

ROR B,n o " ( " o

* +--- 0 ,( *
Rotate LEFT
MSB LSB CY

ROL B,n
" + " 1 o
0 ( * ,( *
Rotate RIGHT THROUGH CARRY
MSB LSB CY

RCR B,n
1 " ( " ( 1
* +--- 0
Rotate LEFT THROUGH CARRY
MSB LSB CY

RCL B,n
" + " 1 + 1
0 ( *

In the case of a rotation by more than one space, the following applies:
" The overflow bit goes HIGH when a 1 has been rotated through CY.
" The negative bit goes HIGH when the MSB contains a 1.
MSB: Bit 7 when OPA = B
MSB: Bit 15 when OPA = W
MSB: Bit 31 when OPA = D

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7-18 Instruction List

7.18 Fixed Point Arithmetic

7.18.1 ADD instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
ADD B I/O/M/SM , R " " " " " ADD W E0,A Fixed-point addition of signed integers:
W T/C/K/SYM " " " " " ADD B 0,B
SRC + DEST = DEST
D S/DF/DP " " " " " ADD W DP0,C
D/DX " " " " " ADD B D0,D
R " " " " " ADD B B,C
OPD[R] " " " " " ADD W M[C],D
P " ADD B P0,A
" " " "
ADC B I/O/M/SM , R " " " " " ADC W E0,A Fixed-point addition of signed integers
W T/C/K/SYM " " " " " ADC B 0,B
allowing for CY.
D S/DF/DP " " " " " ADC W DP0,C
D/DX " " " " " ADC B D0,D SRC + DEST + CY = DEST.
R " " " " " ADC B B,C
OPD[R] " " " " " ADC W M[C],D
P " ADC B P0,A
" " " "

Byte, word, and double-word addition

MSB:
" Bit 7 when OPA = B
" Bit 15 when OPA = W
" Bit 31 when OPA = D
0
ADD OPA B, A sg A
+
sg B
=
sg A

ADC OPA C, A sg A
+
sg C
+
CY
=
sg A

Quad-word addition: Value 1 + value 2

Value 1: LOW DW in B, HIGH DW in A
Value 2: LOW DW in D, HIGH DW in C
LOW DW 31 0
ADD D D, B B
+
D
=
B

HIGH DW
ADC D C, A sg A
+
sg C
+
Cy
=
sg A

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 Instruction List 7-19

7.18.2 SUBTRACT instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SUB B I/O/M/SM , R " " " " " SUB W E0,A Fixed-point subtraction of signed integers:
W T/C/K/SYM " " " " " SUB B 0,B
DEST - SRC = DEST.
D S/DP/DF/DP " " " " " SUB W DP0,C
D/DX " " " " " SUB B D0,D
R " " " " " SUB B B,C
OPD[R] " " " " " SUB W M[C],D
P " SUB B P0,A
" " " "
SBB B I/O/M/SM , R " " " " " SBB W E0,A Fixed-point subtraction of signed integers
W T/C/K/SYM " " " " " SBB B 0,B
allowing for negative CY.
D S/DP/DF/DP " " " " " SBB W DP0,C
D/DX " " " " " SBB B D0,D DEST - SRC - CY = DEST.
R " " " " " SBB B B,C
OPD[R] " " " " " SBB W M[C],D
P " SBB B P0,A
" " " "

Byte, word, double-word subtraction

MSB:
" Bit 7 when OPA = B
" Bit 15 when OPA = W
" Bit 31 when OPA = D
0
SUB OPA B , A sg A
-
sg B
=
sg A

SBB OPA C , A sg A
-
sg C
-
CY
=
sg A

Quad-word subtraction: Value 1 – value 2

Value 1: LOW DW in B, HIGH DW in A
Value 2: LOW DW in D, HIGH DW in C
LOW DW 31 0
SUB D D, B B
-
D
=
B

HIGH DW
SBB W C, A sg A
-
sg C
-
CY
=
sg A

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7-20 Instruction List

7.18.3 MULTIPLY instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
MUL B K , R " 0 0 " " MUL B 100,A Fixed-point multiplication of signed integers.
W R " 0 0 " " MUL W B,A
D MUL D B,A

In multiplication, the product always occupies the double width of the

output operands.

Byte / word multiplication

7/15 0
MUL B/W B, A ; SRC sg B
B/W
x
; DEST sg A
B/W
15/31 =
; DEST sg A
W/D

Double-word multiplication
31 0
MUL D B, A ; SRC-D sg B
x
; DEST-D sg A

=
; DEST-D A
and
; DEST-D sg B
+1

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 Instruction List 7-21

7.18.4 IVIDE instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
DIV B K , R " 0 " " " DIV B 100,A Fixed-point division of signed integers.
W R " 0 " " " DIV W B,A
D DIV D B,A

In division, the dividend always occupies the double width of the divisor.

Byte / word division

15/31 0
DIV B/W B, A ; DEST sg A
W/D
7/15 : 0
; SRC sg B
B/W
15/31 = 0
; DEST-D A: HIGH BY = Rest sg LOW BY = Quotient

Double-word division
63 32
DIV W C, A ; DEST-D sg B
+1
31 0
; DEST-D A
31 : 0
; SRC-D sg C
=
; DEST-D sg A: Quotient

; DEST-D B: Rest
+1

# In the case of a division by 0, the division instruction is not carried

out, and the overflow bit goes HIGH. The overflow bit is also set
HIGH in the case of division overflow.

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7-22 Instruction List

7.19 Floating Point Arithmetic

Data formats, accuracy

The floating-point arithmetic supports the data formats specified in the
IEEE 754 and IEE 854 standards.

Two data formats, REAL and LREAL, are defined in accordance with
IEC1131.

Data format Data width Mantissa Exponent Range

REAL 32 bits 24 bits 8 bits 10238
Short, real floating-point number, single
precision
LREAL 64 bits 53 bits 11 bits 102308
Long, real floating-point number, double
precision
Data format L always uses the register pairs AB and CD.

When calculating with the REAL data format, inaccuracies in the decimal
range will occur sooner than with the LREAL format. If a high degree of
accuracy is required, the LREAL format should be used. The appropriate
conversion routines are available in WinSPS v2.4 with WinPanel, v1.5
and higher.

The floating-point formats do not permit the representation of all numbers

in any desired resolution. For example, if one wants to work with a unit of
measure such as µm, which is quite common in mechanical engineering,
the REAL data format permits, for each individual µm, a representation
with a limit value of 16.0 metres. If the LREAL format is chosen instead,
the representation of numbers up to 17,179,869,184.0 m becomes
possible.

Display resolution Limit value

Floating-point notation Exponential notation REAL LREAL
0
1.0 E 16,777,228.0 18,014,398,509,481,984.0
-1
0.1 E 1,048,576.0 1,125,899,906,842,624.0
-2
0.01 E 131,072.0 140,737,488,355,328.0
-3
0.001 E milli m 16,384.0 17,592,186,044,416.0
-4
0.0001 E 1,024.0 1,099,511,627,776.0
-5
0.00001 E 128.0 137,438,953,472.0
-6
0.000001 E micro µ 16.0 17,179,869,184.0
-7
0.0000001 E 1.0 1,073,741,824.0
-8
0.00000001 E 0.125 134,217,728.0
-9
0.000000001 E nano n 0.015625 16,777,216.0
-10
0.0000000001 E 0. 000976563 1,048,576.0
-11
0.00000000001 E 131,072.0
-12
0.000000000001 E pico p 16,384.0
-13
0.0000000000001 E 1,024.0
-14
0.00000000000001 E 128.0
-15
0.000000000000001 E femto f 16.0
-16
0.0000000000000001 E 1.0
-17
0.00000000000000001 E 0.125
-18
0.000000000000000001 E atto a 0.015625

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 Instruction List 7-23

Operands
Depending on the instruction, the following may be used as floating-point
operands:
" M, S, DM, DF, D, DX
with both direct and indirect addressing.
The specified operand address must be divisible as follows: - by 4 for
REAL data format REAL
- by 8 for LREAL data format.
" K, register
" P
A PM parameter may not be used as a floating-point constant. In the
event that this is required, the constant may first be loaded into a
marker word, for example.

Instructions
The floating-point data formats and operands may be used in the
following instruction types:
" LOAD floating point value
" TRANSFER floating point value
" CONVERT
" COMPARE floating point values
" Basic arithmetic functions
" Forming absolute value
" Extracting square root
" Logarithmic functions
" Trigonometric functions

Error displays, range overlaps

Calculating errors and range violations (overlaps) are displayed on the
screen of the Programming Unit (PG) in Monitor Mode.

Exceeding the greatest possible number, and division by 0:

++++++.++++++

Shortfall of smallest possible number:

------.------

Nondisplayable number, calculating errors:

******.******

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7-24 Instruction List

7.19.1 LOAD floating point value

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
L R K , R " L R 12,321,A REAL constant ( Register A
L R " L L A,C LREAL Register pair AB ( CD
M, S, " L L M8,C LREAL M8 through M15 ( Register pair CD
DP, DF, D, DX " L R DF16,B REAL DF16 through DF23 ( Register B
P " L R P0,D REAL P0 ( Register D
OPD[R] " L L D[A],C LREAL contents of operand addressed by Register A (
Register C

7.19.2 TRANSFER floating point value

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
T R R , M, S, " T R A,M0 REAL Register A ( M0 through M3
L , DP, DF, D, DX " T L A,DF0 LREAL Register pair AB ( DF0 through DF7
, P " T R D,P0 REAL Register D ( P0
, OPD[R] " T L D,[A] LREAL contents of register D
to operand addressed by register A.

7.19.3 CONVERT number formats

" Converting 32-bit integer values to floating-point REAL / LREAL.
" Converting floating-point REAL / LREAL to 32-bit integer values.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
ITF R R " ITF R A Converts 32-bit integer values from
L
register A to REAL floating-point format.
ITF L C Converts 32-bit integer value from
register C to LREAL floating point. .The
result is written to register pair CD.
FTI R R " FTI R A Converts REAL floating-point from
L
register A to 32-bit integer value.
FTI L C Converts LREAL floating-point from
register pair CD to 32-bit integer value. The
result is written to register C.

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 Instruction List 7-25

7.19.4 CONVERT data formats

In the REAL data format, inaccuracies may occur in the decimal
positions. If better accuracy is required, the LREAL data format must be
used. To handle the required data format conversion, specific convert
instructions are provided.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
RTL R " RTL A Converts the LREAL value of register A to a
REAL value.
Destination register pair = AB.
RTL C Converts the REAL value of register C to an
LREAL value.
Destination register pair = CD.
LTR R " LTR A Converts the LREAL value of register pair AB
to REAL value.
Destination register = A.
LTR C Converts the LREAL value of register pair
CD to a REAL value.
Destination register = C.

7.19.5 Removing decimal positions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
TRC R R " TRC R A Writes the value in register A back to register
L
A, but without decimal positions.
TRC L C Writes the value in register pair CD back to
CD, but without decimal positions.

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7-26 Instruction List

7.19.6 COMPARE floating point values

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z AG LG
CPLA R M/K , R " " " " " " CPLA R M4,A Compare REAL M4 thru M7 w/ register A.
L
S/DF/D/ " " " " " " CPLA L D200,C Compare LREAL D200 thru D208 w/ register
DX/DP
CD.
R " " " " " " CPLA L A,C Compare LREAL register pair AB w/ CD.
P " " " " " " CPLA R P62,A Compare REAL REAL P62 w/ register A.
OPD[R] " " " " " " CPLA L M[C],A Compare LREAL contents of operand
addressed by register C w/ register pair AB.
When comparing the REAL and LREAL data formats, the flags require
arithmetical interpretation.

Examples:

Compare DEST A with SRC B CPLA B,A

Jump instruction
Equal A=B JPZ
Unequal A/B JPN
Less than A<B JPM
Less than / equal A'B JPMZ
Greater than A>B JPAG
Greater than/ equal A)B SPP

# When using the CPLA instruction, the evaluation of the compare

results must always be programmed immediately following the
compare instruction itself. The user is advised to bear in mind that
binary operations will cause a modification of the flags. Therefore, a
compare result can be used only in a link. Following this, another
CPLA instruction must again be programmed.

# With various resolutions (decimal positions) the compare operation

in the REAL data format returns correct results only up to specific
limit values.

Display resolution Limit value

0.001953125 256.0000
0.03125000 2048.000
0.2500000 32768.00
2.000000 262144.0
32.00000 2097152
Example:
L R 2048.00000,A
CPLA R 2048.00009,A
The difference is not found, and the numbers are recognized as being
equal, Z = 1.

For large numbers at high resolution the LREAL data format must be
used.

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 Instruction List 7-27

7.19.7 Calculating with floating point values

For working with floating-point values, the basic arithmetic functions are
available:
Addition, subtraction, multiplication and division.

The instructions handling the four basic arithmetic functions offset the
contents of the destination register or register pair against the contents of
the SRC operand. The results are always written to the destination
register or register pair.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
ADD R M/K , R " " " " " ADD R M2,A REAL M2 thru M5 plus register A contents.
SUB L S/DF/D/DX/DP " " " " " SUB L D200,C LREAL register CD minus D200 thru D208.
R " " " " " ADD L A,C LREAL register pair AB plus CD.
P " " " " " SUB R P62,A REAL register A minus P62.
OPD[R] " " " " " SUB L M[C],A LREAL contents of register pair AB minus
operand addressed by register C.
MUL R K , R " " " " " MUL R 123.456,A REAL 123.456 multiplied w/ contents of
DIV L
register A.
R " " " " " DIV L A,C LREAL register pair CD divided by register pair
AB.

7.19.8 Forming absolute value

Absolute values are always formed with the use of a register or register
pair. The ABS instruction returns the absolute value of a number.
Negative numbers are returned as positive values. If the number is 0, the
zero bit will go HIGH.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
ABS R R " " ABS R A Return absolute value of REAL contents of
L
register A.
ABS L C Return absolute value of LREAL contents of
register pair CD.

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7-28 Instruction List

7.19.9 Extracting square root

Square root extraction always uses a register or register pair. The result
is then written to the same register or register pair.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SQRT R R " " " " " SQRT R A Extract square root of REAL contents of
L
register a.
SQRT L C Extract square root from LREAL contents of
register pair CD.

7.19.10 Exponentiation
Y
For exponentiation X , the following procedure is used:
" In REAL format, registers A and C are used, with register A holding
the base, and C the exponent. The result is written to register A.
" In LREAL format, register pairs AB and CD are used, with AB holding
the base, and CD the exponent. The result is written to register pair
AB.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
POW R R R " " " " " POW R A,C Exponentiate the REAL contents of register A
L
with the REAL contents of register C. The
result is written to register A.
POW L A,C Exponentiate the LREAL contents of register
pair AB with the LREAL contents of CD. The
result is written to register pair AB.

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 Instruction List 7-29

7.19.11 Logarithmic functions

The instructions for logarithmic functions calculate the contents of a
register or register pair. The results are always written to the destination
register or register pair.

Realisiert sind:
" Natural logarithm
" Base-10 logarithm
" Forming exponential function from base-10 (common) logarithm

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
LN R R " " " " " LN R A Form natural logarithm from REAL contents of
LOG L
EXP
register A.
LOG L C Form common logarithm from LREAL contents
of register pair CD.
EXP R C Form exponential value from common
logarithm of REAL contents in register C.

7.19.12 Trigonometric functions

The instructions for trigonometric functions calculate the contents of a
register or register pair. The results are always written to the destination
register or register pair.

Realized are:
" Sinus, with entry in radian measure
" Cosine, with entry in radian measure
" Tangent, with entry in radian measure
" Arc sine, main value
" Ant cosine, main value
" Arc tangent, main value

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
SIN R R " " " " " SIN R A Form sine from REAL contents of register A.
COS L
TAN COS L C Form cosine from LREAL contents of register
ASIN pair CD.
ACOS
TAN R C Form tangent from REAL contents of register
ATAN
C.
ASIN R A Form arc sine from REAL contents of register
A.
ACOS L C Form arc cosine from LREAL contents of
register pair CD.
ATAN R C Form arc tangent from REAL contents of
register C.

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7-30 Instruction List

7.20 Parameter Assignments

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
Pn B/W/D/ I/O/M/T/C/K " P0 I0.0 Parameter definition for parameterized module
R/L S/SM/SYM " P1 W S0
calls.
D/DX/DF/DP " P2 W D0
FC/DM " P3 PM0 REAL and LREAL not as a constant.
n: 0 through 62

7.21 Local Symbol Names & Auxiliary Markers for Program Tracking

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
DEF I/O/M/T/C/K , SYM DEF I0.0,-Symbol Definition of symbolic names that are locally
S/SM/SYM DEF I0,-Name
D/DX/DF/DP
valid only within the module in which they have
FC/DM been entered. Essential for the creation of
library modules.
* n * 1 Definition of auxiliary flags for program
n = 0 bis 63
tracking. Processing of these flags is written
only into the marker buffer, and is interpretable
only in case of an error. The auxiliary flag has
no influence on the program.

7.22 System Variable

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
DEFW W K DEFW W 16#0000 Definition of function for system variable in
OM2.

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 Instruction List 7-31

7.23 Jump Instructions

Jump operations may be executed unconditionally, and also in
dependence of a binary link and/or mathematical operation (see also
Section 7.2, ). With one exception (JP [R]), Jump instructions are
programmed symbolically, with the understanding that the entry point
may not bee located within a program branch because this would also
cause the RES at the jump origin point to be linked.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z AG LG
JP SYM " JP -LABEL1 Unconditional to -LABEL
[R],n* " JP [A]
destination.
Unconditional, by jump distance in
register A.
JPB SYM " " 1 JPB -LABEL2 Conditional, see flags.
JPCI SYM " " 0 JPCI -LABEL3 Conditional, see flags.
JPCY SYM " 1 JPCY -LABEL4 Conditional, see flags.
JPCN SYM " 0 JPCN -LABEL5 Conditional, see flags.
JPO SYM " 1 JPO -LABEL6 Conditional, see flags.
JPON SYM " 0 JPON -LABEL7 Conditional, see flags.
JPM SYM " 1 JPM -LABEL8 Conditional, see flags.
SPP SYM " 0 SPP -LABEL9 Conditional, see flags.
JPZ SYM " 1 JPZ -LABEL10 Conditional, see flags.
JPN SYM " 0 JPN -LABEL11 Conditional, see flags.
JPAG SYM " 1 JPAG -LABEL12 Conditional, see flags.
JPMZ SYM " 0 JPMZ -LABEL13 Conditional, see flags.
JPLG SYM " 1 JPLG -LABEL14 Conditional, see flags.
JPCZ SYM " 0 JPCZ -LABEL15 Conditional, see flags.
The JP [R] instruction causes an unconditional jump whose entry point
must always be a jump instruction. This instruction variant was created
specifically for the simple implementation of jump distributors. The
controller monitors the mnemonical code of the entry point, and enters
STOP mode if this fails to correspond to any jump instruction. In such
case, the error status of the Programming Unit (PG) provides information
about the cause of the error.

The parameter n can be specified for the purpose of jump sequence

monitoring, i.e., n can be less or equal to the jump count.

The following example denotes the application of this jump instruction.

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7-32 Instruction List

Example:

PLC program interlude

Fixed program sequence

Jump distance calculation in register A for the following jump sequence:

A may have odd-numbered values only (1, 3, 5, ...).

JP [A],n ; 1-word instruction

JP Ziel1 ; 2-word instruction
JP Ziel2 ; 2-word instruction
:
:
JP Zieln ; 2-word instruction

Ziel1: ; Program part 1

PLC program

JP End

Ziel2: ; Program part 2

PLC program

JP End
:
:
:
:
:
Zieln: ;Program part n

PLC program

JP End
:
:
End
PLC successor program
:

1070 072 189 - 108 (02.09) GB

 Instruction List 7-33

7.24 Module Calls

Module calls may be executed unconditionally, in dependence of a binary
link, or as a result of a calculation example (see also Section 7.2, ).

The PCL uses a module nesting depth of 63 program modules.

Two data modules may be kept enabled at the same time. For this
purpose the following module calls are available:
CM, BAB, BAI DMx: enables DMx as 1st DM
BX, BXB, BXI DMy: enables DMy as 2nd DM

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
CM DM " CM DM0 Unconditional, direct.
BX PM " CM PM0
PM , n " CM PM1,2 Parameterized, list to follow.
P " CM P0 As parameter.
P , n " CM P0,2 As parameter; parameterized, list to follow.
PM[R] " CM PM[A] Indirect
CMC DM " " 1 CMC DM0 Conditional, see flags.
BXB PM " CMC PM0 Direct
PM , n " CMC PM1,2 Parameterized, list to follow.
P " CMC P0 As parameter.
P , n " CMC P0,2 As parameter; parameterized, list to follow.
PM[R] " CMC PM[A] Indirect
CMCI DM " " 0 CMCI DM0 Conditional, see flags.
BXI PM " CMCI PM0 Direct
PM , n " CMCI PM1,2 Parameterized, list to follow.
P " CMCI P0 As parameter.
P , n " CMCI P0,2 As parameter, parameterized. List to follow.
PM[R] " CMCI PM[A] Indirect
CMCY DM " 1 CMCY DM0 Conditional, see flags.
PM " CMCY PM0 Direct
PM , n " CMCY PM1,2 Parameterized, list to follow.
P " CMCY P0 As parameter.
P , n " CMCY P0,2 As parameter; parameterized, list to follow.
PM[R] " CMCY PM[A] Indirect
CMCN DM " 0 CMCN DM0 Conditional, see flags.
PM " CMCN PM0 Direct
PM , n " CMCN PM1,2 Parameterized, list to follow.
P " CMCN P0 As parameter.
P , n " CMCN P0,2 As parameter; parameterized, list to follow.
PM[R] " CMCN PM[A] Indirect
CMO DM " 1 CMO DM0 Conditional, see flags.
PM " CMO PM0 Direct
PM , n " CMO PM1,2 Parameterized, list to follow.
P " CMO P0 As parameter.
P , n " CMO P0,2 As parameter; parameterized, list to follow.
PM[R] " CMO PM[A] Indirect
CMON DM " 0 CMON DM0 Conditional, see flags.
PM " CMON PM0 Direct
PM , n " CMON PM1,2 Parameterized, list to follow.
P " BAPN P0 As parameter.
P , n " CMON P0,2 As parameter; parameterized, list to follow.
PM[R] " CMON PM[A] Indirect

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7-34 Instruction List

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z AG LG
CMM DM " 1 CMM DM0 Conditional, see flags.
PM " CMM PM0 Direct
PM , n " CMM PM1,2 Parameterized, list to follow.
P " CMM P0 As parameter.
P , n " CMM P0,2 As parameter, parameterized.
[R] " CMM PM[A] Indirect
CMP DM " 0 CMP DM0 Conditional, see flags.
PM " CMP PM0 Direct
PM , n " CMP PM1,2 Parameterized, list to follow.
P " CMP P0 As parameter.
P , n " CMP P0,2 As parameter, parameterized.
[R] " CMP PM[A] Indirect
CMZ DM " 1 CMZ DM0 Conditional, see flags.
PM " CMZ PM0 Direct
PM , n " CMZ PM1,2 Parameterized, list to follow.
P " CMZ P0 As parameter.
P , n " CMZ P0,2 As parameter, parameterized.
PM[R] " CMZ PM[A] Indirect
CMN DM " 0 CMN DM0 Conditional, see flags.
PM " CMN PM0 Direct
PM , n " CMN PM1,2 Parameterized, list to follow.
P " CMN P0 As parameter.
P , n " CMN P0,2 As parameter, parameterized.
PM[R] " CMN PM[A] Indirect
DM " 1 CMAG DM0 Conditional, see flags.
CMAG PM " CMAG PM0 Direct
PM , n " CMAG PM1,2 Parameterized, list to follow.
P " CMAG P0 As parameter.
P , n " CMAG P0,2 As parameter, parameterized.
PM[R] " CMAG PM[A] Indirect
DM " 0 CMMZ DM0 Conditional, see flags.
CMMZ PM " CMMZ PM0 Direct
PM , n " CMMZ PM1,2 Parameterized, list to follow.
P " CMMZ P0 As parameter.
P , n " CMMZ P0,2 As parameter, parameterized.
PM[R] " CMMZ PM[A] Indirect
DM " 1 CMLG DM0 Conditional, see flags.
CMLG PM " CMLG PM0 Direct
PM , n " CMLG PM1,2 Parameterized, list to follow.
P " CMLG P0 As parameter.
P , n " CMLG P0,2 As parameter, parameterized.
Fc[R] " CMLG PM[A] Indirect
DM " 0 CMCZ DM0 Conditional, see flags.
CMCZ PM " CMCZ PM0 Direct
PM , n " CMCZ PM1,2 Parameterized, list to follow.
P " CMCZ P0 As parameter.
P , n " CMCZ P0,2 As parameter, parameterized.
PM[R] " CMCZ PM[A] Indirect

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 Instruction List 7-35

7.25 End of Module Instruction

The use of End of Module instructions is possible either unconditional,
conditional by a binary link or based on the result of an arithmetical
operation (see also section 7.2).

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z AG LG
EM EM Unconditional
EMC 1 EMC Conditional, see flags.
BEI 0 BEI Conditional, see flags.
EMCY 1 EMCY Conditional, see flags.
EMCN 0 EMCN Conditional, see flags.
EMO 1 EMO Conditional, see flags.
EMON 0 EMON Conditional, see flags.
EEM 1 EEM Conditional, see flags.
EMP 0 EMP Conditional, see flags.
EMZ 1 EMZ Conditional, see flags.
EMN 0 EMN Conditional, see flags.
EMAG 1 EMAG Conditional, see flags.
EMMZ 0 EMMZ Conditional, see flags.
EMLG 1 EMLG Conditional, see flags.
EMCZ 0 EMCZ Conditional, see flags.

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7-36 Instruction List

7.26 FIFO Instructions

The PCL provides four FIFO buffers, designated FI0 through FI3. Each
FIFO buffer has a size of 1024 bytes. Reading from and writing to the
FIFO buffers is accomplished with the LFI and TFI instructions.

A single instruction reads or writes 1 to 32 bytes.

The number of bytes to be handled by means of the LFI / TFI instruction

is variable, and is declared in Register C.

Exception: In the event that register contents are written to or read from
FIFO buffers, the number of bytes will be defined via the operand
attribute W/BY. Accordingly, operand attribute BY = one byte; operand
attribute W = two bytes.

When the number of bytes to be handled is variably declared in Register

C, each FIFO byte that is read or written causes the value in Register C
to be decremented.

In the case of a FIFO buffer overflow or underflow, the value stored in

Register C provides information about the number of bytes that could no
longer be read or written.

FIFO overflow or underrun will not automatically cause a ZS STOP. As

an indication of a FIFO overflow, carry bit SM31.3 goes HIGH. A FIFO
underrun causes zero bit SM31.7 to go HIGH.

The FIFO buffer is flushed with the RFI (Reset FIFO) instruction.

FIFO buffers are always remanent.

All FIFO instructions are RES-independent.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
LFI B FIn , M/S/SYM " Ü:" U:" LFI B FI2,DF30 Read from FIFO buffer.
W n = 0 bis 3 , D/DX " Ü:" U:" LFI B FI3,D[A] Number of bytes in C.
D , DF/DP " Ü:" U:" LFI B FI0,A 1 Bytes from FIFO into register A
R , OPD[R] " Ü:" U:" LFI W FI0,A 2 Bytes from FIFO into register A
L , R " Ü:" U:" LFI D FI0,A 4 Bytes from FIFO into register A
TFI B M/S/SYM , FIn " Ü:" U:" TFI B DF0,FI2 Write to FIFO buffer.
W D/DX n = 0 bis 3 " Ü:" U:" TFI B D[A],FI3 Number of bytes in C.
D DF " Ü:" U:" TFI B A,FI0 1 Bytes from register A into FIFO.
R [R] " Ü:" U:" TFI W A,FI0 2 Bytes from register A into FIFO.
L R " Ü:" U:" TFI D A,FI0 4 Bytes from register A into FIFO.
RFI FIn RFI FI0 Flush FIFO bugger.
n = 0 bis 3

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 Instruction List 7-37

7.27 Block Commands

Block commands are provided as a comfortable means of loading and
transferring, and also comparing and searching data blocks within the
PCL. The maximum size of the referred data blocks is 512 bytes/256
words/128 double words. The operand attribute indicates whether the
block size refers to byte, word, double word, REAL or LREAL size.

# The following minimum release versions are a prerequisite for the

use of operands I and O in block commands:
WinSPS v3.1
PCL v2.2
CL550 v1.1.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
BLT B/W/D/ M/S , M/S " BLT B M0,D0 Block transfer from source address (
R/L E/A , A " BLT W DF[B],M[A]
D/DX , D/DX destination address, block size in Register C
"
DP/DF , DP/DF "
OPD[B] OPD[A] "
CFxx B/W/D M/S , M/S " " CFZ W M0,D0 Forward/ backward Compare operation
CBxx E/A , E/A " CBN B M[B],D[C]
within block.
D/DX , D/DX "
DP/DF , DP/DF "
OPD[B] OPD[A] "
SFxx B/W/D K , M/S " " SFZ W 50,M20 Forward/ backward Search operation within
SBxx R , E/A " SBLG B B,M[A]
block.
, D/DX "
, DP/DF "
OPD[A] "

Block transfer
Block transfers are accomplished by shifting data block of defined size, whereby
the data block may not overlap. Block transfers use only ascending addresses
(incremental).

Example 1
CM DM10 ; 1st DM
BX DM9 ; 2nd DM
L D 50,C ; Block size = 50
BLT W D20,DX40 ; Copy 50 words, from DM9/D20 up, to DM10/D40.

Example 2
L D 50,A ; DEST address offset
L D 50,B ; SRC address offset
L D 50,C ; Block size = 50
BLT D DF[B],M[A] ; Copy 50 double words, from DF50 up, to M50.

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7-38 Instruction List

Block COMPARE
The function compares two data blocks.
When the compare condition is met, processing is stopped, and the
number of uncompared bytes/words written to register C. When using
prefix addressing, the operand addresses too are output to registers a
and B.

The zero flag goes HIGH when the compare conditions were not met
throughout the entire range.

Block compare operations are possible in forward direction on ascending

addresses, and in backward direction on descending addresses.

By interpreting the flags, C, and M, and their respective combinations, 8

compare criteria are available.

OPP Explanation
Compare Forward operation for the following:
CFZ Equal
CFN Unequal
CFAG Arithmetical greater
CFM Arithmetical less
CFLG Logical greater
CFCY Logical less
CFCN Logical greater or equal
CFCZ Logical less or equal
Compare Backward operation for the following:
CBZ Equal
CBN Unequal
CBAG Arithmetical greater
CBM Arithmetical less
CBLG Logical greater
CBCY Logical less
CBCN Logical greater or equal
CBCZ Logical less or equal
DEST block address direct or in register A, SRC block address direct or
in register B, block size always in register C.

Example 1
CM DM10 ; 1st DM
L D 50,C ; Block size = 50
CFLG W D20,M20 ; Compare forward 50 words f. Logical Greater,
; starting at DM10/D20 with marker from M20 up.

Example 2:
L D 50,A ; DEST address offset
L D 50,B ; SRC address offset
L D 50,C ; Block size = 50
CBZ D DF[B],M[A] ; Compare backward 50 double words for Equal,
; starting at DF50 with marker from M50 up.

Result evaluation of compare condition:

" Not met: Z-flag = 1
" Met: Z-flag = 0
" Register A contains the operand offset in the DEST block.
" Register B contains the operand offset in the SRC block.
" Register C contains the count of data that was not compared.

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 Instruction List 7-39

Block search
The function searches for a character within a data block.
When the character is found, the number of bytes/words that were not
searched is stored in register C. With the use of prefix addressing,
register A will also contain the operand address.

If the character was not found (search condition not met) throughout the
entire range, the zero flag goes HIGH.

Through the interpretation of flags C, M, and Z, and their respective

combinations, 8 search criteria are available.

OPP Explanation
Search Forward for character:
SFZ Equal
SFN Unequal
SFAG Arithmetical greater
SFM Arithmetical less
SFLG Logical greater
SFCY Logical less
SFCN Logical greater or equal
SFCZ Logical less or equal
Search Backward for character:
SBZ Equal
SBN Unequal
SBAG Arithmetical greater
SBM Arithmetical less
SBLG Logical greater
SBCY Logical less
SBCN Logical greater or equal
SBCZ Logical less or equal
Block start address direct or in register A, search values as constants or
in register B; block size always in register C.

Example 1
L D 50,C ; Block size = 50
SFLG B 35,M20 ; Search forward 50 bytes, starting at M20,
; for the value 35.

Example 2
CM DM10
L D 10,C ; Block size = 10
L D 50,B ; Search value
L D 20,A ; DEST address offset
SRZ D B,M[A] ; Search backward 10 bytes , starting at M20,
; for the value 50.

Result evaluation of Search operation (condition):

" Not met: Z-flag = 1
" Met: Z-flag and = 0
" Register A contains the operand offset in the DEST block.
" Register C contains the count of data was not searched.

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7-40 Instruction List

7.28 Interrupt Instructions

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
TIM R , TI " TIM A,TI Transfers interrupt mask. Writes interrupt mask
for enabling / disabling interrupts. The mask was
first loaded into a register.
LIM TI , R " LIM TI,B Loads interrupt mask, define interrupt mask.
EAI TI " EAI TI Enables interrupt group.
DAI TI " DAI TI Disables interrupt group.
LAI TI , R " LAI TI Loads interrupt register, reads statuses.
RI R , TI " RI A,TI Resets interrupts based on a mask that was first
loaded.

7.29 Program Stop & Program End

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
HLT HLT HALT instruction. Controller enters STOP mode,
program address is entered into error stack, and
outputs are cleared (deleted).
PE PE Program End. I/O state is initialized, and the
program cycle start again at the beginning. At
least one EP instruction must be present.

7.30 Backing Up & Loading Remanence Areas

Backing up and loading remanent data between static RAM and PLC:
" Backup: PLC " static RAM
" Loading: static RAM " PLC

Remanence areas to be backed up or loaded are:

" Only data modules as marked with remanence ID in symbol file.

" Operands as per remanence limits set in OM2.

For PCL, refer to Section PCL 2.5.3.2, "Backing up remanence areas on

request"; for CL550, see Section 3.5.2.2.

In the case of markers and the data field, specific areas of the defined
remanence area (Offset, Number in table below) can be specified for the
backup / loading procedures.

Controller Instruction RG Addr. Flag Example Comment

OPP OPA SRC Z-OPD A E D R [R] V CY O N Z
RS DMn RS DM1 Backs up DM1 to static RAM.
M, T, Z, RS M Backs up remanent area, as defined in OM2.
DF, DP RS DF
M, DF Off,Anz RS M10,50 Remanence from M10 up, backup of 50 bytes.
RL DMn RL DM1 Loads DM1 from static RAM.
M, T, Z, RL M Loads remanent area, as defined in OM2.
DF, DP RL DF
M, DF Off,Anz RL M10,50 Remanence from M10 up, loads 50 bytes.

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 Processing Times 8-1

8. Processing Times

8.1 PCL Processing Intervals

The program cycle time in the PCL is dependent on the interaction
between the Microsoft Windows and VxWorks operating systems, and
on several parameters that are discussed below.

" Processor speed. The PC processor responds to the instruction

processing times in an almost linear fashion.
Example: Processing times for a 200 MHz Intel Pentium CPU:
Bit instructions approx. 55 ns
Word / double word approx. 30 ns
instructions
Data module access approx. 110 ns
Floating point instructions approx. 300 to 500 ns

" System timing. Selectable in WinPanel in increments of 1 ms, 2 ms, 5

ms and 10 ms. Especially in the case of very short PLC programs
(shorter than system timing intervals), system timing is essentially
governing PLC cycle time because the next PLC cycle is always
started only after receiving the subsequent system timing signal, refer
to example 1.
Exceptional case:
At least 25% of the system clock speed must be available to process
Windows applications, otherwise another clock will be provides for
their processing, see Example 2.

" Allocated Windows calculating time ('calc-time'). Selectable in

WinPanel as an interrelation of system clock speed and Windows
calculating time. Possible settings are 9/1, 3/1, 1/1, 1/3, and 1/9. This
speed ratio takes effect only if the PLC processing time exceeds the
currently selected system clock speed, see Examples 3 and 4.

" WinPanel startup with fixed default cycle time. The PLC cycle time can
be preset to a fixed value. This is accomplished by means of one of
the WinPanel startup parameters, i.e., WinPanel/Zn, where n is the
value in ms. In this context, care must be taken that the actual PLC
processing time is smaller than the selected value because otherwise
the preselected cycle time will be exceeded. See Example 5.

" I/O image transfer time to bus master. The image transfer time to the
bus master handling the decentralized peripherals is approx. 1 ms.
This time value is integrated in the PLC processing time in the
following sample diagrams.

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8-2 Processing Times

System clock speed vs. Windows calculating time

Selectable combinations:
10 25 50 75 90
Windows calc-time / system speed
ratio [%].
9/1 3/1 1/1 1/3 1/9 System clock / Windows clock ratio
System 1 x x x x x
clock [ms] 2 x x x
5 x
10 x x: permitted settings

# Default setting:
System clock = 1 ms, share in Windows calc-time = 50 %. In normal
circumstances these values do not require user modification. Only
in the event that a specific application necessitates another setting
– because significantly more calc-time is required for Windows
applications – should these values be changed.
When using an integration of the MMI-MADAP and the PCL in the
same device, the following settings have produced good results:
System speed = 5 ms, Windows calc-time ratio = 50 %.

PLC Processing Time

Throughout the following examples, the PLC processing time denotes the
actual length of the program processing interval, which includes the
transfer of the I/O image to the bus master.

Die SPS-Zykluszeit ist als die Zeit definiert die von einem
Programmanfang bis zum nächsten vergeht.

System clock
OM1 ... ... I/O image Windows calc-time OM1 ...
PE

+ PLC Processing Time (

+ PLC Cycle Time (

System clock / Windows clock ratio

The system clock / Windows clock ratio will be effective only if the PLC
processing time is greater than the system clock speed.

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 Processing Times 8-3

PLC processing time vs. Windows calc-time

When the PLC processing time is shorter than 75% of the system clock
speed, Windows still has free resources available for other applications,
see also Example 1. In this case the next PLC cycle starts with the next
system clock pulse.

+ System clock ( + System clock ( + System clock (

3 3 PLC

4 Windows
+ <75 % ( 3 3
3 3
Next PLC Next PLC
cycle cycle

A more critical controller behavior occurs when the PLC processing time
exceeds this 75% limit. In this case, all settings must be optimized.

Example 1
Preconditions:
" System clock = 2 ms
" System clock / Windows clock ratio = 3/1
" PLC processing time = 1.2 ms

+ 2 ms (
1 2 3 4 5 6 System clock
3 3 PLC

4 Windows
3 3 3 3 3
3 3 3 3 3
Next PLC Next PLC Next PLC Next PLC Next PLC
cycle cycle cycle cycle cycle

In this situation, because the PLC processing time of 1.2 ms is shorter

than 75% of the system clock of 2 ms, the system clock / Windows clock
ratio of 1/3 does not have an effect.

The PLC program finishes in time, and Windows is given sufficient time
for processing Windows applications.

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8-4 Processing Times

Example 2
Preconditions:
" System clock = 2 ms
" System clock / Windows clock ratio = 3/1
" PLC processing time = 1.6 ms

+ 2 ms (
1 2 3 4 5 6 System clock
3 3 PLC

4 Windows
<25% 3 3
for 3 3
Windo Next PLC Next PLC
ws cycle cycle

The length of the PLC processing time exceeds 75% of the system clock
rate.

In this case, a stipulation takes effect stating that >25% of the system
clock rate must be provided for Windows applications. Because this is not
the case, there remains insufficient time for processing Windows
programs, and an additional pulse for Windows is inserted. In this
example, the system clock / Windows clock ratio of 1/3 has no effect.

Example 3
Preconditions:
" System clock = 2 ms
" System clock / Windows clock ratio = 3/1
" PLC processing time = 2.2 ms

+ 2 ms (
1 2 3 4 5 6 System clock
3 3 PLC

4 Windows
2 ms PLC 0.2 ms leftover 3
processing time PLC processing 3
time Next PLC cycle
+ 25 % PLC ( + 75 % Windows (

The PLC program takes longer than the selected system clock speed.
Upon conclusion of the first system cycle, Windows receives 3 cycles for
processing. The remainder of the PLC program is processed during the
5th system cycle. The next PLC cycle will start only in the 6th system
cycle. In this example, the system clock / Windows clock ratio of 3/1
takes effect.

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 Processing Times 8-5

Example 4
Preconditions:
" System clock = 2 ms
" System clock / Windows clock ratio = 3/1
" PLC processing time = 5.6 ms

+ 2 ms (
1 2 3 4 5 6 System clock
3 3 PLC

4 Windows
5.6 ms PLC processing time 3
3
Next PLC cycle
+ 75 % PLC ( + 25 % Windows (

The PLC program takes longer than the selected system clock speed.
Upon conclusion of the first system cycle, Windows receives 1 cycle for
processing. The next PLC cycle will start only in the 5th system cycle. In
this example, the system clock / Windows clock ratio of 3/1 takes effect.

Example 5
Preconditions:
" System clock = 2 ms
" System clock / Windows clock ratio = 1/1
" Fixed predefined PLC cycle time = 20 ms, WinPanel start parameter
/Z20
" Actual PLC processing time = 3.0 ms
+ 2 ms (

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 System clock
3 3 PLC

4 Windows
2 ms PLC 1 ms Windows, until predefined time has elapsed. 3
processing leftover 3
time PLC Next PLC
processi cycle
ng time

The PLC program takes longer than the selected system clock speed.
Upon conclusion of the first system cycle, Windows receives 1 system
cycle for processing. The remainder of the PLC program is processed
during the 3rd system cycle. At the end of this interval, Windows is able
to use the CPU performance until the 20 ms have elapsed. In this
example, the system clock / Windows clock ratio of 1/1 takes effect.

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8-6 Processing Times

8.2 CL550 Processing Intervals

In the CL550, the command processing times are as follows:

Bit instructions approx. 60 ns

Word / double word instructions approx. 35 ns
Data module access approx. 130 ns
Floating point instructions approx. 350 to 600 ns

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 Sample Programs 9-1

9. Sample Programs

9.1 Indirect Addressing

; DM verification, checking
; a) for attendance of DM1-DM16, plus generating
; b) "attendance bits" in result DM0/D0
; c) Writing DM sizes into result DM, starting with D2

L D 1,A ; Starting with DM1

L D 0,B ; DM attendance bits in result DM in D0
L D 2,C ; DM sizes in result DM, starting with D2
L D 0,D ; DM no of result DM

CM DM[D] ; result DM indirect module call

nicht_fertig:
; Check DMs and write results
U DM[A] ; Check DM, indirect module attendance check
= D[B] ; If applicable, set attendance bit HIGH, ind. bit addressing.
PUSH D A ; Save DM no.
L D DM[A] ; Load DM size, indirect module length verification.
T W A,D[C] ; Write to size word, indirect double word addressing
POP D A ; Write back DM no.
; Increment address
INC D A,1 ; next DM
INC D B0.1 ; next DM attendance bit
INC D C0.2 ; next DM size word
; All 16 predefined DMs processed?
CPLA D 16,A
JPCZ nicht_fertig; Jump on less than or equal

EM

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9-2 Sample Programs

9.2 COMPARE Instruction

; Simulated compare value
;----------------------------
L W M0,A ; Load markers M0-M1
INC W A,1 ; Increment register
T W A,M0 ; Write value into markers M0-M1

; 1. Compare for "equal"

;-----------------------------

L W M0,A ; current M0-M1 status

CPLA W 10000,A ; value 10.000 attained?

; Interpretation via links

U Z ; value 10.000 attained!
CU Z0 ; increment counter C0 by 1

; Ínterpretation via jump instruction

JPN nicht_0
L W 0,A ; upon attaining value 10.000,
T W A,M0 ; ... delete M0-M1
nicht_0:

; 2. Range/area monitoring
;------------------------

; Check value range 4000-6000

CPLA W 4000,A
JPCY Bereich_niO ; Value must not be less than 4000
CPLA W 6000,A
JPCN Bereich_niO ; ... and not greater than 6000

; Increment marker M2 in value window 4000-6000

L D M4,B ; Read markers M4-M7
INC D B0.100 ; Increment register
T D B,M4 ; Write value to markers M4-M7

Bereich_niO:

(range NOK) ; Delete markers M0-M1 and counter C0 via trigger pulse
U -RI_Anl
JPCI kein_RI
L D 0,A ; Write value 0
T W A,M0 ; ... to markers M0-M1
SC A,Z0 ; ... and T0
T D A,M4 ; ... on markers M4-M7
kein_RI:

EM

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 Sample Programs 9-3

9.3 FIFO Instructions

DEF SM31.1,-log1
DEF SM31.6,-carry
DEF SM31.7,-zero
DEF M0.0,-trouble
DEF M2.0,-nofifo
DEF M6,-rest
DEF M8.0,-RFI

;Transferring data into a FIFO buffer:

BX -db5 ; open data module

A -nofifo ; FIFO instruction locked?

JPB end ; then no transfer to FIFO

L W K30D,C ; Task is to transfer 30 bytes from 2nd active DM,

TFI B DX10,FI3 ; starting with D10, into FIFO FI3.

A -log1 ; Lock FIFO instruction to prevent repeat execution

S -nofifo

A -carry ; FIFO overflow?

O -zero ; FIFO underflow?
S -trouble
JPCI nosave
T W C,-rest ; In the case of overflow/underflow, the count of remaining data
nosave: ; that could not be transferred is written to register C.

L W C,C ; Monitor Help

end:

;Delete FIFO:
A -RFI ; Delete locked?
JPCI noreset

RFI FI3 ; Delete FIFO FI3

A B -log1
R B -RFI ; Lock delete sequence to prevent repeat execution of same.
noreset:

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9-4 Sample Programs

9.4 Bit-indirect Writing to Inputs

For simulation purposes, describing inputs via PLC program is helpful in
many situations.

This can be accomplished with the commands:

= I[R] ; Assigning an input

S I[R] ; Latching setting of inputs

R I[R] ; Latching RESET of inputs

To preset a range of inputs in a DM, proceed as follows:

; Presetting of 20 input bytes, starting with I10.0, ; from DM20,

D10.0 and up. CM DB20 ; Activate DM20
L D 160,C ; 20 bytes = 160 bits
L D 80,A ; starting with I10.0 or D20.0
Loop:
A D[A] ; Write data bit
= E[A] ; to input bit. INC A,1 ; Process next I or
D bit
DEC B,1 ; loop counter –1
JPN Loop ; until loop = 0.

1070 072 189 - 108 (02.09) GB

1070 072 189 - 108 (02.09) GB " HB SP " BRC/EPY " Printed in Germany